Method and apparatus for detecting a storage unit
By performing two read operations on the DRAM memory cell, the bit line voltage is reduced to detect leakage current in the storage capacitor, thus solving the problem of memory cell failure detection and improving detection accuracy and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-27
- Publication Date
- 2026-07-31
AI Technical Summary
Existing technologies are insufficient to effectively detect whether leakage current in the storage capacitors of DRAM memory cells leads to capacitor failure, resulting in inconsistencies in stored data and abnormal functionality of the memory cells.
After writing data to the storage cell, two read operations are performed. The first read reduces the voltage of the bit line back to the first plate to reduce the read error rate. The second read acquires the data and compares the consistency of the first and second data to determine whether the storage capacitor has failed.
It improves the detection capability for storage capacitors with small leakage current, enabling more accurate identification of failed storage capacitors and reducing the read error rate.
Smart Images
Figure CN115083502B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for detecting memory cells. Background Technology
[0002] DRAM (Dynamic Random Access Memory) is a type of internal memory that stores data through a memory array. A memory array can include M×N memory cells, each capable of storing one bit of data. Each memory cell stores charge through a capacitor (called a storage capacitor), and the amount of charge affects the voltage across the capacitor's plates. Therefore, different amounts of data correspond to different amounts of charge, resulting in different voltages across the plates.
[0003] It can be seen that when leakage occurs between the two plates of a storage capacitor, the amount of charge and the voltage on the plates will change over time. Significant changes can lead to alterations in the stored data and ultimately, failure of the storage capacitor in the storage cell. Therefore, how to detect whether leakage in a storage capacitor will cause its failure is a pressing technical problem that needs to be solved. Summary of the Invention
[0004] This disclosure provides a method and apparatus for detecting a storage cell, so as to detect whether leakage current in the storage capacitor will cause the storage capacitor of the storage cell to fail.
[0005] In a first aspect, embodiments of this disclosure provide a method for detecting a storage cell, the method comprising:
[0006] Write the first data into the storage unit;
[0007] A first read is performed on the storage cell to adjust the first voltage of the first plate of the storage capacitor;
[0008] A second read is performed on the storage unit to obtain the second data corresponding to the adjusted first voltage;
[0009] Based on whether the second data and the first data are consistent, it is determined whether the storage capacitor of the storage unit has failed.
[0010] In some embodiments, performing a first read on the memory cell to adjust the first voltage of the first plate of the memory capacitor includes:
[0011] The transistor of the memory cell is turned on to enable charge sharing between the bit line of the memory cell and the storage capacitor;
[0012] The bit line after the charge sharing is performed at least once;
[0013] The voltage of the bit line after at least one read is stored back to the storage capacitor to adjust the first voltage.
[0014] In some embodiments, before the transistor that turns on the memory cell is further comprising:
[0015] The bit lines and complementary bit lines of the memory cell are precharged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach a first standard voltage. When the first data is "1", the first standard voltage is greater than VCC / 2, and when the first data is "0", the first standard voltage is less than VCC / 2. VCC is the logic voltage of data "1".
[0016] In some embodiments, after storing back the data to the storage capacitor based on the voltage of the bit line after the at least one read to adjust the first voltage, the method further includes:
[0017] The first standard voltage is adjusted to precharge the bit lines and complementary bit lines of the memory cell so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the first standard voltage.
[0018] In some embodiments, prior to performing the first read on the storage unit, the method further includes:
[0019] Waiting for a preset time, the preset time being used to wait for the plates of the storage capacitor to leak current.
[0020] In some embodiments, after determining whether the storage capacitor of the storage cell has failed based on whether the second data and the first data are consistent, the method further includes:
[0021] Switch to the second voltage;
[0022] The second voltage after switching is applied to the second plate of the storage capacitor, and the step of writing the first data into the storage cell is initiated. The voltage difference between the second voltage and the first voltage is the condition for leakage current to occur in the first plate or the second plate.
[0023] In some embodiments, after determining whether the storage capacitor of the storage cell has failed based on whether the second data and the first data are consistent, the method further includes:
[0024] Adjust the first data and proceed to the step of writing the first data into the storage unit.
[0025] In some embodiments, determining whether the storage capacitor of the storage cell has failed based on whether the second data and the first data are consistent includes:
[0026] If the second data is consistent with the first data, then it is determined that the storage capacitor has not failed;
[0027] If the second data and the first data are inconsistent, then the storage capacitor is determined to be faulty.
[0028] In some embodiments, the method further includes:
[0029] The storage unit is refreshed according to a preset time period, and then the process proceeds to the step of waiting for a preset time, or to the step of performing a second read on the storage unit to obtain the second data corresponding to the adjusted first voltage.
[0030] In some embodiments, some adjacent storage cells in the same storage array correspond to different first data, while other adjacent storage cells correspond to the same first data.
[0031] In some embodiments, after performing a second read on the storage unit to obtain the second data corresponding to the adjusted first voltage, the step of waiting for a preset time is entered.
[0032] In some embodiments, performing a second read on the storage unit to obtain second data corresponding to the adjusted first voltage includes:
[0033] The bit lines and complementary bit lines of the memory cell are pre-charged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the second standard voltage.
[0034] After the charge of the first electrode plate is shared with the bit line, the current voltage of the bit line is obtained;
[0035] The second data to be read is determined based on the voltage difference between the current voltage of the bit line and the second standard voltage of the complementary bit line.
[0036] Secondly, embodiments of this disclosure provide a detection device for a memory cell, the memory cell including a storage capacitor, the device comprising:
[0037] The first data writing module is used to write first data into the storage unit;
[0038] The first read module is used to perform a first read on the storage unit in order to adjust the first voltage of the first plate of the storage capacitor;
[0039] The second reading module is used to perform a second reading on the storage unit to obtain the second data corresponding to the adjusted first voltage;
[0040] The failure detection module is used to determine whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent.
[0041] In some embodiments, the first reading module is further configured to:
[0042] The transistor of the memory cell is turned on to enable charge sharing between the bit line of the memory cell and the storage capacitor;
[0043] The bit line after the charge sharing is performed at least once;
[0044] The voltage of the bit line after at least one read is stored back to the storage capacitor to adjust the first voltage.
[0045] In some embodiments, the apparatus further includes:
[0046] A pre-charge module is used to pre-charge the bit lines and complementary bit lines of the memory cell before turning on the transistor of the memory cell, so that the voltage of the bit lines and the voltage of the complementary bit lines both reach a first standard voltage. When the first data is "1", the first standard voltage is greater than VCC / 2, and when the first data is "0", the first standard voltage is less than VCC / 2, where VCC is the logic voltage of data "1".
[0047] In some embodiments, the above-described apparatus further includes:
[0048] A voltage adjustment module is used to adjust the first standard voltage after storing back the voltage of the bit line according to the voltage of the bit line after at least one read to the storage capacitor to adjust the first voltage, and then to enter the pre-charge module.
[0049] In some embodiments, the apparatus further includes:
[0050] A waiting module is used to wait for a preset time before performing the first read on the storage unit. The preset time is used to wait for the plates of the storage capacitor to leak current.
[0051] In some embodiments, the apparatus further includes:
[0052] The second voltage switching module is used to switch the second voltage after determining whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent.
[0053] The voltage application module is used to apply the switched second voltage to the second plate of the storage capacitor and enter the first data writing module. The voltage difference between the second voltage and the first voltage is the condition for the first plate or the second plate to generate leakage current.
[0054] In some embodiments, the apparatus further includes:
[0055] The first data adjustment module is used to adjust the first data and then enter the first data writing module after determining whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent.
[0056] In some embodiments, the failure detection module is further configured to:
[0057] If the second data is consistent with the first data, then it is determined that the storage capacitor has not failed;
[0058] If the second data and the first data are inconsistent, then the storage capacitor is determined to be faulty.
[0059] In some embodiments, the apparatus further includes:
[0060] The refresh module is used to refresh the data of the storage unit according to a preset time period and then enter the waiting module or the second read module.
[0061] In some embodiments, some adjacent storage cells in the same storage array correspond to different first data, while other adjacent storage cells correspond to the same first data.
[0062] In some embodiments, after performing a second read on the storage unit to obtain the second data corresponding to the adjusted first voltage, the process enters a waiting module.
[0063] In some embodiments, the second reading module is further configured to:
[0064] The bit lines and complementary bit lines of the memory cell are pre-charged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the second standard voltage.
[0065] After the charge of the first electrode plate is shared with the bit line, the current voltage of the bit line is obtained;
[0066] The second data to be read is determined based on the voltage difference between the current voltage of the bit line and the second standard voltage of the complementary bit line.
[0067] Thirdly, embodiments of this disclosure also provide an electronic device, including: at least one processor and a memory;
[0068] The memory stores computer-executed instructions;
[0069] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to implement the method described in the first aspect.
[0070] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method described in the first aspect.
[0071] Fifthly, embodiments of this disclosure also provide a computer program product for performing the method described in the first aspect.
[0072] The storage cell detection method and apparatus provided in this disclosure can write first data into the storage cell; perform a first read on the storage cell to adjust the first voltage of the first plate of the storage capacitor; perform a second read on the storage cell to obtain second data corresponding to the adjusted first voltage; and determine whether the storage capacitor of the storage cell is faulty based on whether the second data and the first data are consistent. Before performing the second read, this disclosure performs a first read. The purpose of the first read is not to read data, but to reduce the voltage stored back to the first plate by the bit line, thereby increasing the read error rate during the subsequent second read and enabling the detection of more faulty storage capacitors. In this way, outlier storage capacitors with smaller leakage current can be detected. Attached Figure Description
[0073] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.
[0074] Figure 1 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this disclosure;
[0075] Figure 2 This is a flowchart of the steps of a method for detecting a storage unit provided in an embodiment of this disclosure;
[0076] Figure 3 This is a schematic diagram of a Y-page write operation mode for writing data to a storage array, provided in an embodiment of this disclosure;
[0077] Figure 4 This is a schematic diagram of a data topology for writing to a storage array provided in an embodiment of this disclosure;
[0078] Figure 5 This is a detailed flowchart of a storage capacitor detection method provided in an embodiment of this disclosure;
[0079] Figure 6This is a schematic diagram of the structure of a storage unit detection device provided in an embodiment of this disclosure;
[0080] Figure 7 This is a structural block diagram of an electronic device provided in an embodiment of this disclosure.
[0081] The accompanying drawings have illustrated specific embodiments of the present disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0082] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this disclosure as detailed in the appended claims.
[0083] To determine if a storage unit has failed, data can be written to the storage unit and then read from it. The results can be compared to see if the read data matches the written data. If they match, the storage unit is considered to be working; otherwise, it is considered to have failed.
[0084] Storage cell failure can be understood as a malfunction in the storage cell's data storage function, making it impossible to guarantee consistency between read and written data. This disclosure embodiment can detect storage cell failure caused by leakage in the storage capacitor.
[0085] Before explaining how to detect memory cell failure, let's first describe the structure of the memory cell. Figure 1 This is a schematic diagram of the structure of a storage unit provided in an embodiment of this disclosure. (Refer to...) Figure 1 As shown, a memory cell may include a storage capacitor, a transistor, a bit line, and a word line.
[0086] The storage capacitor is the circuit device in the storage unit that actually stores data. It has two plates, called the first plate and the second plate. The first plate stores charge, and a voltage can be applied to the second plate. After the first plate stores charge, a voltage is formed on it. The difference between the voltage of the first plate and the voltage of the second plate can be used to represent the written data. With a fixed voltage on the second plate, the voltage of the first plate is related to the written data; that is, the amount of charge on the first plate is related to the amount of data written. When the written data is "1", the amount of charge on the first plate is larger, resulting in a larger voltage on the first plate. When the written data is "0", the amount of charge on the first plate is smaller, resulting in a smaller voltage on the first plate.
[0087] The transistor can be any MOS transistor, including but not limited to: PMOS (positive metal-oxide-semiconductor field-effect transistor) and NMOS (negative metal-oxide-semiconductor field-effect transistor). The transistor is used to control access to the storage capacitor by turning itself on or off. Specifically, see [reference needed]. Figure 1 As shown, the gate G of the transistor is connected to the word line of the memory cell. The electrical signal on the word line controls the transistor to turn on or off, thereby controlling access to the memory capacitor. The source S of the transistor is connected to the first plate of the memory capacitor, and the drain D of the transistor is connected to the bit line of the memory cell. When the transistor is on, the charge on the bit line can reach the first plate of the memory capacitor through the transistor, realizing data writing; or, the charge on the first plate of the memory capacitor can reach the bit line through the transistor, realizing data reading. When the transistor is off, the bit line and the first plate of the memory capacitor are isolated, so external devices cannot access the first plate through the bit line, that is, data reading and data writing cannot be performed.
[0088] In one example of failure detection of the above-mentioned memory cell, firstly, a voltage can be applied to the second plate of the memory capacitor, then first data can be written to the memory capacitor to form another voltage on the first plate, and finally, the memory cell can be read to obtain second data, so that the memory cell is determined to be faulty when the first data and the second data are inconsistent.
[0089] Considering that storage capacitors inevitably leak current, the above failure detection process can only detect storage cell failures caused by large leakage currents, and cannot detect failures caused by small leakage currents.
[0090] To address the aforementioned issues, this embodiment performs a first read before the second read. The purpose of the first read is not to read data, but rather to reduce the voltage stored back to the first plate by the bit line, thereby increasing the error rate during the subsequent second read and enabling the detection of more failed storage capacitors. This allows for the detection of outlier storage capacitors with smaller leakage current.
[0091] Figure 2 This is a flowchart illustrating the steps of a method for detecting a storage unit according to an embodiment of this disclosure. Please refer to... Figure 2 The above methods include:
[0092] S101: Write the first data into the storage unit.
[0093] The first data is a single bit of binary data, meaning it can be either "1" or "0". Writing the first data to the memory unit here means writing the first data into... Figure 1 In the storage capacitor of the shown memory cell, the first plate can also be understood as being charged according to the first data, with the amount of charge being related to the first data. For example, when the first data is "1", the amount of charge is greater. When the first data is "0", the amount of charge is less.
[0094] The process of writing first data to one of the aforementioned memory cells may include the following steps: First, turn on the word line of the memory cell to receive an activation signal through the word line, the activation signal being used to turn on the transistor of the memory cell; then, receive the first data through the bit line of the memory cell to cause the sensing amplifier circuit to pull up the voltage of the bit line; finally, charge the first plate of the memory cell through the bit line to realize the writing of the first data.
[0095] In some embodiments, the present disclosure may also batch write first data to multiple memory cells of the memory array to test whether the storage capacitors of multiple or even all memory cells of the memory array have failed. The methods for writing data to the memory array may include, but are not limited to: Y-page write operation, Y-fast write operation, and X-fast write operation.
[0096] In one example, data can be written to multiple memory cells of a storage array in batches using Y-page write operations. Before each Y-page write, a word line of the storage array is opened to sequentially write data to all memory cells on that word line. After writing data to all memory cells on a word line, that word line can be closed to open the next word line for writing data to all memory cells on that word line. This process is repeated until all memory cells on all word lines of the storage array have been written with data, at which point the write operation to the storage array is complete.
[0097] Figure 3 This is a schematic diagram illustrating a Y-page write operation for writing data to a storage array, as provided in an embodiment of this disclosure. (Refer to...) Figure 3 As shown, first open word line WL1 to write data to all memory cells on WL1; then close WL1 and open WL2 to write data to all memory cells on WL2; finally, close WL2 and open WL3 to sequentially write data to all memory cells on WL3. After writing to all memory cells on WL3, close WL3.
[0098] As can be seen, the Y-page write operation mode allows for sequential writing to multiple memory cells after opening one word line at a time. Compared to opening one word line at a time to write data to one memory cell, the Y-page write operation mode effectively reduces the number of word line openings, thereby saving the time required to open word lines and helping to improve the data writing efficiency to the storage array.
[0099] Of course, data can also be written to the storage array through other write operation methods, and the embodiments of this disclosure do not limit the write methods.
[0100] In another example, X-Fast write operation mode or Y-Fast write operation mode can also be used, as detailed below:
[0101] X-Fast write operation is a write operation mode in the X direction, meaning it writes based on bit lines. Before each write operation, for the same bit line, all word lines on that bit line are opened sequentially. After opening each word line, data is written sequentially to a predetermined number of memory cells on that word line, and then the word line is closed. This process is repeated until all word lines of that bit line have been written with data, and then the next bit line is started, until all bit lines have been written, which means the memory array write is complete.
[0102] Y-Fast write operation mode is a write operation mode in the Y direction. Before each write operation, a word line is opened. Data is sequentially written to a preset number of memory cells on this word line, and then the word line is closed. Then the word line is opened again, and data is written to the preset number of memory cells on this word line. This opening and closing of the word line is repeated until all the corresponding memory cells on the word line are written, and then the next word line is opened and the same operation is performed.
[0103] S102: Perform a first read of the storage cell to adjust the first voltage of the first plate of the storage capacitor.
[0104] It is understandable that the process of performing the first read on a memory cell is the process of accessing the first plate, which will cause a voltage change on the first plate. This voltage change may lead to additional leakage current at the plates of the memory capacitor, which then adds to the leakage current inherent to the memory capacitor itself. Therefore, with the total leakage current remaining constant, the leakage current of the memory capacitor in a non-failed memory cell decreases.
[0105] Under normal circumstances, the reading process for a memory cell includes: pre-charging process, charge sharing, sensing amplification, and write-back.
[0106] The pre-charge process is used to pull the bit lines and supplementary bit lines of the memory cell to a preset standard voltage (which may be called the first standard voltage).
[0107] Charge sharing is used to turn on the transistor according to the signal on the bit line of the memory cell, so as to form a path between the bit line and the first plate through the turned-on transistor, so that charge can move between the bit line and the first plate.
[0108] Sensing amplification is used to amplify the voltage on the bit line after charge sharing, so that external devices can read data from the bit line.
[0109] Data recall refers to the process of charging the first plate via the bit line after sensing amplification, restoring the first plate to its state before reading. This avoids a rapid drop in voltage of the first plate during data reading, which could lead to inaccurate stored data.
[0110] As can be seen, the bit line is read only once during the above reading process. This minimizes the impact on the bit line voltage, and consequently minimizes the impact on the voltage stored back to the first plate. Therefore, in this embodiment, the bit line can be read multiple times. In some embodiments, for each memory cell, the first reading process may include the following steps: first, turning on the transistor of the memory cell to share charge between the bit line and the storage capacitor; then, reading the bit line at least once after charge sharing; and finally, storing the bit line back to the storage capacitor based on the voltage of the bit line after at least one reading to adjust the first voltage.
[0111] To achieve the aforementioned multiple first reads, the TRCD can be increased initially to allow for multiple first reads within that larger TRCD. It's important to note that with each read, the voltage on the bit lines can be reduced slightly. Multiple reads can further reduce the voltage on the bit lines, resulting in a lower write-back voltage. This leads to a higher read error rate in subsequent reads, allowing for the detection of more faulty memory capacitors. In this way, outlier memory capacitors with smaller leakage current can be detected.
[0112] Before the transistors of the memory cell are turned on, the bit lines and complementary bit lines of the memory cell can be pre-charged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the first standard voltage. When the first data is "1", the first standard voltage is greater than VCC / 2, and when the first data is "0", the first standard voltage is less than VCC / 2. VCC is the logic voltage of the data "1".
[0113] Thus, after adjusting the first voltage by storing the bit line voltage back to the storage capacitor based on the bit line voltage after at least one read, the first standard voltage can also be adjusted to enter the step of pre-charging the bit line and complementary bit line of the storage cell so that the voltage of the bit line and the voltage of the complementary bit line both reach the first standard voltage.
[0114] As can be seen, the embodiments of this disclosure can detect failed storage capacitors as much as possible by adjusting the first standard voltage.
[0115] In some embodiments, a preset time period can be waited before the first read of the storage cell. This preset time period is used to wait for leakage current to occur at the plates of the storage capacitor. This allows time for leakage current to occur at the plates of the storage capacitor, enabling additional leakage current to occur within the preset time period. This additional leakage current can then reduce the leakage current of the storage capacitor itself, thereby reducing the leakage current of the non-failed storage capacitors.
[0116] S103: Perform a second read of the storage cell to obtain the second data corresponding to the adjusted first voltage.
[0117] The purpose of the second read is to retrieve data from the storage unit, using this read data as the second data. It is understood that, assuming the storage unit is not invalid, the second data read is consistent with the first data written.
[0118] For each memory cell, the process of reading the second data may include the following steps: First, pre-charging the bit line and complementary bit line of the memory cell so that the voltage of the bit line and the voltage of the complementary bit line both reach the second standard voltage; then, after the charge of the first plate is shared with the bit line, obtaining the current voltage of the bit line; finally, determining the second data to be read based on the voltage difference between the current voltage of the bit line and the second standard voltage of the complementary bit line.
[0119] The process of determining the second data to be read based on the voltage difference between the current voltage of the bit line and the second standard voltage of the complementary bit line may include the following steps: First, the current voltage of the bit line is amplified by sensing amplification. Specifically, when the current voltage is greater than the second standard voltage, the current voltage of the bit line is pulled to the maximum logic voltage, which is the voltage corresponding to the data "1", and the voltage of the complementary bit line is pulled to the minimum logic voltage, which is the voltage corresponding to the data "0", indicating that the second data to be read is "1"; when the current voltage is less than the second standard voltage, the current voltage of the bit line is pulled to the minimum logic voltage and the voltage of the complementary bit line is pulled to the maximum logic voltage, indicating that the second data to be read is "0".
[0120] In some embodiments, both the first and second reads described above can be performed in batches at once. Batch reads can be performed, but are not limited to, Y-fast read operations or X-fast read operations.
[0121] X-Fast read operation is a read operation method in the X direction, meaning it reads data based on bit lines. Before each read operation, for the same bit line, the word lines on that bit line are opened sequentially. After opening each word line, data is first read from a predetermined number of memory cells on that word line, and then the word line is closed. This process is repeated until all word lines of that bit line have been read, then the next bit line is read, until all bit lines have been read, meaning the memory array read operation is complete.
[0122] Y-Fast read operation is a read operation method in the Y direction. Before each read operation, a word line is opened. Data is sequentially read from a predetermined number of memory cells on this word line, and then the word line is closed. The word line is then opened again to read data from the predetermined number of memory cells. This opening and closing of the word line is repeated until all corresponding memory cells on the word line have been read, and then the next word line is opened and the same operation is performed.
[0123] S104: Determine whether the storage capacitor of the storage cell is faulty based on whether the second data and the first data are consistent.
[0124] In some embodiments, when the second data and the first data are consistent, it can be determined that the storage capacitor is not faulty, that is, the leakage current of the storage capacitor itself is very small, the storage performance is good, and it will not cause read / write errors; when the second data and the first data are inconsistent, it can be determined that the storage capacitor is faulty, that is, the leakage current of the storage capacitor itself is large, the storage performance is poor, and it may cause read / write errors.
[0125] To detect failed storage capacitors as accurately as possible, embodiments of this disclosure can apply a second voltage to the second plate of the storage capacitor, and this second voltage can be switched. Specifically, after determining whether the storage capacitor of the storage cell is failed based on whether the second data and the first data are consistent, the second voltage can be switched; then, the switched second voltage is applied to the second plate of the storage capacitor, and the step of writing the first data into the storage cell is initiated. The voltage difference between the second voltage and the first voltage is the condition for causing leakage current in either the first plate or the second plate.
[0126] It can be seen that the voltage difference between the first voltage and the second voltage can cause leakage current in either the first or second plate. When the first voltage is higher than the second voltage, the first plate may leak current. When the first voltage is lower than the second voltage, the second plate may leak current.
[0127] The aforementioned second voltage can be switched between the logic voltage corresponding to "0" and the logic voltage corresponding to "1". For example, the second voltage can first be set to the logic voltage corresponding to "0" and applied to the second plate of the storage capacitor in each storage cell of the storage array. This can cause additional leakage current in the storage capacitor of the storage cell where the first data written is "1", thus detecting whether there is a large leakage current in the first plate of these storage capacitors. Then, the second voltage can be set to the logic voltage corresponding to "1" and applied to the second plate of the storage capacitor in each storage cell of the storage array. This can cause additional leakage current in the storage capacitor of the storage cell where the first data written is "0", thus detecting whether there is a large leakage current in the second plate of these storage capacitors. In this way, for a single write of the first data, leakage current detection of the first and second plates can be achieved by switching the second voltage.
[0128] Of course, besides the aforementioned method of switching the second voltage, the voltage of the first plate can also be adjusted by switching the written first data. In some embodiments, after determining whether the storage capacitor of the memory cell has failed based on whether the second data and the first data are consistent, the first data can be adjusted, and the step of writing the first data into the memory cell can proceed. In this way, different first voltages can be generated on the first plate for the same memory cell using different first data, thereby providing different leakage conditions for the storage capacitor and causing the storage capacitor to experience additional leakage as much as possible. In this way, due to the additional leakage of the storage capacitor, the leakage of the unfailed storage capacitor itself can be minimized as much as possible.
[0129] In one alternative example, first data can be written in batches to multiple or even all memory cells of the memory array at once, with some adjacent memory cells in the same array corresponding to different first data, and other adjacent memory cells corresponding to the same first data. This not only prevents additional leakage current from occurring between the storage capacitors of adjacent memory cells due to coupling effects, but also increases leakage paths due to the diversity of data.
[0130] Figure 4 This is a schematic diagram of a data topology for writing to a storage array provided in an embodiment of this disclosure. (Refer to...) Figure 4 As shown, there are 8 data topologies, from D_0 to D_7. Each data topology can write data to 4 word lines WL0 to WL3. Each word line corresponds to 8 bit lines, and each bit line writes one bit of data.
[0131] Specifically, the 8-bit data written to the 8 bit lines of word line WL0 in data topology D_0 is: 10101010, the 8-bit data written to the 8 bit lines of word line WL1 in data topology D_0 is: 00000000, the 8-bit data written to the 8 bit lines of word line WL2 in data topology D_0 is: 10101010, and the 8-bit data written to the 8 bit lines of word line WL3 in data topology D_0 is: 00000000.
[0132] The 8-bit data written to the 8 bit lines of word line WL0 by data topology D_1 is: 01010101; the 8-bit data written to the 8 bit lines of word line WL1 by data topology D_1 is: 00000000; the 8-bit data written to the 8 bit lines of word line WL2 by data topology D_1 is: 01010101; and the 8-bit data written to the 8 bit lines of word line WL3 by data topology D_1 is: 00000000.
[0133] The 8-bit data written to the 8 bit lines of word line WL0 in data topology D_2 is: 00000000; the 8-bit data written to the 8 bit lines of word line WL1 in data topology D_2 is: 10101010; the 8-bit data written to the 8 bit lines of word line WL2 in data topology D_2 is: 00000000; the 8-bit data written to the 8 bit lines of word line WL3 in data topology D_2 is: 10101010.
[0134] The 8-bit data written to the 8 bit lines of word line WL0 in data topology D_3 is: 00000000; the 8-bit data written to the 8 bit lines of word line WL1 in data topology D_3 is: 01010101; the 8-bit data written to the 8 bit lines of word line WL2 in data topology D_3 is: 00000000; and the 8-bit data written to the 8 bit lines of word line WL3 in data topology D_3 is: 01010101.
[0135] The 8-bit data written to the 8 bit lines of word line WL0 in data topology D_4 is: 01010101; the 8-bit data written to the 8 bit lines of word line WL1 in data topology D_4 is: 11111111; the 8-bit data written to the 8 bit lines of word line WL2 in data topology D_4 is: 01010101; and the 8-bit data written to the 8 bit lines of word line WL3 in data topology D_4 is: 11111111.
[0136] The 8-bit data written to the 8 bit lines of word line WL0 in data topology D_5 is: 11111111; the 8-bit data written to the 8 bit lines of word line WL1 in data topology D_5 is: 01010101; the 8-bit data written to the 8 bit lines of word line WL2 in data topology D_5 is: 11111111; the 8-bit data written to the 8 bit lines of word line WL3 in data topology D_5 is: 01010101.
[0137] The 8-bit data written to the 8 bit lines of word line WL0 by data topology D_6 is: 10101010; the 8-bit data written to the 8 bit lines of word line WL1 by data topology D_6 is: 11111111; the 8-bit data written to the 8 bit lines of word line WL2 by data topology D_6 is: 10101010; and the 8-bit data written to the 8 bit lines of word line WL3 by data topology D_6 is: 11011111.
[0138] The 8-bit data written to the 8 bit lines of word line WL0 by data topology D_7 is: 11111111; the 8-bit data written to the 8 bit lines of word line WL1 by data topology D_7 is: 10101010; the 8-bit data written to the 8 bit lines of word line WL2 by data topology D_7 is: 11111111; the 8-bit data written to the 8 bit lines of word line WL3 by data topology D_7 is: 10101010.
[0139] It can be seen that within the same data topology, some adjacent storage cells write the same data, while others write different data. Furthermore, the data written to the same storage cell can be the same or different across different data topologies. Thus, by continuously switching between these different data topologies, various leakage current scenarios can be effectively detected.
[0140] In some embodiments, the storage cell can be refreshed according to a preset time period, and then proceed to a step of waiting for a preset time, or proceed to a step of performing a second read on the storage cell to obtain the second data corresponding to the adjusted first voltage. In this way, it can be determined whether the refreshed storage cell has failed, thereby determining the impact of the refresh on leakage current, and ensuring that the storage performance of the detected non-failed storage capacitors is not reduced due to the refresh.
[0141] Furthermore, after performing a second read on the memory cell to obtain the second data corresponding to the first voltage of the adjusted first plate, a step of waiting for a preset time can be initiated. In this way, the first data written once can be repeatedly checked in a loop to detect as many faulty memory cells as possible.
[0142] Figure 5 This is a detailed flowchart of a storage capacitor detection process provided in an embodiment of this disclosure. (Refer to...) Figure 5 As shown, the detailed detection process may include:
[0143] S1: Apply a second voltage to the second plate.
[0144] S2: Write the first data to the storage unit.
[0145] S3: Data refresh.
[0146] S4: Wait for the preset time.
[0147] S5: Precharge the bit lines and complementary bit lines of the memory cell so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the first standard voltage. When the first data written is "1", the first standard voltage is greater than VCC / 2. When the first data written is "0", the first standard voltage is less than VCC / 2. VCC is the logic voltage of the data "1".
[0148] Understandably, when the first data written is "1", the first standard voltage can be appropriately increased from VCC / 2. This pulls the voltage of both the bit line and the complementary bit line above VCC / 2. This might cause the "1" to be read as "0", resulting in a read error. In this way, storage capacitors with significant leakage current can be detected as failed storage capacitors.
[0149] Accordingly, when the written data is "0", the first standard voltage can be appropriately reduced from VCC / 2. This pulls the voltage of both the bit line and the complementary bit line below VCC / 2. This might cause a "0" to be read as a "1", resulting in a read error. In this way, storage capacitors with significant leakage current can be detected as failed storage capacitors.
[0150] S6: Turns on the transistor of the memory cell to enable charge sharing between the bit line and the storage capacitor of the memory cell.
[0151] S7: Perform at least one read of the bit line after charge sharing.
[0152] S8: Memory is written back to the storage capacitor based on the voltage of the bit line after at least one read, so as to adjust the first voltage.
[0153] S9: Determine if the first standard voltage is the last acceptable voltage. If yes, proceed to S11; otherwise, proceed to S10.
[0154] The first standard voltage can be adjusted within multiple permissible voltage ranges, ensuring that it cannot be adjusted further once the last first standard voltage is reached. When writing data "1", the permissible voltage range is greater than VCC / 2 and less than VCC / 2+V, where v is a very small value, allowing the first standard voltage to be adjusted among several discrete values within this range. When writing data "0", the permissible voltage range is less than VCC / 2 and greater than VCC / 2-V, allowing the first standard voltage to be adjusted among several discrete values within this range. This multiple first standard voltage settings allow for the detection of more failed storage capacitors.
[0155] S10: Adjust the first standard voltage and proceed to S5.
[0156] S11: Data refresh.
[0157] S12: Perform a second read of the storage unit to obtain the second data.
[0158] S13: Based on whether the second data and the first data are consistent, determine whether the storage capacitor of the storage unit has failed, and proceed to S4 to perform multiple second reads. When the number of second reads reaches a preset threshold, proceed to S14.
[0159] S14: Determine if the current second voltage is the last second voltage. If yes, proceed to S16; otherwise, proceed to S15.
[0160] The second voltage can be switched among multiple allowed second voltages, so that when switching to the last second voltage, the current second voltage is determined to be the last second voltage.
[0161] S15: Adjust the second voltage and enter S1.
[0162] S16: Determine if the first data is the final data topology. If yes, proceed to S18; otherwise, proceed to S17.
[0163] The first data can be switched between multiple sets of permissible data topologies, for example, such as Figure 4 As shown, the data written to the storage array can be switched between D0 and D7, so that when D7 is reached, the first data is determined to be the final data topology.
[0164] S17: Adjust the first data and proceed to S2.
[0165] S18: End of detection.
[0166] It can be seen that the above Figure 5 The scheme shown is a detection process for a single storage cell. The above method can be used to detect multiple or even all storage cells in a storage array.
[0167] Corresponding to the above method embodiments, Figure 6 This is a schematic diagram of the structure of a storage unit detection device provided in an embodiment of this disclosure. Please refer to... Figure 6 The detection device 200 for the aforementioned storage unit includes:
[0168] The first data writing module 201 is used to write first data into the storage unit.
[0169] The first reading module 202 is used to perform a first reading on the storage unit in order to adjust the first voltage of the first plate of the storage capacitor.
[0170] The second reading module 203 is used to perform a second reading on the storage unit to obtain the second data corresponding to the adjusted first voltage.
[0171] The failure detection module 204 is used to determine whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent.
[0172] In some embodiments, the first reading module 202 is further configured to:
[0173] The transistor of the memory cell is turned on to enable charge sharing between the bit line of the memory cell and the storage capacitor.
[0174] The bit line after the charge sharing is read at least once.
[0175] The voltage of the bit line after at least one read is stored back to the storage capacitor to adjust the first voltage.
[0176] In some embodiments, the apparatus further includes:
[0177] A pre-charge module is used to pre-charge the bit lines and complementary bit lines of the memory cell before turning on the transistor of the memory cell, so that the voltage of the bit lines and the voltage of the complementary bit lines both reach a first standard voltage. When the first data is "1", the first standard voltage is greater than VCC / 2, and when the first data is "0", the first standard voltage is less than VCC / 2, where VCC is the logic voltage of the data "1".
[0178] In some embodiments, the apparatus further includes:
[0179] A voltage adjustment module is used to adjust the first standard voltage after storing back the voltage of the bit line according to the voltage of the bit line after at least one read to the storage capacitor to adjust the first voltage, and then to enter the pre-charge module.
[0180] In some embodiments, the apparatus further includes:
[0181] A waiting module is used to wait for a preset time before performing the first read on the storage unit. The preset time is used to wait for the plates of the storage capacitor to leak current.
[0182] In some embodiments, the apparatus further includes:
[0183] The second voltage switching module is used to switch the second voltage after determining whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent.
[0184] The voltage application module is used to apply the switched second voltage to the second plate of the storage capacitor and enter the first data writing module. The voltage difference between the second voltage and the first voltage is the condition for the first plate or the second plate to generate leakage current.
[0185] In some embodiments, the apparatus further includes:
[0186] The first data adjustment module is used to adjust the first data and then enter the first data writing module after determining whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent.
[0187] In some embodiments, the failure detection module is further configured to:
[0188] If the second data is consistent with the first data, then it is determined that the storage capacitor has not failed.
[0189] If the second data and the first data are inconsistent, then the storage capacitor is determined to be faulty.
[0190] In some embodiments, the apparatus further includes:
[0191] The refresh module is used to refresh the data of the storage unit according to a preset time period and then enter the waiting module or the second read module.
[0192] In some embodiments, some adjacent storage cells in the same storage array correspond to different first data, while other adjacent storage cells correspond to the same first data.
[0193] In some embodiments, after performing a second read on the storage unit to obtain the second data corresponding to the adjusted first voltage, the process enters a waiting module.
[0194] In some embodiments, the second reading module is further configured to:
[0195] The bit lines and complementary bit lines of the memory cell are precharged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the second standard voltage.
[0196] After the charge of the first electrode plate is shared with the bit line, the current voltage of the bit line is obtained.
[0197] The second data to be read is determined based on the voltage difference between the current voltage of the bit line and the second standard voltage of the complementary bit line.
[0198] The above-described apparatus embodiment is an embodiment corresponding to the foregoing method embodiment, and has the same technical effects as the method embodiment. A detailed description of this apparatus embodiment can be found in the detailed description of the foregoing method embodiment, and will not be repeated here.
[0199] This disclosure also provides an electronic device, including at least one processor and a memory.
[0200] The memory stores computer-executed instructions.
[0201] The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to implement the above-described method for detecting the memory unit.
[0202] Figure 7This is a structural block diagram of an electronic device provided in an embodiment of the present disclosure. The electronic device 600 includes a memory 602 and at least one processor 601.
[0203] Among them, memory 602 stores computer-executed instructions.
[0204] At least one processor 601 executes computer execution instructions stored in memory 602, causing electronic device 601 to implement the aforementioned detection method for memory unit.
[0205] In addition, the electronic device may also include a receiver 603 and a transmitter 604, wherein the receiver 603 is used to receive information from other devices or equipment and forward it to the processor 601, and the transmitter 604 is used to send information to other devices or equipment.
[0206] This disclosure also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a computing device, enable the computing device to implement a storage unit detection method.
[0207] This disclosure also provides a computer program product for executing the above-described storage unit detection method.
[0208] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0209] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0210] The above are merely preferred embodiments of the present disclosure and do not limit the patent scope of the present disclosure. Any equivalent structural or procedural transformations made based on the description and drawings of the present disclosure, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present disclosure.
Claims
1. A method for detecting a storage cell, characterized in that, The storage unit includes a storage capacitor, and the method includes: Write the first data into the storage unit; A first read is performed on the storage cell to adjust the first voltage of the first plate of the storage capacitor; A second read is performed on the storage unit to obtain the second data corresponding to the adjusted first voltage; Based on whether the second data and the first data are consistent, determine whether the storage capacitor of the storage unit is faulty; the step of performing a first read on the storage unit to adjust the first voltage of the first plate of the storage capacitor includes: The transistor of the memory cell is turned on to enable charge sharing between the bit line of the memory cell and the storage capacitor; The bit line after the charge sharing is performed at least once; The voltage of the bit line after at least one read is stored back to the storage capacitor to adjust the first voltage; before the transistor of the storage cell is turned on, the method further includes: The bit lines and complementary bit lines of the memory cell are precharged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach a first standard voltage. When the first data is "1", the first standard voltage is greater than VCC / 2, and when the first data is "0", the first standard voltage is less than VCC / 2. VCC is the logic voltage of the data "1".
2. The method of claim 1, wherein, After storing the data back to the storage capacitor based on the voltage of the bit line after the at least one read to adjust the first voltage, the method further includes: The first standard voltage is adjusted to precharge the bit lines and complementary bit lines of the memory cell so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the first standard voltage.
3. The method according to any one of claims 1 to 2, characterized in that, Before performing the first read from the storage unit, the method further includes: Waiting for a preset time, the preset time being used to wait for the plates of the storage capacitor to leak current.
4. The method according to any one of claims 1 to 2, characterized in that, After determining whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent, the method further includes: Switch to the second voltage; The second voltage after switching is applied to the second plate of the storage capacitor, and the step of writing the first data into the storage cell is initiated. The voltage difference between the second voltage and the first voltage is the condition for leakage current to occur in the first plate or the second plate.
5. The method according to any one of claims 1 to 2, characterized in that, After determining whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent, the method further includes: Adjust the first data and proceed to the step of writing the first data into the storage unit.
6. The method of claim 3, wherein, The step of determining whether the storage capacitor of the storage unit is faulty based on whether the second data and the first data are consistent includes: If the second data is consistent with the first data, then it is determined that the storage capacitor has not failed; If the second data and the first data are inconsistent, then the storage capacitor is determined to be faulty.
7. The method of claim 6, wherein, The method further includes: The storage unit is refreshed according to a preset time period, and then the process proceeds to the step of waiting for a preset time, or to the step of performing a second read on the storage unit to obtain the second data corresponding to the adjusted first voltage.
8. The method according to any one of claims 1 to 2, characterized in that, Some adjacent storage cells in the same storage array correspond to different first data, while other adjacent storage cells correspond to the same first data.
9. The method of claim 3, wherein, After performing a second read on the storage unit to obtain the second data corresponding to the adjusted first voltage, the process proceeds to the step of waiting for a preset time.
10. The method according to any one of claims 1 to 2, characterized in that, The second reading of the storage unit to obtain the second data corresponding to the adjusted first voltage includes: The bit lines and complementary bit lines of the memory cell are pre-charged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach the second standard voltage. After the charge of the first electrode plate is shared with the bit line, the current voltage of the bit line is obtained; The second data to be read is determined based on the voltage difference between the current voltage of the bit line and the second standard voltage of the complementary bit line.
11. A detection device for a storage cell, characterized in that, The storage unit includes a storage capacitor, comprising: The first data writing module is used to write first data into the storage unit; A first reading module is used to perform a first reading on the storage unit to adjust the first voltage of the first plate of the storage capacitor; a second reading module is used to perform a second reading on the storage unit to obtain second data corresponding to the adjusted first voltage; The failure detection module is used to determine whether the storage capacitor of the storage unit has failed based on whether the second data and the first data are consistent. The step of performing a first read on the storage cell to adjust the first voltage of the first plate of the storage capacitor includes: The transistor of the memory cell is turned on to enable charge sharing between the bit line of the memory cell and the storage capacitor; The bit line after the charge sharing is performed at least once; The voltage of the bit line after at least one read is stored back to the storage capacitor to adjust the first voltage; before the transistor of the storage cell is turned on, the method further includes: The bit lines and complementary bit lines of the memory cell are precharged so that the voltage of the bit lines and the voltage of the complementary bit lines both reach a first standard voltage. When the first data is "1", the first standard voltage is greater than VCC / 2, and when the first data is "0", the first standard voltage is less than VCC / 2. VCC is the logic voltage of the data "1".
12. An electronic device, comprising: include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the electronic device to perform the method as described in any one of claims 1 to 10.
13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a computing device, cause the computing device to implement the method as described in any one of claims 1 to 10.
14. A computer program product, characterised in that, The computer program product is used to perform the method according to any one of claims 1 to 10.