Method of manufacturing fin field effect transistor

Abstract

The application discloses a manufacturing method of fin field effect transistor, comprising the following steps: step one, forming a fin body on a semiconductor substrate; step two, forming a first gate structure; step three, forming a source region and a drain region, comprising: step 31, forming a second hard mask layer; step 32, opening a forming area of the fin field effect transistor, and exposing a top surface of the fin body by performing first overall etching on the second hard mask layer, and exposing a surface of an isolation medium layer at the same time; step 33, forming a first groove in the fin body by performing second etching; the second etching simultaneously produces longitudinal and transverse etching on the surface-exposed isolation medium layer to form a second groove, so that the fin body and the first polysilicon gate are surface-exposed and a bridging path is formed; step 34, forming a sacrifice side wall to fill the bridging path; and step 35, filling an epitaxial layer in the first groove to form an embedded epitaxial layer. The application can prevent the bridging of the source / drain epitaxial layer and the gate, so that the device performance can be maintained without degradation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a FinField Effect Transistor (FinFET). Background Technology

[0002] With the development of semiconductor manufacturing technology, gate widths are constantly shrinking, and traditional planar CMOS devices can no longer meet device requirements, such as the control of short-channel effects. For technology nodes below 20nm, fin field-effect transistor structures have better electrical performance.

[0003] Embedded epitaxial layers are introduced into the source and drain regions of fin field-effect transistors (FETs). These embedded epitaxial layers alter the stress in the channel region, thereby improving carrier mobility and ultimately enhancing device performance. Starting with the 90nm technology node, embedded SiGe epitaxial layers were introduced to improve PMOS performance; while at the 14nm technology node, embedded SiP epitaxial layers were introduced to improve NMOS performance. To better modify the channel stress, the volume of the embedded epitaxial layer typically needs to be increased. However, this increased volume carries the risk of bridging between the embedded epitaxial layers in the source and drain regions and the gate, which can negatively impact device performance and lead to degradation. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a fin field-effect transistor that can prevent source-drain epitaxy and gate bridging, thereby maintaining the device performance without degradation.

[0005] To solve the above-mentioned technical problems, the manufacturing method of the fin field-effect transistor provided by the present invention includes the following steps: Step 1: Form fins on a semiconductor substrate. The fins have spacer regions between them. An isolation dielectric layer is filled in the spacer regions. The top surface of the isolation dielectric layer is lower than the top surface of the fins. The fins are longitudinally divided into a bottom portion and a top portion that are stacked sequentially. The top portion is located above the top surface of the isolation dielectric layer and below the top surface of the isolation dielectric layer.

[0006] Step 2: Form a first gate structure, which is formed by stacking a first gate dielectric layer and a first polysilicon gate; a first hard mask layer is formed on the top surface of the first polysilicon gate, and the formation area of ​​the first gate structure is defined by the first hard mask layer.

[0007] The first gate structure covers the top surface and side surface of the fin located in the gate forming region, and the first gate structure also extends to the surface of the isolation dielectric layer in the spacer region.

[0008] Step 3: Forming source and drain regions in the fins on both sides of the first gate structure, including the following sub-steps: Step 31: Form a second hard mask layer, which covers the side surface of the first gate structure, the top surface of the first hard mask layer, the top surface and side surface of the fin outside the first gate structure, and the surface of the isolation dielectric layer outside the first gate structure.

[0009] Step 32: Open the formation area of ​​the fin field-effect transistor and perform a first full etching on the second hard mask layer. The first full etching removes the second hard mask layer on the top surface of the fin and exposes the surface of the fin. The first full etching also removes the second hard mask layer on the surface of the isolation dielectric layer and exposes the surface of the isolation dielectric layer.

[0010] Step 33: Using the second hard mask layer as a mask, perform a second etching, which etches the exposed fin to form a first groove; The second etching simultaneously etches the exposed isolation dielectric layer longitudinally and laterally to form a second groove. The bottom surface of the second groove is lower than the bottom surface of the second hard mask layer, and the second groove extends laterally to directly below the bottom surface of the second hard mask layer and directly below the bottom surface of the first polysilicon gate, so that the side of the bottom portion of the fin and the bottom surface of the first polysilicon gate are simultaneously exposed and a bridging path is formed.

[0011] Step 34: A sacrificial sidewall is formed on the side of the second groove, which fills the entire bridging path.

[0012] Step 35: Fill the first groove with an epitaxial layer to form an embedded epitaxial layer, and perform source and drain doping in the embedded epitaxial layer to form the source region and the drain region.

[0013] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0014] A further improvement is that the isolation medium layer adopts a shallow trench isolation oxide layer.

[0015] A further improvement is that the first hard mask layer is composed of a first oxide layer and a first nitride layer stacked together.

[0016] A further improvement is that the second hard mask layer is composed of a second oxide layer and a second nitride layer stacked together.

[0017] A further improvement is that, in step 34, the formation step of the sacrificial sidewall includes: A layer of material is deposited over the entire sacrificial sidewall.

[0018] The sacrificial sidewall is formed by fully etching the material layer of the sacrificial sidewall.

[0019] A further improvement is that the deposition process of the material layer of the sacrificial sidewall adopts the ALD process.

[0020] A further improvement is that the material layer of the sacrificial sidewall includes oxides, nitrides, oxynitrides, or low-K materials.

[0021] A further improvement is that, in step two, the first gate dielectric layer includes a gate oxide layer or a high dielectric constant layer.

[0022] A further improvement is that the fin field-effect transistor includes an N-type fin field-effect transistor and a P-type fin field-effect transistor.

[0023] A further improvement is that when the fin field-effect transistor is an N-type fin field-effect transistor, the embedded epitaxial layer is an embedded SiP epitaxial layer, and both the source region and the drain region are heavily N-type doped.

[0024] A further improvement is that when the fin field-effect transistor is a P-type fin field-effect transistor, the embedded epitaxial layer is an embedded SiGe epitaxial layer, and both the source region and the drain region are heavily P-type doped.

[0025] A further improvement is that, when the N-type fin field-effect transistor and the P-type fin field-effect transistor are simultaneously integrated on the semiconductor substrate, the source and drain regions of the N-type fin field-effect transistor and the source and drain regions of the P-type fin field-effect transistor are formed sequentially in step three.

[0026] When the source and drain regions of the N-type fin field-effect transistor are formed, step 32 opens the formation region of the N-type fin field-effect transistor and simultaneously covers the formation region of the P-type fin field-effect transistor.

[0027] When the source and drain regions of the P-type fin field-effect transistor are formed, step 32 opens the formation region of the P-type fin field-effect transistor and simultaneously covers the formation region of the N-type fin field-effect transistor.

[0028] A further improvement is that, in step one, the fins are formed by etching the semiconductor substrate, and in a top view, each fin has a parallel strip structure.

[0029] A further improvement is that, in step two, each of the first gate structures in the same row is connected together to form a gate structure row; in top view, the gate structure row and the fin are perpendicular to each other.

[0030] After etching the first groove of the embedded epitaxial layer in the source and drain regions and before filling the epitaxial layer, the present invention also uses sacrificial sidewalls to fill the bridging path, thereby preventing the formation of an epitaxial layer in the bridging path during the epitaxial filling process of the first groove, and finally preventing source-drain epitaxy and gate bridging, thereby maintaining the device performance without degradation. Attached Figure Description

[0031] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a flowchart of a method for manufacturing a fin field-effect transistor according to an embodiment of the present invention; Figure 2 This is a plan view of a fin field-effect transistor formed by the manufacturing method of the fin field-effect transistor according to an embodiment of the present invention; Figure 3A , Figure 4A , Figure 5A and Figure 6A This is along the steps in the manufacturing method of the fin field-effect transistor in the embodiments of the present invention. Figure 2 Cross-sectional structural diagram at the dashed line AA in the diagram; Figure 3B , Figure 4B , Figure 5B and Figure 6B This is along the steps in the manufacturing method of the fin field-effect transistor in the embodiments of the present invention. Figure 2 Cross-sectional structural diagram at the dashed line BB in the diagram; Figure 3C , Figure 4C , Figure 5C and Figure 6C This is along the steps in the manufacturing method of the fin field-effect transistor in the embodiments of the present invention. Figure 2 Cross-sectional view of the dashed line CC in the diagram; Figure 3D , Figure 4D , Figure 5D and Figure 6D This is along the steps in the manufacturing method of the fin field-effect transistor in the embodiments of the present invention. Figure 2 Cross-sectional structural diagram at the dashed line DD in the diagram; Figure 6C1 The existing manufacturing method of fin field-effect transistors, after forming the embedded epitaxial layer, Figure 6C Cross-sectional structural diagram at the same location; Figure 6D1 The existing manufacturing method of fin field-effect transistors, after forming the embedded epitaxial layer, Figure 6D Cross-sectional structural diagram at the same location. Detailed Implementation

[0032] like Figure 1 The diagram shown is a flowchart of a method for manufacturing a finned field-effect transistor according to an embodiment of the present invention; as shown... Figure 2 The diagram shown is a plan view of a fin field-effect transistor formed by the manufacturing method of the fin field-effect transistor according to an embodiment of the present invention; as shown... Figure 3A , Figure 4A , Figure 5A and Figure 6A The diagram illustrates the steps along the manufacturing process of the fin field-effect transistor according to an embodiment of the present invention. Figure 2 Cross-sectional view of the structure at point AA (dashed line); as shown Figure 3B , Figure 4B , Figure 5B and Figure 6B The diagram illustrates the steps along the manufacturing process of the fin field-effect transistor according to an embodiment of the present invention. Figure 2 Cross-sectional structural diagram at the dashed line BB in the diagram; as shown Figure 3C , Figure 4C , Figure 5C and Figure 6C The diagram illustrates the steps along the manufacturing process of the fin field-effect transistor according to an embodiment of the present invention. Figure 2 Cross-sectional view of the structure at the dashed line CC; as shown in the figure. Figure 3D , Figure 4D , Figure 5D and Figure 6D The diagram illustrates the steps along the manufacturing process of the fin field-effect transistor according to an embodiment of the present invention. Figure 2 The cross-sectional structure at the dashed line DD in the figure is shown. The manufacturing method of the fin field-effect transistor according to an embodiment of the present invention includes the following steps: Step 1, please combine Figure 2 and Figure 3A For reference, fins 201 are formed on a semiconductor substrate 201a, with spacer regions between the fins 201. An isolation dielectric layer 208 is filled in the spacer regions, with the top surface of the isolation dielectric layer 208 being lower than the top surface of the fins 201. The fins 201 are longitudinally divided into a bottom portion and a top portion that are stacked sequentially. The top portion is located above the top surface of the isolation dielectric layer 208 and below the top surface of the isolation dielectric layer 208.

[0033] In this embodiment of the invention, the semiconductor substrate 201a includes a silicon substrate.

[0034] The isolation medium layer 208 adopts a shallow trench isolation oxide layer.

[0035] The fin 201 is formed by etching the semiconductor substrate 201a. Figure 2 As shown, in a top view, each of the fins 201 has a parallel strip structure.

[0036] Step Two, please combine Figure 2 and Figure 3A For reference, a first gate structure is formed, which is formed by stacking a first gate dielectric layer (not shown) and a first polysilicon gate 202; a first hard mask layer 209 is formed on the top surface of the first polysilicon gate 202, and the formation area of ​​the first gate structure is defined by the first hard mask layer 209.

[0037] The first gate structure covers the top surface and side surface of the fin 201 located in the gate forming region, and the first gate structure also extends to the surface of the isolation dielectric layer 208 in the spacer region.

[0038] In this embodiment of the invention, the fin field-effect transistor includes an N-type fin field-effect transistor and a P-type fin field-effect transistor. Figure 2 In the diagram, dashed box 203 corresponds to the formation region of one of the N-type fin field-effect transistors; dashed box 204 corresponds to the formation region of one of the P-type fin field-effect transistors.

[0039] Figure 3B The image shows a cross-sectional view of the formation region of one of the P-type fin field-effect transistors along the dashed line BB. Figure 3B A cross-section of the first polysilicon gate 202 along its width direction is shown, and the first hard mask layer 209 is formed on the top surface of the first polysilicon gate 202.

[0040] Figure 3C The image shows a cross-sectional view along the dashed line CC, including the two fins 201. Figure 3C The first polysilicon gate 202 is not formed in the corresponding region.

[0041] Figure 3D The image shows a cross-sectional view along the dashed line DD, including a first polysilicon gate 202. Figure 3D The image also shows a cross-section of the first polysilicon gate 202 along its width direction, but... Figure 3D The first polysilicon gate 202 is formed on the surface of the isolation dielectric layer 208, and Figure 3B The first polysilicon gate 202 is formed on the surface of the fin 202.

[0042] In this embodiment of the invention, the first hard mask layer 209 is formed by stacking a first oxide layer and a first nitride layer.

[0043] The first gate dielectric layer includes a gate oxide layer or a high dielectric constant layer.

[0044] Depend on Figure 2 As shown, the first gate structures on the same row are connected together to form a gate structure row; in top view, the gate structure row and the fin 201 are perpendicular to each other.

[0045] Step 3: Forming source and drain regions in the fins 201 on both sides of the first gate structure, including the following sub-steps: Step 31: Form a second hard mask layer 210, which covers the side surface of the first gate structure, the top surface of the first hard mask layer 209, the top and side surfaces of the fin 201 outside the first gate structure, and the surface of the isolation dielectric layer 208 outside the first gate structure.

[0046] In this embodiment of the invention, the second hard mask layer 210 is formed by stacking a second oxide layer and a second nitride layer.

[0047] Step 32: Open the formation area of ​​the fin field-effect transistor and perform a first full etching on the second hard mask layer 210. The first full etching removes the second hard mask layer 210 on the top surface of the fin 201 and exposes the surface of the fin 201. The first full etching also removes the second hard mask layer 210 on the surface of the isolation dielectric layer 208 and exposes the surface of the isolation dielectric layer 208.

[0048] Figure 3A The cross-sectional structure along the dashed line AA is shown after step 32. In step 31, the surface of the first hard mask layer 209 is covered by the second hard mask layer 210. After the first full etching in step 32, the second hard mask layer 210 on the surface of the first hard mask layer 209 is removed.

[0049] Depend on Figure 3B As shown, the second hard mask layer 210 on the side of the first gate structure is retained after the first full etching in step 32. Figure 3B The second hard mask layer 210 shown is located on the side of the first polysilicon gate 202.

[0050] like Figure 3CAs shown, in step 31, the second hard mask layer 210 is also formed on the surface of the fin 201 and the surface of the isolation medium layer 208; after the first full etching in step 32, the second hard mask layer 210 located on the surface of the fin 201 and the surface of the isolation medium layer 208 is removed. Thus, in Figure 3C In this configuration, the second hard mask layer 210 is located on the side of the fin 201.

[0051] like Figure 3D As shown, in step 31, the second hard mask layer 210 is also formed on the surface of the first hard mask layer 209 and the surface of the isolation dielectric layer 208; after the first full etching in step 32, the second hard mask layer 210 located on the surface of the first hard mask layer 209 and the surface of the isolation dielectric layer 208 is removed. Thus, in Figure 3D In this process, the second hard mask layer 210 is located on the side of the first polysilicon gate 202.

[0052] Step 33: Using the second hard mask layer 210 as a mask, a second etching is performed. This second etching etches the exposed fins 201 to form a first groove 211. Since the first groove 211 is formed only in the fins 201 on both sides of the first polysilicon gate 202, it... Figure 4A The first groove 211 is not shown in the image. Figure 4B The image shows the cross-sectional structure of the first groove 211 along the dashed line BB. Figure 4C The image shows the cross-sectional structure of the first groove 211 along the dashed line CC; Figure 4C As shown, the top surface of the second hard mask layer 210 on both sides of the first groove 211 will also be lowered.

[0053] The second etching simultaneously etches the exposed isolation dielectric layer 208 longitudinally and laterally to form a second groove. The bottom surface of the second groove is lower than the bottom surface of the second hard mask layer 210, and the second groove extends laterally to directly below the bottom surface of the second hard mask layer 210 and directly below the bottom surface of the first polysilicon gate 201, so that the side of the bottom portion of the fin 201 and the bottom surface of the first polysilicon gate 202 are simultaneously exposed and a bridging path is formed.

[0054] Depend on Figure 2 As shown, the area where the second groove is formed is indicated by the dashed box 207.

[0055] Depend on Figure 4CAs shown, the area where the second groove is formed is indicated by the dashed box 207a. The second groove extends to the bottom of the second hard mask layer 210 and exposes the side of the bottom portion of the fin 201. It can be seen that the top surface of the isolation medium layer 208 descends from the dashed line EE position.

[0056] Depend on Figure 4D As shown in the figure, the area where the second groove is formed is indicated by the dashed box 207b. It can be seen that the second groove extends to the bottom of the second hard mask layer 210 and exposes the bottom surface of the first polysilicon gate 202.

[0057] Step 34, as Figure 5C and Figure 5D As shown, a sacrificial sidewall 213 is formed on the side of the second groove, which completely fills the bridging path.

[0058] Figure 5A and Figure 5B The second groove was not formed in the middle, therefore in Figure 5A and Figure 5B The sacrificial sidewall 213 is not shown in the image.

[0059] In this embodiment of the invention, the step of forming the sacrificial sidewall 213 includes: The material layer of the sacrificial sidewall 213 is deposited comprehensively. Preferably, the deposition process of the material layer of the sacrificial sidewall 213 is an ALD process. The material of the material layer of the sacrificial sidewall 213 includes oxides, nitrides, oxynitrides, or low-k materials.

[0060] The material layer of the sacrificial sidewall 213 is fully etched to form the sacrificial sidewall 213.

[0061] Step 35, as follows Figure 6B and Figure 6C As shown, an epitaxial layer is filled in the first groove 211 to form an embedded epitaxial layer 212, and source and drain doping is performed in the embedded epitaxial layer 212 to form the source region and the drain region.

[0062] Figure 6A and Figure 6D The first groove was not formed in the middle, therefore in Figure 6A and Figure 6D The embedded epitaxial layer 212 is not shown in the image.

[0063] When the fin field-effect transistor is an N-type fin field-effect transistor, the embedded epitaxial layer 212 is an embedded SiP epitaxial layer, and both the source region and the drain region are heavily N-type doped. Figure 2 As shown, the embedded SiP epitaxial layer is indicated by the symbol 205.

[0064] When the fin field-effect transistor is a P-type fin field-effect transistor, the embedded epitaxial layer 212 is an embedded SiGe epitaxial layer, and both the source and drain regions are heavily P-type doped. Figure 2 As shown, the embedded SiGe epitaxial layer is indicated by the symbol 206.

[0065] When the N-type fin field-effect transistor and the P-type fin field-effect transistor are simultaneously integrated on the semiconductor substrate 201a, the source and drain regions of the N-type fin field-effect transistor and the source and drain regions of the P-type fin field-effect transistor are formed sequentially in step three.

[0066] When the source and drain regions of the N-type fin field-effect transistor are formed, step 32 opens the formation region of the N-type fin field-effect transistor and simultaneously covers the formation region of the P-type fin field-effect transistor.

[0067] When the source and drain regions of the P-type fin field-effect transistor are formed, step 32 opens the formation region of the P-type fin field-effect transistor and simultaneously covers the formation region of the N-type fin field-effect transistor.

[0068] After completing step three, the following steps are also included: Forming a contact etch stop layer (CESL); Formation of the zeroth interlayer membrane; A chemical mechanical polishing process is performed to make the surfaces of the zeroth interlayer film and the contact etch stop layer flush with the first polysilicon gate 202, while the first hard mask layer 209 on the surface of the first polysilicon gate 202 is removed.

[0069] If the first gate structure is the final gate structure, the metal interconnect process will be performed after the first gate structure is exposed.

[0070] If the first gate structure is used as a dummy gate structure, a metal gate replacement process is required. This process includes removing the first gate structure and forming a second gate structure in the region where the first gate structure was removed. The second gate structure is composed of a second gate dielectric layer and a metal gate, wherein the second gate dielectric layer includes a high-dielectric material layer. Subsequent metal interconnect processes are then performed.

[0071] In this embodiment of the invention, after etching the first groove 211 of the embedded epitaxial layer 212 in the source and drain regions and before filling the epitaxial layer, a sacrificial sidewall 213 is used to fill the bridging path. This prevents the formation of an epitaxial layer in the bridging path during the epitaxial filling process of the first groove 211, and finally prevents source / drain epitaxy and gate bridging, thereby maintaining the device performance without degradation.

[0072] To further illustrate how the embodiments of the present invention can prevent source-drain epitaxy and gate bridging, a counterexample is given below: For instance... Figure 6C1 The existing manufacturing method of fin field-effect transistors, after forming the embedded epitaxial layer, Figure 6C Cross-sectional structural diagrams at the same location; such as Figure 6D1 The diagram shows the manufacturing process of a conventional finned field-effect transistor after the formation of the embedded epitaxial layer. Figure 6C A cross-sectional view at the same location; compared with the manufacturing method of the fin field-effect transistor in the embodiment of the present invention, the existing manufacturing method of the fin field-effect transistor omits step 34 of the method in the embodiment of the present invention, that is, after the second etching in step 33 is completed, the process of filling the epitaxial layer in the first groove 211 in step 35 is directly performed. Because as the required volume of the embedded epitaxial layer 12 increases, the depth and lateral dimensions of the second groove will increase, which can easily expose the surfaces of the first polysilicon gate 202 and the fin 201. Thus, in the epitaxial layer filling process in step 35, since the epitaxial process is selective growth, selective growth means that growth will occur on the surface of the fin 201 with a single crystal structure, and will not occur outside the surface of the fin 201; since the surface of the fin 201 in the second groove is exposed, the epitaxial layer will grow from the exposed surface of the fin 201 in the second groove. Figure 6C1 and Figure 6D1 In the text, the epitaxial layer grown in the second groove is separately indicated by the designation 213a. Figure 6D1 As can be seen, the epitaxial layer 213a will contact the first polysilicon gate 202, resulting in a source-drain epitaxy and gate bridging defect. However, the method of the embodiment of the present invention can avoid the occurrence of source-drain epitaxy and gate bridging.

[0073] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a finned field-effect transistor, characterized in that, Includes the following steps: Step 1: Form fins on a semiconductor substrate. The fins have spacer regions between them. An isolation dielectric layer is filled in the spacer regions. The top surface of the isolation dielectric layer is lower than the top surface of the fins. The fins are longitudinally divided into a bottom portion and a top portion that are stacked sequentially. The top portion is located above the top surface of the isolation dielectric layer, and the bottom portion is located below the top surface of the isolation dielectric layer. Step 2: Form a first gate structure, which is formed by stacking a first gate dielectric layer and a first polysilicon gate; a first hard mask layer is formed on the top surface of the first polysilicon gate, and the formation area of ​​the first gate structure is defined by the first hard mask layer; The first gate structure covers the top surface and side surface of the fin located in the gate forming region, and the first gate structure also extends to the surface of the isolation dielectric layer in the spacer region; Step 3: Forming source and drain regions in the fins on both sides of the first gate structure, including the following sub-steps: Step 31: Form a second hard mask layer, the second hard mask layer covering the side surface of the first gate structure, the top surface of the first hard mask layer, the top surface and side surface of the fin outside the first gate structure, and the surface of the isolation dielectric layer outside the first gate structure. Step 32: Open the formation area of ​​the fin field-effect transistor and perform a first full etching on the second hard mask layer. The first full etching removes the second hard mask layer on the top surface of the fin and exposes the surface of the fin. The first full etching also removes the second hard mask layer on the surface of the isolation dielectric layer and exposes the surface of the isolation dielectric layer. Step 33: Using the second hard mask layer as a mask, perform a second etching, which etches the exposed fin to form a first groove; The second etching simultaneously etches the exposed isolation dielectric layer in both longitudinal and lateral directions to form a second groove. The bottom surface of the second groove is lower than the bottom surface of the second hard mask layer, and the second groove extends laterally to directly below the bottom surface of the second hard mask layer and directly below the bottom surface of the first polysilicon gate, thereby exposing the side of the bottom portion of the fin and the bottom surface of the first polysilicon gate simultaneously and forming a bridging path. Step 34: A sacrificial sidewall is formed on the side of the second groove, which fills the entire bridging path; Step 35: Fill the first groove with an epitaxial layer to form an embedded epitaxial layer, and perform source and drain doping in the embedded epitaxial layer to form the source region and the drain region.

2. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

3. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: The isolation medium layer adopts a shallow trench isolation oxide layer.

4. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: The first hard mask layer is composed of a first oxide layer and a first nitride layer stacked together.

5. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: The second hard mask layer is composed of a second oxide layer and a second nitride layer stacked together.

6. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: In step 34, the steps for forming the sacrificial sidewall include: A material layer was deposited across the entire sacrificial sidewall; The sacrificial sidewall is formed by fully etching the material layer of the sacrificial sidewall.

7. The method for manufacturing a fin field-effect transistor as described in claim 6, characterized in that: The material layer of the sacrificial sidewall was deposited using the ALD process.

8. The method for manufacturing a fin field-effect transistor as described in claim 6, characterized in that: The material layer of the sacrificial sidewall includes oxides, nitrides, nitrogen oxides, or low-K materials.

9. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: In step two, the first gate dielectric layer includes a gate oxide layer or a high dielectric constant layer.

10. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that: The fin field-effect transistor includes N-type fin field-effect transistors and P-type fin field-effect transistors.

11. The method for manufacturing a fin field-effect transistor as described in claim 10, characterized in that: When the fin field-effect transistor is an N-type fin field-effect transistor, the embedded epitaxial layer is an embedded SiP epitaxial layer, and both the source region and the drain region are heavily N-type doped.

12. The method for manufacturing a fin field-effect transistor as described in claim 10, characterized in that: When the fin field-effect transistor is a P-type fin field-effect transistor, the embedded epitaxial layer is an embedded SiGe epitaxial layer, and both the source region and the drain region are heavily P-type doped.

13. The method for manufacturing a fin field-effect transistor as described in claim 10, characterized in that: When the N-type fin field-effect transistor and the P-type fin field-effect transistor are simultaneously integrated on the semiconductor substrate, the source and drain regions of the N-type fin field-effect transistor and the source and drain regions of the P-type fin field-effect transistor are formed sequentially in step three. When the source and drain regions of the N-type fin field-effect transistor are formed, in step 32, the formation region of the N-type fin field-effect transistor is opened and the formation region of the P-type fin field-effect transistor is covered at the same time. When the source and drain regions of the P-type fin field-effect transistor are formed, step 32 opens the formation region of the P-type fin field-effect transistor and simultaneously covers the formation region of the N-type fin field-effect transistor.

14. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that: In step one, the fins are formed by etching the semiconductor substrate, and in top view, each fin has a parallel strip structure.

15. The method for manufacturing a fin field-effect transistor as described in claim 14, characterized in that: In step two, the first gate structures on the same row are connected together to form a gate structure row; in top view, the gate structure row and the fin are perpendicular to each other.

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