LDMOS with improved breakdown performance

Abstract

A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region below the isolation region is formed, where the drain electrode is spaced apart from a first location of the plate structure by a first distance in a direction of current flow between a source and a drain of the semiconductor device along a central axis of an active region of the semiconductor device, the drain electrode is spaced apart from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active region. The first distance is less than the second distance.

Description

Technical Field

[0001] This disclosure generally relates to manufacturing processes for high-voltage semiconductor devices. Background Technology

[0002] Smart power technologies are increasingly in demand across automotive, industrial, and consumer applications. Integrating high-voltage devices with high side-capability into advanced CMOS platforms presents both technical and economic challenges. In many applications, integrated high-voltage devices are typically protected by ESD clamps to prevent damage from electrostatic discharge (ESD) effects, which are triggered above the operating voltage and below the device breakdown voltage. Therefore, achieving a sufficiently high breakdown voltage with a close distribution is crucial for successful ESD protection.

[0003] In some cases, as the device width of conventional high-voltage devices decreases, the breakdown voltage (BV) of these devices also decreases. Furthermore, the BV variation of these narrow devices may also increase. Therefore, providing adequate ESD protection becomes more challenging as the size of high-voltage devices shrinks to achieve specific design goals. Increasing the minimum device width of high-voltage devices will improve BV characteristics. However, a larger minimum device width will lead to some undesirable characteristics (e.g., higher sense current when the high-voltage device is used as a sensing FET, and larger parasitic capacitance to the substrate). Therefore, there is a strong need to improve breakdown performance through innovative device design while maintaining a minimum device width. Summary of the Invention

[0004] According to a first aspect of the present invention, a method for manufacturing a laterally diffused metal-oxide semiconductor (LDMOS) is provided, comprising:

[0005] A conductive electrode is formed above the isolation zone; and

[0006] A drain electrode is formed electrically connected to the drift region below the isolation region. The conductive electrode surrounds the drain electrode. The drain electrode is spaced apart from the conductive electrode at a first position by a first distance along the central axis of the active region of the LDMOS in the direction of current flow between the source and drain of the LDMOS. The drain electrode is spaced apart from the conductive electrode at a second position by a second distance along a line parallel to the central axis and within the active region. The first distance is less than the second distance.

[0007] In one or more embodiments, manufacturing the LDMOS includes manufacturing a p-type field-effect transistor.

[0008] In one or more embodiments, manufacturing the LDMOS includes manufacturing an n-type field-effect transistor.

[0009] In one or more embodiments, forming the conductive electrode includes forming a linear polycrystalline silicon flap at the first location, wherein the linear polycrystalline silicon flap is not at the second location.

[0010] In one or more embodiments, forming the conductive electrode includes forming a chamfered polycrystalline silicon flap at the first location, wherein the chamfered polycrystalline silicon flap is not at the second location.

[0011] In one or more embodiments, forming the conductive electrode includes forming a stepped polycrystalline silicon flap at the first location, wherein the stepped polycrystalline silicon flap is not at the second location.

[0012] In one or more embodiments, the conductive electrode includes a polysilicon gate portion connected to a field plate portion in the active region of the LDMOS.

[0013] In one or more embodiments, the conductive electrode includes a field plate, wherein the field plate is laterally spaced from the conductive gate structure in the active region of the LDMOS.

[0014] According to a second aspect of the present invention, an apparatus is provided, comprising:

[0015] The conductive electrode above the isolation zone; and

[0016] A drain electrode is connected to the drift region below the isolation region, the conductive electrode surrounds the drain electrode, wherein the drain electrode is spaced apart from the conductive electrode at a first position by a first distance along the central axis of the active region of the LDMOS in the direction of current flow between the source and drain of the LDMOS, the drain electrode is spaced apart from the conductive electrode at a second position by a second distance along a line parallel to the central axis and within the active region, and the first distance is less than the second distance.

[0017] In one or more embodiments, the LDMOS is a p-type field-effect transistor.

[0018] In one or more embodiments, the LDMOS is an n-type field-effect transistor.

[0019] In one or more embodiments, the first position includes a linear polycrystalline silicon flip plate, wherein the linear polycrystalline silicon flip plate is not located at the second position.

[0020] In one or more embodiments, the first position includes a chamfered polycrystalline silicon flap, wherein the chamfered polycrystalline silicon flap is not located at the second position.

[0021] In one or more embodiments, the first position includes a stepped polycrystalline silicon flap, wherein the stepped polycrystalline silicon flap is not located at the second position.

[0022] In one or more embodiments, the conductive electrode includes a polysilicon gate portion connected to a field plate portion in the active region of the LDMOS.

[0023] In one or more embodiments, the conductive electrode includes a field plate, wherein the field plate is laterally spaced from the conductive gate structure in the active region of the device.

[0024] According to a third aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising:

[0025] A slab structure is formed above the isolation zone; and

[0026] A drain electrode is formed that is electrically connected to a drift region below the isolation region, wherein the drain electrode is spaced apart from a first position of the plate structure by a first distance along the central axis of the active region of the semiconductor device in the direction of current flow between the source and drain of the semiconductor device, and the drain electrode is spaced apart from a second position of the plate structure by a second distance along a line parallel to the central axis and within the active region, and the first distance is less than the second distance.

[0027] In one or more embodiments, the plate structure is laterally spaced from the conductive electrodes in the active region of the semiconductor device.

[0028] In one or more embodiments, forming the plate structure includes forming a linear polycrystalline silicon flap at the first location, wherein the linear polycrystalline silicon flap is not at the second location.

[0029] In one or more embodiments, forming the plate structure includes forming a chamfered polycrystalline silicon flap at the first location, wherein the chamfered polycrystalline silicon flap is not at the second location.

[0030] These and other aspects of the invention will become apparent from the embodiments described below, and will be illustrated with reference to these embodiments. Attached Figure Description

[0031] The invention is illustrated by way of example and is not limited to the drawings, in which similar reference numerals indicate similar elements. Elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0032] Figure 1 This is a cross-sectional view of an example embodiment of a p-type laterally diffused metal-oxide semiconductor (LDMOS).

[0033] Figure 2 for Figure 1 A plan view of a subset of layers in an example embodiment.

[0034] Figure 3 for Figure 1 A plan view of the polysilicon (poly) layer and drain region in an example embodiment.

[0035] Figure 4 For corresponding Figure 1 Example Implementation Figure 2 and Figure 3 A top view of the layer.

[0036] Figure 5 For the case where the device width is 40 μm Figure 1 A graphical view of the BV characteristics of an example embodiment.

[0037] Figure 6 For the case where the device width is 5μm Figure 1 A graphical view of the BV characteristics of an example embodiment.

[0038] Figure 7 For example embodiments of this disclosure having a modified polysilicon layer Figure 1 A graphical view of the BV characteristics of an LDMOS, wherein the modified polysilicon layer has various polysilicon markings to the drain spacing.

[0039] Figure 8 Examples of embodiments according to this disclosure include Figure 1 A schematic diagram of a single stepped flap and a modified polysilicon layer of drain region.

[0040] Figure 9 Examples of embodiments according to this disclosure include Figure 1 A schematic diagram of the chamfered flip plate and the modified polysilicon layer of the drain region.

[0041] Figure 10 Examples of embodiments according to this disclosure include Figure 1 A schematic diagram of a modified polysilicon layer with multiple stepped flaps and drain regions.

[0042] Figure 11 For example embodiments according to this disclosure, in the case of a device width of 40 μm and further including a polysilicon flap, Figure 1 A graphical view of the BV characteristics.

[0043] Figure 12 For example embodiments according to this disclosure, in the case where the device width is 5 μm and further includes a polysilicon flap, Figure 1A graphical view of the BV characteristics.

[0044] Figure 13 This is a flowchart representation of a method for manufacturing an LDMOS with improved breakdown performance according to an example embodiment of the present disclosure.

[0045] Figure 14 This is a flowchart representation of another method for manufacturing an LDMOS with improved breakdown performance according to an example embodiment of the present disclosure. Detailed Implementation

[0046] The embodiments described herein provide improvements in BV. Specifically, a unique polysilicon flap is used in the main device operating region, wherein the polysilicon flap has a length greater than the gate length near the device termination end (and therefore a shorter distance to the active drain region). Thus, the BV dependency on device width is reduced, and the BV distribution is narrowed without the need for a corresponding increase in parasitic capacitance and a wider device width for higher sensing current in certain sensing applications.

[0047] Figure 1 An example embodiment 10 of a p-type LDMOS arranged as a pair of split-gate transistors is shown. The LDMOS is formed on an n-type wafer (e.g., n-wafer) 12. A bulk oxide (e.g., embedded oxide) 14 is formed on the n-wafer 12. Oxide 16 encloses a vertical n-type polysilicon 18. An n-type embedded layer (e.g., lnbl) 20 is formed on the embedded oxide 14. The embedded oxide 14 and oxide 16 form a shielding region within which a transistor is formed. A p-type epitaxial layer (e.g., p-epi) 22 is formed over the lnbl 20. An N-type high-voltage implant (e.g., NHV) 24 is formed over the lnbl 20 to form a corresponding body region for each of the two transistors included in embodiment 10. The p-type epitaxial layer 22 is held between the oxide 16 and the corresponding NHV 24. A pair of p-type high-voltage p-wells (e.g., HVPW) 26 are formed in the p-epi 22. Shallow trench isolation (STI) 28 is formed between the body contact 40 of each respective transistor and the deep trench isolation (DTI) formed of oxide 16 and polysilicon 18. The body contact 40 forms a low-impedance connection to nhv 24. A source contact 42 is adjacent to the body contact 40. A pair of p-type lightly doped drain implants (e.g., pldd) 44 are formed adjacent to the source contact 42. STI 50 is formed in the hvpw 26 drift region for each respective transistor.

[0048] A first polysilicon gate electrode 52 is formed above the channel region 56 and controls the formation and conductivity of the channel region 56. A shared drain 53 is formed in hvpw 26 and p-epi 22. A second polysilicon gate electrode 54 is formed above each of the STI 50 for each corresponding transistor to form a corresponding field plate. Each of the second polysilicon gate electrodes 54 forms a corresponding field plate having a lower drift region in hvpw 26. Spacers 58 are laterally formed on the side of the first polysilicon gate electrode 52 near the source 42 and on the side of the second polysilicon gate electrode 54 near the drain 53. Spacers 59 are formed between each of the first polysilicon gate electrodes 52 and the second polysilicon gate electrode 54. A silicide 60 is formed above the body contact 40 and the source contact 42 for docking each corresponding transistor. The silicide 60 is also formed above each polysilicon gate electrode 52 and 54 and the shared drain 53. In another embodiment, the drift region in hvpw 26 further includes an n-type compensation (NCOM) region 62 to reduce the doping concentration in this region. The second polysilicon gate electrode 54 is spaced apart from the drain electrode 53 by a first distance 64. Figure 1 Example embodiment 10 illustrates a split gate design. It should be understood that the teachings throughout this disclosure also apply to embodiments using a single polysilicon gate design, wherein the single polysilicon gate is used to form the channel region 56 and the field plate.

[0049] Figure 2 To show Figure 1 A plan view of an example embodiment 70 of several processing layers of embodiment 10. Figure 3 To show Figure 1 A plan view of example embodiment 80, which includes an additional processing layer in embodiment 10. (Continue to refer to...) Figure 1 , Figure 2 A DTI 18 is shown surrounding the NHV region 24 forming the body region. The NHV region 24 surrounds the HVPW region 26 forming the drift region. In one embodiment, the drift region further includes an implanted NCOM region 62 to improve hot carrier injection (HCI)-time-dependent dielectric breakdown (TDDB) robustness by reducing the doping concentration in the drift region. The DTI 18 and the buried oxide 14 (not shown) isolate the transistor pair from adjacent devices to improve isolation. A p-type epitaxial layer 22 (…) is shown between the DTI 18 and the NHV 24. Figure 2 The unfilled area in the channel further increases the BV for both high-side (HS) and low-side (LS) power applications. The active region 72 is defined at the location where channel conductivity occurs. In example embodiment 70, the active region 72 is shown as a single rectangular region. A central axis 74 is defined, which bisects the active region 72 in the direction of current flow between the source 42 and the drain 53.

[0050] Continue to refer to Figure 1 and Figure 2 , Figure 3 A merged polysilicon layer 82 is shown, conductively merging a first gate electrode 52 (forming a polysilicon gate above channel region 56) and a second gate electrode 54 (forming a field plate above STI 50) outside the active region 72. A pair of gaps 84 are used to form a split gate transistor by spacing the first gate electrode 52 and the second gate electrode 54 apart. A drain 53 is spaced apart from the second polysilicon gate electrode 54 by a first distance 64 at a first position 90 on the central axis 74 of the active region 72. The second polysilicon gate electrode 54 includes a first field plate length 92 at the first position 90. The drain 53 is spaced apart from the second polysilicon gate electrode 54 by a second distance 86 at a second position 94 away from the central axis 74 and within the active region 72 of Example Embodiment 10. The second polysilicon gate electrode 54 includes a second field plate length 96 at the second position 94.

[0051] The second gate electrode 54 of the STI 50, covering the hvpw 26 or drift region, includes a right-side portion 100, a left-side portion 102, a top portion 104, and a bottom portion 106. Figure 3 The terms right, left, top, and bottom are provided in the context for ease of explanation and are not intended to impose a directional limitation on the example embodiment 80. The charge balance near the first position 90 differs from the charge balance at the device terminal (e.g., near the second position 94). For example, the drift region near the first position 90 (in the hvpw 26 region) is depleted only by the body region below the right portion 100. In contrast, the depletion of the drift region near the second position 94 is achieved by the body region below both the right portion 100 and the top portion 104. Therefore, the BV characteristics and the first position 90 and the second position 94 are different, and consequently, the required lengths of the first field flap length 92 and the second field flap length 96 are different. Figure 4 It shows Figure 2 and Figure 3 Example embodiment 120 of the combined layer is presented separately for clarity of explanation.

[0052] Figure 5 A schematic view showing the BV characteristics of Example Embodiment 10 with a device width of 40 μm is illustrated. Figure 5 In the example shown, the measured BV 132 for all five dies exceeds the BV threshold of 135V 130. The measured BV 132 also exhibits a tight voltage distribution. However, as Figure 6 As shown, when the device width is reduced to 5 μm, the measured BV 140 decreases to below the BV threshold 130 of 135V and exhibits a wider voltage distribution.

[0053] Figure 7 For example embodiments of this disclosure having a modified polysilicon layer Figure 1 A graphical view of the BV characteristics of an LDMOS, wherein the modified polysilicon layer has various polysilicon markings to the drain spacing. Figure 7 The BV was compared with the first distance 64 between the polysilicon flap and the drain when the device width was 40 μm and 5 μm. Figure 7 In an example embodiment, for a 40 μm device width, an optimal first distance 150 of 3.4 μm is empirically determined to maximize BV (exceeding the BV threshold 130). For a 5 μm device width, an optimal first distance 152 of 3.8 μm is empirically determined to maximize BV (exceeding the BV threshold 130). The optimization of the first distance 64 depends on the device width because the device termination plays a more significant role in narrower devices, where the drift region can be fully exhausted with the aid of a shorter polysilicon flap (e.g., a larger flap to the drain space, or the first distance 64).

[0054] Figure 8 , Figure 9 and Figure 10 Three example embodiments, 160, 170, and 180, are shown, each featuring a modified polysilicon flap design to improve BV characteristics. To account for the impact of device termination on device performance, the polysilicon flap in each embodiment is shortened at and near the termination, while the polysilicon flap at the central axis 74 of the active region 72 remains unchanged. (Reference) Figure 8 ,refer to Figure 3 and Figure 7 An example embodiment of a single stepped flap is shown. As discussed, regarding Figure 7 In one embodiment, a first distance 64 is determined empirically (and thus a first flap length 92 is determined). Similarly, in another embodiment, a flap width 162 and a flap spacing 164 are determined empirically to maximize the BV beyond a BV threshold 130. Figure 9 Example embodiment 170 is shown, which is similar to the single stepped flap of embodiment 160 but has a chamfered flap. Figure 10 Example embodiment 180 is shown, which is similar to the single stepped flap of embodiment 160 but has multiple stepped flaps.

[0055] Figure 11 and Figure 12 It shows having Figure 8 A schematic view of the BV characteristics of Example 10 of the polycrystalline silicon flip plate in Example 160. Similar to Figure 5 With a device width of 40 μm, Figure 11The embodiment shown illustrates the measured BV 190 for five dies with a BV threshold 130 exceeding 135V. The measured BV 190 exhibits characteristics similar to... Figure 5 A similar tight voltage distribution is shown in the diagram. (Compared to...) Figure 6 In contrast, when the device width is 5μm, Figure 12 The embodiments shown illustrate the measured BV 200 for five dies with a BV threshold of 130 exceeding 135V. The measured BV 200 further exhibits characteristics similar to... Figure 6 The distribution shown is a significant improvement over the compact voltage distribution.

[0056] Figure 13 An example embodiment 210 of a method for manufacturing an LDMOS with improved breakdown performance is shown. (See reference...) Figure 13 Continue to refer to Figure 1 and Figure 3 At 214, a conductive electrode 54 (e.g., a field plate) is formed above the isolation region 50. At 216, a drain electrode 53 is formed and connected to the drift region 26. The drain electrode 53 is surrounded by the conductive electrode 54. The first position 90 of the gate electrode 54 is on the central axis 74 of the active region 72. The conductive electrode 54 has a field plate length 92 on a line parallel to the central axis 74 and within the active region 72 that is longer than that at the second position 94 of the conductive electrode 54.

[0057] Figure 14 Another example embodiment 220 of a method for manufacturing LDMOS with improved breakdown performance is shown. (See reference...) Figure 14 Continue to refer to Figure 1 and Figure 3 At position 222, a plate structure 54 is formed above the isolation region 50. A drain electrode 53 is formed and connected to the drift region 26. The first position 90 of the plate structure 54 is on the central axis 74 of the active region 72. The plate structure 54 has a field flap length 92 on a line parallel to the central axis 74 and within the active region 72 that is longer than that at the second position 94 of the plate structure 54.

[0058] As should be understood, the disclosed embodiments include at least the following. In one embodiment, a method for manufacturing a laterally diffused metal-oxide-semiconductor (LDMOS) includes forming a conductive electrode over an isolation region. A drain electrode is formed electrically connected to a drift region below the isolation region. The conductive electrode surrounds the drain electrode, wherein the drain electrode is spaced apart from a first location of the conductive electrode by a first distance along a central axis of the active region of the LDMOS in the direction of current flow between the source and drain of the LDMOS. The drain electrode is spaced apart from a second location of the conductive electrode by a second distance along a line parallel to the central axis and within the active region. The first distance is smaller than the second distance.

[0059] Alternative embodiments of the method for manufacturing a laterally diffused metal-oxide-semiconductor (LDMOS) include one or any combination of the following features: Manufacturing the LDMOS includes manufacturing a p-type field-effect transistor. Manufacturing the LDMOS includes manufacturing an n-type field-effect transistor. Forming the conductive electrode includes forming a linear polysilicon flap at a first location, wherein the linear polysilicon flap is not at a second location. Forming the conductive electrode includes forming a chamfered polysilicon flap at the first location, wherein the chamfered polysilicon flap is not at a second location. Forming the conductive electrode includes forming a stepped polysilicon flap at the first location, wherein the stepped polysilicon flap is not at a second location. The conductive electrode includes a polysilicon gate portion connected to a field plate portion in the active region of the LDMOS. The conductive electrode includes a field plate, wherein the field plate is laterally spaced from the conductive gate structure in the active region of the LDMOS.

[0060] In another embodiment, a device includes a conductive electrode above an isolation region. A drain electrode is connected to a drift region below the isolation region. The conductive electrode surrounds the drain electrode, wherein the drain electrode is spaced apart from a first location of the conductive electrode by a first distance along the central axis of the active region of the LDMOS in the direction of current flow between the source and drain of the LDMOS. The drain electrode is spaced apart from a second location of the conductive electrode by a second distance along a line parallel to the central axis and within the active region. The first distance is smaller than the second distance.

[0061] Alternative embodiments of the device include one or any combination of the following features: LDMOS is a p-type field-effect transistor. LDMOS is an n-type field-effect transistor. The first location includes a linear polysilicon flap, wherein the linear polysilicon flap is not located at the second location. The first location includes a chamfered polysilicon flap, wherein the chamfered polysilicon flap is not located at the second location. The first location includes a stepped polysilicon flap, wherein the stepped polysilicon flap is not located at the second location. The conductive electrode includes a polysilicon gate portion connected to a field plate portion in the active region of the LDMOS. The conductive electrode includes a field plate, wherein the field plate is laterally spaced from the conductive gate structure in the active region of the device.

[0062] In another embodiment, a method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode is formed electrically connected to a drift region below the isolation region, wherein the drain electrode is spaced apart from a first location of the plate structure by a first distance along a central axis of an active region of the semiconductor device in the direction of current flow between the source and drain of the semiconductor device. The drain electrode is spaced apart from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active region. The first distance is smaller than the second distance.

[0063] Alternative embodiments of the method for manufacturing a semiconductor device include one or any combination of the following features. The plate structure is laterally spaced from conductive electrodes in the active region of the semiconductor device. Forming the plate structure includes forming a linear polysilicon flap at a first location, wherein the linear polysilicon flap is not at a second location. Forming the plate structure includes forming a chamfered polysilicon flap at the first location, wherein the chamfered polysilicon flap is not at the second location.

[0064] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative and not restrictive, and all such modifications are intended to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0065] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of such elements.

Claims

1. A method for manufacturing laterally diffused metal-oxide-semiconductor LDMOS, characterized in that, include: Conductive electrodes are formed above the isolation zone; as well as A drain electrode is formed electrically connected to the drift region below the isolation region. A conductive electrode surrounds the drain electrode, wherein the drain electrode is spaced a first distance from the conductive electrode at a first position along the central axis of the active region of the LDMOS in the direction of current flow between the source and drain of the LDMOS. The drain electrode is spaced a second distance from the conductive electrode at a second position along a line parallel to the central axis and within the active region, and the first distance is less than the second distance. The method further includes one of the following: i) Forming the conductive electrode includes forming a linear polycrystalline silicon flap at the first position, wherein the linear polycrystalline silicon flap is not at the second position; ii) Forming the conductive electrode includes forming a chamfered polycrystalline silicon flap at the first location, wherein the chamfered polycrystalline silicon flap is not at the second location; iii) Forming the conductive electrode includes forming a stepped polycrystalline silicon flap at the first location, wherein the stepped polycrystalline silicon flap is not at the second location.

2. The method according to claim 1, characterized in that, Manufacturing the LDMOS includes manufacturing a p-type field-effect transistor.

3. The method according to claim 1, characterized in that, Manufacturing the LDMOS includes manufacturing an n-type field-effect transistor.

4. The method according to claim 1, characterized in that, The conductive electrode includes a polysilicon gate portion, which is connected to the field plate portion in the active region of the LDMOS.

5. The method according to claim 1, characterized in that, The conductive electrode includes a field plate, wherein the field plate is laterally spaced from the conductive gate structure in the active region of the LDMOS.

6. A laterally diffused metal-oxide-semiconductor (LDMOS) device, characterized in that, include: Conductive electrodes above the isolation zone; as well as A drain electrode is connected to the drift region below the isolation region, and a conductive electrode surrounds the drain electrode. The drain electrode is spaced a first distance from the conductive electrode at a first position along the central axis of the active region of the LDMOS in the direction of current flow between the source and drain of the LDMOS. The drain electrode is spaced a second distance from the conductive electrode at a second position along a line parallel to the central axis and within the active region, and the first distance is less than the second distance. The device further includes one of the following: i) The first position includes a linear polycrystalline silicon flip plate, wherein the linear polycrystalline silicon flip plate is not located at the second position; ii) The first position includes a chamfered polycrystalline silicon flap, wherein the chamfered polycrystalline silicon flap is not located at the second position; iii) The first position includes a stepped polycrystalline silicon flip plate, wherein the stepped polycrystalline silicon flip plate is not located at the second position.

7. A method for manufacturing a semiconductor device, characterized in that, include: A slab structure is formed above the isolation zone; as well as A drain electrode is formed that is electrically connected to the drift region below the isolation region. This drain electrode is spaced a first distance from a first position on the plate structure along the central axis of the active region of the semiconductor device in the direction of current flow between the source and drain of the semiconductor device. The drain electrode is also spaced a second distance from a second position on the plate structure along a line parallel to the central axis and within the active region. The first distance is less than the second distance. The method further includes one of the following: i) Forming the plate structure includes forming a linear polycrystalline silicon flip plate at the first position, wherein the linear polycrystalline silicon flip plate is not at the second position; ii) Forming the plate structure includes forming a chamfered polycrystalline silicon flap at the first position, wherein the chamfered polycrystalline silicon flap is not at the second position; iii) Forming the plate structure includes forming a stepped polycrystalline silicon flap at the first position, wherein the stepped polycrystalline silicon flap is not at the second position.

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