Anti-warpage packaging method, chip packaging structure and electronic device
By using Pyrelin materials and room temperature deposition technology, combined with reactive ion etching, the warping problem caused by the mismatch of thermal expansion coefficients in the redistribution layer was solved, achieving a highly efficient chip packaging structure and improving yield and process applicability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU ROUGU TECH CO LTD
- Filing Date
- 2021-03-11
- Publication Date
- 2026-07-14
AI Technical Summary
In existing redistribution layer (RDL) processes, the mismatch in thermal expansion coefficients between silicon and molding compound can cause device warping or breakage, reducing yield.
Using Pyrelin material instead of the high-temperature dielectric layer, and completing the patterning of the redistribution layer through room temperature deposition and reactive ion etching technology, the high-temperature processing is avoided. Combined with metal mask and RIE etching process, a chip packaging structure is formed.
It effectively reduces warpage and breakage, improves yield, and the process can be completed in existing mature systems, suitable for wafer-level and board-level packaging.
Smart Images
Figure CN115083930B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of packaging technology, specifically relating to anti-warping packaging methods, chip packaging structures, and electronic devices. Background Technology
[0002] Wafer-level packaging (WLP) is a chip packaging method where the entire wafer is manufactured first, and then the packaging and testing are performed directly on the wafer before it is diced into individual chips. This eliminates the need for wire bonding or adhesive filling. WLP offers advantages such as small package size and excellent electrical performance after packaging. It is also easily compatible with wafer manufacturing and chip assembly, simplifying the process from wafer fabrication to product shipment and reducing overall production costs. As the scale and complexity of WLP increase, it becomes necessary to introduce redistribution layer (RDL) technology.
[0003] In existing technologies, the redistribution layer (RDL) process often uses a high-temperature process with cross-linked dielectric materials. This can lead to device warping or breakage due to the mismatch in the coefficient of thermal expansion (CTE) between silicon and molding compound, thus reducing the yield. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides an anti-warping encapsulation method that eliminates the need for high-temperature treatment of the dielectric layer.
[0005] Firstly, anti-warping packaging methods include:
[0006] Temporary bonding step: Provide a chip and a carrier board, and temporarily bond the chip to the carrier board;
[0007] Rerouting step: A dielectric layer and a rerouting layer are fabricated on the chip, wherein the dielectric layer is made of pyrene material;
[0008] Debonding step: Remove the carrier plate.
[0009] As an optimization, after the rewiring step and before the debonding step, the method further includes:
[0010] Solder ball fabrication steps: Fabricate solder balls on the pads of the redistribution layer.
[0011] As an optimization, the rerouting step includes at least one iteration of the following steps:
[0012] A perylene layer is deposited at room temperature on the side of the carrier plate where the chip is bonded to form the dielectric layer;
[0013] A metal mask is fabricated on the dielectric layer;
[0014] The dielectric layer is etched to expose the pads of the chip;
[0015] Remove the metal mask;
[0016] The redistribution layer is fabricated on the pads and the dielectric layer.
[0017] As an optimization, after depositing a paraffin layer at room temperature on one side of the carrier bonding the chip to form a dielectric layer, and before fabricating a metal mask on the dielectric layer, the method further includes:
[0018] The carrier plate is subjected to plasma surface treatment.
[0019] As an optimization, the fabrication of a metal mask on the dielectric layer includes:
[0020] Deposit metal on the dielectric layer to form a metal layer;
[0021] Photoresist is coated on the metal layer, and a window area is formed by photolithography. The window area includes a pad area and a non-chip area.
[0022] The portion of the metal layer corresponding to the windowed area and the photoresist are removed to form the metal mask.
[0023] As an optimization, the width of the non-chip region between two adjacent chips is slightly smaller than the spacing between the two chips.
[0024] As an optimization, the etching of the dielectric layer is performed using a reactive ion etching method.
[0025] As an optimization, the debonding step includes:
[0026] Attach the front of the carrier plate to the protective film;
[0027] The temporarily bonded carrier is released through a debonding process, leaving the chip on the protective film;
[0028] The back side of the chip is bonded to the cutting tape, and the protective film on the front side of the chip is removed.
[0029] Secondly, the chip packaging structure is prepared using any of the aforementioned anti-warping packaging methods.
[0030] Thirdly, electronic devices, including chip packaging structures as described in the second aspect.
[0031] Compared with the prior art, the present invention has the following beneficial effects:
[0032] This invention uses phenelzine to replace the existing redistribution layer (RDL) dielectric material, eliminating the need for high-temperature treatment and effectively reducing overall warpage, bending, and breakage. Furthermore, the phenelzine patterning is achieved using a metal mask and reactive ion etching. The entire process does not involve non-standard processes or equipment and can utilize existing mature systems. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 This is a schematic diagram of step 1 of the anti-warping packaging method of the present invention;
[0035] Figure 2 This is a schematic diagram of step 2 of the anti-warping packaging method of the present invention;
[0036] Figure 3 This is a structural schematic diagram of step 2.1 of the anti-warping packaging method of the present invention;
[0037] Figure 4 This is a schematic diagram of step 3 of the anti-warping packaging method of the present invention;
[0038] Figure 5 This is a schematic diagram of step 4 of the anti-warping packaging method of the present invention;
[0039] Figure 6 This is a schematic diagram of the structure after removing the windowed area in step 5 of the anti-warping packaging method of the present invention;
[0040] Figure 7 This is a schematic diagram of the structure after removing the photoresist in step 5 of the anti-warping packaging method of the present invention;
[0041] Figure 8 This is a schematic diagram of step 6 of the anti-warping packaging method of the present invention;
[0042] Figure 9 This is a structural schematic diagram of step 7 of the anti-warping packaging method of the present invention;
[0043] Figure 10 This is a schematic diagram of step 8 of the anti-warping packaging method of the present invention;
[0044] Figure 11 This is a schematic diagram of the structure after steps 8.1-8.7 of the anti-warping packaging method of the present invention;
[0045] Figure 12 This is a schematic diagram of step 9 of the anti-warping packaging method of the present invention;
[0046] Figure 13 This is a schematic diagram of the structure after step 10.1 in the anti-warping packaging method of the present invention;
[0047] Figure 14 This is a schematic diagram of the structure in step 10.3 of the anti-warping packaging method of the present invention, in which the chip is bonded to the ring-cut tape;
[0048] Figure 15 This is a flowchart of the anti-warping packaging method of the present invention;
[0049] Figure 16 This is a flowchart of the rewiring steps in the anti-warping packaging method of the present invention;
[0050] Figure 17 This is a flowchart of the debonding steps in the anti-warping encapsulation method of the present invention.
[0051] Among them, 1. wafer; 2. carrier board; 3. chip; 4. temporary bonding film; 5. dielectric layer; 51. first dielectric layer; 52. second dielectric layer; 6. first metal layer; 61. metal mask; 7. photoresist; 8. window area; 9. redistribution layer; 91. first redistribution layer; 92. second redistribution layer; 10. solder ball; 11. protective film; 12. dicing tape with ring. Detailed Implementation
[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0054] Firstly, anti-warping packaging methods, such as Figure 15-17 As shown, it includes:
[0055] Step 1: Provide chip 3 and carrier board 2. Attach the back side of chip 3 to carrier board 2 using temporary bonding film 4, such as... Figure 1 As shown.
[0056] In this process, chip 3 can be picked from wafer 1 and temporarily bonded to carrier 2. The temporary bonding film 4 can be made of pyrolytic tape, UV-release tape, etc. The carrier 2 can be selected based on the wavelength transmittance of the temporary bonding film 4, using glass, carrier wafer, etc. The back side of chip 3 refers to the side without pads. This step is the temporary bonding step; steps 2-8 are rewiring steps.
[0057] Step 2: Deposit phenelzine material at room temperature on the temporary bonding film 4 and the chip 3 to form a dielectric layer 5, which is the first dielectric layer 51 in this case. Figure 2 As shown.
[0058] After attachment, the carrier 2 can be placed in a pyrelin vacuum deposition system to deposit pyrelin material covering both the carrier 2 and the chip 3 at room temperature. The deposition thickness can be greater than 10 μm to ensure adequate protection of the chip's sharp corners; or less than 50 μm to facilitate effective removal of the pyrelin material during subsequent reactive ion etching (RIE). Furthermore, if... Figure 3 As shown, after forming the first dielectric layer 51, step 2.1 may be included: performing plasma surface treatment on the carrier plate 2 to increase surface energy, which is beneficial for subsequent metal deposition. Steps 3-5 are metal mask fabrication steps.
[0059] Step 3: Deposit metal on the first dielectric layer 51 to form a first metal layer 6, such as... Figure 4 As shown.
[0060] The carrier plate 2 can be placed in a metal deposition apparatus such as magnetron sputtering or evaporation to deposit a first metal layer 6 on its surface. The first metal layer 6 can be made of a metal that is relatively easy to remove later, such as Cu or Au, and the deposited thickness can be above 500 nm to provide better protection. The first metal layer 6 is used to subsequently fabricate a metal mask for etching the pyrene layer 51.
[0061] Step 4: Coat the first metal layer 6 with photoresist 7 and photolithographically form a window region 8. The window region 8 includes a pad region and a non-chip region, such as... Figure 5 As shown.
[0062] This step involves fabricating a photoresist mask 7 on the surface of the first metal layer 6. The pad area refers to the region corresponding to the pad positions of the chip 3, and the non-chip area refers to the region where the first dielectric layer 51 (or the first metal layer 6) is not used to cover the chip 3. To ensure that the first dielectric layer 51 remains on the sidewalls of the chip 3 after etching to cover the sides of the chip 3, the width of the non-chip area between two adjacent chips 3 can be slightly smaller than the chip spacing.
[0063] Step 5: Remove the portion of the first metal layer 6 corresponding to the windowed area 8; remove the photoresist 7 to obtain the metal mask 61, as shown below. Figure 6-7 As shown.
[0064] The removal of the first metal layer 6 corresponding to the windowed area 8 can be achieved using chemical etching or electrochemical etching processes.
[0065] Step 6: Etch the first dielectric layer 51 according to the metal mask 61 to expose the chip 3 pads, such as... Figure 8 As shown.
[0066] The etching process can employ reactive ion etching (RIE). Specifically, a small amount of SiF4 or similar gas can be introduced into an oxygen atmosphere to assist etching. During this process, the pyrite in the area containing the metal mask 61 is protected, while the pyrite in the chip 3 pads and non-chip areas is etched away. The RIE power and time should be appropriately adjusted to reduce the heat accumulation effect and the impact of thermal stress by using low power, short time, and step-by-step etching. The RIE process ends when the metal portion of the chip 3 pads is exposed.
[0067] Step 7: Remove the metal mask 61 on the first dielectric layer 51, such as... Figure 8-9 As shown.
[0068] The metal mask 61 can be removed by chemical corrosion or electrochemical corrosion processes.
[0069] Step 8: Fabricate a redistribution layer 9 on the pads of the chip 3, here it is the first redistribution layer 91, as shown. Figure 10 As shown.
[0070] The first redistribution layer 91 can be obtained by depositing metal on the chip 3 and etching the metal. Specifically, the first redistribution layer 91 can consist of a seed layer and an electroplating layer. The seed layer can be prepared by sputtering, with the thickness of the lower metal layer being approximately 150 nm and the thickness of the upper metal layer being approximately 350 nm. The seed layer can be Ti / Cu, or TiW / Cu, Cr / Au, or Ti / TiW / Cu, etc. The electroplating layer can be Cu, Cr, or Au, generally Cu electroplating. The electroplating system selected for the copper electroplating layer can be a conventional copper sulfate electroplating system, for example, the thickness of the electroplated metallic copper can be approximately 8 μm. In addition, the redistribution layer 91 can be more than one layer, and more than two layers can be set; for example, if the steps 2-8 are repeated, a second redistribution layer can be obtained. Specifically, as... Figure 11 As shown, the process of obtaining the second redistribution layer may further include the following steps after step 8:
[0071] Step 8.1: Deposit pyrene at room temperature on the first redistribution layer 91 to form a second dielectric layer 52.
[0072] The carrier plate 2 can be placed in a pyrelin vacuum deposition system, and pyrelin material can be deposited at room temperature to cover the carrier plate 2 and the chip 3. Furthermore, after forming the second dielectric layer 52, the carrier plate 2 can be removed and subjected to plasma treatment to increase its surface energy, facilitating subsequent metal deposition. Steps 8.2-8.4 describe the metal mask fabrication steps.
[0073] Step 8.2: Deposit metal on the second dielectric layer 52 to form a second metal layer.
[0074] The second metal layer is used to subsequently fabricate a metal mask for etching the pyrene layer 52. The fabrication method of the second metal layer can be the same as that in step 3 described above.
[0075] Step 8.3: Coat the second metal layer with photoresist and photolithographically form a window area, the window area including a pad area and a non-chip area.
[0076] This step involves fabricating a photoresist mask on the surface of the second metal layer. The pad area refers to the region corresponding to the pad positions of chip 3, and the non-chip area refers to the region where the second dielectric layer 52 (or the second metal layer) is not used to cover chip 3. The non-chip area may correspond to the non-chip area described in step 4 above.
[0077] Step 8.4: Remove the portion of the second metal layer corresponding to the windowed area and remove the photoresist to form a metal mask.
[0078] Step 8.5: Etch the second dielectric layer 52 to expose the pads of the first redistribution layer 91.
[0079] The pad refers to the corresponding pad area on the first redistribution layer 91.
[0080] Step 8.6: Remove the metal mask.
[0081] Step 8.7: Fabricate a second routing layer 92 on the pads of the first routing layer 91.
[0082] The second redistribution layer 92 can be obtained by depositing metal on the pads and etching it, specifically referring to the preparation method of the first redistribution layer in step 8. Similarly, to create more redistribution layers 9, steps 8.1 to 8.7 can be repeated.
[0083] Step 9: Fabricate solder balls 10 on the pads of the redistribution layer 9, such as... Figure 12 As shown.
[0084] If this step follows step 8, the pads correspond to the pads of the first redistribution layer 91; if it follows step 8.7, the pads correspond to the pads of the second redistribution layer 92. This step is the solder ball fabrication step; the debonding step will follow.
[0085] Step 10: Remove the carrier board 2 to obtain the chip packaging structure.
[0086] The removal of the carrier plate 2 may include the following steps:
[0087] Step 10.1: Attach the front side of the carrier plate 2 to the protective film 11, as follows: Figure 13 As shown.
[0088] The protective film 11 should match the height and size of the solder ball 10, and the protective film 11 should cover the solder ball 10. The protective film can be a blue film or a UV film, etc.
[0089] Step 10.2: Release the temporarily bonded carrier through a debonding process, leaving the chip on the protective film.
[0090] The debonding process can be selected according to the type of temporary bonded film, such as UV irradiation debonding or laser peeling.
[0091] Step 10.3: Bond chip 3 onto the ring-cut adhesive tape 12, and peel off the protective film 11 on the front side of chip 3 using a film peeling device, as shown. Figure 13-14 As shown, the chip packaging structure is obtained.
[0092] At this point, chip 3 is facing upwards, exposing solder balls 10, which can be used for subsequent flip-chip bonding and other processes.
[0093] This embodiment of the anti-warpage packaging method utilizes phenelzine material to optimize existing wafer-level packaging processes. By replacing the existing RDL dielectric material with phenelzine, the impact of warpage and breakage caused by high-temperature processes involving epoxy resin and polyimide in wafer-level packaging can be effectively reduced. It also enables in-hole protection in multilayer circuits, reducing the formation of adhesive buildup and bubbles within the holes. Furthermore, phenelzine patterning is achieved using RIE etching. The entire process does not involve non-standard processes or equipment and can utilize existing mature systems. This method can be applied not only to wafer-level packaging but also to board-level packaging.
[0094] Secondly, the chip packaging structure includes:
[0095] The chip, and a dielectric layer and a redistribution layer located on the chip, wherein the dielectric layer is made of pyrene material.
[0096] Parylene, a novel conformal coating material developed and applied in the mid-1960s, is a general term for polymers of para-xylene. Based on different molecular structures, it can be classified into various types, including N-type, C-type, D-type, and HT-type. Parylene thin film coatings prepared by room temperature deposition are uniform in thickness, dense and pinhole-free, transparent and stress-free, additive-free, do not damage the workpiece, and have excellent electrical insulation and protective properties. They are currently the most effective moisture-proof, mildew-proof, corrosion-proof, and salt spray-proof coating materials. In existing technologies, parylene is mainly used in the encapsulation and protection of devices.
[0097] In existing RDL processes, the dielectric layer is typically fabricated using materials such as epoxy resin or polyimide. These materials require high-temperature processing, which can lead to device warping or breakage due to the mismatch in thermal expansion coefficients between silicon and the dielectric layer material. The inventors of this application discovered that using phenelzine material to fabricate the dielectric layer allows for vacuum deposition at room temperature, eliminating the need for high-temperature processing. This effectively solves the warping and breakage problems in wafer packaging, reduces process complexity, and improves yield. Furthermore, phenelzine's excellent material properties provide excellent insulation and water / oxygen barrier functions. It also demonstrates the feasibility of multi-layer phenelzine deposition, and the phenelzine deposition method allows for better coverage within the vias. The vacuum deposition method for phenelzine material at room temperature is prior art and will not be elaborated upon here.
[0098] In one embodiment, the dielectric layer also covers the sides of the chip.
[0099] Among them, Parylene deposition can better protect the fragile sidewalls of the chip and encapsulate them according to their shape, providing better protection without increasing the area.
[0100] In one embodiment, the dielectric layer is fabricated using a metal mask and reactive ion etching method.
[0101] The process involves using a metal mask combined with RIE etching to complete the patterning of the P-ring. The entire process does not involve non-standard processes or equipment and can utilize existing mature systems.
[0102] Thirdly, electronic devices, including chip packaging structures as described in any embodiment of the second aspect.
[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0104] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.
Claims
1. A warp-resistant packaging method, characterized in that, include: Temporary bonding step: Provide a chip and a carrier board, and temporarily bond the chip to the carrier board; Rerouting step: A dielectric layer and a rerouting layer are fabricated on the chip, wherein the dielectric layer is made of pyrene material; Debonding step: Remove the carrier plate; The rerouting step includes at least one iteration of the following steps: A perylene layer is deposited at room temperature on the side of the carrier plate where the chip is bonded to form the dielectric layer; A metal mask is fabricated on the dielectric layer; The dielectric layer is etched to expose the pads of the chip; Remove the metal mask; The redistribution layer is fabricated on the pads and the dielectric layer; The process of fabricating a metal mask on the dielectric layer includes: Deposit metal on the dielectric layer to form a metal layer; Photoresist is coated on the metal layer, and a window area is formed by photolithography. The window area includes a pad area and a non-chip area. The portion of the metal layer corresponding to the windowed area and the photoresist are removed to form the metal mask; The width of the non-chip area between two adjacent chips is slightly smaller than the distance between the two chips.
2. The anti-warping packaging method as described in claim 1, characterized in that, After the rewiring step and before the debonding step, the method further includes: Solder ball fabrication steps: Fabricate solder balls on the pads of the redistribution layer.
3. The anti-warping packaging method as described in claim 1, characterized in that: After depositing a paraffin layer at room temperature on one side of the carrier substrate where the chip is bonded to form a dielectric layer, and before fabricating a metal mask on the dielectric layer, the process further includes: The carrier plate is subjected to plasma surface treatment.
4. The anti-warping packaging method as described in claim 1, characterized in that: The etching of the dielectric layer is performed using reactive ion etching.
5. The anti-warping packaging method as described in claim 1, characterized in that: The debonding step includes: Attach the front of the carrier plate to the protective film; The temporarily bonded carrier is released through a debonding process, leaving the chip on the protective film; The back side of the chip is bonded to the cutting tape, and the protective film on the front side of the chip is removed.
6. A chip packaging structure, characterized in that, It is prepared using the anti-warping encapsulation method as described in any one of claims 1 to 5.
7. An electronic device, characterized in that, Includes the chip packaging structure as described in claim 6.