Semiconductor manufacturing apparatus

Abstract

According to this embodiment, a semiconductor manufacturing apparatus includes a stage capable of holding a wiring substrate. A tool presses the wiring substrate and a semiconductor chip between itself and the stage. The tool includes a main body having a holding surface for holding the semiconductor chip. A first protrusion is provided along the outer edge of the holding surface and protrudes from the holding surface onto the stage. A second protrusion is provided along the outer edge of the holding surface at a position further outward than the first protrusion and protrudes from the holding surface onto the stage. A groove is provided between the first and second protrusions.

Description

[0001] Related applications

[0002] This application is based on and claims the benefit of priority derived from Japanese Patent Application No. 2021-040446, filed on March 12, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This embodiment relates to a semiconductor manufacturing apparatus. Background Technology

[0004] A bonding apparatus is used to connect multiple flip-chip semiconductor chips. The bonding apparatus mounts the semiconductor chips on a wiring substrate, surrounds the semiconductor chips using a mounting (bonding) tool, and applies pressure to the wiring substrate while heating the semiconductor chips. This connects the electrode bumps of the semiconductor chips to the pads (lead electrodes) of the wiring substrate. Simultaneously, the space between the semiconductor chips and the wiring substrate is filled with resin (such as NCF underfill material), sealing the semiconductor chips onto the wiring substrate with resin.

[0005] However, the height of the mounting tool relative to the wiring substrate depends on the volume of the resin, which can cause deviations in the height of the semiconductor chip relative to the wiring substrate. These deviations in the height of the semiconductor chip can lead to deviations in the thickness of the semiconductor package.

[0006] Furthermore, when sealing semiconductor chips with resin, air bubbles generated within the resin sometimes remain trapped without a release point. These bubbles can cause steam explosions during subsequent reflow soldering processes, becoming a leakage path and compromising reliability. Summary of the Invention

[0007] In one embodiment, a semiconductor manufacturing apparatus is provided that can suppress height deviation of the semiconductor chip relative to the wiring substrate and the generation of bubbles inside the underfill, thereby manufacturing a highly reliable semiconductor device.

[0008] According to this embodiment, a semiconductor manufacturing apparatus includes a stage capable of holding a wiring substrate. A bonding tool presses the wiring substrate and a semiconductor chip between itself and the stage. The bonding tool includes a main body having a holding surface for holding the semiconductor chip. A first protrusion is provided along the outer edge of the holding surface and protrudes from the holding surface onto the stage. A second protrusion is provided along the outer edge of the holding surface at a position further outward than the first protrusion and protrudes from the holding surface onto the stage. A groove is provided between the first and second protrusions.

[0009] Based on the above structure, a semiconductor manufacturing apparatus can be provided that can suppress the height deviation of the semiconductor chip relative to the wiring substrate and the generation of bubbles inside the bottom filler, and manufacture a semiconductor device with high reliability. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional view showing a structural example of the coupling device in the first embodiment.

[0011] Figure 2 This is a top view showing a structural example of a joining tool.

[0012] Figure 3 This is a cross-sectional view showing a bonding tool pressing a semiconductor chip onto a wiring substrate.

[0013] Figure 4 This is a top view showing a bonding tool pressing a semiconductor chip onto a wiring substrate.

[0014] Figure 5 This is a schematic cross-sectional view showing a structural example of the joining device in the second embodiment.

[0015] Figure 6 This is a schematic top view showing a structural example of the joining device in the second embodiment.

[0016] Figure 7 This is a schematic top view showing a structural example of a modified coupling device.

[0017] Figure 8 It means Figure 3 A top view of the structural example within the dashed box B. Detailed Implementation

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be the same as in reality. In the specification and drawings, elements identical to those described with respect to previously seen drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0019] (First Implementation)

[0020] Figure 1This is a schematic cross-sectional view showing a structural example of the bonding apparatus 1 according to the first embodiment. The bonding apparatus 1, as a semiconductor manufacturing apparatus, includes a worktable 10 and a bonding tool 20. The bonding apparatus 1 mounts a semiconductor chip CHP on a wiring substrate SUB placed on the worktable 10. By applying pressure and heating, the electrodes ELD of the semiconductor chip CHP are electrically connected to the lead electrodes LEL of the wiring substrate SUB via bumps BMP. Furthermore, the pressing direction of the bonding tool 20 (a direction approximately perpendicular to the mounting surface of the worktable 10) is defined as the Z direction. One direction perpendicular to the Z direction is defined as the X direction, and the direction orthogonal to the X direction is defined as the Y direction.

[0021] The worktable 10 is configured to hold the wiring substrate SUB on its surface. The worktable 10 secures the wiring substrate SUB using a vacuum chuck or an electromagnetic chuck. The worktable 10 is made of a metal such as stainless steel. The wiring substrate SUB is a multilayer wiring substrate formed by stacking multiple wiring layers and multiple insulating layers. The wiring layers are made of conductive metals such as copper. The insulating layers are made of insulating materials such as glass epoxy resin. Solder resist RES and lead electrodes LEL are provided on the surface of the wiring substrate SUB. The solder resist RES is disposed around the area of ​​the wiring substrate SUB for connecting semiconductor chip CHP, and contacts at least a portion of the protrusion 22 during bonding.

[0022] The bonding tool 20 includes a main body 21 with a holding surface F20 for holding a semiconductor chip CHP and a protrusion 22 protruding from the holding surface F20 toward the worktable 10 in the Z direction. The bonding tool 20 presses the semiconductor chip CHP held on the holding surface F20 toward the wiring substrate SUB on the worktable 10 in the Z direction. The bonding tool 20 has a heater (not shown) capable of heating the metal bumps BMP and the underfill material UDF. Furthermore, in the semiconductor chip CHP bonding process, either the bonding tool 20 moves toward the worktable 10, or the worktable 10 moves toward the bonding tool 20.

[0023] A through-hole 3c is provided on the holding surface F20 of the bonding tool 20. The through-hole 3c extends from the holding surface F20 through the interior of the bonding tool 20 and connects to a vacuum device (not shown) located outside the tool. Furthermore, the through-hole 3c also penetrates a membrane 24 sandwiched between the semiconductor chip CHP and the holding surface F20, allowing the surface of the semiconductor chip CHP to be adsorbed by vacuuming. That is, the membrane 24 covers the holding surface F20, but has an opening at a position corresponding to the through-hole 3c that communicates with the exterior of the bonding tool 20. Therefore, even if the holding surface F20 of the bonding tool 20 faces vertically, the semiconductor chip CHP can remain adsorbed on the holding surface F20. The membrane 24 is made of an insulating material such as resin. The membrane 24 prevents the underfill material UDF from directly adhering to the bonding tool 20.

[0024] In this way, the bonding tool 20 can hold the semiconductor chip CHP while heating and pressing the holding surface F20 towards the worktable 10 onto the wiring substrate SUB on the worktable 10. The bonding tool 20 can move up and down and left and right relative to the worktable 10 while holding the semiconductor chip CHP. At this time, the metal bump BMP is heated and melted, connecting the electrode ELD and the lead electrode LEL. The metal bump BMP is, for example, a solder material with tin (Sn) as its main component. In addition, the underfill material UDF attached to the semiconductor chip CHP deforms, filling the space between the semiconductor chip and the wiring substrate SUB. The underfill material UDF seals the area around the electrode ELD, the lead electrode LEL, and the metal bump BMP, protecting their connection portions. The underfill material UDF is, for example, an insulating material such as liquid resin (NCP (Non-Conductive Paste)) or film resin (NCF (Non-Conductive Film)).

[0025] Furthermore, the joining tool 20 is disposed around the holding surface F20 and has a protrusion 22 protruding from the holding surface F20 toward the worktable 10. The protrusion 22 includes a first protrusion 22a, a second protrusion 22b, and a groove 22c. The first protrusion 22a is disposed along the outer edge of the holding surface F20 in the XY plane and protrudes from the holding surface F20 toward the worktable 10 in the Z direction. The second protrusion 22b is disposed along the outer edge of the holding surface F20 in the XY plane outside the first protrusion 22a and protrudes from the holding surface F20 toward the worktable 10 in the Z direction. The groove 22c is disposed between the first protrusion 22a and the second protrusion 22b, and when the protrusion 22 is pressed toward the wiring substrate SUB, it can accommodate the bottom filler material UDF that overflows from the holding surface F20 toward the outer side of the first protrusion 22a. The groove 22c is provided along the outer edge of the retaining surface F20 in the XY plane and is recessed in the Z direction corresponding to the protrusions of the first protrusion 22a and the second protrusion 22b. The depth and width of the groove 22c are configured to adequately accommodate the amount of bottom filler material UDF overflowing to the outside of the first protrusion 22a. For example, the depth of the groove 22c can be at the same height as the retaining surface F20. The width of the groove 22c (the distance between the front ends of the first protrusion 22a and the second protrusion 22b) can be approximately 100 μm to 300 μm. The first protrusion 22a and the second protrusion 22b are made of a material with a lower elastic modulus than that of the main body 21 of the engagement tool 20. For example, the main body 21 is made of a metal material such as stainless steel, while the first protrusion 22a and the second protrusion 22b can be made of a resin material such as rubber. Therefore, even if the first protrusion 22a and the second protrusion 22b come into contact with the wiring substrate SUB, damage to the wiring substrate SUB can be suppressed.

[0026] The bonding tool 20 presses the semiconductor chip CHP onto the wiring substrate SUB until the bumps BMP of the semiconductor chip CHP contact the lead electrodes LEL and at least a portion of the protrusion 22 contacts the wiring substrate SUB. When the protrusion 22 contacts the wiring substrate SUB, the main body 21, the protrusion 22, and the wiring substrate SUB form a space to accommodate the semiconductor chip CHP. An underfill material UDF is pre-attached or coated onto the semiconductor chip CHP, and the underfill material UDF fills the space formed by the bonding tool 20 and the wiring substrate SUB. Simultaneously, the underfill material UDF overflows from the space to the outside of the first protrusion 22a and is contained in the groove 22c.

[0027] Through holes 3a, 3b, and 3c are provided on the bonding tool 20. Through hole 3a is provided on the outer side of the holding surface F20 and the protrusion 22, adsorbing the film 24. Through hole 3b is provided in a manner that communicates with the groove 22c between the first protrusion 22a and the second protrusion 22b, adsorbing the film 24. Through hole 3c is provided in a manner that communicates with the holding surface F20 as described above, and the semiconductor chip CHP is adsorbed through the holes provided in the film 24.

[0028] Figure 2 This is a top view showing a structural example of the joining tool 20. Figure 2 The image also shows a semiconductor chip CHP held on the holding surface F20 of the bonding tool 20. Figure 1 Indicates along Figure 2 The cross section of the BB line.

[0029] like Figure 2 As shown, the protrusion 22 is provided along the outer edge of the holding surface F20, i.e., the outer edge of the semiconductor chip CHP. A first protrusion 22a is provided along the outer edge of the holding surface F20, and a portion thereof has a cutout 23a serving as a first cutout. Cutouts 23a are provided at approximately equal intervals along the outer edge of the holding surface F20 in the first protrusion 22a. The cutouts 23a are formed lower than the first protrusions 22a in other areas, with reference to the holding surface F20. Therefore, when the first protrusion 22a contacts the wiring substrate SUB, a gap Ga is formed between the cutout 23a and the wiring substrate SUB. The gap Ga communicates with the outside of the space housing the semiconductor chip CHP formed by the bonding tool 20 and the wiring substrate SUB in the XY plane.

[0030] The second protrusion 22b is provided along the outer edge of the holding surface F20, and a portion thereof has a cutout 23b serving as a second cutout. The cutouts 23b are provided at approximately equal intervals along the outer edge of the holding surface F20 in the second protrusion 22b. The cutouts 23b are formed lower than the second protrusions 22b in other areas, with reference to the holding surface F20. Therefore, when the second protrusion 22b contacts the wiring substrate SUB, a gap Gb is formed between the cutout 23b and the wiring substrate SUB. This gap Gb connects the groove 22c between the first protrusion 22a and the second protrusion 22b to its outside.

[0031] Figure 3 This is a cross-sectional view showing the state in which the bonding tool 20 presses the semiconductor chip CHP onto the wiring substrate SUB. Figure 4 This is a top view showing the state in which the bonding tool 20 presses the semiconductor chip CHP onto the wiring substrate SUB. Figure 3 Along Figure 4 The cross-section of the BB line corresponds to this. Figure 4In the image, the location of the semiconductor chip CHP is represented by a virtual line.

[0032] exist Figure 1 In this state, the bonding tool 20 heats the semiconductor chip CHP to approximately 100°C to 200°C while moving it toward the wiring substrate SUB. The bonding tool 20 heats and presses the semiconductor chip CHP toward the wiring substrate SUB until the bumps BMP and lead electrodes LEL contact and the protrusions 22 contact the solder resist RES of the wiring substrate SUB.

[0033] Next, the temperature of the bonding tool 20 is raised above the melting temperature of the metal bump BMP. As a result, the bump BMP melts, connecting the electrode ELD and the lead electrode LEL, and the underfill material UDF deforms, sealing the semiconductor chip CHP, the electrode ELD, the lead electrode LEL, and the bump BMP. The underfill material UDF fills the space surrounded by the main body 21, the protrusion 22, and the wiring substrate SUB of the bonding tool 20. Furthermore, the remaining underfill material UDF overflows from the gap Ga between the cutout 23a of the first protrusion 22a and the solder resist RES of the wiring substrate SUB. Thus, the underfill material UDF accumulates in the groove 22c. The gap Ga functions as a vent (exhaust port) when the underfill material UDF is filled into the space, and also as an outlet hole for the underfill material UDF. At this time, the gap Gb between the cutout 23b of the second protrusion 22b and the solder resist RES of the wiring substrate SUB functions as a vent, allowing air to escape from the groove 22c so that the underfill material UDF can accumulate smoothly in the groove 22c. As a result, air bubbles generated inside the underfill material UDF move from the cutout 23a to the groove 22c due to the pressure difference between the space on the semiconductor chip CHP side and the groove 22c, and are then expelled from the space on the semiconductor chip CHP side after passing through the cutout 23b. This suppresses the formation of water vapor explosions and leakage paths during the reflow soldering process. This improves the reliability of the semiconductor package.

[0034] The volume of the underfill material UDF attached or coated to the semiconductor chip CHP is greater than Figure 3The volume shown is the first space obtained by removing the volume of structures other than the underfill material UDF (e.g., semiconductor chip CHP, electrode ELD, bump BMP, lead electrode LEL, etc.) located within the space surrounded by the main body 21, the protrusion 22, and the wiring substrate SUB. Therefore, when the bonding tool 20 presses the semiconductor chip CHP onto the wiring substrate SUB, the underfill material UDF can fill the first space. Furthermore, the volume of the underfill material UDF is preferably smaller than the volume obtained by adding the first space to the second space surrounded by the groove 22c and the solder resist RES of the wiring substrate SUB. Therefore, the underfill material UDF can adequately seal the semiconductor chip CHP, electrode ELD, bump BMP, and lead electrode LEL, and can prevent excess underfill material UDF from leaking outwards from the second protrusion 22b. Additionally, it saves on underfill material UDF.

[0035] The electrode ELD and the lead electrode LEL are connected via metal bumps BMP. When the bottom filler material UDF reaches a removable curing degree, the pressure and heating action of the bonding tool 20 is released, causing the bonding tool 20 to rise and remove the product.

[0036] Alternatively, the first protrusion 22a can be integrally formed as part of the joining tool 20, or it can be a separate part and fixed to the joining tool 20 using bolts or adhesives.

[0037] Furthermore, by setting groove 22c, deviations in the volume of the underfill material UDF are absorbed. Therefore, even if there is a deviation in the volume of the space formed by groove 22c and solder resist RES, the underfill material UDF can stably seal the semiconductor chip CHP, electrode ELD, bump BMP, and lead electrode LEL.

[0038] Incisions 23a and 23b can also be made as follows: Figure 4 As shown, when viewed from the Z direction, the cutouts are staggered (by half a distance) along the outer edge of the retaining surface F20 in the X or Y direction. The cutouts 23a and 23b are also staggered when viewed from the X or Y direction. In this case, the cutouts 23a and 23b are not connected when viewed from the X or Y direction. On the other hand, as shown in the reference... Figure 7 As will be described later, the cutouts 23a and 23b can also be arranged at the same spacing along the outer edge of the retaining surface F20 and aligned in the corresponding positions.

[0039] Furthermore, a protrusion 22 is provided on the bonding tool 20, so that when the protrusion 22 contacts the wiring substrate SUB, the bonding tool 20 stops, and the height of the semiconductor chip CHP relative to the wiring substrate SUB is determined. That is, the height of the semiconductor chip CHP relative to the wiring substrate SUB is determined by the height of the protrusion 22. Therefore, even if there is a deviation in the volume of the underfill material UDF attached or coated to the semiconductor chip CHP, the height of the semiconductor chip CHP relative to the wiring substrate SUB remains approximately constant. As a result, the package thickness is stable, and the connection area between the electrode ELD and the lead electrode LEL is stable, improving reliability.

[0040] Furthermore, air bubbles generated inside the bottom filler material UDF can be expelled from the space on the CHP side of the semiconductor chip via the cutout 23b. This suppresses water vapor explosions during the reflow soldering process and inhibits leakage paths.

[0041] (Second Implementation)

[0042] Figure 5 This is a schematic cross-sectional view showing a structural example of the joining device 1 in the second embodiment. Figure 6 This is a schematic top view showing a structural example of the coupling device 1 in the second embodiment. Figure 5 Corresponding to Figure 6 The cross-section along line BB. Additionally... Figure 5 as well as Figure 6 This illustrates the situation where the bonding tool 20 has pressed the semiconductor chip CHP onto the wiring substrate SUB. Additionally, in Figure 6 In the image, the location of the semiconductor chip CHP is represented by a virtual line.

[0043] In the second embodiment, the second protrusion 22b bends outward (radially) from the center of the holding surface F20 toward the outer edge as it approaches the worktable 10. That is, as... Figure 5 As shown, the second protrusion 22b is a plate-shaped member with an extended end. Furthermore, in the first protrusion 22a, similar to the first embodiment, a material such as resin with a lower elastic modulus than the main body 21 is used. The first protrusion 22a is separately provided from the main body 21 and can be fixed to the joining tool 20 by means of, for example, bolts or adhesives.

[0044] The second protrusion 22b is made of a material with a higher elastic modulus than the first protrusion 22a. The second protrusion 22b is separate from the joining tool 20. For example, the second protrusion 22b can be a plate-shaped component made of the same material as the joining tool 20 (e.g., a metal material such as stainless steel). The second protrusion 22b presses the bottom filling material UDF laterally with a pressure, for example, less than 10% of the pressure applied by the joining tool 20. Thus, the pressure applied by the joining tool 20 can be applied to the bottom filling material UDF, further promoting the removal of air bubbles.

[0045] The bonding tool 20 stops when the second protrusion 22b contacts the wiring substrate SUB. The second protrusion 22b slightly flexes and presses the underfill material UDF laterally with the aforementioned pressure. By applying pressure from the bonding tool 20 and the second protrusion 22b to the underfill material UDF, air bubbles are expelled. This suppresses steam explosions during the reflow soldering process.

[0046] When the second protrusion 22b contacts the wiring substrate SUB, the main body 21, the second protrusion 22b, and the wiring substrate SUB form a space for accommodating the semiconductor chip CHP. At this time, the first protrusion 22a is set at a height that does not contact the wiring substrate SUB. The height of the semiconductor chip CHP relative to the wiring substrate SUB is determined by the position of the front end of the second protrusion 22b. The first protrusion 22a has the function of defining the boundary between the semiconductor package and the solder pads. In addition, the surface of the second protrusion 22b is covered by a film 24, so even if the second protrusion 22b contacts the solder resist RES, damage to the solder resist RES can be suppressed.

[0047] Other structures in the second embodiment can be the same as the corresponding structures in the first embodiment. Therefore, the second embodiment can further achieve the same effects as the first embodiment.

[0048] (Modified example)

[0049] Figure 7 This is a schematic top view illustrating a structural example of the coupling device 1 in a modified embodiment. In the first and second embodiments, the cutouts 23a and 23b are as follows... Figure 2 , Figure 4 as well as Figure 6 As shown, they are staggered (by half a spacing) along the outer edge of the retaining surface F20. However, the cutouts 23a and 23b can also be arranged as follows: Figure 7As shown, when viewed from the Z direction, the edges of the outer edge of the retaining surface F20 are arranged at approximately the same spacing in the X or Y direction and are aligned. In this case, when viewed from the X or Y direction, the cutouts 23a and 23b are aligned with each other and communicate from the outside to the space housing the semiconductor chip CHP. Even with this structure, the effectiveness of this embodiment is not lost.

[0050] Figure 8 It means Figure 3 A top view of the structural example within the dashed box B. Figure 8 With Figure 3 The structures are represented by a size ratio that is closer to the actual dimensions. The first protrusion 22a and the second protrusion 22b are formed in such a way that they extend in the X direction (the direction of communication between the space containing the semiconductor chip CHP and the outside of that space) as a width.

[0051] The height (width in the Z direction) of gap Ga is greater than the height of gap Gb. Furthermore, the height of gap Ga is... Figure 8 The gap Ga is indicated by a dashed line. Therefore, the gap Ga functions as both a vent (exhaust port) and an outlet for the bottom filling material UDF. Additionally, the gap Gb prevents leakage of the bottom filling material UDF to the outside and also functions as a vent (exhaust port).

[0052] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor manufacturing apparatus, comprising: A worktable capable of holding the wiring board; and A tool that holds a semiconductor chip, pressing the wiring substrate and the semiconductor chip between itself and the worktable. The tool has the following features: The main body has a holding surface for holding the semiconductor chip; A first protrusion is provided along the outer edge of the retaining surface and protrudes from the retaining surface onto the worktable; The second protrusion is disposed along the outer edge of the retaining surface at a position further outward than the first protrusion, and protrudes from the retaining surface onto the worktable; as well as A groove is provided between the first protrusion and the second protrusion. The first protrusion has a first incision in one portion, and the second protrusion has a second incision in one portion. The amount of the first cut in the direction perpendicular to the holding surface, i.e., the first cut amount, is greater than the amount of the second cut in the direction perpendicular to the holding surface, i.e., the second cut amount.

2. The semiconductor manufacturing apparatus as claimed in claim 1, wherein, The tool is capable of pressing the semiconductor chip against the wiring substrate until at least a portion of the first protrusion or the second protrusion contacts the wiring substrate.

3. The semiconductor manufacturing apparatus as claimed in claim 1, wherein, When the first protrusion or the second protrusion comes into contact with the wiring substrate, the main body, the first protrusion or the second protrusion, and the wiring substrate can form a space surrounding the semiconductor chip, and resin can be filled in the space.

4. The semiconductor manufacturing apparatus as claimed in claim 3, wherein, When the first protrusion or the second protrusion is pressed onto the wiring substrate, the groove can contain the resin overflowing from the space.

5. The semiconductor manufacturing apparatus as claimed in claim 1, wherein, When the main body is cut off with a section perpendicular to the main body and observed, The first cut and the second cut are shown simultaneously.

6. The semiconductor manufacturing apparatus according to any one of claims 1 to 5, wherein, The first protrusion and the second protrusion are made of a material with a lower elastic modulus than the main body.

7. The semiconductor manufacturing apparatus according to any one of claims 1 to 5, wherein, The second protrusion bends from the center of the retaining surface toward the outer edge as it approaches the worktable from the retaining surface.

8. The semiconductor manufacturing apparatus according to any one of claims 1 to 5, wherein, The second protrusion is made of a material with a higher elastic modulus than the first protrusion.

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