A semiconductor processing system

CN115083943BActive Publication Date: 2026-09-25INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD +1
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Patent Information

Application Number
CN202110267663.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-03-11
Publication Date
2026-09-25
Estimated Expiration
2041-03-11

AI Technical Summary

Technical Problem

在刻蚀完毕后,此类反应气体会残留在晶圆的表面,当刻蚀后的晶圆与刻蚀前的晶圆放置在同一空间内,会使刻蚀前的晶圆与刻蚀后的晶圆出现交叉污染的情况

Benefits of technology

[0006]与现有技术相比,本发明提供的半导体处理系统,包括:控制器及与控制器通信的处理腔室、设备前端模块、位于设备前端模块内的第一缓冲腔室及第二缓冲腔室,第一缓冲腔室及第二缓冲腔室均与处理腔室连通。其中,设备前端模块用于对晶圆进行上下料,第一缓冲腔室及第二缓冲腔室均用于对晶圆进行清洁。

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Abstract

The application discloses a semiconductor processing system, relates to the technical field of semiconductor processing, and is used for placing a wafer before processing and a wafer after processing in different spaces and removing residual gas on the surface of the wafer before processing and the wafer after processing. The semiconductor processing system comprises a controller and a processing chamber, a vacuum transmission chamber, an equipment front end module, a first buffer chamber and a second buffer chamber in the equipment front end module in communication with the controller. The first buffer chamber and the second buffer chamber are in communication with the processing chamber. The controller is used for controlling the equipment front end module to load and unload the wafer and controlling the processing chamber to process the wafer. The controller is further used for controlling the first buffer chamber to clean the wafer before the wafer enters the processing chamber and controlling the second buffer chamber to clean the wafer after the wafer leaves the processing chamber.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, and more particularly to a semiconductor processing system. Background Technology

[0002] Currently, most semiconductor process equipment, such as etching equipment, physical vapor deposition equipment, and chemical vapor deposition equipment, requires the transfer of wafers between different chambers.

[0003] In some processes, such as etching, the etching equipment uses reactive gases like HBr, which are corrosive to the wafer surface, to perform plasma etching. After etching, these reactive gases remain on the wafer surface. When the etched wafer is placed in the same space as the unetched wafer, cross-contamination can occur. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor processing system for placing a wafer before processing and a wafer after processing in different spaces, and for removing residual gas from the surfaces of both wafers before and after processing.

[0005] This invention provides a semiconductor processing system, comprising: a controller and a processing chamber communicating with the controller; a device front-end module; and a first buffer chamber and a second buffer chamber located within the device front-end module. Both the first and second buffer chambers are connected to the processing chamber. The controller controls the device front-end module to load and unload wafers and controls the processing chamber to process the wafers. The controller also controls the first buffer chamber to clean the wafers before they enter the processing chamber and controls the second buffer chamber to clean the wafers after they leave the processing chamber.

[0006] Compared with the prior art, the semiconductor processing system provided by the present invention includes: a controller and a processing chamber communicating with the controller, a device front-end module, a first buffer chamber and a second buffer chamber located within the device front-end module, both of which are connected to the processing chamber. The device front-end module is used for loading and unloading wafers, and both the first and second buffer chambers are used for cleaning the wafers.

[0007] During wafer processing using this semiconductor processing system, after the wafer is loaded via the front-end module, it enters the first buffer chamber before being processed in the main processing chamber. The first buffer chamber cleans the wafer, ensuring no residual gas remains on its surface before it enters the main processing chamber, thus preventing contamination. After the wafer undergoes processing within the main processing chamber, the second buffer chamber cleans it again to remove any remaining gas, ensuring the wafer proceeds to the next processing step in a clean state.

[0008] As can be seen from the above usage process, this semiconductor processing system can clean both the pre-processed and post-processed wafers and spatially separate them, effectively solving the problem of cross-contamination between the pre-processed and post-processed wafers. Furthermore, the first and second buffer chambers are located within the front-end module of the equipment, simplifying auxiliary equipment and reducing initial equipment costs and subsequent maintenance costs. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0010] Figure 1 This is a schematic diagram of the structure of a semiconductor processing system provided in an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of the structure of the first buffer chamber provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0013] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0014] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0015] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0016] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0017] In semiconductor manufacturing processes, such as semiconductor etching, a certain amount of process gases remain on the surface of the wafer after processing in the processing chamber. If these process gases remain on the wafer surface for a long time, they will inevitably lead to defects in the wafer.

[0018] In existing technologies, ashing, resist removal, or wet cleaning processes are used to remove residual process gases from the wafer surface, performing secondary processing on the etched wafer. However, since the wafers before and after etching are in the same space, cross-contamination can occur.

[0019] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor processing system. Figure 1 A schematic diagram of the semiconductor processing system provided in an embodiment of the present invention is illustrated. (Refer to...) Figure 1 The semiconductor processing system includes: a controller and a processing chamber 1 communicating with the controller, a device front-end module 2, and a first buffer chamber 3 and a second buffer chamber 4 located within the device front-end module 2. Both the first buffer chamber 3 and the second buffer chamber 4 are connected to the processing chamber 1.

[0020] The controller is used to control the front-end module 2 of the equipment to load and unload wafers, and to control the processing chamber 1 to process the wafers. The controller is also used to control the first buffer chamber 3 to clean the wafers before they enter the processing chamber 1, and to control the second buffer chamber 4 to clean the wafers after they leave the processing chamber 1.

[0021] Compared to existing technologies, in the wafer processing process using this semiconductor processing system, after the wafer is loaded by the front-end module 2, it enters the first buffer chamber 3 before being processed in the processing chamber 1. The first buffer chamber 3 cleans the wafer, ensuring that there is no residual gas on the surface of the wafer entering the processing chamber 1, thus guaranteeing that the wafer is not contaminated in the processing chamber 1. After the wafer undergoes processing in the processing chamber 1, the second buffer chamber 4 cleans the processed wafer to remove any residual gas from its surface, ensuring that the wafer entering the next process flow is in a clean state.

[0022] As can be seen from the above usage process, this semiconductor processing system can clean both the wafers before and after processing, and spatially separate the wafers before and after processing, effectively solving the problem of cross-contamination between the wafers before and after processing. Meanwhile, the first buffer chamber 3 and the second buffer chamber 4 are located within the front-end module 2 of the equipment, simplifying auxiliary equipment and reducing initial equipment costs and subsequent maintenance costs.

[0023] In practical applications, after the unprocessed wafer transfer box is loaded into loading port 7, the controller controls the front-end module 2 of the equipment to feed the unprocessed wafers. After the processed wafers are cleaned in the second buffer chamber 4, the controller controls the front-end module 2 of the equipment to unload the processed wafers.

[0024] In one example, refer to Figure 1 The aforementioned semiconductor processing system may further include a vacuum transfer chamber 5 and a loading and locking chamber 6. The vacuum transfer chamber 5 is connected to the first buffer chamber 3 and the second buffer chamber 4 via the loading and locking chamber 6. The vacuum transfer chamber 5 is used to transfer the wafer between the first buffer chamber 3 and the processing chamber 1, or between the second buffer chamber 4 and the processing chamber 1, under vacuum conditions. The loading and locking chamber 6 is used to balance the gas pressure between the vacuum transfer chamber 5 and the first buffer chamber 3, or between the vacuum transfer chamber 5 and the second buffer chamber 4.

[0025] In practical applications, refer to Figure 1The aforementioned semiconductor processing system may include a first loading locking chamber and a second loading locking chamber, wherein the first loading locking chamber has a first loading locking module and the second loading locking chamber has a second loading locking module. The first loading locking chamber is connected to a first buffer chamber 3, and the second loading locking chamber is connected to a second buffer chamber 4.

[0026] When the wafer is transferred from the first buffer chamber 3 to the first loading and locking chamber, the first loading and locking module converts the gas pressure in the first loading and locking chamber from atmospheric pressure to vacuum pressure. When the wafer is transferred from the vacuum transfer chamber 5 to the second loading and locking chamber, the second loading and locking module converts the gas pressure in the second loading and locking chamber from vacuum pressure to atmospheric pressure.

[0027] Reference Figure 1 The controller mentioned above can be a controller in a general sense, used to control the working status of the first buffer chamber 3, the second buffer chamber 4, the equipment front-end module 2 and the processing chamber 1.

[0028] Reference Figure 1 The aforementioned processing chamber 1 may include multiple chambers. For example, processing chamber 1 may include four chambers. Processing chamber 1 may be an etching processing chamber 1, but is not limited to this.

[0029] Reference Figure 1 The aforementioned front-end module 2 can load and unload multiple wafers at once, improving work efficiency. The first buffer chamber 3 and the second buffer chamber 4 are located within the front-end module 2, which simplifies auxiliary equipment and reduces wafer transportation costs.

[0030] Figure 2 A schematic diagram of the structure of the first buffer chamber 3 provided in an embodiment of the present invention is shown. It should be noted that the first buffer chamber 3 and the second buffer chamber 4 have the same structure. The following description uses the first buffer chamber 3 as an example.

[0031] Reference Figure 2 Each of the aforementioned first buffer chambers 3 may be equipped with a gas purging device 31. The gas purging device 31 has a cleaning station for holding wafers, and the gas purging device 31 is used to purge the wafers on the cleaning station with gas.

[0032] In practical use, the aforementioned semiconductor processing system also includes a gas generating device, and the inlet end of the gas purging device 31 can be connected to the gas generating device. The gas generating device can be used to supply gas to the gas purging device 31, and the gas can be nitrogen or an inert gas, etc., which will not react with the wafer upon contact.

[0033] In one example, refer to Figure 2The aforementioned gas purging device 31 may include multiple gas diffusers 311 communicatively connected to the aforementioned controller. These gas diffusers 311 are used to diffuse the gas entering the first buffer chamber 3 and the second buffer chamber 4 from the gas generating device. The gas diffusers 311 may be located at the inlet end of the gas purging device 31. When the gas generating device supplies gas to the gas purging device 31, the gas diffusers 311 can be used to diffuse the gas generated by the gas generating device into the first buffer chamber 3 and the second buffer chamber 4.

[0034] In one example, refer to Figure 2 The gas purging device 31 may further include an automatic flow regulator 312 that is communicatively connected to the controller. One end of the automatic flow regulator 312 is connected to the gas generating device, and the other end is connected to the gas diffuser 311. The automatic flow regulator 312 can be used to regulate the gas flow rate within the gas purging device 31. The gas flow rate can be controlled within the range of 0.1 LPM to 15 LPM.

[0035] For example, when performing processes with line dimensions below 15nm, after etching, the wafer is transferred from the vacuum transfer chamber 5 to the second buffer chamber 4. At this time, in order to prevent the pattern on the wafer from tilting due to excessive gas flow, the gas flow of the gas purging device 31 needs to be reduced.

[0036] In one example, refer to Figure 2 The gas purging device 31 may also include a throttle valve that is communicatively connected to the controller, and the throttle valve may be located at the outlet end of the gas purging device 31. The throttle valve can be used to regulate the gas pressure within the gas purging device 31.

[0037] Reference Figure 2 To accurately adjust the gas pressure within the gas purging device 31, a pressure gauge connected to the controller can be installed at the outlet of the gas purging device 31 to obtain the gas pressure in real time. When the pressure gauge obtains the gas pressure within the gas purging device 31, it sends the gas pressure to the controller, which compares the gas pressure within the gas purging device 31 with a preset gas pressure. When the gas pressure within the gas purging device 31 is inconsistent with the preset gas pressure, the controller controls the throttle valve to adjust the gas pressure within the gas purging device 31.

[0038] In one example, refer to Figure 2The gas purging device 31 also includes a heater and a temperature sensor that are communicatively connected to the controller. The heater can be located at the inlet of the gas purging device 31 to raise the temperature of the gas entering the gas purging device 31, so as to more quickly remove residual gas from the surface of the wafer. The temperature sensor is located inside the gas purging device 31 to facilitate real-time detection of the gas temperature inside the gas purging device 31 and transmit the gas temperature to the controller so that the controller can adjust the heating temperature of the heater in a timely manner.

[0039] Reference Figure 2 The aforementioned heating assembly may include a heating element and a voltage regulator connected in series in the power supply circuit of the heating element. The voltage regulator is communicatively connected to a controller. During the heating process, the controller controls the voltage regulator to adjust the voltage applied to the heating element.

[0040] In practical applications, according to Joule's law Q = I 2 According to Rt and Ohm's law U=IR, when the resistance R is constant, the larger the voltage U, the larger the current I. Therefore, in the same amount of time, the same resistor will generate more heat.

[0041] The heating element described above can be a thermoelectric element. This thermoelectric element can be made of materials such as bismuth telluride and its alloys, lead telluride and its alloys, or silicon-germanium alloys, but is not limited to these, and the embodiments of the present invention do not impose specific limitations in this regard.

[0042] The heating element described above can be a tropical heating element or a wound heating element, but is not limited to these, and the embodiments of the present invention do not impose specific limitations on this. The heating band type heating element mainly consists of heating materials and insulating materials. The heating material is a nickel-chromium alloy strip, which features rapid heating, high thermal efficiency, and long service life. The insulating material is multi-layered alkali-free glass fiber, which has good temperature resistance and reliable insulation performance. The hot wire type heating element refers to a heating tube with metal heat sinks wound around its surface, which increases the heat dissipation area and accelerates heat dissipation.

[0043] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor processing system, characterized in that, include: The system includes a controller and a processing chamber that communicates with the controller, a device front-end module, a first buffer chamber and a second buffer chamber located within the device front-end module; both the first buffer chamber and the second buffer chamber are connected to the processing chamber. The controller is used to control the front-end module of the equipment to load and unload the wafers, and to control the processing chamber to process the wafers; The controller is also configured to control the first buffer chamber to clean the wafer before the wafer enters the processing chamber, and to control the second buffer chamber to clean the wafer after the wafer leaves the processing chamber; The semiconductor processing system further includes a vacuum transfer chamber and a loading and locking chamber; the vacuum transfer chamber is connected to the first buffer chamber and the second buffer chamber through the loading and locking chamber. The vacuum transfer chamber is used to transfer the wafer between the first buffer chamber and the processing chamber, or between the second buffer chamber and the processing chamber, under vacuum conditions. The loading locking chamber is used to balance the gas pressure between the vacuum transmission chamber and the first buffer chamber, or between the vacuum transmission chamber and the second buffer chamber; Both the first buffer chamber and the second buffer chamber are equipped with gas purging devices, and both the first buffer chamber and the second buffer chamber have cleaning stations for holding the wafers. The gas purging devices are used to purge the wafers at the cleaning stations with gas; and / or, The gas used in the gas purging device is nitrogen or an inert gas; The gas purging device also includes a heating component and a temperature sensor that are communicatively connected to the controller. The heating component is located at the inlet end of the gas purging device and is used to heat the gas blown out by the gas purging device. The temperature sensor is located inside the gas purging device and is used to obtain the gas temperature inside the gas purging device.

2. The semiconductor processing system according to claim 1, characterized in that, The semiconductor processing system also includes a gas generating device, and the gas inlet of the gas purging device is connected to the gas generating device.

3. The semiconductor processing system according to claim 2, characterized in that, The gas purging device includes a plurality of gas diffusers that are communicatively connected to the controller. The plurality of gas diffusers are used to diffuse the gas entering the first buffer chamber and the second buffer chamber from the gas generating device.

4. The semiconductor processing system according to claim 3, characterized in that, The gas purging device also includes an automatic flow regulator that is communicatively connected to the controller. One end of the automatic flow regulator is connected to the gas generating device, and the other end of the automatic flow regulator is connected to the gas diffuser.

5. The semiconductor processing system according to claim 4, characterized in that, The gas flow rate adjustment range of the automatic flow regulator is 0.1 LPM to 15 LPM.

6. The semiconductor processing system according to any one of claims 1 to 4, characterized in that, The gas purging device also includes a throttle valve that is communicatively connected to the controller, and the throttle valve is located at the gas outlet of the gas purging device.

7. The semiconductor processing system according to claim 1, characterized in that, The heating assembly includes: a heating element and a voltage regulator connected in series in the power supply circuit of the heating element, wherein the voltage regulator is communicatively connected to the controller; The controller is used to control the voltage applied to the heating element by the voltage regulator based on a preset temperature and the gas temperature inside the gas purging device obtained by the temperature sensor during the heating process of the heating element; and / or, The heating temperature range of the heating component is 20℃ to 150℃.

Citation Information

Patent Citations

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