Method of manufacturing fin field effect transistor
By using two etching processes and a doped dielectric layer, a damage-free, highly doped anti-penetration layer is formed, which solves the problems of damage and inhomogeneous doping caused by ion implantation and improves the carrier mobility and overall performance of the fin field-effect transistor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2021-03-15
- Publication Date
- 2026-07-14
AI Technical Summary
In the formation of the punch-through barrier layer of existing fin field-effect transistors, damage caused by ion implantation and uneven doping distribution affect the carrier mobility and device performance in the channel region.
The fins are formed by etching in two stages. A non-penetration layer is formed at the bottom of the fins using sacrificial sidewalls and a doped dielectric layer. Solid-phase doping is achieved through a doping-driven process to avoid ion implantation damage and ensure the integrity of the channel layer.
A non-damaging, highly doped anti-penetration layer is formed at the bottom of the channel layer, which improves carrier mobility and enhances the electrical performance of the device.
Smart Images
Figure CN115084025B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a FinField Effect Transistor (FinFET). Background Technology
[0002] With the advancement of semiconductor manufacturing technology, gate widths are continuously shrinking, and traditional planar CMOS devices can no longer meet device requirements, such as controlling short-channel effects. For technology nodes below 20nm, fin field-effect transistor structures offer better electrical performance. Figure 1 The diagram shown is a plan view of the first type of fin field-effect transistor. Figure 2 It is along Figure 1 Cross-sectional view of the dashed line AA; Figure 3 It is along Figure 1 Cross-sectional view with dashed line BB; the first type of fin field-effect transistor includes:
[0003] Fins 2 are formed on a semiconductor substrate such as a silicon substrate 1. The bottom of the fins 2 is isolated by an insulating layer 3, which is typically made of shallow trench field oxide (STI).
[0004] A metal gate (MG) is covered on the top and side surfaces of the fin 2. Typically, a gate dielectric layer 2042 with a high dielectric constant (HK) layer is used to isolate the metal gate and the fin 2 material; the entire gate structure 204 is HKMG. Figure 1 As can be seen from the plan view, fin 2 consists of multiple parallel lines, and the metal grilles also consist of multiple parallel lines, with the length direction of each metal grille perpendicular to the length direction of fin 2. Combined with... Figure 3 As shown in the figure, the gate structure is illustrated by the dashed box 204 below. The gate dielectric layer of the gate structure 204 includes an interface layer 2041, a high dielectric constant layer 2042, and a bottom barrier layer 2043 stacked sequentially. The metal gate of the gate structure 204 includes a work function layer 2044, a top barrier layer 2045, and a metal conductive material layer 4 stacked sequentially. Figure 1 The top view of the structure shows the metal conductive material layer 4. A sidewall 203 is formed on the side of the gate structure 204. A contact etch stop layer (CESL) 201 covers the sidewall 203 and the surface of the silicon substrate 1 and the insulating layer 3 outside the gate structure 204. A zero-layer interlayer film 202 is formed in the spacing region of the gate structure 204.
[0005] Figure 1The image shows an N-type fin field-effect transistor 101 and a P-type fin field-effect transistor 102. The N-type fin field-effect transistor 101 has source and drain regions formed on both sides of its metal gate, and embedded SiP epitaxial layers 5 are formed in the source and drain regions. The P-type fin field-effect transistor 102 has source and drain regions formed on both sides of its metal gate, and embedded SiGe epitaxial layers 6 are formed in the source and drain regions. The embedded SiGe epitaxial layers 6 and the embedded SiP epitaxial layers 5 are formed epitaxially after etching the fin body 2.
[0006] The work function layer 1024 of the N-type fin field-effect transistor 101 is an N-type work function layer. The work function layer 1024 of the P-type fin field-effect transistor 102 is a P-type work function layer.
[0007] Depend on Figure 2 As shown, the fin 2 includes a bottom portion 2a and a top portion 2b, with the bottom portion 2a located within the insulating layer 3. The metal grille covers the top surface and sides of the top portion 2b of the fin 2. Figure 3 As shown, the top portion 2b of the fin 2 covered by the metal grid serves as the channel region 2c. Figure 2 The image shows that the height of the top portion 2b of the fin 2 is h1, and h1 is also the height of the channel region 2c. Figure 3 The height of the channel region 2c is also shown to be h1.
[0008] Figure 3 A cross-sectional view of the N-type fin field-effect transistor 101 is shown. It can be seen that an active region 5a and a drain region 5b are formed on both sides of the gate structure 204, and an embedded SiP epitaxial layer 5 is formed in the active region 5a and the drain region 5b.
[0009] Figure 3 In the diagram, the dashed line CC represents the bottom surface position of the top portion 2b of the fin 2, and the dashed line DD represents the bottom surface position of the bottom portion 2a of the fin 2. It can be seen that the gate structure 204 weakens its control over the bottom region of the dashed line CC corresponding to mark 205. The source region 5a and the drain region 5b easily deplete the bottom region of the dashed line CC corresponding to mark 205, causing the source region 5a and the drain region 5b to connect with the depletion region of the bottom region of the dashed line CC corresponding to mark 205, thus forming a punchthrough. The punchthrough between the source region 5a and the drain region 5b through the depletion region will generate leakage current. Typically, an anti-punchthrough layer (APT) is needed to prevent punchthrough.
[0010] like Figure 4 The diagram shown is a schematic diagram of the structure of the fin in an existing second-fin field-effect transistor with a punch-through layer. Figure 4The image shows a fin 302 and an insulating layer 303 composed of STI. The area between the dashed lines EE and FF represents the top region of the fin 302, and the height h301 of the top region of the fin 302 is the height of the channel region. A penetration-blocking layer 304 is formed at the bottom of the top region of the fin 302. In the prior art, the penetration-blocking layer 304 is typically formed using an ion implantation process. Research has found that the penetration-blocking layer 304 formed by the existing method has the following drawbacks:
[0011] First, ion implantation can cause ion implantation damage, which reduces the carrier mobility in the channel region, thereby reducing device performance.
[0012] Secondly, the doping distribution morphology of the ion implantation-formed anti-penetration layer 304 is shown as marked 304a. It can be seen that the doping of the anti-penetration layer 304 gradually decreases upward and downward from the peak position. During the upward decrease, the tail formed will enter the top region of the fin 302. Since the channel region is formed in the top region of the fin 302, the tail doping of the anti-penetration layer 304 will affect the doping of the channel region, and finally affect the performance of the channel region, such as the threshold voltage and carrier mobility, thereby reducing the device performance. Summary of the Invention
[0013] The technical problem to be solved by the present invention is to provide a method for manufacturing a fin field-effect transistor that can form a damage-free, highly doped anti-penetration layer at the bottom of the channel layer without affecting the carrier mobility of the channel layer.
[0014] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a fin field-effect transistor, comprising the following steps:
[0015] Step 1: Provide a semiconductor substrate, define the fin formation area, and perform a first etching on the semiconductor substrate to form the top portion of the fin; the top portion is further divided into a first segment and a second segment, with the second segment superimposed on top of the first segment.
[0016] The second section serves as the channel layer.
[0017] Step 2: Form a sacrificial sidewall on the side of the second segment, the sacrificial sidewall exposing the side of the first segment.
[0018] Step 3: Form a doped dielectric layer to cover the side of the first segment.
[0019] Step 4: Perform a dopant drive process to diffuse impurities from the doped dielectric layer into the first segment to achieve doping of the first segment. The doped first segment then serves as a punch-through barrier layer.
[0020] Step 5: Remove the doped dielectric layer and the sacrificial sidewall.
[0021] Step 6: Perform a second etching on the semiconductor substrate to form the bottom portion of the fin, and then stack the bottom portion and the top portion to form the fin.
[0022] Step 7: Form a medium isolation layer between the fins, wherein the top surface of the medium isolation layer is located between the top and bottom surfaces of the anti-penetration layer.
[0023] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0024] A further improvement is that the fin field-effect transistor includes N-type fin field-effect transistors and P-type fin field-effect transistors.
[0025] A further improvement is that, in the formation region of the N-type fin field-effect transistor, the doped dielectric layer is a P-type doped dielectric layer, and the anti-penetration layer is a P-type anti-penetration layer.
[0026] A further improvement is that, in step one, the top portion of the N-type fin field-effect transistor formation region is intrinsically doped or P-type doped.
[0027] A further improvement is that the P-type doped dielectric layer is a BSG thin film.
[0028] A further improvement is that, in the formation region of the P-type fin field-effect transistor, the doped dielectric layer is an N-type doped dielectric layer, and the anti-penetration layer is an N-type anti-penetration layer.
[0029] A further improvement is that, in step one, the top portion of the formation region of the P-type fin field-effect transistor is intrinsically doped or N-type doped.
[0030] A further improvement is that the N-type doped dielectric layer is a PSG thin film.
[0031] A further improvement is that step one includes the following sub-steps:
[0032] Step 11: Form a hard mask layer on the surface of the semiconductor substrate.
[0033] Step 12: Form a photoresist pattern that covers the fin formation area and opens up the area outside the fin formation area.
[0034] Step 13: Etch the hard mask layer to transfer the pattern structure of the photoresist pattern into the hard mask layer.
[0035] Step 14: Perform the first etching on the semiconductor substrate using the hard mask layer as a mask.
[0036] The photoresist pattern is removed after the etching of the hard mask layer in step 13 is completed, or after the first etching in step 14 is completed.
[0037] A further improvement is that step two includes the following sub-steps:
[0038] An organic dielectric layer (ODL) is deposited, which fills the spacers between the top portion and has a height equal to the height of the first segment.
[0039] The material layer of the sacrificial sidewall is deposited and etched to form the sacrificial sidewall by self-alignment on the side of the second segment.
[0040] Remove the organic dielectric layer.
[0041] A further improvement is that step three includes the following sub-steps:
[0042] The material layer deposition and etching process for the doped dielectric layer is performed to form the doped dielectric layer by self-alignment on the side of the top portion where the sacrificial sidewall is formed, the doped dielectric layer covering the side of the sacrificial sidewall and the side of the first segment.
[0043] A further improvement is that, in step four, the doping driving process is achieved by thermal annealing, and the process conditions for the doping driving process include: a temperature of 1050°C, a time of 30 seconds, and an oxygen atmosphere.
[0044] A further improvement is that step seven includes the following sub-steps:
[0045] Step 71: The material layer of the deposited medium isolation layer completely fills the gap between the fins and extends over the surface of the fins.
[0046] Step 72: Perform a chemical mechanical polishing process to make the surface of the material layer of the media isolation layer and the surface of the fin flush.
[0047] Step 73: The material layer of the dielectric isolation layer is etched back to form the dielectric isolation layer.
[0048] A further improvement is that, in step 71, a material layer of the dielectric isolation layer is deposited using a flowable chemical vapor deposition (FCVD) process.
[0049] A further improvement is that the top surface of the dielectric isolation layer is located in the middle between the top and bottom surfaces of the anti-penetration layer.
[0050] The fins of this invention are formed by two etching processes. After the first etching, the top portion of the fin is divided into two sections according to the required channel layer and punch-through layer. Then, sacrificial sidewalls are used to cover the side of the second section at the top. In this way, the side of the first section at the bottom can be covered by the doped dielectric layer, and the impurities of the doped dielectric layer can be diffused into the first section to achieve doping of the first section and form the punch-through layer. Therefore, this invention can achieve punch-through layer doping using solid-phase source doping. Compared with ion implantation doping, solid-phase source doping does not generate ion defects and can prevent impurities from diffusing upward into the channel layer. Finally, this invention can form a high-doped punch-through layer at the bottom of the channel layer without damage, without affecting the carrier mobility of the channel layer and achieving high carrier mobility, thereby improving the performance of the device. Attached Figure Description
[0051] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0052] Figure 1 This is a plan view of the first existing fin field-effect transistor;
[0053] Figure 2 It is along Figure 1 Cross-sectional view of the dashed line AA;
[0054] Figure 3 It is along Figure 1 Cross-sectional view of the dashed line BB;
[0055] Figure 4 This is a schematic diagram of the structure of the fin in an existing second-fin field-effect transistor with a punch-through layer;
[0056] Figure 5 This is a flowchart of a method for manufacturing a fin field-effect transistor according to an embodiment of the present invention;
[0057] Figures 6A-6I This is a schematic diagram of the device structure in each step of the manufacturing method of the fin field-effect transistor according to an embodiment of the present invention. Detailed Implementation
[0058] like Figure 5 The diagram shown is a flowchart of a method for manufacturing a finned field-effect transistor according to an embodiment of the present invention; as shown... Figures 6A to 6I The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the fin field-effect transistor according to an embodiment of the present invention. The manufacturing method of the fin field-effect transistor according to an embodiment of the present invention includes the following steps:
[0059] Step 1, such as Figure 6AAs shown, a semiconductor substrate 401 is provided, the formation region of the fin 402 is defined, and the semiconductor substrate 401 is first etched to form the top portion 402a of the fin 402.
[0060] In the method of this embodiment of the invention, the semiconductor substrate 401 includes a silicon substrate.
[0061] Fin field-effect transistors include N-type fin field-effect transistors and P-type fin field-effect transistors. Figure 6A In the diagram, the left side of the dashed line HH corresponds to the formation region 601 of the N-type fin field-effect transistor, and the right side of the dashed line HH corresponds to the formation region 602 of the P-type fin field-effect transistor.
[0062] The top portion 402a is further divided into a first segment 402a1 and a second segment 402a2, with the second segment 402a2 superimposed on top of the first segment 402a1. Figure 6A In the diagram, the dashed line GG represents the interface between the first segment 402a1 and the second segment 402a2.
[0063] The second segment 402a2 serves as the channel layer.
[0064] In the formation region 601 of the N-type fin field-effect transistor, the top portion 402a is intrinsically doped or P-type doped.
[0065] In the formation region 602 of the P-type fin field-effect transistor, the top portion 402a is intrinsically doped or N-type doped.
[0066] The preferred option is that step one includes the following sub-steps:
[0067] Step 11: Form a hard mask layer 501 on the surface of the semiconductor substrate 401.
[0068] The hard mask layer 501 is composed of an oxide layer 501a and a nitride layer 501b stacked together.
[0069] Step 12: Form a photoresist pattern that covers the formation area of the fin 402 and opens up the area outside the formation area of the fin 402.
[0070] Step 13: Etch the hard mask layer 501 to transfer the pattern structure of the photoresist pattern into the hard mask layer 501.
[0071] Step 14: Perform the first etching on the semiconductor substrate 401 using the hard mask layer 501 as a mask.
[0072] The photoresist pattern is removed after the etching of the hard mask layer 501 in step 13 is completed, or after the first etching in step 14 is completed.
[0073] Step Two, as follows Figure 6C As shown, a sacrificial sidewall 503 is formed on the side of the second segment 402a2, the sacrificial sidewall 503 exposing the side of the first segment 402a1.
[0074] In the method of this embodiment of the invention, step two includes the following sub-steps:
[0075] like Figure 6B As shown, an organic dielectric layer 502 is deposited, which fills the spaced regions between the top portion 402a and the height of the organic dielectric layer 502 is equal to the height of the first segment 402a1, as shown by the dashed line GG.
[0076] like Figure 6B As shown, the deposition process of the material layer 503a of the sacrificial sidewall 503 is carried out.
[0077] like Figure 6C As shown, the material layer 503a of the sacrificial sidewall 503 is etched to form the sacrificial sidewall 503 by self-alignment on the side of the second segment 402a2.
[0078] Remove the organic dielectric layer 502. It can be seen that after removing the organic dielectric layer 502, the side of the first segment 402a1 is exposed.
[0079] Step 3, as follows Figure 6D As shown, a doped dielectric layer is formed to cover the side of the first segment 402a1.
[0080] In the method of this embodiment of the invention, step three includes the following sub-steps:
[0081] The material layer deposition and etching process for the doped dielectric layer is performed to form the doped dielectric layer by self-alignment on the side of the top portion 402a where the sacrificial sidewall 503 is formed, and the doped dielectric layer covers the side of the sacrificial sidewall 503 and the side of the first segment 402a1.
[0082] In the formation region 601 of the N-type fin field-effect transistor, the doped dielectric layer is P-type doped. Preferably, the doped dielectric layer is a BSG thin film 504a.
[0083] In the formation region 602 of the P-type fin field-effect transistor, the doped dielectric layer is N-type doped, preferably, the doped dielectric layer is a PSG thin film 504b.
[0084] In the method of this embodiment, the BSG film 504a and the PSG film 504b need to be formed separately. The BSG film 504a can be formed first, followed by the PSG film 504b. In this case, the process sequence includes: first opening the formation region 601 of the N-type fin field-effect transistor and the formation region 602 covering the P-type fin field-effect transistor; then forming the BSG film 504a in the formation region 601 of the N-type fin field-effect transistor; then opening the formation region 602 of the P-type fin field-effect transistor and the formation region 601 covering the N-type fin field-effect transistor; and then forming the PSG film 504b in the formation region 602 of the P-type fin field-effect transistor. Alternatively, the PSG film 504b can be formed first, followed by the BSG film 504a, in which case the process sequence is exactly the reverse of the above sequence.
[0085] Step 4, as follows Figure 6E As shown, a doping-driven process is performed to diffuse impurities from the doped dielectric layer into the first segment 402a1 to achieve doping of the first segment 402a1. The doped first segment 402a1 serves as a punch-through barrier layer.
[0086] In the formation region 601 of the N-type fin field-effect transistor, the doped dielectric layer is P-type doped, and the anti-penetration layer is a P-type anti-penetration layer 403a.
[0087] In the formation region 602 of the P-type fin field-effect transistor, the doped dielectric layer is N-type doped, and the punch-through barrier layer is an N-type punch-through barrier layer 403b.
[0088] The doping driving process is achieved by thermal annealing, and the process conditions of the doping driving process include: a temperature of 1050°C, a time of 30 seconds, and an ambient atmosphere of oxygen.
[0089] Step 5, as follows Figure 6F As shown, the doped dielectric layer and the sacrificial sidewall 503 are removed.
[0090] Step Six, as Figure 6G As shown, the semiconductor substrate 401 is etched a second time to form the bottom portion 402b of the fin 402, and the fin 402 is formed by superimposing the bottom portion 402b and the top portion 402a.
[0091] Step 7, as follows Figure 6I As shown, a medium isolation layer 404 is formed between the fins 402, and the top surface of the medium isolation layer 404 is located between the top surface and the bottom surface of the anti-penetration layer.
[0092] In the method of this embodiment of the invention, step seven includes the following sub-steps:
[0093] Step 71, as follows Figure 6H As shown, the material layer 404a deposited in the medium isolation layer 404 completely fills the spacer area between the fins 402 and extends over the surface of the fins 402.
[0094] Preferably, the material layer 404a of the dielectric isolation layer 404 is deposited using an FCVD process. After the FCVD deposition is completed, an annealing process is typically included to cure the material layer 404a of the dielectric isolation layer 404.
[0095] Step 72, as follows Figure 6H As shown, a chemical mechanical polishing process is performed to make the surface of the material layer 404a of the dielectric isolation layer 404 and the surface of the fin 402 flush. In the method of this embodiment of the invention, since the hard mask layer 501 is also formed on the surface of the fin 402, after the chemical mechanical polishing process in step 72, the surface of the material layer 404a of the dielectric isolation layer 404 and the surface of the hard mask layer 501 on the surface of the fin 402 are flush.
[0096] Step 73, as follows Figure 6I As shown, the dielectric isolation layer 404 is formed by etching back the material layer 404a. The hard mask layer 501 is removed before or after the etching back of the dielectric isolation layer 404.
[0097] Preferably, the top surface of the dielectric isolation layer 404 is located at the midpoint between the top and bottom surfaces of the anti-penetration layer.
[0098] Through the above steps, the fin 402 with the anti-penetration layer can be obtained.
[0099] Based on the formation of the fin 402, the subsequent steps include forming the gate structure, source and drain regions, and metal interconnect structure of the fin field-effect transistor. The formation process of these structures is the same as that of the prior art, and will not be described in detail here.
[0100] In this embodiment of the invention, the fin 402 is formed by two etching processes. After the first etching, the top portion 402a of the fin 402 is divided into two segments according to the required channel layer and punch-through layer. Then, a sacrificial sidewall 503 is used to cover the side of the second segment 402a2 at the top. In this way, the side of the first segment 402a1 at the bottom can be covered by the doped dielectric layer, and the impurities of the doped dielectric layer can be diffused into the first segment 402a1 to achieve doping of the first segment 402a1 and form a punch-through layer. Therefore, this embodiment of the invention can use solid-phase source doping to achieve punch-through layer doping. Compared with ion implantation doping, solid-phase source doping does not generate ion defects and can prevent impurities from diffusing upward into the channel layer. Finally, this embodiment of the invention can form a damage-free, highly doped punch-through layer at the bottom of the channel layer without affecting the carrier mobility of the channel layer and achieve high carrier mobility, thereby improving the performance of the device.
[0101] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A method for manufacturing a fin field-effect transistor, characterized in that, Includes the following steps: Step 1: Provide a semiconductor substrate, define the fin formation area, and perform a first etching on the semiconductor substrate to form the top portion of the fin; the top portion is further divided into a first segment and a second segment, with the second segment superimposed on top of the first segment; The second section serves as the channel layer; Step 2: Form a sacrificial sidewall on the side of the second segment, the sacrificial sidewall exposing the side of the first segment; Step 3: Form a doped dielectric layer to cover the side of the first segment; Step 4: Perform a doping drive process to diffuse the impurities of the doped dielectric layer into the first segment to achieve doping of the first segment. The doped first segment serves as a punch-through barrier layer. Step 5: Remove the doped dielectric layer and the sacrificial sidewalls; Step 6: Perform a second etching on the semiconductor substrate to form the bottom portion of the fin, and then stack the bottom portion and the top portion to form the fin; Step 7: Form a medium isolation layer between the fins, wherein the top surface of the medium isolation layer is located between the top and bottom surfaces of the anti-penetration layer.
2. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.
3. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: Fin field-effect transistors include N-type fin field-effect transistors and P-type fin field-effect transistors.
4. The method for manufacturing a finned field-effect transistor as described in claim 3, characterized in that: In the formation region of the N-type fin field-effect transistor, the doped dielectric layer is a P-type doped dielectric layer, and the anti-penetration layer is a P-type anti-penetration layer.
5. The method for manufacturing a finned field-effect transistor as described in claim 4, characterized in that: In step one, in the formation region of the N-type fin field-effect transistor, the top portion is intrinsically doped or P-type doped.
6. The method for manufacturing a finned field-effect transistor as described in claim 4, characterized in that: The P-type doped dielectric layer is a BSG thin film.
7. The method for manufacturing a finned field-effect transistor as described in claim 3, characterized in that: In the formation region of the P-type fin field-effect transistor, the doped dielectric layer is an N-type doped dielectric layer, and the anti-penetration layer is an N-type anti-penetration layer.
8. The method for manufacturing a fin field-effect transistor as described in claim 7, characterized in that: In step one, in the formation region of the P-type fin field-effect transistor, the top portion is intrinsically doped or N-type doped.
9. The method for manufacturing a finned field-effect transistor as described in claim 7, characterized in that: The N-type doped dielectric layer is a PSG thin film.
10. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that: Step one includes the following sub-steps: Step 11: Form a hard mask layer on the surface of the semiconductor substrate; Step 12: Form a photoresist pattern, wherein the photoresist pattern covers the fin formation area and opens up the area outside the fin formation area; Step 13: Etch the hard mask layer to transfer the pattern structure of the photoresist pattern into the hard mask layer; Step 14: Perform the first etching on the semiconductor substrate using the hard mask layer as a mask; The photoresist pattern is removed after the etching of the hard mask layer in step 13 is completed, or after the first etching in step 14 is completed.
11. The method for manufacturing a fin field-effect transistor as described in claim 10, characterized in that: Step two includes the following sub-steps: An organic dielectric layer is deposited, the organic dielectric layer filling the spacers between the top portion and the height of the organic dielectric layer being equal to the height of the first segment; The material layer of the sacrificial sidewall is deposited and etched to form the sacrificial sidewall by self-alignment on the side of the second segment; Remove the organic dielectric layer.
12. The method for manufacturing a finned field-effect transistor as described in claim 1, characterized in that: Step three includes the following sub-steps: The material layer deposition and etching process for the doped dielectric layer is performed to form the doped dielectric layer by self-alignment on the side of the top portion where the sacrificial sidewall is formed, the doped dielectric layer covering the side of the sacrificial sidewall and the side of the first segment.
13. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that: In step four, the doping driving process is achieved by thermal annealing. The process conditions for the doping driving process include: a temperature of 1050°C, a time of 30 seconds, and an ambient atmosphere of oxygen.
14. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that: Step seven includes the following sub-steps: Step 71: The material layer of the deposited medium isolation layer completely fills the gap area between the fins and extends over the surface of the fins; Step 72: Perform a chemical mechanical polishing process to make the surface of the material layer of the dielectric isolation layer and the surface of the fin flush; Step 73: The material layer of the dielectric isolation layer is etched back to form the dielectric isolation layer.
15. The method for manufacturing a fin field-effect transistor as described in claim 14, characterized in that: In step 71, the material layer of the dielectric isolation layer is deposited using the FCVD process.
16. The method for manufacturing a fin field-effect transistor as described in claim 1, characterized in that: The top surface of the dielectric isolation layer is located in the middle between the top and bottom surfaces of the anti-penetration layer.