Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a substrate, an interlayer dielectric layer located on the substrate, a gate dielectric layer covering the interlayer dielectric layer, and a work function layer covering the gate dielectric layer, and a metal gate layer covering the substrate and the work function layer; etching the metal gate layer and the work function layer to form a first groove, the first groove exposing the top of the gate dielectric layer; forming a first mask layer over the first groove and the gate dielectric layer, the first mask layer having a first opening exposing the metal gate layer and the work function layer, and performing an ion implantation process; removing the metal gate layer and the work function layer exposed by the first opening; removing the first mask layer and the gate dielectric layer to expose the substrate. This method can improve the performance of semiconductor structure devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development of very large-scale integrated circuits (VLSI), the critical dimension (CD) of integrated circuits continues to shrink. To adapt to the reduction in feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] To reduce gate leakage, a high-k metal gate (HKMG) process was developed. This process uses a novel high-k dielectric material to replace the traditional silicon oxynitride (SION) as the gate dielectric and a metal gate to replace the polysilicon dummy gate. Furthermore, the thinner equivalent oxide layer of the high-k dielectric material allows for further reduction in transistor feature size.

[0004] Currently, there are still some problems in the process of forming metal gates using poly-open chemical mechanical polishing (POC) technology, such as metal gate residue and interlayer dielectric loss, which affect the performance of semiconductor structure devices. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which can improve the performance of semiconductor structure devices.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, an interlayer dielectric layer located on the substrate, a gate dielectric layer covering the interlayer dielectric layer, and a work function layer covering the gate dielectric layer, and a metal gate layer covering the substrate and the work function layer; etching the metal gate layer and the work function layer to form a first groove, the first groove exposing the top of the gate dielectric layer; forming a first mask layer above the first groove and the gate dielectric layer, the first mask layer having a first opening exposing the metal gate layer and the work function layer, and performing an ion implantation process; removing the metal gate layer and the work function layer exposed by the first opening; removing the first mask layer and the gate dielectric layer to expose the substrate.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] The method for forming a semiconductor structure provided in this invention includes a substrate, the substrate comprising an interlayer dielectric layer on the substrate, a gate dielectric layer covering the interlayer dielectric layer, a work function layer covering the gate dielectric layer, and a metal gate layer covering the substrate and the work function layer. The metal gate layer and the work function layer are etched to form a first groove, the first groove exposing the top of the gate dielectric layer. Subsequently, a first mask layer is formed above the first groove and the gate dielectric layer, the first mask layer having a first opening exposing the metal gate layer and the work function layer. An ion implantation process is then performed to modify the surface of the metal gate layer. During the removal of the metal gate layer and the work function layer exposed by the first opening, the removal rate is more uniform, and the metal gate layer is easier to remove and less likely to remain. Furthermore, since the gate dielectric layer can serve as an etch stop layer, thereby preventing the interlayer dielectric layer from being etched, the performance of the semiconductor device can be improved.

[0009] In an alternative embodiment, since the width of the first opening is greater than the width of the first groove formed by etching the metal gate layer and the work function layer, the metal gate layer to be removed can fully receive the implanted ions during the ion implantation process, making it easier to remove the metal gate layer subsequently.

[0010] In an alternative embodiment, during the step of removing the mask layer and the gate dielectric layer exposed by the second opening, since the removal rate of the gate dielectric layer is greater than the removal rate of the interlayer dielectric, the interlayer dielectric layer can be protected from etching. Attached Figure Description

[0011] Figures 1 to 6This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figures 7 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0013] The performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures still needs improvement by combining a semiconductor structure formation method.

[0014] Reference Figures 1 to 6 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0015] Reference Figure 1 A substrate is provided, the substrate including a substrate 10, an interlayer dielectric layer 11 on the substrate 10, a gate dielectric layer 13 covering the interlayer dielectric layer 11, a work function layer 14 covering the gate dielectric layer 13, and a metal gate layer 15 covering the substrate 10 and the work function layer 14.

[0016] It should be noted that, in the step of providing the substrate, a sidewall layer 12 may also be included above the substrate 10. The sidewall layer 12 is located on both sides of the interlayer dielectric layer 11 and is covered by the gate dielectric layer 13.

[0017] Reference Figure 2 Part of the work function layer 14 and the metal gate layer 15 are removed to form a groove 20, which exposes the top of the gate dielectric layer 13.

[0018] Reference Figure 3 A mask layer 16, an anti-reflective coating 17, and a photoresist layer 18 are sequentially formed above the substrate 10. The photoresist layer 18 has a patterned opening that exposes the anti-reflective coating 17. Figure 3 (Not shown), using the photoresist layer 18 as a mask, the anti-reflective coating 17 and the mask layer 16 are etched sequentially, forming an opening 30 in the mask layer 16, the opening 30 exposing at least a portion of the metal gate layer 15 and the work function layer 14.

[0019] Reference Figure 4 Using the mask layer 16 as a mask, the metal gate layer 15 exposed by the opening 30 and the work function layer 14 covered by the metal gate layer 15 are etched to form an opening 40, which exposes the gate dielectric layer 13 located above the substrate 10.

[0020] It should be noted that after the opening 40 is formed, the anti-reflective coating 17 and the photoresist layer 18 can be removed.

[0021] Reference Figure 5 The mask layer 16 and the gate dielectric layer 13 located above the substrate 10 are removed to form an opening 50 that exposes the substrate 10.

[0022] Reference Figure 6 An insulating layer 19 is formed on the substrate.

[0023] During the formation of the above semiconductor structure, when the metal gate layer 15 is removed by etching, a portion of the metal gate layer 15 remains above the gate dielectric layer 13, such as... Figure 4 As shown in the middle dotted coil region I, the residual metal gate will affect the morphology of the subsequently formed insulating layer 19, and in severe cases, it will cause the insulating layer 19 to break, thereby affecting the performance of the semiconductor device structure.

[0024] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate, an interlayer dielectric layer located on the substrate, a gate dielectric layer covering the interlayer dielectric layer, and a work function layer covering the gate dielectric layer, and a metal gate layer covering the substrate and the work function layer; etching the metal gate layer and the work function layer to form a first groove, the first groove exposing the top of the gate dielectric layer; forming a first mask layer above the first groove and the gate dielectric layer, the first mask layer having a first opening exposing the metal gate layer and the work function layer, and performing an ion implantation process; removing the metal gate layer and the work function layer exposed by the first opening; removing the first mask layer and the gate dielectric layer to expose the substrate.

[0025] In the semiconductor structure formation method provided in this embodiment of the invention, before removing the metal gate layer and the work function layer exposed by the first opening, an ion implantation process is performed to modify the surface of the metal gate layer. This makes the metal gate layer easier to remove and less likely to remain during the removal of the exposed metal gate layer and the work function layer. Furthermore, since the gate dielectric layer can serve as an etch stop layer, the interlayer dielectric layer is prevented from being etched, thereby improving the performance of the semiconductor structure device.

[0026] To enable those skilled in the art to better understand and implement the embodiments of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following drawings describe the embodiments of the present invention from two perspectives.

[0027] Figures 7 to 17 This is a schematic diagram of the structure corresponding to each step in an embodiment of the semiconductor structure formation method of the present invention, wherein... Figures 7 to 17The sub-figure labeled (a) is a cross-sectional structural diagram of the semiconductor structure formation process, and the sub-figure labeled (b) is the corresponding top view of the sub-figure labeled (a).

[0028] like Figure 7 As shown in sub-figure (a), a substrate is provided, the substrate including a substrate 100, an interlayer dielectric layer 110 on the substrate 100, a gate dielectric layer 130 covering the interlayer dielectric layer 110, a work function layer 140 covering the gate dielectric layer 130, and a metal gate layer 150 covering the substrate 100 and the work function layer 140.

[0029] The substrate can provide a process platform for the subsequent formation of semiconductors.

[0030] In this embodiment of the invention, an isolation structure can be formed in the substrate. Figure 7 (Not shown). The isolation structure is used to achieve insulation between different devices. For example, in CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing processes, an isolation structure can be formed between NMOS transistors and PMOS transistors. Specifically, the isolation structure is a shallow trench isolation (STI) structure.

[0031] It should be noted that the semiconductor structure formed in this embodiment of the invention is a FinFET (Fin Field-Effect Transistor).

[0032] In this embodiment of the invention, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be made of germanium, silicon carbide, gallium arsenide, or indium gallium ionide, and the substrate 100 may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0033] In this embodiment of the invention, the material of the interlayer dielectric layer 110 is an insulating material. Specifically, the material of the interlayer dielectric layer 110 can be silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 110.

[0034] It should be noted that, in the step of providing the substrate, the substrate 100 may also include a sidewall layer 120, and the sidewall layer 120 may be located on both sides of the interlayer dielectric layer 110 and covered by the gate dielectric layer 130.

[0035] The sidewall layer 120 can protect the interlayer dielectric layer 110 when the gate dielectric layer 130 is removed, preventing the interlayer dielectric layer 110 from being accidentally etched.

[0036] The sidewall layer 120 is made of one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment of the invention, the sidewall layer 120 is made of silicon nitride.

[0037] Reference Figure 8 ,like Figure 8 As shown in sub-figure (a), the metal gate layer 150 and the work function layer 140 are etched to form a first groove 200, which exposes the top of the gate dielectric layer 130.

[0038] In this embodiment of the invention, the metal gate layer 150 is made of tungsten. Tungsten has stable chemical properties and a mature formation process, which is beneficial for controlling the formation quality of the semiconductor structure and improving the formation rate of the semiconductor structure. In other embodiments, the metal gate layer 150 is made of one or more of ruthenium, cobalt, magnesium-tungsten alloy, and aluminum.

[0039] In a specific implementation, a dry etching process can be used to remove the metal gate layer 150 and the work function layer 140 to form the first groove 200. The dry etching process allows for precise control of the removal thickness of the work function layer 140 and the metal gate layer 150, ensuring that the height of the metal gate layer 150 and the work function layer 140 is less than that of the gate dielectric layer 130. This allows the first groove 200 to expose the top of the gate dielectric layer 130. Furthermore, during the etching process, the metal gate layer 150, the work function layer 140, and the gate dielectric layer 130 have a high etching selectivity, thus reducing damage to the gate dielectric layer 130.

[0040] In specific implementation, the thickness of the gate dielectric layer 130 should not be too small or too large. If the thickness of the gate dielectric layer 130 is too small, it is easy to remove it prematurely, thereby reducing the protective effect on the interlayer dielectric layer 110. In the specific formation process, subsequent steps may also include: removing the second opening 320 (e.g., Figure 15 As shown in sub-figure (a) of the diagram, the exposed gate dielectric layer 130 can be problematic if its thickness is too large, increasing the difficulty of removing it from the second opening 320. Therefore, the thickness of the gate dielectric layer 130 can be appropriately set according to specific process requirements, ensuring that it protects the interlayer dielectric layer 110 during semiconductor structure formation and is easily removed in subsequent processes. For example, the thickness of the gate dielectric layer 130 can be from 0.5 to 5 nm.

[0041] In this embodiment of the invention, the gate dielectric layer 130 is made of hafnium oxide. Hafnium oxide is a commonly used and low-cost high-k dielectric material with high process compatibility. In this embodiment, hafnium oxide can be used as a protective layer in ion implantation to protect the interlayer dielectric layer 110 from damage, and it can also be used as an etching stop layer in plasma etching to prevent the interlayer dielectric layer 110 from being etched. Furthermore, during the plasma etching process to remove the metal gate layer 150 and the work function layer 140, the metal gate layer 150, the work function layer 140, and the hafnium oxide have a high etching selectivity, thus reducing damage to the gate dielectric layer 130.

[0042] In other embodiments, the material of the gate dielectric layer 130 may be zirconium oxide, silicate, hafnium oxynitride silicon, hafnium titanium oxide, or aluminum oxide, etc.

[0043] It should be noted that by using the dry etching process, some of the metal gate layer 150 and the work function layer 140 are removed, and their height (depth) is reduced, while the feature size (width) remains unchanged. Therefore, the aspect ratio (depth-to-width ratio) of the subsequent etching process can be reduced, so that the morphology formed by the etching process in the subsequent process can meet the process requirements.

[0044] Reference Figure 9 , Figure 10 and Figure 11 A first mask layer 160 is formed above the first groove 200 and the gate dielectric layer 130. The first mask layer 160 has a first opening 300, which exposes the metal gate layer 150 and the work function layer 140, and an ion implantation process is performed.

[0045] In an embodiment of the present invention, the step of forming a first mask layer 160 over the first groove 200 and the gate dielectric layer 130, the first mask layer 160 having a first opening 300, the first opening 300 exposing the metal gate layer 150 and the work function layer 140, includes: as follows Figure 9 As shown in sub-figure (a), a first mask layer 160, a first anti-reflective coating 161, and a first photoresist layer 162 are sequentially formed above the first groove 200 and the gate dielectric layer 130. The first photoresist layer 162 has a first patterned opening that exposes a portion of the first anti-reflective coating 161. Figure 9 (Not shown), and using the first photoresist layer 162 as a mask, the first anti-reflective coating 161 and the first mask layer 160 are sequentially etched along the first pattern opening, forming the first opening 300 in the first mask layer 160. The first opening 300 exposes a portion of the metal gate layer 150 and the work function layer 140, as shown. Figure 10The subgraph (a) is shown in the figure.

[0046] It should be noted that the first pattern opening is formed by photolithography processes such as exposure and development on the first photoresist layer 162.

[0047] In specific implementations, chemical vapor deposition (CVD) technology has the advantages of good deposition properties, uniform film thickness, and improved mask layer density. Therefore, CVD technology can be used to form the first mask layer 160 above the first groove 200 and the gate dielectric layer 130. In other embodiments, atomic layer deposition (ALD) technology can also be used to form the first mask layer 160.

[0048] In this embodiment of the invention, the first mask layer 160 needs to be removed subsequently. Therefore, the first mask layer 160 is made of a material that is easy to remove. Spin-on carbon (SOC) materials have low cost, simple formation process, high process compatibility, and good filling performance, making them easy to remove. Therefore, the material of the first mask layer 160 includes SOC materials.

[0049] In other embodiments, the material of the first mask layer 160 may also be an organic dielectric layer (ODL), a deep UV light absorbing oxide (DUO), a dielectric anti-reflective coating (DARC), or a photoresist.

[0050] The first anti-reflective coating 161 is used to reduce the reflection effect during exposure, thereby improving the transfer accuracy of the pattern. In this embodiment of the invention, the material of the first anti-reflective coating 161 can be silicon carbonitride. In other embodiments, the material of the first anti-reflective coating 161 can also be one or more of silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide.

[0051] In this invention, the first anti-reflective coating 161 and the first mask layer 160 can be etched using a dry etching process.

[0052] In this embodiment of the invention, after forming the first opening 300, ion implantation is also performed on the metal gate layer 150 and the work function layer 140 exposed by the first opening 300, such as... Figure 11As indicated by arrow II in sub-figure (a). Specifically, the process parameters for ion implantation may include: implanted ions including at least one of boron or helium, ion implantation energy of 20 KeV to 40 KeV, process temperature of 80°C to 150°C, and ion implantation times of 3.

[0053] It should be noted that during ion implantation, high-energy boron or helium ions are used to bombard the surface of the metal gate layer 150. The metallic bonds of the metal gate layer 150 are broken by the boron or helium ions, causing the surface of the metal gate layer 150 to deform and become a foam-like structure, such as... Figure 11 As shown in neutron diagram (b) 150. By controlling the energy of ion implantation, boron ions or helium ions can penetrate into the interior of the metal gate layer 150. Specifically, the penetration depth of ions implanted into the portion of the metal gate layer 150 exposed by the first opening 300 and the work function layer 140 is three-quarters of the height of the metal gate layer 150 exposed by the first opening 300.

[0054] It should be noted that during the ion implantation process, since the interlayer dielectric layer 110 is covered by the gate dielectric layer 130, and ions can only diffuse on the surface of the gate dielectric layer 130, they will not penetrate into the interior of the gate dielectric layer 130, nor will they cause damage to the surface of the interlayer dielectric layer 110.

[0055] In this embodiment of the invention, after ion implantation, annealing is required. Specifically, annealing can be performed for 30 to 60 seconds in an environment with a process temperature of 300°C to 800°C. Annealing can repair lattice damage caused by ion implantation, while also moving impurity atoms to lattice points and activating some impurity atoms, thereby restoring the crystal structure and eliminating defects.

[0056] It should be noted that during the process of removing the first anti-reflective coating 161 and the first mask layer 160 using the first photoresist layer 162 as a mask to form the first opening 300, the first opening 300 must completely expose the metal gate layer 150 and the work function layer 140. Therefore, the width of the first opening 300 must be greater than [the required width]. Figure 8 The width of the first groove 200 shown in neutron diagram (a) is such that the metal gate layer 150 to be removed can fully receive ion implantation during ion implantation, making it easier to remove the metal gate layer 150 during subsequent etching processes without leaving any metal gate residue.

[0057] It should be noted that after the ion implantation process is completed, the subsequent process also needs to remove the first anti-reflective coating 161 and the first photoresist layer 162.

[0058] Reference Figure 12 ,like Figure 12 As shown in sub-figure (a), the metal gate layer 150 and the work function layer 140 exposed by the first opening 300 are removed.

[0059] Specifically, a plasma etching process can be used to remove the metal gate layer 150 and the work function layer 140 exposed by the first opening 300, forming a third opening 310. The third opening 310 can expose the gate dielectric layer 130 located above the substrate 100. The plasma etching process offers uniform etching rate and high etching selectivity, which is beneficial for improving the removal efficiency of the metal gate layer 150 and the work function layer 140, resulting in an appearance that meets process requirements.

[0060] It should be noted that during the ion implantation process, due to the surface modification of the metal gate layer 150, the metal gate layer 150 and the work function layer 140 are easier to remove during the plasma etching process, thereby avoiding the problem of metal residue. At the same time, since the gate dielectric layer 130 can be used as an etching stop layer to prevent the interlayer dielectric layer 110 from being consumed, the performance of the semiconductor structure device can be improved.

[0061] Reference Figure 13 , Figure 14 , Figure 15 and Figure 16 Remove the first mask layer 160 and the gate dielectric layer 130 to expose the substrate 100.

[0062] In this embodiment of the invention, the material of the first mask layer 160 is SOC (Sodium Organic Carbon), therefore, the first mask layer 160 can be removed using an asher process. The asher process can remove the first mask layer 160 promptly, preventing the organic material in the first mask layer 160 from contaminating the equipment. After removing the first mask layer 160, the metal gate layer 150 and the work function layer 140 can be exposed, such as... Figure 13 As shown.

[0063] In this embodiment of the invention, after removing the first mask layer 160, the gate dielectric layer 130 can be removed by dry etching to expose the substrate 100.

[0064] Specifically, refer to Figure 14 A second mask layer 170, a second anti-reflective coating 171, and a second photoresist layer 172 are sequentially formed on the substrate. A second patterned opening is formed in the second photoresist layer 172 to expose a portion of the second anti-reflective coating 171. Figure 13(Not shown), and using the second photoresist layer 172 as a mask, the second anti-reflective coating 171 and the second mask layer 170 are sequentially etched along the second pattern opening, forming the second opening 320 in the second mask layer 170. The second opening 320 exposes the gate dielectric layer 130 located on the substrate 100 and covering the interlayer dielectric layer 110, as shown. Figure 15 As shown.

[0065] It should be noted that the second pattern opening is formed by photolithography processes such as exposure and development on the second photoresist layer 172.

[0066] In this embodiment of the invention, the second mask layer 170 can be formed using an atomic layer deposition process. The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form a thin film of the desired thickness. By selecting an atomic layer deposition process, it is beneficial to improve the thickness uniformity and density of the second mask layer 170, so that the thickness of the second mask layer 170 can be precisely controlled.

[0067] It should be noted that during the process of removing the second anti-reflective coating 171 and the second mask layer 170 using the second photoresist layer 172 as a mask to form the second opening 320, the width of the second opening 320 cannot be too large. If the width is too large, part of the metal gate layer 150 or the work function layer 140 will be exposed. In the subsequent removal of the gate dielectric layer 130 exposed by the second opening 320, part of the metal gate layer 150 or the work function layer 140 will be mistakenly etched away, affecting the performance of the semiconductor structure device.

[0068] After the second opening 320 is formed, the second anti-reflective coating 171 and the second photoresist layer 172 need to be removed.

[0069] In this embodiment of the invention, reference is made to Figure 16 The gate dielectric layer 130 exposed by the second opening 320 can be removed using a dry etching process to form a fourth opening 330, which exposes the substrate 100. The dry etching process offers good process control, which helps prevent accidental etching of other film structures during the removal of the gate dielectric layer 130. Furthermore, the dry etching process allows for precise control of the removal thickness of the gate dielectric layer 130, ensuring that the height of 130 is consistent with the heights of the work function layer 140 and the metal gate layer 150.

[0070] It should be noted that during the etching process, the removal rate of the gate dielectric layer 130 is greater than the removal rate of the interlayer dielectric layer 110. Under the effect of the high etching selectivity of the gate dielectric layer 130 and the interlayer dielectric layer 110, the gate dielectric layer 130 is easy to remove and the interlayer dielectric layer 110 is not easily damaged.

[0071] In this embodiment of the invention, after removing the first mask layer 160 and the gate dielectric layer 130, the second mask layer 170 also needs to be removed.

[0072] By employing the above-described method for forming a semiconductor structure, problems such as residual gate layer and etching of interlayer dielectric layers can be avoided. Furthermore, the method for forming the semiconductor structure may further include forming an insulating layer over the substrate.

[0073] Reference Figure 17 An insulating layer 180 is formed on the substrate.

[0074] Specifically, the insulating layer 180 is located above the substrate 100 and covers the interlayer dielectric layer 110, the gate dielectric layer 130, the work function layer 140, and the metal gate layer 150.

[0075] In this embodiment of the invention, the insulating layer 180 can be formed using an atomic layer deposition (ALD) process. The ALD process involves performing multiple ALD cycles to form a thin film of the desired thickness. By employing the ALD process, the thickness uniformity and density of the insulating layer 180 can be improved, allowing for precise control of the thickness of the insulating layer 180. Furthermore, the ALD process exhibits good gap-filling performance and step coverage, thereby enhancing the coverage capability of the insulating layer 180.

[0076] It should be noted that, during the formation of the insulating layer 180, the material of the insulating layer 180 can be the same as the material of the sidewall layer 120, both being silicon nitride. Using the same material for the insulating layer 180 and the sidewall layer 120 improves process compatibility. In other embodiments, the material of the insulating layer 180 can also be one of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide.

[0077] In this embodiment of the invention, the insulating layer 180 formed on the substrate can serve as a contact hole plug in subsequent metal interconnect processes. Specifically, the insulating layer 180 can serve as a contact hole plug for the zero-layer metal gate.

[0078] It should be noted that the terms "first," "second," etc., in the embodiments of the present invention are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with terms such as "first," "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or indicate importance.

[0079] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, include: A substrate is provided, the substrate comprising a substrate, an interlayer dielectric layer on the substrate, a gate dielectric layer covering the interlayer dielectric layer, a work function layer covering the gate dielectric layer, and a metal gate layer covering the substrate and the work function layer; The metal gate layer and the work function layer are etched to form a first groove, the first groove exposing the top of the gate dielectric layer; A first mask layer is formed over the first groove and the gate dielectric layer. The first mask layer has a first opening that exposes the metal gate layer and the work function layer, and an ion implantation process is performed thereon. The metal gate layer and the work function layer exposed by the first opening are removed by plasma etching. Remove the first mask layer and the gate dielectric layer to expose the substrate.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the semiconductor structure further includes: An insulating layer is formed on the substrate.

3. The method of forming a semiconductor structure of claim 2, wherein, The insulating layer is made of one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, and boron silicon carbide.

4. The method of forming a semiconductor structure of claim 1, wherein, The width of the first opening is greater than the width of the first groove.

5. The method of forming a semiconductor structure according to any one of claims 1 to 4, wherein The process of forming a mask layer over the first groove and the gate dielectric layer, the mask layer having a first opening exposing the metal gate layer and the work function layer, and performing an ion implantation process includes: A first mask layer, a first anti-reflective coating, and a first photoresist layer are sequentially formed above the first groove and the gate dielectric layer. The first photoresist layer has a first patterned opening that exposes a portion of the first anti-reflective coating. Using the first photoresist layer as a mask, the first mask layer and the first anti-reflection coating are sequentially etched along the first pattern opening to form the first opening, which exposes a portion of the metal gate layer and the work function layer. Ion implantation is performed on the portion of the metal gate and the work function layer exposed by the first opening; After ion implantation, annealing is performed.

6. The method of forming a semiconductor structure of claim 5, wherein, The process of forming the first mask layer over the groove and the gate dielectric layer includes a chemical vapor deposition process.

7. The method of forming a semiconductor structure of claim 5, wherein, The material of the first mask layer includes SOC.

8. The method for forming a semiconductor structure according to claim 5, characterized in that, The ion implantation of the exposed portion of the metal gate layer and the work function layer through the first opening includes: The following ion implantation process parameters are used to implant ions into the exposed portion of the metal gate layer and the work function layer: the implanted ions include at least one of boron or helium, the ion implantation energy is 20 KeV to 40 KeV, the process temperature is 80°C to 150°C, and the number of ion implantation cycles is 3.

9. The method of forming a semiconductor structure of claim 8, wherein, The penetration depth of ion implantation into the exposed portion of the metal gate layer and the work function layer in the first opening is three-quarters of the height of the exposed portion of the metal gate layer in the first opening.

10. The method of forming a semiconductor structure of claim 5, wherein, The annealing process performed after ion implantation includes: Annealing is performed using the following process parameters: annealing time is 30 to 60 seconds, and process temperature is 300°C to 800°C.

11. The method of forming a semiconductor structure of claim 1, wherein, The step of removing the first mask layer and the gate dielectric layer using a plasma etching process to expose the substrate includes: Remove the first mask layer; A second mask layer, a second anti-reflective coating, and a second photoresist layer are sequentially formed on the substrate, wherein the second photoresist layer has a second patterned opening that exposes a portion of the second anti-reflective coating. Using the second photoresist layer as a mask, the second mask layer and the second anti-reflection coating are sequentially etched along the second pattern opening to form a second opening, which exposes the gate dielectric layer. Remove the gate dielectric layer exposed by the second opening and expose the substrate.

12. The method of forming a semiconductor structure of claim 1, wherein, In the step of removing the mask layer and the gate dielectric layer, the removal rate of the gate dielectric layer is greater than the removal rate of the interlayer dielectric layer.

13. The method of forming a semiconductor structure of claim 1, wherein, The substrate further includes a sidewall layer located on the side of the interlayer dielectric layer and covered by the gate dielectric layer.

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