Semiconductor memory structure and method for forming the same

Abstract

A semiconductor memory structure and a method for forming the same include providing a semiconductor substrate, wherein a pair of word lines are buried in an active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction; forming a hard mask layer on the semiconductor substrate; forming a contact opening corresponding to the pair of word lines through the hard mask layer and a portion of the semiconductor substrate; forming a pair of spacers on the sidewalls of the contact openings; filling a conductive material in the contact openings to form a contact piece; forming a bit line directly above the contact piece and the pair of spacers, wherein the bit line extends along a second direction, wherein the first direction is perpendicular to the second direction; and forming a dielectric liner on the sidewalls of the bit line.

Description

Technical Field

[0001] The present application relates to a semiconductor memory structure and a method for forming the same, and in particular to a dynamic random access memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) devices are widely used in consumer electronic products. In order to increase the component density in the DRAM device and improve its overall performance, the manufacturing technology of the DRAM device continues to strive towards miniaturization of the component size.

[0003] However, as the size of components continues to shrink, many challenges arise. For example, in the semiconductor manufacturing process, in order to prevent the bit line contact from shorting with the subsequent capacitor contact, a nitride is generally disposed next to the contact. However, during the process of patterning the nitride, the upper bit line structure may be damaged due to the use of an etchant such as phosphoric acid. Therefore, the industry still needs to improve the manufacturing method of dynamic random access memory devices to overcome the problems caused by the shrinking of component size. Summary of the invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor memory structure. The method includes providing a semiconductor substrate, wherein a pair of word lines are embedded in an active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction; forming a hard shield layer on the semiconductor substrate; corresponding to the pair of word lines, forming a contact opening through the hard shield layer and a portion of the semiconductor substrate; forming a pair of spacers on the sidewalls of the contact opening; filling a conductive material in the contact opening to form a contact; forming a bit line directly above the contact and the pair of spacers, wherein the bit line extends along a second direction, wherein the first direction is perpendicular to the second direction; and forming a dielectric liner on the sidewalls of the bit line.

[0005] An embodiment of the present invention provides a semiconductor memory structure, which includes a semiconductor substrate having an active region; a pair of word lines buried in the active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction; a cap layer disposed on the semiconductor substrate; a contact member passing through the cap layer and partially disposed in the semiconductor substrate; a pair of spacers disposed on the sidewalls of the contact member and corresponding to the pair of word lines; a bit line extending along a second direction, wherein the first direction is perpendicular to the second direction, wherein in a cross section in the first direction, the bit line is disposed directly above the contact member and the pair of spacers; and a dielectric liner disposed on the sidewalls of the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the features and advantages of the present invention more clearly understood, different embodiments are specifically described below with reference to the accompanying drawings as follows:

[0007] Figure 1 is a top view schematically illustrating a semiconductor memory structure according to some embodiments of the present invention;

[0008] Figure 2A-Figure 7A , Figure 2B-Figure 7B is a schematic cross-sectional view of forming a semiconductor memory structure at different stages according to some embodiments of the present invention;

[0009] Figure 8 is a top view schematically illustrating a semiconductor memory structure according to some embodiments of the present invention;

[0010] Figures 9A-20A , Figure 9B-Figure 20B Schematic diagrams of cross-sections of forming a semiconductor memory structure at different stages according to some embodiments of the present invention are shown.

[0011] [Explanation of symbols]

[0012] 100:Semiconductor memory structure

[0013] 102:Semiconductor substrate

[0014] 102A: Active Zone

[0015] 102B: Quarantine Area

[0016] 104: Isolation components

[0017] 1041: Isolation liner

[0018] 1042: Isolation filler

[0019] 106: Word Line

[0020] 1061: Gate dielectric layer

[0021] 1062: Gate liner

[0022] 1063: Gate electrode

[0023] 108: Protective layer

[0024] 110: Hard shielding layer

[0025] 110': Cover layer

[0026] 112,114,116: Dielectric layer

[0027] 120: contact opening

[0028] 131: spacer material layer

[0029] 132: Spacer material

[0030] 133: Conductive material

[0031] 134: Contact

[0032] 136: Spacer

[0033] 140: bit line stack layer

[0034] 141,142: Conductive layer

[0035] 143,144,145: Dielectric layer

[0036] 140': Position line

[0037] 141',142': Conductive pattern

[0038] 143,144,145: Dielectric pattern

[0039] 150: Dielectric liner

[0040] 151: Nitride material liner

[0041] 152: Nitride liner

[0042] 153: Oxide material lining

[0043] 154: Oxide liner

[0044] 156: Nitride liner

[0045] 160: Opening

[0046] 170: Capacitor contact

[0047] 171: Conductive materials

[0048] 172: Conductive layer

[0049] 174: Silicide layer

[0050] 175: Conductive material

[0051] 176: Conductive layer

[0052] WC: Width

[0053] WS: Width DETAILED DESCRIPTION

[0054] The present application is described more fully below with reference to the drawings of the embodiments of the present invention. However, the present application may be implemented in various different embodiments and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings may be exaggerated for clarity, and the same or similar reference numbers in the drawings represent the same or similar elements.

[0055] Figure 1 FIG. 1 is a top view of a semiconductor memory structure 100 according to some embodiments of the present invention. In some embodiments, the semiconductor memory structure 100 is a part of a dynamic random access memory (DRAM) array. In some embodiments, the semiconductor memory structure 100 includes a semiconductor substrate 102, a word line 106, a contact 134, a spacer 136, a bit line 140', and a capacitor contact 170. The semiconductor substrate 102 includes an active region 102A and an isolation region 102B. In this embodiment, the word line 106 extends along a first direction D1, the bit line 140' extends along a second direction D2, and the active region 102A extends along a third direction D3. In this embodiment, the first direction D1 is perpendicular to the second direction D2, and the third direction D3 (i.e., the extension direction of the active region 102A) and the second direction D2 present an angle of about 10-40°, for example, 20°, to improve the integration of the device.

[0056] It should be noted that Figure 1 Only some components of the dynamic random access memory (DRAM) are shown to simplify the diagram. Figure 1 The cross-sectional schematic diagrams shown by the section line AA′ and the section line BB′ are used to facilitate explaining the method of forming the semiconductor memory structure.

[0057] Figure 2A-Figure 7A and Figure 2B-Figure 7B 1 is a schematic cross-sectional view of a semiconductor memory structure 100 at different stages of forming the semiconductor memory structure 100 according to some embodiments of the present invention. Figure 2A-Figure 7A and Figure 2B-Figure 7B The cross-sectional diagrams are respectively along Figure 1 The cross-sectional view is taken along the section line AA′ (the first direction D1) and the section line BB′ (the second direction D2), which may sometimes be referred to as the cross-sectional view in the first direction and the cross-sectional view in the second direction, respectively.

[0058] It should be noted that in the cross-sectional schematic diagrams along the section line A-A' and the section line B-B', the horizontal directions are respectively Figure 1 The first direction D1 and the second direction D2 are shown in FIG. 1 , and the vertical direction is marked as the Z direction.

[0059] like Figure 2A and Figure 2B As shown, a semiconductor substrate 102 is provided. In some embodiments, the semiconductor substrate 102 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the semiconductor substrate 102 may be a semiconductor-on-insulator (SOI) substrate.

[0060] In some embodiments, the semiconductor substrate 102 includes an active region 102A and an isolation region 102B surrounding the active region 102A. In some embodiments, an isolation component 104 is disposed in the isolation region 102B of the semiconductor substrate 102, and includes an isolation liner 1041 and an isolation filler 1042. To simplify the drawings, the active region 102A and the isolation region 102B will be omitted in the subsequent cross-sectional schematic diagrams.

[0061] In some embodiments, the isolation liner 1041 and the isolation filler 1042 may include nitride or oxide, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and / or a combination thereof. The formation of the isolation liner 1041 and the isolation filler 1042 may include a patterning process (such as a lithography process and an etching process), a deposition process (such as chemical vapor deposition (CVD)), and a planarization process (such as chemical mechanical polish (CMP)).

[0062] like Figure 2A As shown in FIG. 1 , in the active region 102A, a pair of word lines 106 and a protection layer 108 thereon are embedded in the semiconductor substrate 102. In some embodiments, the pair of word lines 106 are disposed between the isolation components 104 and do not contact the isolation components 104. It should be noted that since the word lines extend along the first direction D1 and the section line AA' does not contact the word lines 106, Figure 2A Word line 106 does not appear in FIG.

[0063] In some embodiments, the word line 106 serves as a gate and includes a gate dielectric layer 1061 , a gate liner 1062 , and a gate electrode 1063 .

[0064] In some embodiments, a trench (not shown) is first formed by a patterning process, and a gate dielectric layer 1061 is formed in the trench. In some embodiments, the gate dielectric layer 1061 is formed of silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant. In some embodiments, the formation of the gate dielectric layer 1061 includes an oxidation process or a deposition process. The oxidation process includes thermal oxidation. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (physical vapor deposition, PVD), or atomic layer deposition (atomic layer deposition, ALD), etc.

[0065] In some embodiments, a gate liner 1062 is formed on the gate dielectric layer 1061. In some embodiments, the gate liner 1062 is formed of tungsten nitride (WN), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the gate liner 1062 can be formed using the above-mentioned deposition process, so it is not repeated here.

[0066] In some embodiments, a gate electrode 1063 is formed on the gate liner 1062. In some embodiments, the gate electrode 1063 is formed of a conductive material, such as doped polysilicon, metal, or metal nitride. In some embodiments, the gate electrode 1063 can be formed using the above-mentioned deposition process, so it is not repeated here.

[0067] In some embodiments, after depositing materials for the gate dielectric layer 1061, the gate liner 1062, and the gate electrode 1063, the gate liner 1062 and the gate electrode 1063 are etched back, so that the gate dielectric layer 1061, the gate liner 1062, and the gate electrode 1063 become the word line 106. The above-mentioned etching back makes the word line 106 lower than the top surface of the semiconductor substrate 102, so as to form a protection layer 108 on the word line 106 later.

[0068] In some embodiments, a protection layer 108 is formed on the top surfaces of the gate dielectric layer 1061, the gate liner 1062, and the gate electrode 1063. In some embodiments, the protection layer 108 includes silicon nitride, which can be used as a gate dielectric layer to control the channel. In some embodiments, the formation of the protection layer 108 includes first depositing nitride on the word line 106 using a deposition process, and then removing the nitride on the semiconductor substrate 102 using an etch-back process, and the top surface of the remaining nitride is flush with the top surface of the semiconductor substrate 102. The deposition process is similar to that described above, so it is not repeated here.

[0069] Then, if Figure 2A and Figure 2B As shown, a hard mask layer 110 is formed on the semiconductor substrate 102 and the protection layer 108. In some embodiments, the hard mask layer 110 includes a first oxide layer 112, a nitride layer 114, and a second oxide layer 116.

[0070] In some embodiments, the first oxide layer 112 and the second oxide layer 116 include silicon oxide layers formed of tetraethylorthosilicate (TEOS). In some embodiments, the nitride layer 114 includes silicon nitride (SiN) or silicon oxynitride (SiON).

[0071] In some embodiments, the first oxide layer 112 , the nitride layer 114 , and the second oxide layer 116 may be formed sequentially by the deposition process described above.

[0072] It should be noted that, in this embodiment, the second oxide layer 116 is thicker than the first oxide layer 112 to prevent subsequent processes from affecting or damaging the nitride layer 114 therebetween.

[0073] Then, if Figure 3A and Figure 3B As shown, a contact opening 120 is formed between the isolation features 104, wherein the contact opening 120 passes through the hard mask layer 110 and a portion of the semiconductor substrate 102. Figure 3B In the embodiment, the contact opening 120 corresponds to a pair of word lines 106 and passes through a portion of the protection layer 108 but does not contact the word line 106 to prevent leakage when the threshold voltage is increased.

[0074] In some embodiments, one side of the contact opening 120 is located between two edges of a word line, and the other side of the contact opening 120 is also located between two edges of another word line. When the side of the contact opening 120 exceeds the word line 106 and extends toward the isolation component 104, it is easy to cause the contact formed subsequently to directly contact the active region 102A and generate leakage. When the side of the contact opening 120 is located between the word lines 106 and does not contact the word line 106, it is easy to cause the contact area of ​​the contact formed subsequently to be too small and generate a large contact resistance.

[0075] In some embodiments, the formation of the contact opening 120 includes a patterning process, such as lithography and an etching process. The etching process may include a dry etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), inductive coupled plasma etching (ICP), a suitable etching process, or a combination thereof.

[0076] Then, if Figure 4A and Figure 4B As shown, a spacer material layer 131 is formed on the contact opening 120 and the hard mask layer 110. In some embodiments, the spacer material layer includes a dielectric material including a nitride or an oxide. In some embodiments, the spacer material layer 131 can be formed by a deposition process as described above.

[0077] In one embodiment, atomic layer deposition (ALD) is used to conformally deposit silicon nitride as the spacer material layer, which can achieve a denser effect and is not easily etched by subsequent etchants.

[0078] Then, if Figure 5A and Figure 5B As shown, the spacer material layer 131 on the bottom of the contact opening 120 and the hard mask layer 110 is removed, and the remaining spacer material layer 131 on the sidewall of the contact opening 120 serves as a pair of spacers 132. In some embodiments, the removal of the spacer material layer 131 includes an anisotropic etching process, including, for example, using the aforementioned dry etching process.

[0079] Then, if Fig. 6A and Figure 6B As shown, a conductive material 133 is formed on the bottom of the contact opening 120, the spacer 132 and the hard mask layer 110. In some embodiments, the conductive material 133 includes doped polysilicon, metal, or metal nitride. In some embodiments, the formation of the conductive material 133 includes using the aforementioned deposition process, so it is not repeated here.

[0080] In one embodiment, the conductive material 133 is polysilicon with doping to reduce the contact resistance with the subsequently formed bit line. The doping may include n-type or p-type dopants, such as nitrogen, arsenic, phosphorus, antimony ions or boron, aluminum, gallium, indium, boron trifluoride ions (BF 3+ ).

[0081] Then, if Fig. 7A and Figure 7B As shown, a portion of the hard mask layer 110, the conductive material 133 and the spacer 132 are removed, and the remaining hard mask layer 110 is used as the cap layer 110', the remaining conductive material 133 is used as the contact 134, and the remaining spacer 132 is used as the spacer 136. Specifically, the second oxide layer 116, the conductive material 133 and the spacer 132 on the nitride layer 114 are removed, so that the remaining nitride layer 114, the conductive material 133 and the spacer 132 are coplanar. Fig. 7A and Figure 7B In the embodiment, the cap layer 110', the spacer 136 and the top surface of the contact 134 are flush. In some embodiments, the removal includes performing chemical mechanical polishing (CMP).

[0082] because Figure 3A The contact opening 120 formed in FIG. 1 (a cross-sectional view along the first direction D1) is located in the active region 102A between the isolation components 104. Fig. 7A The spacers 136 in FIG. 1 are also located in the active region 102A between the isolation features 104 and do not cross over to the isolation region 102B. Fig. 7A In the embodiment, the contact 134 is laterally spaced apart from the active region 102A in the semiconductor substrate 102 by a pair of spacers 136 to prevent leakage current.

[0083] because Figure 3BOne side of the contact opening 120 formed in the cross-sectional view along the second direction D2 is located between the edges of a word line 106. Figure 7B The spacer 136 in is also located between the edges of a word line 106 and does not extend beyond the edge of the word line 106. Figure 7B In the embodiment, the spacer 136 is disposed directly above the word line 106 and corresponds to the word line 106. Specifically, along the vertical direction Z, the spacer 136 is separated from the word line 106 by the protection layer 108.

[0084] In some embodiments, the ratio of the width WC of the contact 134 to the width WS of the spacer 136 is approximately between 2 and 10. When the ratio is less than 2, the contact area of ​​the contact 134 is too small due to the thickness of the spacer 136, which may easily increase the contact resistance. When the ratio is greater than 10, the contact 134 and the capacitor contact (not shown) formed subsequently are too close due to the thickness of the spacer 136, which may easily cause a short circuit.

[0085] At this time, you can return to Figure 1 The contact 134 and the spacer 136 surrounding the contact 134 can be produced by the aforementioned process. That is, the spacer 136 is disposed on the entire sidewall of the contact. Figure 4A and Figure 4B In the figure, the spacer material layer 131 is formed on the contact opening 120 in the first direction D1 and the second direction D2 at the same time. Therefore, in this embodiment, the thickness of the spacer 136 in the first direction D1 and the second direction D2 are the same.

[0086] Next, refer to Figure 8 . Figure 8 FIG. 2 is a top view schematically showing a semiconductor memory structure 100 according to some embodiments of the present invention. Figure 1 , Figure 8 The relative positions of the dielectric liner 150, the contact 134, the spacer 136, and the capacitor contact 170 are shown after the subsequent formation of the dielectric liner 150. It should be noted that Figure 8 Only some components of the dynamic random access memory (DRAM) are shown to simplify the diagram. Figure 8 The cross-sectional schematic diagrams shown by the section line AA′ and the section line BB′ are used to facilitate explaining the method of forming the semiconductor memory structure.

[0087] Figures 9A-20A and Figure 9B-Figure 20B According to some embodiments of the present invention, Figure 2A-Figure 7A and Figure 2B-Figure 7B The cross-sectional views of the semiconductor memory structure 100 at different stages are shown. Figures 9A-20Aand Figure 9B-Figure 20B The cross-sectional diagrams are respectively along Figure 1 The cross-sectional view is taken along the section line AA′ (the first direction D1) and the section line BB′ (the second direction D2), which may sometimes be referred to as the cross-sectional view in the first direction and the cross-sectional view in the second direction, respectively.

[0088] Continue Fig. 7A and Figure 7B ,like Fig. 9A and Fig. 9B As shown, a bit line stack layer 140 is formed on the cap layer 110'. In some embodiments, the bit line stack layer 140 includes conductive layers 141 and 142 and dielectric layers 143, 144 and 145. In some embodiments, the conductive layers 141 and 142 include doped polysilicon, metal, or metal nitride, such as tungsten (W), titanium (Ti) and titanium nitride (TiN). In some embodiments, the dielectric layers 143, 144 and 145 include nitride or oxide, such as silicon nitride or silicon oxide.

[0089] In a specific embodiment, the uppermost dielectric layer 145 is made of silicon oxide, while the other dielectric layers 143 and 144 are made of silicon nitride to prevent the underlying film layers (eg, the conductive layers 141 and 142 ) from being damaged.

[0090] In some embodiments, the formation of the bit line stack layer 140 includes the deposition process as described above, and thus will not be described in detail herein.

[0091] Then, if Fig. 10A and Fig. 10B As shown, the bit line stack layer 140 is patterned by a patterning process to form a bit line 140'. Specifically, the conductive layers 141 and 142 and the dielectric layers 143, 144 and 145 in the bit line stack layer 140 are etched to form conductive patterns 141' and 142' and dielectric patterns 143', 144' and 145'.

[0092] Next, you can pair Figures 11A-14A and Figure 11B-Figure 14B , forming a dielectric liner 150 (shown in Fig.14A ) on the cap layer 110' and the bit line 140' to isolate the bit line 140' from a capacitor contact formed subsequently.

[0093] First, in Figures 11A-12A and Figure 11B-Figure 12B In the process, a nitride material liner 151 is first conformally deposited on the sidewalls and top surfaces of the cap layer 110 ′ and the bit line 140 ′ using a deposition process, and then an oxide material liner 153 is conformally deposited on the nitride material liner 151 using a deposition process.

[0094] Then, in Fig.13AIn the embodiment, the nitride material liner 151 and the oxide material liner 153 are etched back, so that the remaining nitride material liner 151 and the oxide material liner 153 can be used as the nitride liner 152 and the oxide liner 154 respectively. In this embodiment, the top surface of the nitride liner 152 and the oxide liner 154 is flush with the top surface of the word line 140'. Fig. 13B In the embodiment, the nitride material liner 151 and the oxide material liner 153 are removed, and only the bit line 140' remains.

[0095] Afterwards, in Fig.14A and Fig. 14B In the embodiment, a nitride liner 156 is conformally deposited on the nitride liner 152 , the oxide liner 154 , and the word line 106 using a deposition process.

[0096] It should be noted that in Fig.14A In the figure, with the bit line 140' as the center, from the inside to the outside are the nitride liner 152, the oxide liner 154 and the nitride liner 156. The oxide liner 154 is sandwiched between the two nitride liners 152 and 154, so as to prevent parasitic capacitance between the bit line 140' and the capacitor contact (not shown) formed subsequently. In an alternative embodiment, the oxide liner 154 can also be replaced by an air gap.

[0097] In some embodiments, since the bit line 140' and the contact opening 120 use inverse mask patterns, the widths of the two are substantially the same. That is, the sidewalls of the spacer 136 are substantially flush with the sidewalls of the bit line 140'. Fig.14A and Fig. 14B In FIG. 1 , along the first direction, it can be seen that the spacer 136 is located inside the dielectric liner 150 .

[0098] In some embodiments, nitride liners 152 and 156 include silicon nitride and oxide liner 154 includes silicon oxide. In some embodiments, the deposition process is similar to that described above and thus will not be described again.

[0099] In a comparative embodiment, in order to form a spacer separating a contact and a capacitor contact, after forming the contact and the bit line, it is necessary to additionally etch both sides of the contact and form a groove so that both sides of the contact are exposed due to the groove; an oxide layer is formed by an oxidation process; a nitride is formed on the oxide layer; phosphoric acid is used to remove excess nitride and the remaining nitride is used as a spacer before forming a dielectric liner. However, the process of the above method will affect the profile of both sides of the contact because both sides of the contact are exposed, and the use of an additional oxidation process increases the cost and process complexity. In addition, when phosphoric acid is used to remove the excess spacer, the bit line (such as tungsten) is easily damaged, thereby reducing the yield of the semiconductor memory structure.

[0100] In contrast, the embodiment of the present invention can directly form the dielectric liner 150 after forming the contact 134 and the bit line 140', which not only saves the step of etching the two sides of the contact, but also does not expose the sidewall of the contact 134, and saves the step of oxidation process, thereby simplifying the process steps and saving costs. Furthermore, since the spacer is formed before the contact is formed in the embodiment of the present invention, it is not necessary to use phosphoric acid to remove the excess nitride in order to form the spacer after the contact is formed, and the conductive pattern 141' or 142' in the bit line 140' can be prevented from being damaged.

[0101] Next, you can pair Figures 15A to 20A and Figure 15B - Figure 20B , forming a capacitor contact 170 on the semiconductor substrate 102 and on both sides of the bit line 140' to facilitate the subsequent formation of a capacitor (not shown). In some embodiments, the capacitor contact 170 includes conductive layers 172 and 176, and a silicide layer 174 located between the conductive layers 172 and 176.

[0102] It should be noted that in Figure 15B - Figure 20B There is no significant structural change in the cross section, so this paper will focus on the description of Figures 15A to 20A cross-sectional structure.

[0103] exist Fig.15A In the embodiment, an etch-back process is used to etch back the cap layer 110' and the semiconductor substrate 102 along the sidewalls of the dielectric liner 150 to form an opening 160. The lithography and etching processes used in this embodiment are similar to those described above, and thus will not be described in detail herein.

[0104] exist Fig.16A In the process, a conductive material 171 is formed in the opening 160 and on the semiconductor substrate 102. In some embodiments, the conductive material 171 includes doped polysilicon, metal, or metal nitride.

[0105] exist Fig.17A In the embodiment, the conductive material 171 is etched back to form a conductive layer 172. Fig.18A In the embodiment of the present invention, a silicide layer 174 is formed on the conductive layer 172. In some embodiments, the silicide layer 174 includes cobaltized silicon (CoSi) to reduce contact resistance. The formation of the silicide layer 174 includes depositing a metal (e.g., cobalt) on the conductive layer 172, performing an annealing process on the metal, and then removing the unreacted portion of the metal using a wet etching process to form the silicide layer 174.

[0106] exist Fig.19A In the embodiment, a conductive material 175 is formed on the silicide layer 174. In some embodiments, the conductive material 175 includes doped polysilicon, metal, or metal nitride. Fig. 20AIn the process, the conductive material 175 is etched back to form a conductive layer 176 .

[0107] In some embodiments, the spacer 136, the cap layer 110' and the capacitor contact 170 extend outward from the contact 134. That is, the contact 134 is laterally spaced apart from the capacitor contact 170 by the spacer 136 and the cap layer 110' to more effectively prevent leakage current.

[0108] In some embodiments, the semiconductor substrate 102 below the contact 134 has a doped region (not shown) that can serve as a source, and the semiconductor substrate 102 below the capacitor contact 170 also has a doped region (not shown) that can serve as a drain. Figure 8 In any active region 102A extending along the third direction D3, the arrangement order is capacitor contact 170, word line 106, contact 134, word line 106, capacitor contact 170, which can be used as drain, gate, source, gate, drain respectively. In other words, two sets of transistor structures in the active region 102A share the same source, and the layout can be more effectively utilized to save manufacturing costs.

[0109] It should be understood that after forming the capacitor contact 170 , additional components such as capacitors, metal layers, etc. may still be formed to complete the fabrication of a memory element such as a dynamic random access memory (DRAM).

[0110] In summary, the embodiments of the present invention can avoid damaging the bit line by etching the spacer with phosphoric acid in the process of forming the contact, bit line, and spacer by forming the spacer, contact, and bit line in the order of forming the contact, bit line, and also save the step of additional recessed etching. In addition, the embodiments of the present case can more effectively isolate the contact and the capacitor contact by the spacer. Therefore, the reliability and manufacturing yield of the semiconductor memory device are improved.

[0111] Although the present invention is disclosed as above with the aforementioned embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the scope of protection of the claims of the present invention.

Claims

1. A method for forming a semiconductor memory structure, characterized in that: include: Providing a semiconductor substrate, wherein a pair of word lines are embedded in an active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction; forming a hard shielding layer on the semiconductor substrate; Corresponding to the pair of word lines, forming a contact opening through the hard shield layer and a portion of the semiconductor substrate; forming a pair of spacers on sidewalls of the contact opening; Filling a conductive material into the contact opening to form a contact; forming a bit line directly above the contact and the pair of spacers, wherein the bit line extends along a second direction, wherein the first direction is perpendicular to the second direction; forming a dielectric liner on the sidewall of the bit line, wherein in the first direction on a cross section along the first direction, the pair of spacers are located inside the dielectric liner, wherein forming the dielectric liner comprises: Taking the bit line as the center, forming a nitride liner, an oxide liner and another nitride liner from the inside out, wherein the oxide liner is sandwiched between the nitride liner and the another nitride liner; and A capacitor contact is formed on the sidewall of the dielectric liner and on the hard shield layer.

2. The method for forming a semiconductor memory structure according to claim 1, wherein: After the step of forming the bit line and before the step of forming the dielectric liner, the sidewalls of the contacts are not exposed.

3. A semiconductor memory structure, characterized in that: include: A semiconductor substrate having an active region; a pair of word lines embedded in the active region of the semiconductor substrate, wherein the pair of word lines extend along a first direction; a cap layer, disposed on the semiconductor substrate; a contact member, passing through the cap layer and partially disposed in the semiconductor substrate; a pair of spacers disposed on sidewalls of the contact and corresponding to the pair of word lines; a bit line extending along a second direction, wherein the first direction is perpendicular to the second direction, wherein in a cross section in the first direction, the bit line is disposed directly above the contact and the pair of spacers; a dielectric liner disposed on the sidewall of the bit line, wherein the dielectric liner includes a nitride liner, an oxide liner and another nitride liner in order from the inside to the outside with the bit line as the center, wherein the oxide liner is sandwiched between the nitride liner and the another nitride liner, wherein in the first direction on the cross section along the first direction, the pair of spacers are located inside the dielectric liner; and A capacitor contact is disposed on the sidewall of the dielectric liner and on the cover layer.

4. The semiconductor memory structure according to claim 3, characterized in that: In a cross section along the second direction, the pair of spacers does not exceed an edge of the word line.

5. The semiconductor memory structure according to claim 3, characterized in that: In a cross section along the second direction, the pair of spacers is disposed directly above the pair of word lines.

6. The semiconductor memory structure according to claim 3, characterized in that: The semiconductor substrate further includes an isolation region surrounding the active region, and in a cross section along the first direction, the pair of spacers are located in the active region between the isolation regions and do not cross over to the isolation regions.

7. The semiconductor memory structure according to claim 3, characterized in that: The pair of spacers is disposed on the entire sidewall of the contact.

8. The semiconductor memory structure according to claim 3, characterized in that: Also includes: The contact is laterally spaced apart from the capacitor contact by the pair of spacers and the capping layer.

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