Heat dissipation and manufacturing method of semiconductor device

Abstract

This disclosure relates to heat dissipation and manufacturing methods of semiconductor devices. A semiconductor device with improved heat dissipation and a method for forming the same are disclosed. In one embodiment, a device includes a first transistor structure; a front interconnect structure located on the front side of the first transistor structure, the front interconnect structure including front conductive lines; a rear interconnect structure located on the rear side of the first transistor structure, the rear interconnect structure including rear conductive lines having a linewidth greater than that of the front conductive lines; and a first heat dissipation substrate coupled to the rear interconnect structure.

Description

Technical Field

[0001] This disclosure relates to heat dissipation and manufacturing methods for semiconductor devices. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously reducing the minimum feature size and increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a first transistor structure; a front interconnect structure located on the front side of the first transistor structure, the front interconnect structure including front conductive lines; a rear interconnect structure located on the rear side of the first transistor structure, the rear interconnect structure including rear conductive lines having a linewidth greater than that of the front conductive lines; and a first heat dissipation substrate coupled to the rear interconnect structure.

[0005] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material includes thinning a back side of the first substrate; replacing the first epitaxial material with a first back-side via, the first back-side via being electrically coupled to a first source / drain region of the first transistor; forming a back-side interconnect structure over the first back-side via opposite to the first source / drain region; and coupling a first heat-dissipating substrate to the back-side interconnect structure opposite to the first back-side via.

[0006] According to one aspect of this disclosure, a method of manufacturing a semiconductor device is provided, comprising: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material includes thinning a back side of the first substrate; replacing the first epitaxial material with a first back-side via, the first back-side via being electrically coupled to a first source / drain region of the first transistor; forming a back-side interconnect structure over the first back-side via opposite to the first source / drain region; and coupling a first heat-dissipating substrate to the back-side interconnect structure opposite to the first back-side via. Attached Figure Description

[0007] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field-effect transistor (nanoFET) is shown in a three-dimensional view according to some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A, Figure 22B , Figure 22C , Figure 23A , Figure 23B , Figure 23C , Figure 24A , Figure 24B , Figure 24C , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 27C , Figure 28A , Figure 28B , Figure 28C , Figure 29A , Figure 29B , Figure 29C , Figure 30A , Figure 30B , Figure 30C , Figure 31A , Figure 31B and Figure 31C This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0012] Various embodiments provide semiconductor devices with improved heat dissipation and methods of forming the same. The semiconductor device may include a front-side interconnect structure (also referred to as a back-end (BEOL) interconnect structure) and a rear-side interconnect structure (also referred to as a buried power network (BPN)) located on opposite sides of a transistor structure. Providing a rear-side interconnect structure reduces the number of layers required for the front-side interconnect structure, and the rear-side interconnect structure may have wider lines than the front-side interconnect structure, both of which provide improved heat dissipation through the front-side and rear-side interconnect structures. In some embodiments, the front-side interconnect structure may be coupled to a heat sink, and the rear-side interconnect structure may be coupled to a substrate. The substrate may include embedded fluid channels and can dissipate heat through both the heat sink and the substrate. In some embodiments, the front-side interconnect structure may be coupled to the substrate, and the rear-side interconnect structure may be coupled to a heat sink. Heat can be dissipated through the heat sink. Providing a rear-side interconnect structure and dissipating heat through both the rear-side and front-side interconnect structures improves heat dissipation, improves device performance, and reduces device defects.

[0013] The embodiments are described below in a specific context (i.e., including dies containing nanoFETs). However, various embodiments can be applied to dies that include other types of transistors (e.g., FinFETs, planar transistors, etc.) that replace or combine with nanoFETs.

[0014] Figure 1 Examples of nanoFETs (e.g., nanowire FETs, nanosheet FETs, etc.) in three-dimensional views according to some embodiments are shown. The nanoFET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) on a fin 66 of a substrate 50 (e.g., a semiconductor substrate). The nanostructure 55 serves as the channel region of the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, and the fins 66 may protrude above the isolation regions 68 between adjacent isolation regions 68. Although the isolation regions 68 are described and shown as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of the fin 66 is shown as being a single continuous material with the substrate 50, the bottom portion of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0015] A gate dielectric layer 100 is located on the top surface and sidewalls of fin 66, and along the top surface, sidewalls, and bottom surface of nanostructure 55. A gate electrode 102 is located on the gate dielectric layer 100. An epitaxial source / drain region 92 is disposed on fin 66, on the opposite side of the gate dielectric layer 100 and the gate electrode 102.

[0016] Figure 1 Reference cross sections used in the following figures are further illustrated. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in a direction, for example, perpendicular to the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. Cross section B-B' is parallel to cross section A-A' and extends through the epitaxial source / drain regions 92 of the multiple nanoFETs. Cross section C-C' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the nanoFET fin 66 and in a direction, for example, the current flow direction between the epitaxial source / drain regions 92 of the nanoFET. These reference cross sections are referenced in subsequent figures for clarity.

[0017] Some of the embodiments discussed herein are discussed in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are considered for use with planar devices (e.g., planar FETs) or fin field-effect transistors (FinFETs).

[0018] Figures 2 to 31C This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A and Figure 31A It shows Figure 1 The reference section A-A' is shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B and Figure 31B It shows Figure 1 The reference section B-B' is shown in the figure. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 11D , Figure 12C , Figure 12E , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C , Figure 21C , Figure 22C , Figure 23C , Figure 24C , Figure 25C , Figure 26C , Figure 27C , Figure 28C , Figure 29C , Figure 30C and Figure 31C It shows Figure 1 The reference section C-C' shown in the figure.

[0019] exist Figure 2A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which can be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate (typically a silicon or glass substrate). Other substrates can also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 can include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide indium, and / or gallium indium arsenide; or combinations thereof.

[0020] Substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors or n-type nanoFETs. The p-type region 50P can be used to form p-type devices, such as PMOS transistors or p-type nanoFETs. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0021] Further in Figure 2 In this process, a multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the second semiconductor layers 53 will be removed and the first semiconductor layers 51 will be patterned to form channel regions of the nanoFET in the n-type region 50N and the p-type region 50P. In such an embodiment, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously.

[0022] In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the p-type region 50P. In some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the p-type region 50P. In some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P.

[0023] For illustrative purposes, the multilayer stack 64 is shown as comprising three first semiconductor layers 51 and three second semiconductor layers 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In some embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for p-type nanoFETs (e.g., silicon germanium). The second semiconductor layer 53 may be formed of a second semiconductor material suitable for n-type nanoFETs (e.g., silicon, silicon carbide, etc.). For illustrative purposes, the multilayer stack 64 is shown as having a bottom first semiconductor layer 51 formed of a first semiconductor material. In some embodiments, the multilayer stack 64 may be formed as having a bottom second semiconductor layer 53 formed of a second semiconductor material.

[0024] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity relative to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material. This allows the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material. This allows the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0025] exist Figure 3In this process, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0026] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern the fins 66 and nanostructures 55. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, a smaller pitch than that achievable using a single direct photolithography process in other ways. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can subsequently be used to pattern the fins 66 and nanostructures 55.

[0027] Figure 3 Fins 66 and nanostructures 55 in n-type region 50N and p-type region 50P are shown, and for illustrative purposes they have substantially the same width. In some embodiments, the width of the fins 66 and nanostructures 55 in n-type region 50N may be greater than or less than the width of the fins 66 and nanostructures 55 in p-type region 50P. Furthermore, although each of the fins 66 and nanostructures 55 is shown generally as having a uniform width, in some embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls. Thus, the width of each fin 66 and / or nanostructure 55 may increase continuously in the direction toward the substrate 50. In such embodiments, each nanostructure 55 in a vertical stack may have a different width and may be trapezoidal in shape.

[0028] exist Figure 4In the substrate 50, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66, and the nanostructure 55, and between adjacent fins 66 and nanostructures 55. The insulating material can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) can be formed along the surfaces of the substrate 50, the fin 66, and the nanostructure 55. A filler material, such as the filler material discussed above, can then be formed on the liner.

[0029] The removal process is then applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back, or combinations thereof, can be used. The planarization process exposes the nanostructure 55 such that, after the planarization process is completed, the nanostructure 55 and the top surface of the insulating material are flush.

[0030] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the nanostructures 55 and fins 66 in the n-type region 50N and p-type region 50P protrude from between adjacent STI regions 68. The top surface of the STI region 68 can have a flat surface, a convex surface, a recessed surface (e.g., a dish shape), or a combination thereof, as shown. The top surface of the STI region 68 can be formed as flat, convex, and / or recessed by appropriate etching. The STI regions 68 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the nanostructures 55). Figure 4 As shown, the top surface of the STI region 68 may be located above the top surface of the fin 66. However, in some embodiments, the top surface of the STI region 68 may be flush with or below the top surface of the fin 66. In some embodiments, the removal of oxides using dilute hydrofluoric acid (dHF) can be used to etch back the insulating material.

[0031] The above regarding Figures 2 to 4The described process is merely one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structure may include alternating layers of semiconductor materials (e.g., a first semiconductor material and a second semiconductor material) discussed above. In some embodiments of epitaxial growth of the epitaxial structure, the epitaxial growth material can be doped in situ during growth, which avoids prior and / or subsequent implantation. In some embodiments, in-situ doping and implantation doping can be used together.

[0032] Furthermore, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as containing the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials, or may be formed in different orders in the p-type region 50P and the n-type region 50N.

[0033] Further in Figure 4 In this process, suitable wells (not shown separately) can be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P can be achieved using photoresist or other masks (not shown separately). For example, photoresist can be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can act as a mask to prevent n-type impurities from being implanted into n-type regions 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration ranging from about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0034] After or before implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted into the region, with a concentration ranging from approximately 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 After implantation, the photoresist can be removed, for example, through an acceptable ashing process.

[0035] Following implantation into the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which can avoid implantation. In some embodiments, in-situ doping and implantation doping can be used together.

[0036] exist Figure 5 In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, or combinations thereof. The dummy dielectric layer 70 can be deposited or thermally grown according to acceptable techniques.

[0037] A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 may be formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials that have high etch selectivity compared to the etching of the STI region 68.

[0038] A mask layer 74 may be deposited over the dummy gate layer 72. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that it covers the STI region 68. Therefore, the dummy dielectric layer 70 may extend between the dummy gate layer 72 and the STI region 68.

[0039] Figures 6A to 31C Various additional steps in manufacturing the embodiment device are shown. Figures 6A to 31C Features in the n-type region 50N or the p-type region 50P are shown. Figures 6A to 6C In this process, acceptable photolithography and etching techniques can be used to process mask layer 74 (see...). Figure 5 The mask 78 is patterned to form a dummy gate layer 72 and a dummy dielectric layer 70. The pattern of the mask 78 can be transferred to the dummy gate layer 72 and the dummy gate dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers the corresponding channel region of the nanostructure 55. The pattern of the mask 78 can be used to physically separate each dummy gate 76 from its adjacent dummy gate 76. The longitudinal direction of the dummy gate 76 can be perpendicular to the longitudinal direction of the corresponding fin 66 and the nanostructure 55.

[0040] exist Figures 7A to 7C In, respectively in Figures 6A to 6C A first spacer layer 80 and a second spacer layer 82 are formed on top of the structure shown. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figures 7A to 7C In this process, a first spacer layer 80 is formed on the following structures: the top surface of the STI region 68; the top surface and sidewalls of the nanostructure 55 and the mask 78; and the sidewalls of the dummy gate 76, the dummy gate dielectric 71, and the fin 66. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc., using techniques such as thermal oxidation, or deposited by CVD, ALD, etc. The second spacer layer 82 can be formed from a material having a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and can be deposited by CVD, ALD, etc.

[0041] Implantation for lightly doped source / drain (LDD) regions (not shown separately) can be performed after the formation of the first spacer layer 80 and before the formation of the second spacer layer 82. In embodiments with different device types, this is similar to the above. Figure 4The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an appropriate type (e.g., p-type) impurity into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The impurity concentration of the lightly doped source / drain regions can be approximately 1 x 10⁻⁶. 15 atoms / cm 3 To approximately 1x10 19 atoms / cm 3 Within a certain range. Annealing can be used to repair injection damage and activate injected impurities.

[0042] exist Figures 8A to 8C In this process, a first spacer layer 80 and a second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used for self-alignment of the subsequently formed source / drain regions and to protect the sidewalls of the fin 66 and / or nanostructure 55 during subsequent processing. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when the second spacer layer 82 is patterned, and the second spacer layer 82 can act as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer. The remaining portion of the second spacer layer 82 forms the second spacer 83, such as Figure 8B As shown. Afterwards, as... Figure 8B and Figure 8C As shown, when etching the exposed portion of the first spacer layer 80, the second spacer 83 acts as a mask to form the first spacer 81.

[0043] like Figure 8B As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the nanostructure 55 and the fin 66. Figure 8CAs shown, in some embodiments, the second spacer layer 82 can be removed from the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy gate dielectric 71. In other embodiments, a portion of the second spacer layer 82 may remain on the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric 71.

[0044] It should be noted that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different step sequences can be used (e.g., the first spacer 81 can be patterned before depositing the second spacer layer 82), additional spacers can be formed and removed, and so on. Furthermore, different structures and steps can be used to form n-type devices and p-type devices.

[0045] exist Figures 9A to 9C In this process, a first recess 86 and a second recess 87 are formed in nanostructures 55, fins 66, and substrate 50. Epitaxial material, which can be used as source / drain regions and / or dummy regions, is then formed in the first recess 86 and the second recess 87. The first recess 86 may extend through the first nanostructures 52A-52C and the second nanostructures 54A-54C and into the fins 66 and substrate 50. In some embodiments, the top surface of the STI region 68 may be flush with the bottom surface of the first recess 86. In some embodiments, the top surface of the STI region 68 may be higher or lower than the bottom surface of the first recess 86. The second recess 87 may extend through the first nanostructures 52A-52C and the second nanostructures 54A-54C and into the fins 66 and substrate 50, with a depth greater than that of the first recess 86. The bottom surface of the second recess 87 may be set lower than the bottom surface of the first recess 86 and the top surface of the STI region 68.

[0046] The first recess 86 and the second recess 87 can be formed by etching the nanostructure 55, fin 66, and substrate 50 using an anisotropic etching process (e.g., RIE, NBE, etc.). During the etching process for forming the first recess 86 and the second recess 87, a first spacer 81, a second spacer 83, and a mask 78 mask portions of the nanostructure 55, fin 66, and substrate 50. Each layer of the nanostructure 55, fin 66, and substrate 50 can be etched using a single etching process or multiple etching processes. A timed etching process can be used to stop etching after the first recess 86 and the second recess 87 have reached the desired depth. The second recess 87 can be etched before or after etching the first recess 86 using the same process as for etching the first recess 86 and additional etching processes. In some embodiments, the area corresponding to the first recess 86 can be masked during the additional etching process of the second recess 87.

[0047] exist Figures 10A to 10C In the process, the portions of the sidewalls of the layer formed by the first semiconductor material (e.g., the first nanostructure 52) in the multilayer stack 64 exposed by the first recess 86 and the second recess 87 are etched to form sidewall recesses 88 in the n-type region 50N and the p-type region 50P. Although in Figure 10C The sidewalls of the adjacent sidewall recesses 88 of the first nanostructure 52 are shown as straight, but the sidewalls can be recessed or convex. The sidewalls can be etched using an isotropic etching process (e.g., wet etching, etc.). In embodiments where the second nanostructure 54 comprises, for example, Si or SiC and the first nanostructure 52 comprises, for example, SiGe, a wet or dry etching process using hydrogen fluoride, another fluorine-based etchant, etc., can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N and the p-type region 50P.

[0048] exist Figures 11A to 11D In the middle, a first internal spacer 90 is formed in the sidewall recess 88. This can be achieved by... Figures 10A to 10C An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86 and the second recess 87, and the first nanostructure 52 will be replaced by the corresponding gate structure.

[0049] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, etc. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material such as a low-k material with a k-value less than about 3.5 can be used. The internal spacer layer can then be anisotropically etched to form the first internal spacer 90. Although the outer wall of the first internal spacer 90 is shown flush with the sidewall of the second nanostructure 54, the outer wall of the first internal spacer 90 may extend beyond or be recessed from the sidewall of the second nanostructure 54.

[0050] Furthermore, although the outer wall of the first internal spacer 90 is in Figure 11C The middle section is shown as straight, but the outer wall of the first inner spacer 90 may be recessed or convex. As an example, Figure 11D An embodiment is shown in which the sidewalls of the first nanostructure 52 are recessed, the outer sidewalls of the first internal spacer 90 are recessed, and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54. The internal spacer layer can be etched using anisotropic etching processes (e.g., RIE, NBE, etc.). The first internal spacer 90 can be used to prevent subsequent etching processes (e.g., etching processes for forming the gate structure) from affecting the subsequently formed source / drain regions (e.g., epitaxial source / drain regions 92, hereinafter referred to as...). Figures 12A to 12E The damage was caused by what is being discussed.

[0051] exist Figures 12A to 12E In the second recess 87, a first epitaxial material 91 is formed, and epitaxial source / drain regions 92 are formed in the first recess 86 and the second recess 87. In some embodiments, the first epitaxial material 91 in the second recess 87 may be a sacrificial material, which is subsequently removed to form a rear via (e.g., a rear via 130, referred to below). Figures 26A to 26C (Discussed). In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance.

[0052] like Figure 12C As shown, epitaxial source / drain regions 92 are formed in the first recess 86 and the second recess 87, such that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the first nanostructure 52 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 do not short-circuit with the subsequently formed gate of the resulting nanoFET.

[0053] A first epitaxial material 91 can be grown such that the top surface of the first epitaxial material 91 is flush with the bottom surface of the first recess 86 (see...). Figures 11A to 11D The first epitaxial material 91 is flush with the top surface of the STI region 68. However, in some embodiments, the top surface of the first epitaxial material 91 may be set higher or lower than the top surface of the STI region 68. The first epitaxial material 91 can be epitaxially grown in the second recess 87 using processes such as CVD, ALD, VPE, MBE, etc. The first epitaxial material 91 may include any acceptable material, such as silicon germanium, etc. The first epitaxial material 91 may be formed by the substrate 50, the epitaxial source / drain region 92, and the dielectric layer (e.g., STI region 68 and second dielectric layer 125, hereinafter referred to as...). Figures 24A to 24C The material discussed has high etch selectivity in its formation. Therefore, the first epitaxial material 91 can be removed and replaced with a back-side via without significantly removing the epitaxial source / drain region 92, substrate 50, or STI region 68.

[0054] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 and the second recess 87 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile strain is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 92 can have a surface protruding from the corresponding upper surface of the nanostructure 55 and can have a facet.

[0055] The epitaxial source / drain region 92 in the p-type region 50P (e.g., PMOS region) can be formed by masking the n-type region 50N (e.g., NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in the first recess 86 and the second recess 87 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material that applies compressive strain to the second nanostructure 54, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 92 can also have a surface protruding from the corresponding surface of the nanostructure 55 and can have a facet.

[0056] The epitaxial source / drain region 92, the first nanostructure 52, the second nanostructure 54, the fin 66, and / or the substrate 50 can be implanted with dopants to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the source / drain region can be between approximately 1 x 10⁻⁶. 19 atoms / cm 3 1x10 21 atoms / cm 3 Between. The n-type and / or p-type impurities in the source / drain regions can be any impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0057] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has small facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 92 of the same nanoFET to merge, such as... Figure 12D As shown. In other embodiments, such as Figure 12B As shown, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated. Figure 12B and Figure 12D In the illustrated embodiment, a first spacer 81 may be formed extending to the top surface of the STI region 68 to prevent epitaxial growth. In some embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material and allow the epitaxial growth region to extend to the surface of the STI region 68.

[0058] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0059] Figure 12EOne embodiment is shown in which the sidewall of the first nanostructure 52 is a recessed surface, the outer sidewall of the first internal spacer 90 is a recessed surface, and the first internal spacer 90 is recessed from the sidewall of the second nanostructure 54. Figure 12E As shown, the epitaxial source / drain region 92 can be formed to contact the first internal spacer 90 and can extend beyond the sidewalls of the second nanostructure 54.

[0060] exist Figures 13A to 13C In, respectively in Figures 12A to 12C A first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is provided between the first ILD 96 and the epitaxial source / drain region 92, mask 78, first spacer 81, second spacer 83, and STI region 68. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has an etch rate different from that of the overlying first ILD 96.

[0061] exist Figures 14A to 14C In this process, a planarization process (e.g., CMP) can be performed to make the top surfaces of the first ILD 96 and CESL 94 flush with the top surface of the dummy gate 76 or mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, as well as a portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, within process variations, the top surfaces of the dummy gate 76, the first spacer 81, the first ILD 96, and CESL 94 can be flush with each other. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78, the first spacer 81, and CESL 94.

[0062] exist Figures 15A to 15CIn one or more etching steps, the dummy gate 76 and mask 78 (if present) are removed to form a third recess 98. A portion of the dummy gate dielectric 71 in the third recess 98 is also removed. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 76 at a faster rate than the first ILD 96, CESL 94, or the first spacer 81. Each third recess 98 exposes and / or covers a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanoFET. The portions of the nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy gate dielectric 71 can be used as an etch stop layer while the dummy gate 76 is etched. The dummy gate dielectric 71 can then be removed after the removal of the dummy gate 76.

[0063] exist Figures 16A to 16C In this process, the first nanostructure 52 is removed, thereby extending the third recess 98. The first nanostructure 52 can be removed by performing an isotropic etching process (e.g., wet etching) using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, substrate 50, STI region 68, first ILD 96, CESL 94, first spacer 81, and first internal spacer 90 remain relatively unetched compared to the first nanostructure 52. In embodiments where the second nanostructure 54 comprises, for example, Si or SiC and the first nanostructure 52 comprises, for example, SiGe, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to remove the first nanostructure 52.

[0064] exist Figures 17A to 17C In the third recess 98, a gate dielectric layer 100 and a gate electrode 102 are formed to replace the gate. The gate dielectric layer 100 is conformally deposited in the third recess 98. The gate dielectric layer 100 can be formed on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, CESL 94, first spacer 81, and STI region 68.

[0065] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric layer 100 may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. Methods for forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0066] A gate electrode 102 is deposited on the gate dielectric layer 100, and the remaining portion of the third recess 98 is filled. The gate electrode 102 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although a single-layer gate electrode 102... Figure 17A and Figure 17C As shown, however, gate electrode 102 may include any number of liner layers, any number of work function tuning layers, and filler material. Any combination of layers constituting gate electrode 102 may be deposited between adjacent layers in the second nanostructure 54.

[0067] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed by different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed by different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0068] After filling the third recess 98, a planarization process (e.g., CMP) can be performed to remove excess material from the gate dielectric layer 100 and gate electrode 102, where the excess material lies above the top surfaces of the first ILD 96, the first spacer 81, and CESL 94. The material of the gate electrode 102 and the remaining portion of the gate dielectric layer 100 thus form the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the “gate structure”.

[0069] exist Figures 18A to 18C In this process, the gate structures (including the gate dielectric layer 100 and the corresponding overlying gate electrode 102) are recessed, such that recesses are formed directly on each gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled into the recesses, followed by a planarization process to remove excess dielectric material extending over the first ILD 96, CESL 94, and the first spacer 81. Subsequently formed gate contacts (e.g., gate contact 114, hereinafter referred to...) Figure 20A and Figure 20C (Discussed) Penetrates the gate mask 104 to contact the top surface of the recessed gate electrode 102.

[0070] like Figures 18A to 18C As further shown, a second ILD 106 is deposited over the first ILD 96, CESL 94, and gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and can be deposited by any suitable method such as CVD, PECVD, etc.

[0071] exist Figures 19A to 19C In this process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a fourth recess 108, thereby exposing the surfaces of the epitaxial source / drain regions 92 and / or the gate structure. The fourth recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the fourth recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; the fourth recess 108 can be etched through the gate mask 104 using a second etching process; and the fourth recess 108 can be etched through the CESL 94 using a third etching process. A mask, such as a photoresist, can be formed and patterned on the second ILD 106 to mask portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process can over-etch, so that the fourth recess 108 can extend into the epitaxial source / drain regions 92 and / or the gate structure. The bottom surface of the fourth recess 108 may be flush with the top surface of the epitaxial source / drain region 92 and / or gate structure (e.g., at the same level, or at the same distance from the substrate 50), or lower than the top surface of the epitaxial source / drain region 92 and / or gate structure (e.g., closer to the substrate 50). Although Figure 19CThe fourth recess 108 is shown to expose the epitaxial source / drain region 92 and gate structure in the same cross section, but in some embodiments, the epitaxial source / drain region 92 and gate structure may be exposed in different cross sections, thereby reducing the risk of short circuits in the subsequently formed contacts.

[0072] After the fourth recess 108 is formed, a first silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium, etc.) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region. The metal may include nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited over the exposed portion of the epitaxial source / drain region 92, and then a thermal annealing process may be performed to form the first silicide region 110. Unreacted portions of the deposited metal are then removed by, for example, an etching process. Although the first silicide region 110 is referred to as a silicide region, it may also be a germanide region or a silicon-germanide region (e.g., a region containing silicon and germanium), etc. In one embodiment, the first silicide region 110 comprises TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0073] exist Figures 20A to 20C In this embodiment, source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recess 108. Source / drain contacts 112 and gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, source / drain contacts 112 and gate contacts 114 each include a barrier layer and a conductive material. Source / drain contacts 112 and gate contacts 114 are each electrically coupled to an underlying conductive feature (e.g., in the illustrated embodiment, the gate electrode 102 or the first silicide region 110 over the epitaxial source / drain region 92). Gate contact 114 is electrically coupled to the gate electrode 102, and source / drain contact 112 is electrically coupled to the first silicide region 110 over the epitaxial source / drain region 92. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process (e.g., CMP) can be performed to remove excess portions of the source / drain contacts 112 and gate contacts 114 located on the top surface of the second ILD 106.

[0074] The epitaxial source / drain region 92, the second nanostructure 54, and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) can be collectively referred to as the transistor structure 109. A first interconnect structure (e.g., front interconnect structure 120, hereinafter referred to as...) can be formed on the front side of the transistor structure 109. Figures 21A to 21C (as discussed), and a second interconnect structure (e.g., rear interconnect structure 140, hereinafter referred to) can be formed on the rear side of transistor structure 109. Figures 27A to 27C (As discussed). Although transistor structure 109 is described as including nano-FETs, other embodiments may include transistor structure 109 having different types of transistors (e.g., planar FETs, FinFETs, thin-film transistors (TFTs), etc.).

[0075] although Figures 20A to 20C Source / drain contacts 112 extending to each epitaxial source / drain region 92 are shown, but source / drain contacts 112 may be omitted from certain regions of the epitaxial source / drain regions 92. For example, as explained in more detail below, conductive features (e.g., rear vias or power rails) may subsequently be attached to the rear side of one or more epitaxial source / drain regions 92. For these particular epitaxial source / drain regions 92, source / drain contacts 112 may be omitted, or may be not electrically connected to any overlying conductive lines (e.g., first conductive feature 122, hereinafter referred to as...). Figures 21A to 21C The dummy contact (discussed).

[0076] Figures 21A to 27C Intermediate steps in forming a front-side interconnect structure and a rear-side interconnect structure on transistor structure 109 are illustrated. The front-side interconnect structure and the rear-side interconnect structure may each include conductive features electrically connected to transistor structure 109 (e.g., a nanoFET). Figures 21A to 27C The attached diagram ending with "A" shows the route along... Figure 1 The cross-sectional view of line A-A', and the attached figure ending with "B" show the view along... Figure 1 The cross-sectional view of line B-B', and the attached figure ending with "C" shows the view along... Figure 1 A cross-sectional view of line C-C'. Figures 21A to 27C The process steps described herein can be applied to both the n-type region 50N and the p-type region 50P. As described above, back-side conductive features (e.g., back-side vias or power rails) can be connected to one or more epitaxial source / drain regions 92. Therefore, source / drain contacts 112 can be optionally omitted from the epitaxial source / drain regions 92.

[0077] exist Figures 21A to 21CIn this process, a front-side interconnect structure 120 is formed on the second ILD 106. The front-side interconnect structure 120 may be referred to as a front-side interconnect structure because it is formed on the front side of the transistor structure 109 (e.g., the side of the transistor structure opposite to the substrate 50 on which the transistor structure 109 is formed).

[0078] The front-side interconnect structure 120 may include one or more first conductive features 122 formed in one or more stacked first dielectric layers 124. Each stacked first dielectric layer 124 may include a dielectric material, such as a low-k dielectric material, an ultra-low-k (ELK) dielectric material, etc. The first dielectric layer 124 may be deposited using appropriate processes (e.g., CVD, ALD, PVD, PECVD, etc.).

[0079] The first conductive feature 122 may include conductive lines and conductive vias in layers interconnecting the conductive lines. The conductive vias may extend through corresponding layers in the first dielectric layer 124 to provide vertical connections between the layers of conductive lines. The first conductive feature 122 may be formed by any acceptable process (e.g., damascene process, dual damascene process, etc.).

[0080] In some embodiments, the first conductive feature 122 may be formed using a damascene process, wherein a combination of photolithography and etching techniques is used to pattern the corresponding first dielectric layer 124 to form trenches corresponding to the desired pattern of the first conductive feature 122. An optional diffusion barrier layer and / or an optional adhesive layer may be deposited, followed by filling the trenches with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, and combinations thereof, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, cobalt, tungsten, ruthenium, and combinations thereof. In one embodiment, the first conductive feature 122 may be formed by depositing a seed layer of copper or a copper alloy and filling the trenches by electroplating. CMP processes, etc., may be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124 and planarize the surfaces of the first dielectric layer 124 and the first conductive feature 122 for subsequent processing.

[0081] Figures 21A to 21C The diagram illustrates four layers of first conductive features 122 and first dielectric layers 124 in a front-side interconnect structure 120. However, it should be understood that the front-side interconnect structure 120 may include any number of first conductive features 122 disposed in any number of first dielectric layers 124. The front-side interconnect structure 120 may be electrically connected to gate contacts 114 and source / drain contacts 112 to form functional circuitry. In some embodiments, the functional circuitry formed by the front-side interconnect structure 120 may include logic circuitry, memory circuitry, image sensor circuitry, etc.

[0082] exist Figures 22A to 22CIn this process, the carrier substrate 180 is bonded to the top surface of the front interconnect structure 120 via a first bonding layer 182A and a second bonding layer 182B (collectively referred to as bonding layers 182). The carrier substrate 180 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The carrier substrate 180 can provide structural support during subsequent processing steps and in the completed device.

[0083] In various embodiments, a suitable technique (e.g., dielectric-dielectric bonding, etc.) can be used to bond the carrier substrate 180 to the front interconnect structure 120. Dielectric-dielectric bonding may include depositing a first bonding layer 182A on the front interconnect structure 120. In some embodiments, the first bonding layer 182A comprises silicon oxide (e.g., high-density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. A second bonding layer 182B may similarly be an oxide layer formed on the surface of the carrier substrate 180 prior to bonding using, for example, CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may be used for the first bonding layer 182A and the second bonding layer 182B.

[0084] The dielectric-to-dielectric bonding process may further include applying a surface treatment to one or more of the first bonding layer 182A and the second bonding layer 182B. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.), which may be applied to one or more bonding layers 182. The carrier substrate 180 is then aligned with the front interconnect structure 120 and pressed together to initiate pre-bonding of the carrier substrate 180 with the front interconnect structure 120. Pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). After pre-bonding, an annealing process may be applied by, for example, heating the front interconnect structure 120 and the carrier substrate 180 to a temperature of about 170°C.

[0085] In addition, Figures 22A to 22C In this process, after the carrier substrate 180 is bonded to the front interconnect structure 120, the device can be flipped so that the rear side of the transistor structure 109 faces upward. The rear side of the transistor structure 109 can refer to the side opposite to the front side of the transistor structure 109.

[0086] exist Figures 23A to 23C In this process, a thinning process is applied to the back side of substrate 50. The thinning process may include planarization processes (e.g., mechanical polishing, CMP, etc.), etch-back processes, and combinations thereof. The thinning process can expose the surface of the first epitaxial material 91 opposite to the front interconnect structure 120. Furthermore, after the thinning process, a portion of substrate 50 may remain on top of transistor structure 109. Figures 23A to 23CAs shown, the back surfaces of the substrate 50, the first epitaxial material 91, the STI region 68, and the fin 66 can be flush with each other after the thinning process.

[0087] exist Figures 24A to 24C In this process, the remaining portions of fin 66 and substrate 50 are removed and replaced with a second dielectric layer 125. A suitable etching process can be used to etch fin 66 and substrate 50, such as an isotropic etching process (e.g., wet etching process), anisotropic etching process (e.g., dry etching process), etc. The etching process can be a process selective for the materials of fin 66 and substrate 50 (e.g., etching the materials of fin 66 and substrate 50 at a faster rate than the materials of STI region 68, gate dielectric layer 100, epitaxial source / drain region 92, first epitaxial material 91, and first internal spacer 90). After etching fin 66 and substrate 50, the surfaces of STI region 68, gate dielectric layer 100, epitaxial source / drain region 92, first epitaxial material 91, and first internal spacer 90 can be exposed.

[0088] Then, a second dielectric layer 125 is deposited on the back side of the transistor structure 109, in the recess formed by removing the fins 66 and the substrate 50. The second dielectric layer 125 can be deposited over the STI region 68, the gate dielectric layer 100, the epitaxial source / drain region 92, the first epitaxial material 91, and the first internal spacer 90. The second dielectric layer 125 can physically contact the surfaces of the STI region 68, the gate dielectric layer 100, the epitaxial source / drain region 92, the first epitaxial material 91, and the first internal spacer 90. The second dielectric layer 125 can be substantially similar to the second ILD 106, as described above regarding... Figures 18A to 18C As described above. For example, the second dielectric layer 125 can be formed of a material similar to the second ILD 106 and using a process similar to that of the second ILD 106. Figures 24A to 24C As shown, CMP processes and the like can be used to remove material from the second dielectric layer 125, so that the top surface of the second dielectric layer 125 is flush with the top surface of the STI region 68 and the first epitaxial material 91.

[0089] exist Figures 25A to 25CIn the process, the first epitaxial material 91 is removed to form the fifth recess 128, and a second silicide region 129 is formed in the fifth recess 128. The first epitaxial material 91 can be removed by a suitable etching process, which can be an isotropic etching process, such as a wet etching process. The etching process can have high etching selectivity for the material of the first epitaxial material 91. Therefore, the first epitaxial material 91 can be removed without significantly removing the material of the second dielectric layer 125, the STI region 68, or the epitaxial source / drain region 92. The fifth recess 128 can expose the sidewalls of the STI region 68, the rear surface of the epitaxial source / drain region 92, and the sidewalls of the second dielectric layer 125.

[0090] Then, a second silicide region 129 can be formed in the fifth recess 128 on the rear side of the epitaxial source / drain region 92. The second silicide region 129 can be similar to the first silicide region 110, as described above. Figures 19A to 19C For example, the second silicide region 129 may be formed of a material similar to the first silicide region 110 and formed using a process similar to that of the first silicide region 110.

[0091] exist Figures 26A to 26C In the fifth recess 128, a rear via 130 is formed. The rear via 130 can extend through the second dielectric layer 125 and the STI region 68, and can be electrically coupled to the epitaxial source / drain region 92 through the second silicide region 129. The rear via 130 can resemble the source / drain contact 112, as described above regarding... Figures 20A to 20C As described above. For example, the rear via 130 can be formed of a material similar to the source / drain contact 112 and using a process similar to that of the source / drain contact 112. The rear via 130 can include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, ruthenium, etc. A planarization process (e.g., CMP) can be performed to remove excess portions of the rear via 130 located above the top surface of the STI region 68 and the second dielectric layer 125.

[0092] exist Figures 27A to 27C In this process, a first conductive line 132 and a third dielectric layer 134 are formed. The first conductive line 132 and the third dielectric layer 134 can be formed over the rear via 130, the second dielectric layer 125, and the STI region 68. The third dielectric layer 134 can be formed of the same or similar material as the second ILD 106 and in the same or similar manner as the second ILD 106, as described above. Figures 18A to 18C As mentioned above.

[0093] A first conductive line 132 is formed in a third dielectric layer 134. Forming the first conductive line 132 may include, for example, patterning recesses in the third dielectric layer 134 using a combination of photolithography and etching processes. The pattern of the recesses in the third dielectric layer 134 may correspond to the pattern of the first conductive line 132. The first conductive line 132 is then formed by depositing a conductive material in the recesses. In some embodiments, the first conductive line 132 includes a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the first conductive line 132 includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. An optional diffusion barrier layer and / or an optional adhesive layer may be deposited before filling the recesses with the conductive material. Suitable materials for the barrier layer / adhesive layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, etc. The first conductive line 132 may be formed using, for example, CVD, ALD, PVD, electroplating, etc. The first conductive line 132 is electrically coupled to the epitaxial source / drain region 92 through the rear via 130 and the second silicide region 129. A planarization process (e.g., CMP, polishing, etch-back, etc.) can be performed to remove excess portions of the first conductive line 132 formed on the third dielectric layer 134.

[0094] In some embodiments, the first conductive line 132 is a rear power rail, which is a conductive line that electrically connects the epitaxial source / drain region 92 to a reference voltage, a power supply voltage, etc. Advantages are achieved by placing the power rail on the rear side of the resulting semiconductor die rather than the front side. For example, by including both the front interconnect structure 120 and the rear interconnect structure 140, heat generated in the transistor structure 109 can be dissipated from both sides of the transistor structure 109 through the front interconnect structure 120 and the rear interconnect structure 140. Specifically, heat can be dissipated through the first conductive feature 122 of the front interconnect structure 120 and the first conductive line 132 and the second conductive feature 136 of the rear interconnect structure 140.

[0095] By moving the power rails to the rear of transistor structure 109, the thickness T1 of front interconnect structure 120 can be reduced. Compared to conventional front interconnect structures, the thickness T1 of front interconnect structure 120 can be reduced by at least 50%, and the thickness T1 of front interconnect structure 120 can be in the range of about 0.5 μm to about 2 μm. Compared to conventional front interconnect structures which can have about 10 interconnect layers, the number of interconnect layers in front interconnect structure 120 can be reduced to about 6. Reducing the thickness of front interconnect structure 120 improves heat dissipation through front interconnect structure 120, and can result in heat dissipation through front interconnect structure 120 being approximately 150% of that through conventional front interconnect structures.

[0096] Furthermore, the width of the conductive features of the rear interconnect structure 140 can be greater than the width of the conductive features of the front interconnect structure 120 (e.g., at least twice the width of the conductive features of the front interconnect structure 120), and the thickness T2 of the rear interconnect structure 140 can be the same as or less than the thickness of the front interconnect structure 120. For example, the conductive features of the front interconnect structure 120 can have a minimum linewidth ranging from about 15 nm to about 45 nm, while the conductive features of the rear interconnect structure 140 can have a minimum linewidth ranging from about 30 nm to about 60 nm. The thickness T2 of the rear interconnect structure 140 can be in the range of about 0.5 μm to about 1 μm. The heat dissipated through the rear interconnect structure 140 may even be greater than the heat dissipated through the front interconnect structure 120. For example, the heat dissipation through the rear interconnect structure 140 can be approximately 300% of the heat dissipation through a conventional front interconnect structure. Therefore, the overall heat dissipation can be improved by approximately 450% compared to conventional devices through the front interconnect structure 120 and the rear interconnect structure 140.

[0097] Furthermore, the gate density of the nanoFET and / or the interconnect density of the front-side interconnect structure 120 can be increased. A wider power rail can be accommodated on the back side of the semiconductor die, thereby reducing resistance and improving the power delivery efficiency of the nanoFET. For example, the width of the first conductive line 132 can be at least twice the width of the first-stage conductive line (e.g., the first conductive feature 122) of the front-side interconnect structure 120.

[0098] The remainder of the rear interconnect structure 140 is formed over the third dielectric layer 134 and the first conductive line 132. The rear interconnect structure 140 may be referred to as a rear interconnect structure because it is formed on the rear side of the transistor structure 109 (e.g., the side of the transistor structure 109 opposite to the side where active devices are formed). The rear interconnect structure 140 may include the third dielectric layer 134 and the first conductive line 132.

[0099] The remainder of the rear interconnect structure 140 may include material and may be formed using the same or similar processes as those used for the front interconnect structure 120, as described above. Figures 21A to 21C Specifically, the rear interconnect structure 140 may include a stacked layer of second conductive features 136 formed in a fourth dielectric layer 138. The second conductive feature 136 may include wiring (e.g., wiring to and from subsequently formed contact pads and external connectors). The second conductive feature 136 may also be patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, etc. The embedded passive devices may be integrated with the first conductive line 132 (e.g., a power rail) to provide circuitry (e.g., power circuitry) on the rear side of the nanoFET.

[0100] exist Figures 28A to 28C In this process, carrier substrate debonding is performed to separate (or “debond”) carrier substrate 180 from rear interconnect structure 120. In some embodiments, debonding includes projecting light, such as laser or ultraviolet (UV) light, onto bonding layer 182, causing bonding layer 182 to decompose under the heat of the light, and carrier substrate 180 can be removed.

[0101] exist Figures 29A to 29C In the middle, flip Figures 28A to 28C The structure attaches a heat sink 160 to a front interconnect structure 120, a first substrate 170 to a rear interconnect structure 140, and a second substrate 190 to the first substrate 170. For example... Figures 29A to 29C As shown, the heat sink 160 can be attached to the first dielectric layer 124 and the first conductive feature 122. In some embodiments, the heat sink 160 may comprise materials such as silicon, glass, metal, polymer, etc. The heat sink 160 can be bonded to the front interconnect structure 120 by means of fusion bonding or the like. In some embodiments, the heat sink 160 can be bonded to the front interconnect structure 120 by dielectric-dielectric bonding without using any adhesive material (e.g., die attachment film). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the heat sink 160 onto the front interconnect structure 120. Pre-bonding is performed at a low temperature, such as room temperature (e.g., a temperature in the range of about 15°C to about 30°C). In some embodiments, an oxide (e.g., a natural oxide) is formed on the surfaces of the heat sink 160 and the front interconnect structure 120 facing each other and is used for bonding. The bond strength is then enhanced in a subsequent annealing step, where the front interconnect structure 120 and the heat sink 160 are annealed at a high temperature (e.g., in the range of about 100°C to about 400°C). After annealing, bonds, such as fusion bonds, are formed that bond the front interconnect structure 120 to the heat sink 160. For example, these bonds can be covalent bonds between the front interconnect structure 120 and the heat sink 160. Directly bonding the heat sink 160 to the front interconnect structure 120 via fusion bonding reduces the thermal resistance between the heat sink 160 and the front interconnect structure 120, which improves the cooling capacity of the heat sink 160. Directly bonding the heat sink 160 to the front interconnect structure 120 further reduces the amount of thermal interface material used to attach the heat sink 160 to the front interconnect structure 120, thus reducing costs.

[0102] In some embodiments, the heat sink 160 may be attached to the front interconnect structure 120 using an adhesive. The heat sink 160 may be attached to the front interconnect structure 120 using an adhesive in combination with or instead of dielectric-dielectric bonding. The adhesive may be a thermal interface material (TIM) or other adhesive. The TIM may be an adhesive material with good thermal conductivity. The adhesive may be any suitable adhesive, epoxy resin, die-attach film (DAF), etc. The adhesive may be deposited between the heat sink 160 and either the first dielectric layer 124 and / or the first conductive feature 122.

[0103] like Figures 29A to 29C As shown, the heat sink 160 may include channels 161 and heat-conducting fins 163, which are formed on the surface of the heat sink 160 opposite to the front interconnect structure 120. The channels 161 may be formed by mechanical processes (e.g., mechanical die sawing), laser cutting, acceptable photolithography and etching techniques, etc. The channels 161 and heat-conducting fins 163 can be used to improve heat transfer from the heat sink 160.

[0104] The first substrate 170 can be attached to the rear interconnect structure 140 via the first conductive connector 162. The first substrate 170 may include a doped or undoped semiconductor substrate (e.g., silicon), or an active layer of a semiconductor-on-insulator (SOI) substrate. The first substrate 170 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the first substrate 170 may be an in-slot substrate. In embodiments where the first substrate 170 is an in-slot substrate, the first substrate 170 may not contain active devices and may provide interconnection between the rear interconnect structure 140 and the second substrate 190. The first substrate 170 may include optional passive devices.

[0105] The first substrate 170 may include conductive vias 178 (sometimes referred to as through-silicon vias or through-substrate vias (TSVs)), bonding pads 174, bonding pads 176, and a metallization layer (not shown separately). The metallization layer may be designed to connect various devices to form functional circuitry. The metallization layer may be formed from alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect the conductive material layers. The metallization layer may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.).

[0106] In some embodiments, bonding pads 174 and 176 can be formed by forming recesses (not shown separately) in a dielectric layer (not shown separately) or on the opposite side of a first substrate 170. The recesses can be formed to allow bonding pads 174 and 176 to be embedded in the dielectric layer / first substrate 170. In some embodiments, the recesses are omitted, and bonding pads 174 and 176 can be formed on the dielectric layer / first substrate 170. In some embodiments, bonding pads 174 and 176 comprise a thin seed layer (not shown separately) made of copper, titanium, nickel, gold, palladium, or combinations thereof. A conductive material for bonding pads 174 and 176 can be deposited over the thin seed layer. The conductive material can be formed by electrochemical plating, chemical plating, CVD, atomic layer deposition (ALD), PVD, or combinations thereof. In one embodiment, the conductive material of bonding pads 174 and 176 includes copper, tungsten, aluminum, silver, gold, or combinations thereof. In some embodiments, bonding pads 174 and 176 are UBMs comprising three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium-tungsten / copper arrangement, or a copper / nickel / gold arrangement, may be used to form bonding pads 174 and 176. In some embodiments, a conductive via 178 extends through a first substrate 170 and couples at least one bonding pad 174 to at least one bonding pad 176.

[0107] In some embodiments, a channel 172 is formed in the first substrate 170. The channel 172 may be a void in which a coolant (e.g., oil, water, gas, etc.) can flow. A coolant may be introduced into the channel 172 to conduct heat generated in the transistor structure 109 away. Forming the channel 172 may include etching the first substrate (e.g., ...). Figures 29A to 29C The first substrate 170 includes substrates 170A and 170C. A substrate 170B is used to form microtrenches. The microtrenches are then covered with a second substrate and a third substrate (e.g., substrates 170A and 170C) to seal them. Openings are formed in substrates 170A and 170C to connect to the microtrenches. The openings in substrates 170A and 170C, along with the microtrenches, are collectively referred to as channels 172. The first substrate 170 includes substrates 170A-170C. Channels 172 are shown using dashed lines to indicate that they may or may not be formed. In some embodiments, the heat sink 160 may include channels similar to or identical to channels 172.

[0108] The first substrate 170 can be mechanically and electrically bonded to the front interconnect structure 120 using bonding pads 176 and a first conductive connector 162. The first conductive connector 162 can be a ball grid array (BGA) connector, solder balls, metal pillars, controlled folded chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, etc. The first conductive connector 162 can include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. The first substrate 170 can be disposed on the front interconnect structure 120, and a reflow process can be performed to reflow the first conductive connector 162, and the bonding pads 176 can be bonded to the front interconnect structure 120 through the first conductive connector 162.

[0109] The second substrate 190 can be attached to the first substrate 170 via a second conductive connector 164. The second conductive connector 164 may be the same as or similar to the first conductive connector 162. The second substrate 190 may be made of semiconductor materials such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide, gallium indium phosphide, and combinations thereof may also be used. Alternatively, the second substrate 190 may be a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate comprises layers of semiconductor materials (e.g., epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof). In some embodiments, the second substrate 190 may be based on an insulating core, such as a glass fiber reinforced resin core. In some embodiments, the core material may be a glass fiber resin, such as FR4. In some embodiments, the core material may include bismaleimide triazine (BT) resin, other printed circuit board (PCB) materials, or other thin films. Deposited films such as laminates may be used for the second substrate 190. The second substrate 190 can be mechanically and electrically bonded to the first substrate 170 by means of the bonding pad 174 and the second conductive connector 164, using a method similar to or the same as the method described above for mechanically and electrically bonding the first substrate 170 to the front interconnect structure 120.

[0110] As mentioned above Figures 27A to 27CIn addition to the front interconnect structure 120, a rear interconnect structure 140 is also included to improve the heat dissipation of the transistor structure 109. A heat sink 160 can be thermally coupled to the transistor structure 109 via a first conductive feature 122 of the front interconnect structure 120. A first substrate 170 can be thermally coupled to the transistor structure 109 via a first conductive connector 162, a second conductive feature 136, a first conductive line 132, and a rear via 130. The heat sink 160 and the first substrate 170 can be used to further dissipate heat from the front interconnect structure 120 and the rear interconnect structure 140, respectively, thereby further improving the heat dissipation of the transistor structure 109. Improving the heat dissipation of the transistor structure 109 enhances device performance and reduces device defects.

[0111] exist Figures 30A to 30C In this configuration, heat sink 160 is attached to rear interconnect structure 140, first substrate 170 is attached to front interconnect structure 120, and second substrate 190 is attached to first substrate 170. Each of heat sink 160, first substrate 170, and second substrate 190 can be respectively connected to the aforementioned... Figures 29A to 29C The heat sink 160, the first substrate 170, and the second substrate 190 discussed are the same or similar, and can be described in conjunction with the above regarding... Figures 29A to 29C The methods and apparatus discussed are similar or identical to those used in the attachment. Figures 30A to 30C The embodiments shown can be similar to Figures 29A to 29C The embodiment shown is different in that Figures 28A to 28C The structure shown was not flipped before attaching the heat sink 160, the first substrate 170, and the second substrate 190.

[0112] As mentioned above Figures 27A to 27C In addition to the front interconnect structure 120, a rear interconnect structure 140 is also included to improve the heat dissipation of the transistor structure 109. The first substrate 170 can be thermally coupled to the transistor structure 109 via the first conductive feature 122 of the front interconnect structure 120. The heat sink 160 can be thermally coupled to the transistor structure 109 via the first conductive connector 162, the second conductive feature 136, the first conductive line 132, and the rear via 130. The heat sink 160 and the first substrate 170 can be used to further dissipate heat from the rear interconnect structure 140 and the front interconnect structure 120, respectively, thereby further improving the heat dissipation of the transistor structure 109. Improving the heat dissipation of the transistor structure 109 improves device performance and reduces device defects.

[0113] exist Figures 31A to 31CIn this configuration, a second substrate 190 is attached to a front interconnect structure 120, a first substrate 170 is attached to a rear interconnect structure 140, and a heat sink 160 is attached to the first substrate 170 opposite to the rear interconnect structure 140. Each of the heat sink 160, the first substrate 170, and the second substrate 190 can be respectively associated with the aforementioned... Figures 29A to 29C The heat sink 160, the first substrate 170, and the second substrate 190 discussed are the same or similar, and can be described in conjunction with the above regarding... Figures 29A to 29C The methods and apparatus discussed are similar or identical for attachment. The second substrate 190 can be attached to the front interconnect structure 120, similar to... Figures 29A to 29C The heat sink 160 discussed herein, and the heat sink 160 can be attached to the first substrate 170, similar to... Figures 29A to 29C The second substrate 190 discussed in the text. Figures 31A to 31C The embodiments shown can be similar to Figures 29A to 29C The embodiment shown differs in that the first substrate 170 is located between the rear interconnect structure 140 and the heat sink 160, rather than between the front interconnect structure 120 and the second substrate 190.

[0114] As mentioned above Figures 27A to 27C In addition to the front interconnect structure 120, a rear interconnect structure 140 is also included to improve the heat dissipation of the transistor structure 109. The first substrate 170 can be thermally coupled to the transistor structure 109 via the first conductive connector 162, the second conductive feature 136, the first conductive line 132, and the rear via 130. A heat sink can be thermally coupled to the transistor structure 109 via the first substrate 170. The second substrate 190 can be thermally coupled to the transistor structure 109 via the first conductive feature 122 of the front interconnect structure 120. The heat sink 160 and the first substrate 170 can be used to further dissipate heat from the rear interconnect structure 140, thereby further improving the heat dissipation of the transistor structure 109. Improving the heat dissipation of the transistor structure 109 improves device performance and reduces device defects.

[0115] The embodiments can achieve advantages. For example, including a rear interconnect structure 140 in addition to the front interconnect structure 120 helps reduce the thickness of the front interconnect structure 120, thereby improving heat dissipation through the front interconnect structure 120. Compared to the front interconnect structure 120, the rear interconnect structure 140 can have a larger linewidth and a smaller thickness, and can further be used to dissipate heat generated in the transistor structure 109. The front interconnect structure 120 and the rear interconnect structure 140 can be attached to the heat sink 160 or the first substrate 170, which can further dissipate heat from the front interconnect structure 120 and the rear interconnect structure 140. Improved heat dissipation improves device performance and reduces device defects.

[0116] According to one embodiment, a device includes: a first transistor structure; a front interconnect structure located on the front side of the first transistor structure, the front interconnect structure including front conductive lines; a rear interconnect structure located on the rear side of the first transistor structure, the rear interconnect structure including rear conductive lines having a linewidth greater than that of the front conductive lines; and a first thermal substrate coupled to the rear interconnect structure. In one embodiment, the first thermal substrate includes a heat sink including channels and fins in a surface opposite to the rear interconnect structure. In one embodiment, the first thermal substrate includes embedded fluid channels. In one embodiment, the device further includes a second thermal substrate coupled to the front interconnect structure. In one embodiment, the front interconnect structure has a thickness in the range of 0.5 μm to 2 μm, and the rear interconnect structure has a thickness in the range of 0.5 μm to 1 μm. In one embodiment, the minimum linewidth of the front interconnect structure ranges from 15 nm to 45 nm, and the minimum linewidth of the rear interconnect structure ranges from 30 nm to 60 nm. In one embodiment, the device further includes a second substrate coupled to the first heat-dissipating substrate opposite the rear interconnect structure, wherein the second substrate is a printed circuit board.

[0117] According to another embodiment, a device includes: a gate structure located over a semiconductor channel region; a first source / drain region adjacent to the gate structure and the semiconductor channel region; a gate contact coupled to a surface of the gate structure facing a first direction; a first source / drain contact coupled to a surface of the first source / drain region facing a second direction opposite to the first direction; a first interconnect structure coupled to the first source / drain contact opposite to the first source / drain region in the second direction; and a first thermal substrate coupled to the first interconnect structure opposite to the first source / drain contact in the second direction. In one embodiment, the first thermal substrate includes a heat sink having fins and channels in a surface opposite to the first interconnect structure. In one embodiment, the first thermal substrate includes a plurality of embedded fluid channels. In one embodiment, the device further includes: a second interconnect structure coupled to the gate contact opposite to the gate structure in the first direction; and a second thermal substrate coupled to the second interconnect structure opposite to the gate contact in the first direction. In one embodiment, the second thermal substrate includes a heat sink having fins and channels in a surface opposite to the second interconnect structure. In one embodiment, the second heat dissipation substrate includes a plurality of embedded fluid channels. In another embodiment, the device further includes a second heat dissipation substrate coupled to the first heat dissipation substrate opposite the first interconnect structure in the second direction, the second heat dissipation substrate including a heat sink having fins and channels in a surface opposite to the first heat dissipation substrate.

[0118] According to another embodiment, a method includes: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material includes thinning a back side of the first substrate; replacing the first epitaxial material with a first back-side via, the first back-side via being electrically coupled to a first source / drain region of the first transistor; forming a back-side interconnect structure over the first back-side via opposite to the first source / drain region; and coupling a first heat-dissipating substrate to the back-side interconnect structure opposite to the first back-side via. In one embodiment, the method further includes: dissipating heat generated in the first transistor by means of fins disposed in a surface of the first heat-dissipating substrate opposite to the back-side interconnect structure. In one embodiment, the method further includes: dissipating heat generated in the first transistor by means of fluid in an embedded fluid channel disposed in the first heat-dissipating substrate. In one embodiment, the method further includes: forming a front-side interconnect structure over the first transistor opposite to the back-side interconnect structure; and coupling a second heat-dissipating substrate to the front-side interconnect structure opposite to the back-side interconnect structure. In one embodiment, the method further includes: dissipating heat generated in the first transistor by means of fins disposed in a surface of the second heat-dissipating substrate opposite to the front-side interconnect structure. In one embodiment, the method further includes dissipating heat generated in the first transistor by means of fluid in an embedded fluid channel disposed in the second heat dissipation substrate.

[0119] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0120] Example 1. A semiconductor device, comprising:

[0121] First transistor structure;

[0122] A front interconnect structure is located on the front side of the first transistor structure, and the front interconnect structure includes front conductive lines;

[0123] A rear interconnect structure, located on the rear side of the first transistor structure, includes a rear conductive line having a linewidth greater than that of the front conductive line; and

[0124] A first heat dissipation substrate is coupled to the rear interconnect structure.

[0125] Example 2. The device according to Example 1, wherein the first heat dissipation substrate includes a heat sink, the heat sink including channels and fins in a surface opposite to the rear interconnect structure.

[0126] Example 3. The device according to Example 1, wherein the first heat dissipation substrate includes an embedded fluid channel.

[0127] Example 4. The device according to Example 1 further includes a second heat dissipation substrate coupled to the front interconnect structure.

[0128] Example 5. The device according to Example 1, wherein the front interconnect structure has a thickness in the range of 0.5 μm to 2 μm, and the rear interconnect structure has a thickness in the range of 0.5 μm to 1 μm.

[0129] Example 6. The device according to Example 1, wherein the minimum linewidth of the front interconnect structure ranges from 15 nm to 45 nm, and wherein the minimum linewidth of the rear interconnect structure ranges from 30 nm to 60 nm.

[0130] Example 7. The device according to Example 1 further includes a second substrate coupled to the first heat-dissipating substrate opposite the rear interconnect structure, wherein the second substrate is a printed circuit board.

[0131] Example 8. A semiconductor device comprising:

[0132] The gate structure is located above the semiconductor channel region;

[0133] The first source / drain region is adjacent to the gate structure and the semiconductor channel region;

[0134] A gate contact is coupled to the surface of the gate structure facing the first direction;

[0135] The first source / drain contact is coupled to the surface of the first source / drain region facing a second direction opposite to the first direction;

[0136] A first interconnect structure is coupled to a first source / drain contact opposite to the first source / drain region in the second direction; and

[0137] A first heat dissipation substrate is coupled to the first interconnect structure which is opposite to the first source / drain contact in the second direction.

[0138] Example 9. The device according to Example 8, wherein the first heat dissipation substrate includes a heat sink having fins and channels in a surface opposite to the first interconnect structure.

[0139] Example 10. The device according to Example 8, wherein the first heat dissipation substrate includes a plurality of embedded fluid channels.

[0140] Example 11. The device according to Example 8 further includes:

[0141] A second interconnect structure is coupled to the gate contact opposite the gate structure in the first direction; and

[0142] A second heat dissipation substrate is coupled to a second interconnect structure that is opposite to the gate contact in the first direction.

[0143] Example 12. The device according to Example 11, wherein the second heat dissipation substrate includes a heat sink having fins and channels in a surface opposite to the second interconnect structure.

[0144] Example 13. The device according to Example 11, wherein the second heat dissipation substrate includes a plurality of embedded fluid channels.

[0145] Example 14. The device according to Example 8 further includes a second heat dissipation substrate coupled to the first heat dissipation substrate opposite to the first interconnect structure in the second direction, wherein the second heat dissipation substrate includes a heat sink having fins and channels in a surface opposite to the first heat dissipation substrate.

[0146] Example 15. A method of manufacturing a semiconductor device, comprising:

[0147] A first transistor is formed on a first substrate;

[0148] Exposing the first epitaxial material, wherein exposing the first epitaxial material includes thinning the back side of the first substrate;

[0149] The first epitaxial material is replaced with a first rear-side via, and the first rear-side via is electrically coupled to the first source / drain region of the first transistor.

[0150] A rear-side interconnect structure is formed on the first rear-side via opposite to the first source / drain region; and

[0151] The first heat dissipation substrate is coupled to the rear interconnect structure opposite to the first rear via.

[0152] Example 16. The method according to Example 15 further includes: dissipating heat generated in the first transistor by means of fins disposed in a surface of the first heat dissipation substrate opposite to the rear interconnect structure.

[0153] Example 17. The method according to Example 15 further includes: dissipating heat generated in the first transistor by means of fluid in an embedded fluid channel disposed in the first heat dissipation substrate.

[0154] Example 18. The method according to Example 15 further includes:

[0155] A front interconnect structure is formed on top of the first transistor, which is opposite to the rear interconnect structure; and

[0156] The second heat dissipation substrate is coupled to the front interconnect structure opposite to the rear interconnect structure.

[0157] Example 19. The method according to Example 18 further includes: dissipating heat generated in the first transistor by means of fins disposed in a surface of the second heat dissipation substrate opposite to the front interconnect structure.

[0158] Example 20. The method according to Example 19 further includes: dissipating heat generated in the first transistor by means of fluid in an embedded fluid channel disposed in the second heat dissipation substrate.

Claims

1. A semiconductor device, comprising: First transistor structure; A front interconnect structure is located on the front side of the first transistor structure, and the front interconnect structure includes front conductive lines; A rear interconnect structure is located on the rear side of the first transistor structure. The rear interconnect structure includes a rear conductive line, which has a larger line width than the front conductive line. as well as A first heat dissipation substrate is coupled to the rear interconnect structure, wherein the first heat dissipation substrate includes embedded fluid channels.

2. The device of claim 1, wherein, The first heat dissipation substrate includes a heat sink, which includes channels and fins in a surface opposite to the rear interconnect structure.

3. The device of claim 1 further includes a second heat dissipation substrate coupled to the front interconnect structure.

4. The device of claim 1, wherein, The front interconnect structure has a thickness ranging from 0.5 µm to 2 µm, and the rear interconnect structure has a thickness ranging from 0.5 µm to 1 µm.

5. The device of claim 1, wherein, The minimum linewidth of the front interconnect structure ranges from 15 nm to 45 nm, and the minimum linewidth of the rear interconnect structure ranges from 30 nm to 60 nm.

6. The device of claim 1, further comprising a second substrate coupled to the first heat spreading substrate opposite the backside interconnect structure, wherein, The second substrate is a printed circuit board.

7. A semiconductor device, comprising: The gate structure is located above the semiconductor channel region; The first source / drain region is adjacent to the gate structure and the semiconductor channel region; A gate contact is coupled to the surface of the gate structure facing the first direction; The first source / drain contact is coupled to the surface of the first source / drain region facing a second direction opposite to the first direction; A first interconnect structure is coupled to a first source / drain contact that is opposite to the first source / drain region in the second direction; as well as A first heat dissipation substrate is coupled to a first interconnect structure opposite to the first source / drain contact in the second direction, wherein the first heat dissipation substrate includes a plurality of embedded fluid channels.

8. The device of claim 7, wherein, The first heat dissipation substrate includes a heat sink having fins and channels in a surface opposite to the first interconnect structure.

9. The device according to claim 7, further comprising: A second interconnect structure is coupled to the gate contact opposite the gate structure in the first direction; as well as A second heat dissipation substrate is coupled to a second interconnect structure that is opposite to the gate contact in the first direction.

10. The device of claim 9, wherein, The second heat dissipation substrate includes a heat sink having fins and channels in a surface opposite to the second interconnect structure.

11. The device of claim 9, wherein, The second heat dissipation substrate includes multiple embedded fluid channels.

12. The device of claim 7, further comprising a second heat spreading substrate coupled to the first heat spreading substrate opposite the first interconnect structure in the second direction, wherein, The second heat dissipation substrate includes a heat sink having fins and channels in a surface opposite to the first heat dissipation substrate.

13. A method for manufacturing a semiconductor device, comprising: A first transistor is formed on a first substrate; Exposing the first epitaxial material, wherein exposing the first epitaxial material includes thinning the back side of the first substrate; The first epitaxial material is replaced with a first rear-side via, and the first rear-side via is electrically coupled to the first source / drain region of the first transistor. A rear interconnect structure is formed on the first rear via opposite to the first source / drain region; Couple the first heat dissipation substrate to the rear interconnect structure opposite to the first rear via; and The heat generated in the first transistor is dissipated by fluid in an embedded fluid channel disposed in the first heat dissipation substrate.

14. The method of claim 13, further comprising: Heat generated in the first transistor is dissipated by fins disposed on the surface of the first heat dissipation substrate opposite to the rear interconnect structure.

15. The method of claim 13, further comprising: A front interconnect structure is formed on the first transistor opposite to the rear interconnect structure; as well as The second heat dissipation substrate is coupled to the front interconnect structure opposite to the rear interconnect structure.

16. The method of claim 15, further comprising: The heat generated in the first transistor is dissipated by fins disposed on the surface of the second heat dissipation substrate opposite to the front interconnect structure.

17. The method of claim 16, further comprising: The heat generated in the first transistor is dissipated by fluid in an embedded fluid channel disposed in the second heat dissipation substrate.

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