Semiconductor device

Abstract

Embodiments provide a semiconductor device with improved reliability. The semiconductor device of the embodiments includes a first substrate including a first metal layer, a first insulating layer surrounding the first metal layer, and a second substrate including a second metal layer in contact with the first metal layer, a second insulating layer surrounding the second metal layer and in contact with the first insulating layer, and a first conductive body disposed in part in the second metal layer and extending in a first direction from the second metal layer toward the first metal layer.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-42893 (filed on March 16, 2021), which is the basic application. This application includes all contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Technology

[0004] Bonding techniques, for example, enable high-functionality or highly integrated semiconductor devices by bonding two wafers on which electronic circuitry is formed. For instance, high-functionality or highly integrated semiconductor memories are achieved by dicing a semiconductor wafer into multiple wafers, whereby the semiconductor wafers are bonded together by bonding a semiconductor wafer forming a memory cell array with a semiconductor wafer forming control circuitry for the memory cell array, followed by heat treatment.

[0005] In semiconductor devices manufactured using bonding technology, improved reliability is desired. Summary of the Invention

[0006] Embodiments of the present invention provide a semiconductor device with improved reliability.

[0007] The semiconductor device of the embodiment includes: a first substrate comprising a first metal layer and a first insulating layer surrounding the first metal layer; and a second substrate comprising a second metal layer connected to the first metal layer, a second insulating layer surrounding the second metal layer and connected to the first insulating layer, and a first conductor partially disposed in the second metal layer and extending in a first direction from the second metal layer toward the first metal layer. Attached Figure Description

[0008] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic cross-sectional view of the connection area of ​​the semiconductor device according to the first embodiment.

[0010] Figures 3-13 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0011] Figure 14 , 15 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment.

[0012] Figure 16This is a schematic cross-sectional view of the connection area of ​​the semiconductor device in the second embodiment.

[0013] Figure 17 This is a schematic cross-sectional view of the connection area of ​​the semiconductor device in the third embodiment.

[0014] Figure 18 This is a schematic cross-sectional view of the connection area of ​​the semiconductor device in the fourth embodiment. Detailed Implementation

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same symbols, and descriptions of components that have already been described once will be appropriately omitted.

[0016] In addition, for convenience, the terms "upper" or "lower" are sometimes used in this specification. "Upper" or "lower" is, for example, a term indicating a relative positional relationship within the accompanying drawings. The terms "upper" or "lower" do not necessarily specify a positional relationship relative to gravity.

[0017] Qualitative and quantitative analyses of the chemical composition of the components constituting the semiconductor device described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectrometry (EDX). Furthermore, measurements of the thickness of the components constituting the semiconductor device, the distance between components, etc., can be performed using, for example, a transmission electron microscope (TEM) or a scanning electron microscope (SEM).

[0018] (First Embodiment)

[0019] The semiconductor device of the first embodiment includes: a first substrate including a first metal layer and a first insulating layer surrounding the first metal layer; and a second substrate including a second metal layer connected to the first metal layer, a second insulating layer surrounding the second metal layer and connected to the first insulating layer, and a first conductor partially disposed in the second metal layer and extending in a first direction from the second metal layer toward the first metal layer.

[0020] The semiconductor device in the first embodiment is a non-volatile semiconductor memory 100. The non-volatile semiconductor memory 100 is, for example, a 3D NAND flash memory with memory cells arranged in 3D.

[0021] Figure 1This is a schematic cross-sectional view of the semiconductor memory device according to the first embodiment.

[0022] The non-volatile semiconductor memory 100 of the first embodiment includes a memory chip 101 and a control chip 102. The memory chip 101 is an example of a first substrate. The control chip 102 is an example of a second substrate.

[0023] The memory chip 101 and the control chip 102 are joined by a sticking interface S. The memory chip 101 and the control chip 102 are joined using a bonding technology.

[0024] The memory chip 101 includes a first semiconductor layer 10, a plurality of first metal pads 11, a first interlayer insulating layer 12, a first contact plug 13a, a first wiring layer 14, and a memory cell array 15.

[0025] The control chip 102 includes a second semiconductor layer 20, a plurality of second metal pads 21, a second interlayer insulating layer 22, a second contact plug 23a, a second wiring layer 24, and a control circuit 25.

[0026] The first metal pad 11 is an example of a first metal layer. The first interlayer insulating layer 12 is an example of a first insulating layer. The first contact plug 13a is an example of a second conductor.

[0027] The second metal pad 21 is an example of a second metal layer. The second interlayer insulating layer 22 is an example of a second insulating layer. The second contact plug 23a is an example of a first conductor. The second wiring layer 24 is an example of a conductive layer.

[0028] The first semiconductor layer 10 is, for example, monocrystalline silicon.

[0029] The memory cell array 15 is disposed between the first semiconductor layer 10 and the control chip 102. For example, the memory cells are arranged in three dimensions in the memory cell array 15.

[0030] The first metal pad 11 is electrically connected to the memory cell array 15. The first metal pad 11 is electrically connected to the memory cell array 15 via the first contact plug 13a and the first wiring layer 14.

[0031] A first interlayer insulating layer 12 is disposed between the first semiconductor layer 10 and the control wafer 102. The first interlayer insulating layer 12, for example, has the function of ensuring electrical insulation of wiring within the memory cell array 15 or wiring within the memory wafer 101. The first interlayer insulating layer 12, for example, comprises silicon oxide.

[0032] The second semiconductor layer 20 is, for example, monocrystalline silicon.

[0033] A control circuit 25 is disposed between the second semiconductor layer 20 and the memory chip 101. The control circuit 25 includes multiple semiconductor elements such as transistors and a multilayer wiring layer that electrically connects the semiconductor elements. The control circuit 25 has the function of controlling the memory cell array 15.

[0034] The second metal pad 21 is electrically connected to the control circuit 25. The second metal pad 21 is electrically connected to the memory cell array 15 via the second contact plug 23a and the second wiring layer 24.

[0035] A second interlayer insulating layer 22 is disposed between the second semiconductor layer 20 and the memory wafer 101. The second interlayer insulating layer 22, for example, has the function of ensuring electrical insulation of semiconductor elements within the control circuit 25 or wiring in a multilayer wiring layer. The second interlayer insulating layer 22, for example, comprises silicon oxide.

[0036] The second metal pad 21 is in contact with the first metal pad 11 via the mating surface S. The second metal pad 21 is electrically connected to the first metal pad 11.

[0037] The memory chip 101 and the control chip 102 are electrically connected via the first metal pad 11 and the second metal pad 21.

[0038] The area near the first metal solder pad 11 and the second metal solder pad 21 connected by the bonding surface S will be described below. Figure 1 The region X in the diagram is called the connected region.

[0039] Figure 2 This is a schematic cross-sectional view of the connection area of ​​the semiconductor device according to the first embodiment.

[0040] The portion of the non-volatile semiconductor memory 100 on the memory wafer 101 side of the connection region includes a first metal pad 11, a first interlayer insulating layer 12, a first contact plug 13a, a first wiring layer 14, a first barrier metal film 16, a first anti-diffusion film 17a, and a first anti-diffusion film 17b.

[0041] The portion of the non-volatile semiconductor memory 100 on the control chip 102 side of the connection region includes a second metal pad 21, a second interlayer insulating layer 22, a second contact plug 23a, a second wiring layer 24, a second barrier metal film 26, a second anti-diffusion film 27a, and a second anti-diffusion film 27b.

[0042] The first metal pad 11 is an example of a first metal layer. The first interlayer insulating layer 12 is an example of a first insulating layer. The first contact plug 13a is an example of a second conductor.

[0043] The second metal pad 21 is an example of a second metal layer. The second interlayer insulating layer 22 is an example of a second insulating layer. The second contact plug 23a is an example of a first conductor. The second wiring layer 24 is an example of a conductive layer. The second barrier metal film 26 is an example of a conductive film.

[0044] The direction from the second metal pad 21 toward the first metal pad 11 and the direction from the first metal pad 11 toward the second metal pad 21 are defined as the first direction. The direction perpendicular to the first direction is defined as the second direction.

[0045] The first metal pad 11 is surrounded by the first interlayer insulating layer 12. The first metal pad 11 is metal. The first metal pad 11 may contain, for example, copper (Cu).

[0046] The first wiring layer 14 is located in the first direction of the first metal solder pad 11. The first wiring layer 14 is surrounded by the first interlayer insulation layer 12. The first wiring layer 14 is separated from the first metal solder pad 11 by a first contact plug 13a.

[0047] The first wiring layer 14 is a conductor. The first wiring layer 14 is, for example, a metal. The first wiring layer 14 contains, for example, copper (Cu) or tungsten (W).

[0048] A first contact plug 13a is disposed between the first metal pad 11 and the first wiring layer 14. The first contact plug 13a extends along a first direction. The first contact plug 13a is, for example, cylindrical. The first contact plug 13a is, for example, cylindrical or conical trapezoidal in shape. The first contact plug 13a electrically connects the first metal pad 11 and the first wiring layer 14.

[0049] The first contact plug 13a is a conductor. The first contact plug 13a is, for example, a metal. The first contact plug 13a contains, for example, tungsten (W). The first contact plug 13a is, for example, tungsten (W).

[0050] A first barrier metal film 16 is disposed between the first metal pad 11 and the first interlayer insulating layer 12. The first barrier metal film 16 is also disposed between the first metal pad 11 and the first contact plug 13a. For example, the first barrier metal film 16 has the function of inhibiting the diffusion of metal contained in the first metal pad 11 into the first interlayer insulating layer 12.

[0051] The first barrier metal film 16 is a conductor. The first barrier metal film 16 is, for example, a metal or a metal nitride.

[0052] The first barrier metal film 16, for example, contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), manganese (Mn), and cobalt (Co). The first barrier metal film 16 is, for example, a titanium film, a titanium nitride film, or a tantalum nitride film.

[0053] The thickness of the first barrier metal film 16 is, for example, 10 nm or more and 30 nm or less.

[0054] A first anti-diffusion film 17a is disposed in the first interlayer insulating layer 12. A first anti-diffusion film 17b is disposed in the first interlayer insulating layer 12. The first anti-diffusion film 17a and the first anti-diffusion film 17b, for example, have the function of preventing the metal contained in the first metal pad 11 or the first wiring layer 14 from diffusing into the first interlayer insulating layer 12.

[0055] The second metal solder pad 21 is surrounded by the second interlayer insulation layer 22. The second metal solder pad 21 is in contact with the first metal solder pad 11 through the bonding surface S.

[0056] The second metal pad 21 is metal. The second metal pad 21 may contain, for example, copper (Cu).

[0057] The second wiring layer 24 is located in the first direction of the second metal solder pad 21. The second wiring layer 24 is surrounded by a second interlayer insulating layer 22. The second wiring layer 24 is separated from the second metal solder pad 21 by a second contact plug 23a.

[0058] The second wiring layer 24 is a conductor. The second wiring layer 24 is, for example, a metal. The second wiring layer 24 contains, for example, copper (Cu) or tungsten (W).

[0059] The second contact plug 23a is disposed between the second metal solder pad 21 and the second wiring layer 24. The second contact plug 23a extends along the first direction. The second contact plug 23a is, for example, cylindrical. The second contact plug 23a is, for example, cylindrical or conical trapezoidal in shape. The second contact plug 23a electrically connects the second metal solder pad 21 and the second wiring layer 24.

[0060] A portion of the second contact plug 23a is disposed in the second metal solder pad 21. The end of the second contact plug 23a on the first metal solder pad 11 side is disposed in the second metal solder pad 21. A portion of the second contact plug 23a is surrounded by the second metal solder pad 21. The end of the second contact plug 23a on the first metal solder pad 11 side is surrounded by the second metal solder pad 21.

[0061] The second contact plug 23a is separated from the first metal solder pad 11 in the first direction. A second metal solder pad 21 is disposed between the second contact plug 23a and the first metal solder pad 11.

[0062] The distance between the second contact plug 23a and the first metal solder pad 11 in the first direction ( Figure 2 d1) is less than the thickness of the second metal pad 21 in the first direction. Figure 2 (t in the text). The distance d1 between the second contact plug 23a and the first metal pad 11 in the first direction is, for example, less than half of the thickness t of the second metal pad 21 in the first direction.

[0063] The distance d1 between the second contact plug 23a and the first metal pad 11 in the first direction is greater than the distance d1 between the interface of the first interlayer insulation layer 12 and the second interlayer insulation layer 22 and the second contact plug 23a in the second direction. Figure 2 d2) is small.

[0064] The second contact plug 23a is a conductor. The second contact plug 23a is, for example, a metal. The second contact plug 23a contains, for example, tungsten (W). The second contact plug 23a is, for example, tungsten (W).

[0065] The second barrier metal film 26 is disposed between the second metal pad 21 and the second interlayer insulating layer 22. The second barrier metal film 26 is disposed between the second metal pad 21 and the second contact plug 23a.

[0066] The second barrier metal film 26 surrounds the second contact plug 23a in the second metal pad 21. The second barrier metal film 26 is disposed on the side and upper surface of the second contact plug 23a in the second metal pad 21.

[0067] The second barrier metal film 26, for example, has the function of inhibiting the diffusion of the metal contained in the second metal pad 21 into the second interlayer insulating layer 22.

[0068] The second barrier metal film 26 is a conductor. The second barrier metal film 26 is, for example, a metal or a metal nitride.

[0069] The second barrier metal film 26, for example, contains at least one metallic element selected from the group consisting of titanium (Ti), tantalum (Ta), manganese (Mn), and cobalt (Co). The second barrier metal film 26 is, for example, a titanium film, a titanium nitride film, or a tantalum nitride film.

[0070] The thickness of the second barrier metal film 26 is, for example, more than 10 nm and less than 30 nm.

[0071] The second anti-diffusion film 27a is disposed in the second interlayer insulating layer 22. The second anti-diffusion film 27b is disposed in the second interlayer insulating layer 22. The second anti-diffusion film 27a and the second anti-diffusion film 27b, for example, have the function of preventing the metal contained in the second metal pad 21 or the second wiring layer 24 from diffusing into the second interlayer insulating layer 22.

[0072] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described. Figures 3-13 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the first embodiment.

[0073] The manufacturing method will now be described with a focus on the connection region X of the non-volatile semiconductor memory 100.

[0074] First, the manufacturing method of the portion of the memory chip 101 side of the connection region X will be described.

[0075] A tungsten layer 52 is formed in the silicon oxide film 51. Next, a silicon nitride film 53 and a silicon oxide film 54 are formed on the silicon oxide film 51 and the tungsten layer 52. Figure 3 ).

[0076] Silicon oxide films 51 and 54 ultimately become part of the first interlayer insulating layer 12. Silicon nitride film 53 ultimately becomes the first anti-diffusion film 17b. Tungsten layer 52 ultimately becomes the first wiring layer 14.

[0077] Next, the silicon oxide film 54 and the silicon nitride film 53 are etched to form contact holes reaching the tungsten layer 52. Then, the contact holes formed by the tungsten film 55 are embedded... Figure 4 The tungsten film 55 eventually became the first contact plug 13a.

[0078] Next, a silicon nitride film 56 and a silicon oxide film 57 are formed on the silicon oxide film 54 and the tungsten film 55. Figure 5 The silicon nitride film 56 ultimately becomes the first anti-diffusion film 17a. The silicon oxide film 57 ultimately becomes part of the first interlayer insulating layer 12.

[0079] Next, the silicon oxide film 57 and the silicon nitride film 56 are etched to form the opening 58. Figure 6 At the bottom of the opening 58, a tungsten film 55 is exposed.

[0080] Next, a titanium film 59 and a copper film 60 are formed in the opening 58. Figure 7 The surface of the copper film 60 is planarized, for example, by chemical mechanical polishing (CMP).

[0081] Titanium film 59 ultimately becomes the first barrier metal film 16. In addition, copper film 60 ultimately becomes the first metal pad 11.

[0082] The connection region X is formed on the side of the memory chip 101 by the above manufacturing method.

[0083] Next, the manufacturing method of the portion of the connection region X on the control chip 102 side will be described.

[0084] A tungsten layer 62 is formed in the silicon oxide film 61. Next, a silicon nitride film 63, a silicon oxide film 64, a silicon nitride film 66, and a silicon oxide film 67 are formed on the silicon oxide film 61 and the tungsten layer 62. Figure 8 ).

[0085] Silicon oxide films 61, 64, and 67 ultimately become part of the second interlayer insulating layer 22. Silicon nitride films 63 and 66 ultimately become the first anti-diffusion films 17b and 17a. Tungsten layer 62 ultimately becomes the second wiring layer 24.

[0086] Next, the silicon oxide film 67, silicon nitride film 66, silicon oxide film 64, and silicon nitride film 63 are etched to form contact holes reaching the tungsten layer 62. Then, the contact holes formed by the tungsten film 65 are embedded... Figure 9 The tungsten film 65 eventually becomes the second contact plug 23a.

[0087] Next, a silicon oxide film 68 is formed on the silicon oxide film 67 and the tungsten film 65. Figure 10 The silicon oxide film 68 eventually becomes part of the second interlayer insulating layer 22.

[0088] Next, the silicon oxide film 68, silicon oxide film 67, and silicon nitride film 66 are etched to form an opening 69. Figure 11 It becomes the shape of the upper part of the tungsten film 65 protruding in the opening 69.

[0089] Next, a titanium film 70 and a copper film 71 are formed in the opening 69. Figure 12 The surface of the copper film 71 is planarized, for example, by CMP. This results in a shape where the upper part of the tungsten film 65 protrudes within the copper film 71.

[0090] The titanium film 70 ultimately becomes the second barrier metal film 26. In addition, the copper film 71 ultimately becomes the second metal pad 21.

[0091] The connection region X is formed on the side of the control chip 102 by the above manufacturing method.

[0092] Then, the portion of connection region X on the control chip 102 side and the portion of connection region X on the memory chip 101 side are bonded together with the second metal pad 21 and the first metal pad 11 facing each other. Figure 13 The portion of connection region X on the control chip 102 side and the portion of connection region X on the memory chip 101 side are mechanically pressed together. Then, a heat treatment is performed, thereby bonding the portion of connection region X on the control chip 102 side to the portion of connection region X on the memory chip 101 side.

[0093] The above manufacturing method can be used to manufacture the connection region X of the non-volatile semiconductor memory 100.

[0094] Next, the operation and effects of the semiconductor device of the first embodiment will be explained. Hereinafter, the case in which the material of the first metal pad 11 and the second metal pad 21 is copper (Cu) and the first barrier metal film 16 and the second barrier metal film 26 are titanium films, that is, the case in which the metal element contained in the first barrier metal film 16 and the second barrier metal film 26 is titanium (Ti), will be explained as an example.

[0095] Figure 14 and 15 This is an explanatory diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. Figure 14 This is a schematic cross-sectional view of the connection region of the comparative example semiconductor device. The connection region of the comparative example differs from the connection region X of the non-volatile semiconductor memory 100 of the first embodiment in that the first conductor is not disposed in the second metal layer.

[0096] In the comparative example, the connection region does not have the second contact plug 23a disposed in the second metal pad 21. The connection region of the comparative example is formed by forming the portion of the connection region on the control wafer 102 side of the connection region X on the memory wafer 101 side in the first embodiment using the same method.

[0097] like Figure 14 As shown, after manufacturing the connection area, there is a possibility that pores 80 (voids) may form on the mating surface S between the first metal pad 11 and the second metal pad 21. If pores 80 form on the mating surface S between the first metal pad 11 and the second metal pad 21, there is a concern that the electromigration resistance of the connection area may decrease. Pores 80 can grow due to electromigration, raising concerns about increased contact resistance between the first metal pad 11 and the second metal pad 21, or even the occurrence of a break in the connection between them. Due to the decreased electromigration resistance of the connection area, the reliability of the non-volatile semiconductor memory 100 decreases.

[0098] Consideration is given to improving the electromigration resistance of the connection region by allowing the titanium contained in the first barrier metal film 16 and the second barrier metal film 26 to diffuse into the pores 80 or the bonding surface S and segregate there. It is also considered that the movement of copper atoms can be suppressed by allowing titanium atoms to exist at the grain boundaries of copper (Cu).

[0099] Figure 15 This is a schematic cross-sectional view of the connection area of ​​a semiconductor device.

[0100] In the connection region X of the non-volatile semiconductor memory 100 of the first embodiment, a portion of the second contact plug 23a is disposed in the second metal pad 21. Between the second contact plug 23a and the second metal pad 21, a second barrier metal film 26 comprising titanium (Ti) is disposed.

[0101] By placing a portion of the second contact plug 23a in the second metal pad 21, and providing a titanium (Ti) supply source near the mating surface S between the first metal pad 11 and the second metal pad 21, the amount of titanium supplied to the pore 80 or the mating surface S is increased compared to the connection region of the comparative example. Therefore, the electromigration resistance of the connection region X is improved, and the reliability of the non-volatile semiconductor memory 100 is enhanced.

[0102] The distance between the second contact plug 23a and the first metal solder pad 11 in the first direction ( Figure 2 In the first direction, d1 is preferably the thickness of the second metal pad 21. Figure 2 The amount of titanium supplied to the pores 80 or the bonding surface S is less than 1 / 2, more preferably less than 1 / 3, and even more preferably less than 1 / 4. By bringing the second barrier metal film 26 between the second contact plug 23a and the first metal pad 11 closer to the bonding surface S, the amount of titanium supplied to the pores 80 or the bonding surface S is increased, and the electromigration resistance of the connection region X is further improved.

[0103] The distance d1 between the second contact plug 23a and the first metal pad 11 in the first direction is preferably greater than the distance d1 between the interface of the first interlayer insulation layer 12 and the second interlayer insulation layer 22 and the second contact plug 23a in the second direction. Figure 2 The d2) is smaller. By making the second barrier metal film 26 between the second contact plug 23a and the first metal pad 11 closer to the bonding surface S than the second barrier metal film 26 between the second interlayer insulation layer 22 and the first metal pad 11, the supply of titanium to the pores 80 or the bonding surface S is increased, and the electromigration resistance of the connection region X is further improved.

[0104] Furthermore, the metal elements contained in the first barrier metal film 16 and the second barrier metal film 26 are not limited to titanium (Ti). For example, it is believed that even if the metal element is tantalum (Ta), manganese (Mn), or cobalt (Co), the same effect and function as titanium (Ti) can be obtained.

[0105] According to the first embodiment, a semiconductor device with improved electromigration resistance and improved reliability can be provided.

[0106] (Second Implementation)

[0107] The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that it further includes at least a portion of a second conductor disposed in the first metal layer and extending along the first direction. Hereinafter, some descriptions that are repetitive with those of the first embodiment will be omitted.

[0108] Figure 16This is a schematic cross-sectional view of the connection area of ​​the semiconductor device in the second embodiment.

[0109] The connection region of the non-volatile semiconductor memory in the second embodiment includes a first metal pad 11, a first interlayer insulating layer 12, a first contact plug 13a, a first wiring layer 14, a first barrier metal film 16, a first anti-diffusion film 17a, and a first anti-diffusion film 17b on the memory wafer 101 side.

[0110] The connection region of the non-volatile semiconductor memory in the second embodiment includes, on the control chip 102 side: a second metal pad 21, a second interlayer insulating layer 22, a second contact plug 23a, a second wiring layer 24, a second barrier metal film 26, a second anti-diffusion film 27a, and a second anti-diffusion film 27b.

[0111] The first metal pad 11 is an example of a first metal layer. The first interlayer insulating layer 12 is an example of a first insulating layer. The first contact plug 13a is an example of a second conductor.

[0112] The second metal pad 21 is an example of a second metal layer. The second interlayer insulating layer 22 is an example of a second insulating layer. The second contact plug 23a is an example of a first conductor. The second wiring layer 24 is an example of a conductive layer. The second barrier metal film 26 is an example of a conductive film.

[0113] A portion of the first contact plug 13a is disposed in the first metal solder pad 11. The end of the first contact plug 13a on the side of the second metal solder pad 21 is disposed in the first metal solder pad 11. A portion of the first contact plug 13a is surrounded by the first metal solder pad 11. The end of the first contact plug 13a on the side of the second metal solder pad 21 is surrounded by the first metal solder pad 11.

[0114] The first contact plug 13a and the second metal solder pad 21 are separated in the first direction. The first metal solder pad 11 is disposed between the first contact plug 13a and the second metal solder pad 21.

[0115] The distance between the first contact plug 13a and the second metal pad 21 in the first direction is smaller than the thickness of the first metal pad 11 in the first direction. For example, the distance between the first contact plug 13a and the second metal pad 21 in the first direction is less than half the thickness of the first metal pad 11 in the first direction.

[0116] According to the connection region of the second embodiment, by providing a portion of the first contact plug 13a in the first metal pad 11, the supply of titanium to the pores 80 or the mating surface S is further increased compared to the connection region X of the first embodiment. Therefore, the electromigration resistance of the connection region is further improved.

[0117] According to the second embodiment, a semiconductor device with improved electromigration resistance and improved reliability can be provided.

[0118] (Third Implementation)

[0119] The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment in that it further includes at least a portion of a third conductor disposed in the second metal layer and extending from the second metal layer along the first direction. Hereinafter, some descriptions that are repeated in the first or second embodiments will be omitted.

[0120] Figure 17 This is a schematic cross-sectional view of the connection area of ​​the semiconductor device in the third embodiment.

[0121] The connection region of the non-volatile semiconductor memory in the third embodiment includes a first metal pad 11, a first interlayer insulating layer 12, a first contact plug 13a, a first contact plug 13b, a first contact plug 13c, a first wiring layer 14, a first barrier metal film 16, a first anti-diffusion film 17a, and a first anti-diffusion film 17b.

[0122] The connection region of the non-volatile semiconductor memory in the third embodiment includes a second metal pad 21, a second interlayer insulating layer 22, a second contact plug 23a, a second contact plug 23b, a second contact plug 23c, a second wiring layer 24, a second barrier metal film 26, a second anti-diffusion film 27a, and a second anti-diffusion film 27b on the control chip 102 side.

[0123] The first metal pad 11 is an example of a first metal layer. The first interlayer insulating layer 12 is an example of a first insulating layer. The first contact plug 13a is an example of a second conductor.

[0124] The second metal pad 21 is an example of a second metal layer. The second interlayer insulating layer 22 is an example of a second insulating layer. The second contact plug 23a is an example of a first conductor. The second contact plug 23b is an example of a third conductor. The second wiring layer 24 is an example of a conductive layer. The second barrier metal film 26 is an example of a conductive film.

[0125] A portion of the first contact plug 13a is disposed in the first metal pad 11. A portion of the first contact plug 13b is disposed in the first metal pad 11. A portion of the first contact plug 13c is disposed in the first metal pad 11.

[0126] A portion of the second contact plug 23a is disposed in the second metal pad 21. A portion of the second contact plug 23b is disposed in the second metal pad 21. A portion of the second contact plug 23c is disposed in the second metal pad 21.

[0127] According to the connection region of the third embodiment, the number of first contact plugs in the first metal pad 11 becomes three. Additionally, the number of second contact plugs in the second metal pad 21 also becomes three. Therefore, compared to the connection region X of the second embodiment, the supply amount of titanium to the pores 80 or the mating surface S is further increased. Consequently, the electromigration resistance of the connection region is further improved.

[0128] Furthermore, the number of first contact plugs in the first metal solder pad 11 can be two or more. Similarly, the number of second contact plugs in the second metal solder pad 21 can be two or more.

[0129] According to the third embodiment, a semiconductor device with improved electromigration resistance and improved reliability can be provided.

[0130] (Fourth implementation)

[0131] The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that another portion of the first conductor is disposed in the first metal layer. Hereinafter, some details that are repeated in the first embodiment will be omitted.

[0132] Figure 18 This is a schematic cross-sectional view of the connection area of ​​the semiconductor device in the fourth embodiment.

[0133] The connection region of the non-volatile semiconductor memory in the fourth embodiment includes a first metal pad 11, a first interlayer insulating layer 12, a first contact plug 13a, a first wiring layer 14, a first barrier metal film 16, a first anti-diffusion film 17a, and a first anti-diffusion film 17b on the memory wafer 101 side.

[0134] The connection region of the non-volatile semiconductor memory in the fourth embodiment includes a second metal pad 21, a second interlayer insulating layer 22, a second contact plug 23a, a second wiring layer 24, a second barrier metal film 26, a second anti-diffusion film 27a, and a second anti-diffusion film 27b on the control chip 102 side.

[0135] The first metal pad 11 is an example of a first metal layer. The first interlayer insulating layer 12 is an example of a first insulating layer. The first contact plug 13a is an example of a second conductor.

[0136] The second metal pad 21 is an example of a second metal layer. The second interlayer insulating layer 22 is an example of a second insulating layer. The second contact plug 23a is an example of a first conductor. The second wiring layer 24 is an example of a conductive layer. The second barrier metal film 26 is an example of a conductive film.

[0137] A portion of the second contact plug 23a is disposed in the second metal pad 21. Additionally, another portion of the second contact plug 23a is disposed in the first metal pad 11. The end of the second contact plug 23a on the first metal pad 11 side is disposed in the first metal pad 11.

[0138] A portion of the second contact plug 23a is surrounded by the second metal solder pad 21. Another portion of the second contact plug 23a is surrounded by the first metal solder pad 11. The end of the second contact plug 23a on the side of the first metal solder pad 11 is surrounded by the first metal solder pad 11.

[0139] The distance between the second contact plug 23a and the first metal pad 11 in the first direction is zero. Therefore, the distance between the second contact plug 23a and the first metal pad 11 in the first direction is smaller than the thickness of the second metal pad 21 in the first direction.

[0140] According to the fourth embodiment, in the connection region, another portion of the second contact plug 23a is disposed in the first metal pad 11, thereby further increasing the amount of titanium supplied to the pores 80 or the mating surface S compared to the connection region X of the first embodiment. Therefore, the electromigration resistance of the connection region is further improved.

[0141] According to the fourth embodiment, a semiconductor device with improved electromigration resistance and improved reliability can be provided.

[0142] In embodiments 1 to 4, a bonding surface S is defined. In the final product of a non-volatile semiconductor memory, there are cases where the position of the bonding surface S between the memory chip 101 and the control chip 102 cannot be clearly observed. However, for example, the position of the bonding surface S can be determined based on the positional offset between the first metal pad 11 and the second metal pad 21.

[0143] In the first to fourth embodiments, an example of a non-volatile semiconductor memory having a memory chip 101 as a first substrate and a control chip 102 as a second substrate was described. However, the semiconductor device of the present invention is not limited to a non-volatile semiconductor memory having a memory chip 101 and a control chip 102. For example, the present invention can also be applied to an optical sensor having a pixel chip as a first substrate and a control chip as a second substrate.

[0144] The foregoing has described several embodiments of the present invention, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment can be substituted or modified with the constituent elements of other embodiments. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and its equivalents.

[0145] [Symbol Explanation]

[0146] 11 First metal pad (first metal layer)

[0147] 12. First interlayer insulation layer (first insulation layer)

[0148] 13a First contact plug (second conductor)

[0149] 15 Memory Cell Array

[0150] 21 Second metal pad (second metal layer)

[0151] 22 Second interlayer insulation layer (second insulation layer)

[0152] 23a Second contact plug (first conductor)

[0153] 23b Second contact plug (third conductor)

[0154] 24 Second wiring layer (conductive layer)

[0155] 25 Control Circuit

[0156] 26. Second barrier metal film (conductive film)

[0157] 100 Non-volatile semiconductor memory (semiconductor device)

[0158] 101 Memory Wafer (Substrate 1)

[0159] 102 Control chip (second substrate).

Claims

1. A semiconductor device comprising: A first substrate, comprising a first insulating layer; The second substrate includes a second insulating layer that is in contact with the first insulating layer and is bonded to the first substrate; A metal layer is disposed on the bonding surface of the first substrate and the second substrate, with a first portion surrounded by the first insulating layer and a second portion surrounded by the second insulating layer; A first conductor is disposed in the second part and extends in a first direction from the second part toward the first part; A conductive film is disposed between the first conductor and the second part, and between the second part and the second insulating layer; In the metal layer, the first element constituting the conductive film segregates near the bonding surface; The distance between the first conductor and the first part in the first direction is less than half the thickness of the second part in the first direction.

2. The semiconductor device of claim 1, wherein the distance between the first conductor and the first portion in the first direction is smaller than the distance between the interface between the first insulating layer and the second insulating layer and the first conductor in a second direction perpendicular to the first direction.

3. The semiconductor device according to claim 1 or 2, wherein the first portion comprises copper and the second portion comprises copper.

4. The semiconductor device according to claim 1 or 2, wherein the first conductor comprises tungsten.

5. The semiconductor device according to claim 1, wherein the first element is titanium.

6. The semiconductor device of claim 1, wherein the conductive film comprises at least one metallic element selected from the group consisting of titanium, tantalum, manganese, and cobalt.

7. The semiconductor device according to claim 1 or 2, wherein the second substrate further comprises: a conductive layer spaced apart from the second portion from the first conductor and electrically connected to the first conductor.

8. The semiconductor device according to claim 1 or 2, wherein the first conductor is separated from the first portion in the first direction.

9. The semiconductor device according to claim 1 or 2, wherein another portion of the first conductor is disposed in the first portion.

10. The semiconductor device according to claim 1 or 2, wherein the first substrate further comprises: a second conductor, at least a portion of which is disposed in the first portion and extends along the first direction.

11. The semiconductor device according to claim 1 or 2, wherein the second substrate further comprises: a third conductor, at least a portion of which is disposed in the second portion and extends along the first direction.

12. The semiconductor device of claim 1 or 2, wherein the first substrate further comprises a memory cell array, and The second substrate also includes control circuitry for controlling the memory cell array.

13. The semiconductor device of claim 12, wherein the first portion is electrically connected to the memory cell array. The second part is electrically connected to the control circuit.

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