Composite power components

Abstract

The present application discloses a composite power component, which includes a substrate structure, an insulating layer, a dielectric layer, a metal oxide semi-conductor field effect transistor, and a Zener diode. The metal oxide semi-conductor field effect transistor is formed in the transistor forming region of the substrate structure. The Zener diode is formed in the circuit component forming region of the substrate structure, and includes a Zener diode doping structure formed in the substrate structure and covered by the insulating layer. The Zener diode doping structure includes a first P-type doping region and a first N-type doping region formed inside the first P-type doping region. The Zener diode also includes a Zener diode metal structure, which is formed on the dielectric layer and sequentially penetrates the dielectric layer and the insulating layer to electrically connect the first P-type doping region and the first N-type doping region. By this, the composite power component of the present application can simplify the process complexity by integrating the formation of different electronic components (such as: Zener diode) into the structure of the metal oxide semi-conductor field effect transistor.

Description

Technical Field

[0001] The present application relates to a power component, and in particular to a composite power component. Background Art

[0002] In existing power components, such as metal oxide semiconductor field effect transistors (MOSFETs), if other circuit components (such as Zener diodes) need to be added to the circuit design to form an electronic circuit with specific functions, these circuit components need to be electrically connected to the power components by welding. However, this connection method between the circuit components and the power components will increase the complexity of product manufacturing and cannot effectively reduce the volume of the product.

[0003] Therefore, the applicant feels that the above-mentioned deficiencies can be improved, and therefore conducts intensive research and applies scientific theories, and finally proposes the present application which has a reasonable design and effectively improves the above-mentioned deficiencies. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a composite power component to address the deficiencies of the prior art.

[0005] In order to solve the above-mentioned technical problems, one of the technical solutions adopted in the present application is to provide a composite power component, including: a substrate structure, including a substrate layer and an epitaxial layer formed on the substrate layer; wherein the epitaxial layer is recessed with at least one groove, and the substrate structure defines a transistor formation area and a circuit component formation area adjacent to the transistor formation area along its length direction, and the groove is located in the transistor formation area; an insulating layer, extendedly formed on the epitaxial layer and on the inner wall of the groove; wherein the portion of the insulating layer located on the inner wall of the groove is defined as a trench insulating layer, which is surrounded by a groove, and the portion of the insulating layer located on the surface of the epitaxial layer is defined as a coating insulating layer; a dielectric layer, formed on the coating insulating layer; a metal oxide semiconductor field effect transistor, located in the transistor formation area, and comprising: a gate filling structure formed in the trench insulating layer in the groove; a base doping structure formed in the epitaxial layer and located in the surrounding area of ​​the groove, the base doping structure being covered by the coating insulating layer; a source metal structure formed on the dielectric layer and sequentially penetrating the dielectric layer and the coating insulating layer to contact the base doping structure; and a drain metal structure formed on a bottom surface of the base layer; and a Zener diode located in the circuit component formation area and comprising: a Zener diode doping structure formed in the epitaxial layer and covered by the coating insulating layer; wherein the Zener diode doping structure comprises a first P-type doping region and a first N-type doping region; and a Zener diode metal structure formed on the dielectric layer and sequentially penetrating the dielectric layer and the coating insulating layer to contact the first P-type doping region and the first N-type doping region of the Zener diode doping structure, so that the Zener diode receives a reverse bias when powered on.

[0006] Optionally, in the Zener diode, the first P-type doping region and the first N-type doping region are both formed by doping downward from a top surface of the epitaxial layer, a doping depth of the first P-type doping region is greater than a doping depth of the first N-type doping region, and a doping range of the first P-type doping region is greater than and covers a doping range of the first N-type doping region.

[0007] Optionally, the first N-type doping region is formed on the inner side of the first P-type doping region, a top surface of the first N-type doping region is coplanar with a top surface of the first P-type doping region, and is flush with the top surface of the epitaxial layer, and the first N-type doping region is surrounded by the first P-type doping region except for the outer edge portion of its top surface.

[0008] Optionally, the Zener diode metal structure includes two metal pins, which are spaced apart from each other and sequentially penetrate the dielectric layer and the covering insulating layer to be electrically connected to the first N-type doping region and the first P-type doping region of the Zener diode doping structure respectively.

[0009] Optionally, one of the metal pins of the Zener diode metal structure is extended to contact the first N-type doping region of the Zener diode doping structure and is not in contact with the first P-type doping region, and another one of the metal pins of the Zener diode metal structure is extended to contact the first P-type doping region of the Zener diode doping structure and is not in contact with the first N-type doping region; wherein, when the composite power component is powered on, the potential of the metal pin connected to the first P-type doping region is lower than the potential of the metal pin connected to the first N-type doping region, thereby generating the reverse bias.

[0010] Optionally, the composite power component further includes: a conventional diode; wherein the conventional diode is also located in the circuit component formation area and is spaced apart from the Zener diode, and the conventional diode includes: a conventional diode doping structure and a conventional diode metal structure; wherein the conventional diode doping structure is formed in the epitaxial layer and is covered by the coating insulating layer, and the conventional diode doping structure includes a second P-type doping region and a second N-type doping region; the conventional diode metal structure includes two metal pins, and the two metal pins of the conventional diode metal structure are spaced apart from each other and both sequentially penetrate the dielectric layer and the coating insulating layer to be electrically connected to the second N-type doping region and the second P-type doping region of the conventional diode doping structure, respectively, so that the conventional diode receives a forward bias when power is turned on.

[0011] Optionally, the composite power component further includes: a resistor; wherein the resistor is also located in the circuit component formation area and is spaced apart from the Zener diode and the conventional diode, and the resistor includes: a resistor doping structure and a resistor metal structure; wherein the resistor doping structure is formed on the coating insulating layer and is covered by the dielectric layer, the resistor doping structure is a P-type doped semiconductor or an N-type doped semiconductor, the resistor metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the resistor doping structure; wherein the resistor generates a resistance when power is supplied.

[0012] Optionally, in the metal oxide semi-conductor field effect transistor, the substrate doping structure includes a substrate P-type doping region and two substrate N-type doping regions formed on the substrate P-type doping region; the two substrate N-type doping regions and the substrate P-type doping region are stacked up and down on each other; the substrate P-type doping region is located on the lower side and abuts against the epitaxial layer; the two substrate N-type doping regions are located on the upper side, on both sides of the top of the substrate P-type doping region, and are formed at intervals from each other; and the two substrate N-type doping regions are both covered by the coating insulating layer.

[0013] Optionally, the source metal structure includes: a source metal conductive part and at least one source metal contact plug connected to the source metal conductive part, the source metal conductive part is formed on the dielectric layer, and the source metal contact plug sequentially penetrates the dielectric layer and the covering insulating layer to be electrically connected to the base doping structure; wherein the source metal contact plug extends to the area between the two base N-type doping regions, and contacts the two base N-type doping regions and also contacts the base P-type doping region.

[0014] Optionally, the two substrate N-type doping regions of the substrate doping structure and the first N-type doping region of the Zener diode doping structure are all completed in the same ion implantation process.

[0015] The beneficial effect of the present application is that the composite power component provided in the embodiment of the present application can form the required power component by integrating the formation of different electronic components (such as: Zener diode) into the structure of the metal oxide semi-conductor field effect transistor, without adding additional processes, thereby simplifying the process complexity.

[0016] In addition, the composite power component provided in the embodiment of the present application is based on the silicon architecture in the design of the Zener diode and the conventional diode. Accordingly, the composite power component provided in the embodiment of the present application can obtain a more stable output voltage and can be applied to a lower and wider input voltage range.

[0017] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, such description and drawings are only used to illustrate the present application and are not intended to limit the scope of protection of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1A to FIG. 1I Schematic diagram of a manufacturing method of a composite power component according to the first embodiment of the present application.

[0019] Figure 2 It is a cross-sectional schematic diagram of a composite power component according to the first embodiment of the present application (indicating the equivalent circuit corresponding to the component structure).

[0020] Figure 3 FIG. 4 is an equivalent circuit diagram of a composite power component according to the first embodiment of the present application.

[0021] Figure 4A It is a partial schematic diagram of a composite power component according to the second embodiment of the present application.

[0022] Figure 4B FIG. 4 is an equivalent circuit diagram of a composite power component according to the second embodiment of the present application.

[0023] Figure 5A It is a partial schematic diagram of a composite power component according to the third embodiment of the present application.

[0024] Figure 5B FIG. 4 is an equivalent circuit diagram of a composite power component according to the third embodiment of the present application. DETAILED DESCRIPTION

[0025] The following is to illustrate the implementation methods disclosed in the present application through specific specific embodiments, and those skilled in the art can understand the advantages and effects of the present application from the content disclosed in this specification. The present application can be implemented or applied through other different specific embodiments, and the details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without deviating from the concept of the present application. In addition, the drawings of the present application are only simple schematic illustrations, not depictions based on actual sizes, and are stated in advance. The following implementation methods will further explain the relevant technical content of the present application in detail, but the disclosed content is not intended to limit the scope of protection of the present application. It should be understood that although the terms "first", "second", "third" and the like may be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used in this article should include any one or more combinations of the associated listed items depending on the actual situation.

[0026] [First embodiment]

[0027] See also FIG. 1A to FIG. 1I , Figure 2 and Figure 3 As shown, the first embodiment of the present application provides a method for manufacturing a composite power component 100. The method for manufacturing a composite power component includes steps S101 to S109. FIG. 1A to FIG. 1I FIG. 1 is a schematic flow chart of a method for manufacturing a composite power component according to the first embodiment of the present application. Figure 2 is a cross-sectional schematic diagram of a composite power component according to the first embodiment of the present application (indicating the equivalent circuit corresponding to the component structure), and Figure 3FIG. 4 is an equivalent circuit diagram of a composite power component according to the first embodiment of the present application.

[0028] It must be noted that the sequence of the steps and the actual operation method in this embodiment can be adjusted according to needs and are not limited to those in this embodiment.

[0029] The composite power component 100 of the present embodiment is a power component based on a metal-oxide-semiconductor field-effect transistor (MOSFET). In other words, the composite power component 100 of the present embodiment is a power component that is improved based on a metal-oxide-semiconductor field-effect transistor. Furthermore, the composite power component 100 of the present embodiment can be applied to a high voltage regulator, for example, but the present application is not limited thereto.

[0030] This embodiment first describes the manufacturing method of the composite power component. For ease of understanding, this embodiment takes a unit area of ​​the manufacturing method of the composite power component as an example and illustrates it with a cross-sectional view. Please refer to the corresponding drawings of each step and refer to the drawings of other steps as needed. The specific steps of the manufacturing method of the composite power component are described as follows.

[0031] like Figure 1A As shown, the step S101 includes: providing a substrate structure 1. The substrate structure 1 includes: a substrate layer 11 and an epitaxial layer 12 formed on the substrate layer 11. The two surfaces of the substrate structure 1 located on opposite sides are respectively defined as a top surface 101 and a bottom surface 102. More specifically, the side surface of the epitaxial layer 12 away from the substrate layer 11 is defined as the top surface 101, and the side surface of the substrate layer 11 away from the epitaxial layer 12 is defined as the bottom surface 102.

[0032] The material of the base layer 11 may be, for example, an N+ type doped semiconductor or a P+ type doped semiconductor. The epitaxial layer 12 may be, for example, formed on the base layer 11 by an epitaxial process, and the material of the epitaxial layer 12 may be, for example, an N-type doped semiconductor or a P-type doped semiconductor. The conductivity type of the epitaxial layer 12 may be, for example, the same as the conductivity type of the base layer 11.

[0033] In this embodiment, the base layer 11 is an N+ doped semiconductor (also referred to as N+

[0034] The epitaxial layer 12 is an N-type doped semiconductor (also referred to as N-EPI). Furthermore, the doping concentration of the base layer 11 is higher than the doping concentration of the epitaxial layer 12. That is, the base layer 11 is a heavily doped region, and the epitaxial layer 12 is a lightly doped region, but the present application is not limited thereto.

[0035] Specifically, the substrate structure 1 defines a transistor forming region A and a circuit element forming region B adjacent to the transistor forming region A along its length direction D. The circuit element forming region B can be further divided into a zener diode forming region B1, a normal diode forming region B2, and a resistor forming region B3.

[0036] It should be noted that, in this embodiment, the Zener diode forming region B1 is located between the conventional diode forming region B2 and the resistor forming region B3, but the present application is not limited thereto. In other words, the present application has no particular restrictions on the layout method and layout order of the Zener diode forming region B1, the conventional diode forming region B2, and the resistor forming region B3.

[0037] like Figure 1B As shown, the step S102 includes: performing a first ion implantation operation to form a first P-type doping region 41P and a second P-type doping region 51P in the epitaxial layer 12 of the substrate structure 1. The first P-type doping region 41P and the second P-type doping region 51P are formed spaced apart from each other and are both located in the circuit component forming region B. More specifically, the first P-type doping region 41P is located in the Zener diode forming region B1, and the second P-type doping region 51P is located in the conventional diode forming region B2.

[0038] Specifically, the first P-type doping region 41P and the second P-type doping region 51P are both formed by ion implantation from the top surface 101 of the epitaxial layer 12 toward the bottom surface 102. The top surface of the first P-type doping region 41P is aligned with the top surface 101 of the epitaxial layer 12, and the top surface of the second P-type doping region 51P is also aligned with the top surface 101 of the epitaxial layer 12.

[0039] Furthermore, the first P-type doping region 41P and the second P-type doping region 51P are both completely formed in the epitaxial layer 12. The bottom of the first P-type doping region 41P and the bottom of the second P-type doping region 51P are not in contact with the base layer 11, but are separated from the base layer 11 by a distance. In the present embodiment, the first P-type doping region 41P is a P-type doping region (P-type region), and the second P-type doping region 51P is also a P-type doping region, but the present application is not limited thereto.

[0040] like Figure 1C As shown, the step S103 includes: performing a trench formation operation to form a plurality of trenches 13 on the epitaxial layer 12 in a concave manner, and the plurality of trenches 13 are all located in the transistor forming region A. The plurality of trenches 13 may be formed, for example, by etching.

[0041] More specifically, the plurality of grooves 13 are recessed at intervals along the length direction D on the surface of the epitaxial layer 12 opposite to the base layer 11, and the bottoms of the plurality of grooves 13 are not in contact with the base layer 11 but are spaced apart from the base layer 11 by a distance. In other words, the plurality of grooves 13 are recessed from the top surface 101 of the substrate structure 1 and are not in contact with the base layer 11 of the substrate structure 1.

[0042] It should be noted that the above-mentioned multiple grooves 13 are described from the perspective of cross-section views for grooves 13 at different locations in the epitaxial layer 12. From a holistic perspective, the grooves 13 may be interconnected structures or mutually separated structures, and the present application does not limit this.

[0043] Furthermore, although the present embodiment is described by first performing the first ion implantation operation (step S102) and then performing the trench formation operation (step S103), the present application is not limited thereto. For example, the trench formation operation may also be performed before the first ion implantation operation.

[0044] like Figure 1D As shown, the step S104 includes: performing an insulation layer formation operation to extendly form an insulation layer 2 (or oxide layer) on the top surface 101 of the epitaxial layer 12, the top surface of the first P-type doping region 41P, the top surface of the second P-type doping region 51P, and the inner walls of multiple trenches 13.

[0045] That is, the insulating layer forming operation can make the top surface 101 of the epitaxial layer 12 , the top surface of the first P-type doping region 41P, the top surface of the second P-type doping region 51P, and the inner walls of the plurality of trenches 13 covered by the insulating layer 2 .

[0046] The insulating layer 2 may be formed, for example, by a low temperature oxide deposition (LTO deposition) process or a thermal oxidation process. Furthermore, the insulating layer 2 may be made of a silicon compound. For example, the insulating layer 2 may be made of silicon dioxide, but the present application is not limited thereto.

[0047] Further, the portion of the insulating layer 2 located on the inner wall of each groove 13 is defined as a groove insulating layer 21 (or a groove oxide layer), and each of the groove insulating layers 21 surrounds a groove 22. That is, a plurality of the groove insulating layers 21 are respectively formed on the inner walls of a plurality of grooves 13, and a plurality of the groove insulating layers 21 surround a plurality of grooves 22. In addition, the remaining portion of the insulating layer 2 (that is, the portion of the insulating layer 2 located on the top surface 101 of the epitaxial layer 12, the top surface of the first P-type doping region 41P, and the top surface of the second P-type doping region 51P) is defined as a capping insulating layer 23 (or a capping oxide layer).

[0048] The plurality of trench insulating layers 21 are all located in the transistor forming region A, and the cap insulating layer 23 is extendedly located in the transistor forming region A and the circuit element forming region B.

[0049] like Figure 1E As shown, the step S105 includes: performing a polysilicon material deposition operation to deposit a polysilicon material M on a surface of the insulating layer 2 away from the epitaxial layer 12, so that the polysilicon material M covers the capping insulating layer 23 and fills the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21. The polysilicon material M can be formed by, for example, silane through a low pressure chemical vapor deposition (LPCVD) process, but the present application is not limited thereto.

[0050] In the present embodiment, the polysilicon material M is deposited on the insulating layer 2 to a certain thickness, so that the outer surface of the polysilicon material M (that is, the surface of the polysilicon material M away from the epitaxial layer 12) is a flat surface. More specifically, the outer surface of the polysilicon material M located above the plurality of grooves 22 and above the covering insulating layer 23 is substantially flush with each other, but the present application is not limited thereto.

[0051] like Figure 1F As shown, the step S106 includes: sequentially performing a photolithography operation and an etching operation on the polysilicon material M to remove a portion of the polysilicon material M. Accordingly, a plurality of polysilicon filling structures M1 are respectively formed in the plurality of grooves 22 surrounded by the plurality of trench insulating layers 21. Moreover, the plurality of polysilicon filling structures M1 are the same as the plurality of trench insulating layers 21, and are all located in the transistor forming region A. Furthermore, a polysilicon block structure M2 is formed on the capping insulating layer 23.

[0052] Furthermore, after the etching operation, the exposed surfaces of the polysilicon filling structures M1 (ie, Figure 1F The top surface of the polysilicon filling structure M1 in the embodiment of the present invention is lower than the outer surface of the capping insulating layer 23 (that is, Figure 1F The top surface of the covering insulating layer 23 is shown in FIG. 1 , but the present application is not limited thereto.

[0053] Furthermore, the polysilicon block structure M2 is formed on a surface of the coating insulating layer 23 away from the epitaxial layer 12, and the polysilicon block structure M2 is located in the resistor forming area B3 so as to be made into a specific circuit component (such as a resistor) in the subsequent manufacturing process.

[0054] That is to say, the polycrystalline silicon block structure M2 is different from the first P-type doping region 41P and the second P-type doping region 51P. The polycrystalline silicon block structure M2 is formed on the top surface of the covering insulating layer 23, and the first P-type doping region 41P and the second P-type doping region 51P are formed in the epitaxial layer 12 and are covered by the covering insulating layer 23.

[0055] From another perspective, the polysilicon block structure M2 is located on one side of the covering insulating layer 23, and the first P-type doping region 41P and the second P-type doping region 51P are located on the other side of the covering insulating layer 23. Furthermore, the polysilicon block structure M2 and the first P-type doping region 41P and the second P-type doping region 51P are located at different positions along the length direction D.

[0056] In addition, it is worth mentioning that in the present embodiment, the raw material M of the polysilicon filling structure M1 and the polysilicon block structure M2 is formed in the same polysilicon deposition process, but the present application is not limited thereto. For example, the raw material M of the polysilicon filling structure M1 and the polysilicon block structure M2 can also be formed through different polysilicon deposition processes according to process requirements.

[0057] like Figure 1G As shown, the step S107 includes: implementing a second ion implantation operation to form each of the polysilicon filling structures M1 into a gate filling structure 31 (or doped polysilicon filling structure), forming a portion of the epitaxial layer 12 located between any two adjacent trenches 13 into a matrix doped structure 32 (matrix doped structure), forming a first N-type doped region 41N on the inner side of the first P-type doped region 41P, forming a second N-type doped region 51N on the inner side of the second P-type doped region 51P, and forming the polysilicon block structure M2 into a resistor doped structure 61.

[0058] It is worth mentioning that in this embodiment, in order to perform different doping (such as P-type doping or N-type doping) on ​​the polysilicon materials M1, M2 and the epitaxial layer 12, the ion implantation process may, for example, include multiple ion implantation procedures (such as P-type doping ion implantation procedure and N-type doping ion implantation procedure).

[0059] Furthermore, each of the gate filling structures 31 can be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor, which is not limited in the present application.

[0060] Further, each of the substrate doping structures 32 includes a substrate P-type doping region 32P and two substrate N-type doping regions 32N formed on the substrate P-type doping region 32P. Specifically, in each of the substrate doping structures 32, the two substrate N-type doping regions 32N and the substrate P-type doping region 32P are stacked one above the other. The substrate P-type doping region 32P is located on the lower side and abuts against the epitaxial layer 12. The two substrate N-type doping regions 32N are located on the upper side, on both sides of the top of the substrate P-type doping region 32P, and are formed at intervals from each other. Furthermore, the two substrate N-type doping regions 32N are both covered by the coating insulating layer 23.

[0061] It is worth mentioning that the conductivity type of the substrate P-type doping region 32P is different from the conductivity type of the above-mentioned base layer 11 (N+ type doped semiconductor) and the conductivity type of the above-mentioned epitaxial layer 12 (N- type doped semiconductor). Specifically, the plurality of substrate P-type doping regions 32P of the present embodiment are P-type doped semiconductors, and the implanted ion type can be, for example, boron ions (B+), but the present application is not limited thereto.

[0062] Specifically, the first P-type doping region 41P and the first N-type doping region 41N together form a Zener diode doping structure 41. The first P-type doping region 41P and the first N-type doping region 41N are both formed from the top surface 101 of the epitaxial layer 12 toward the bottom surface 102.

[0063] Furthermore, in the epitaxial layer 12, the doping depth of the first P-type doping region 41P is greater than the doping depth of the first N-type doping region 41N, the doping range of the first P-type doping region 41P is greater than the doping range of the first N-type doping region 41N, and the doping range of the first P-type doping region 41P covers the doping range of the first N-type doping region 41N.

[0064] From another perspective, the first N-type doping region 41N is formed inside the first P-type doping region 41P. The top surface of the first N-type doping region 41N is coplanar with the top surface of the first P-type doping region 41P, and is aligned with the top surface 101 of the epitaxial layer 12. The top surface 101 of the epitaxial layer 12, the top surface of the first N-type doping region 41N, and the top surface of the first P-type doping region 41P are all covered by the capping insulating layer 23. Furthermore, the first N-type doping region 41N is surrounded by the first P-type doping region 41P except for the outer edge of its top surface.

[0065] Further, similar to the Zener diode doping structure 41, the second P-type doping region 51P and the second N-type doping region 51N together form a conventional diode doping structure 51. The second P-type doping region 51P and the second N-type doping region 51N are both formed from the top surface 101 of the epitaxial layer 12 toward the bottom surface 102.

[0066] Furthermore, in the epitaxial layer 12, the doping depth of the second P-type doping region 51P is greater than the doping depth of the second N-type doping region 51N, the doping range of the second P-type doping region 51P is greater than the doping range of the second N-type doping region 51N, and the doping range of the second P-type doping region 51P covers the doping range of the second N-type doping region 51N.

[0067] From another perspective, the second N-type doping region 51N is formed inside the top of the second P-type doping region 51P. The top surface of the second N-type doping region 51N is coplanar with the top surface of the second P-type doping region 51P, and is aligned with the top surface 101 of the epitaxial layer 12. The top surface 101 of the epitaxial layer 12, the top surface of the second N-type doping region 51N, and the top surface of the second P-type doping region 51P are all covered by the capping insulating layer 23. Furthermore, the second N-type doping region 51N is surrounded by the second P-type doping region 51P except for the outer edge of its top surface.

[0068] Furthermore, the resistor doping structure 61 may be, for example, one of a P-type doped semiconductor and an N-type doped semiconductor. In this embodiment, the P-type doped semiconductor is preferred, but the present application is not limited thereto. Furthermore, the doping concentration of the resistor doping structure 61 is lower than the doping concentration of the Zener diode doping structure 41 or the doping concentration of the conventional diode doping structure 51 to produce a resistor effect.

[0069] It is worth mentioning that in the present embodiment, the two substrate N-type doping regions 32N of each of the substrate doping structures 32, the first N-type doping region 41N of the Zener diode doping structure 41, and the second N-type doping region 51N of the conventional diode doping structure 51 are all completed in the same ion implantation process and have substantially the same doping depth, but the present application is not limited thereto.

[0070] It should be noted that the types of ions used in the ion implantation process described in this article may be, for example: boron ions (B+), zinc ions (Zn2+), fluorine ions (F-), nitrogen ions (N-), oxygen ions (O2-), carbon ions (C4+), argon ions (Ar+), phosphorus ions (P+), arsenic ions (As+), or antimony ions (Sb2+).

[0071] like Figure 1HAs shown, the step S108 includes: performing a dielectric layer formation operation to form an inter layer dielectric (ILD) layer 7 on the substrate structure 1 , and making the capping insulating layer 23 , the gate filling structure 31 , and the resistor doping structure 61 covered by the dielectric layer 7 .

[0072] The dielectric layer 7 may be formed, for example, by a chemical vapor deposition process, but the present application is not limited thereto. For example, the dielectric layer 7 may also be formed, for example, by a physical vapor deposition process or other suitable deposition processes. Furthermore, the material of the dielectric layer 7 may be, for example, a silicon compound or other dielectric material.

[0073] Furthermore, the outer surface of the dielectric layer 7 may be planarized by, for example, a chemical mechanical polishing (CMP) process, but the present application is not limited thereto.

[0074] like Fig. 1I As shown, the step S109 includes: performing a metallization operation to form a source metal structure 33, a Zener diode metal structure 42, a conventional diode metal structure 52, and a resistor metal structure 62 on the dielectric layer 7, and forming a drain metal structure 34 on the bottom surface 102 of the substrate structure 1.

[0075] It should be noted that the “metal structure” mentioned in this article can be formed by deposition, for example, and the “metal structure” can be an integrated structure formed by aluminum / silicon / copper alloy, but in practical applications, it is not limited to this.

[0076] Specifically, the source metal structure 33 is located in the transistor forming region A. The source metal structure 33 is formed on a surface of the dielectric layer 7 away from the base layer 11 , and sequentially penetrates the dielectric layer 7 and the covering insulating layer 23 to be electrically connected to at least one of the plurality of base doping structures 32 .

[0077] In this embodiment, the source metal structure 33 includes a source metal conductive portion 331 and two source metal contact plugs 332 connected to the source metal conductive portion 331 .

[0078] The source metal conductive portion 331 is formed on a surface of the dielectric layer 7 opposite to the base layer 11. The two source metal contact plugs 332 are arranged at intervals from each other and sequentially penetrate the dielectric layer 7 and the covering insulating layer 23, so that the source metal conductive portion 331 can be electrically connected to two adjacent base doping structures 32 among the plurality of base doping structures 32 through the two source metal contact plugs 332.

[0079] Furthermore, the width of each source metal contact plug 332 is smaller than the width of the base doping structure 32 to which it is connected. Each source metal contact plug 332 extends to the area between the two corresponding base N-type doping regions 32N, and contacts the two base N-type doping regions 32N and the base P-type doping region 32P. Thus, the two source metal contact plugs 332 are set at the same potential compared to the two base doping structures 32 to which they are electrically connected.

[0080] It is worth mentioning that, in the present embodiment, the extension depth of each source metal contact plug 332 extending between the two base N-type doping regions 32N is preferably less than the doping depth of the two base N-type doping regions 32N. In other words, the extension depth of each source metal contact plug 332 extending between the two base N-type doping regions 32N is preferably not more than the two base N-type doping regions 32N, but the present application is not limited thereto.

[0081] The drain metal structure 34 is formed on the bottom surface 102 of the substrate structure 1. In other words, the drain metal structure 34 is formed on a surface of the base layer 11 opposite to the epitaxial layer 12. In this embodiment, the drain metal structure 34 fully covers the bottom surface 102 of the substrate structure 1, but the present application is not limited thereto.

[0082] According to the above configuration, if Figure 2 As shown, the source metal structure 33 can be used to electrically connect a source wire 33L to define a source S (source) of the metal oxide semi-conductor field effect transistor. The drain metal structure 34 can be used to electrically connect a drain wire 34L to define a drain D (drain) of the metal oxide semi-conductor field effect transistor. Furthermore, one of the gate filling structures 31 (such as Figure 2 The rightmost gate filling structure in the figure can be used to electrically connect a gate wire 31L to define the gate G (gate) of the MOSFET. The above-mentioned components located in the transistor forming area A (such as: source metal structure 33, drain metal structure 34, gate filling structure 31, etc.) can form a MOSFET 3, and its equivalent circuit is as follows: Figure 3 shown.

[0083] Please continue reading Fig. 1I and Figure 2 As shown, the Zener diode metal structure 42 , the conventional diode metal structure 52 , and the resistor metal structure 62 are all located in the circuit element forming region B.

[0084] The Zener diode metal structure 42 is located in the Zener diode forming region B1, and the Zener diode metal structure 42 is formed on a surface of the dielectric layer 7 opposite to the base layer 11, and sequentially penetrates the dielectric layer 7 and the covering insulating layer 23 to contact and electrically connect to the Zener diode doping structure 41 covered by the covering insulating layer 23. The Zener diode metal structure 42 and the Zener diode doping structure 41 can be matched with each other to form a Zener diode 4 (Vz). The Zener diode 4 is configured to receive a reverse bias, and the Zener diode 4 can withstand a voltage between 5 volts and 6 volts.

[0085] In this embodiment, the Zener diode metal structure 42 includes two metal pins 421. The two metal pins 421 of the Zener diode metal structure 42 are spaced apart from each other and sequentially penetrate the dielectric layer 7 and the covering insulating layer 23 to be electrically connected to the first N-type doping region 41N and the first P-type doping region 41P of the Zener diode doping structure 41, respectively, so as to form the Zener diode 4.

[0086] More specifically, one of the metal pins 421 of the Zener diode metal structure 42 extends to contact the first N-type doping region 41N of the Zener diode doping structure 41, and does not contact the first P-type doping region 41P. In other words, an extension depth of the metal pin 421 contacting the first N-type doping region 41N preferably does not exceed a doping depth of the first N-type doping region 41N.

[0087] Furthermore, another metal pin 421 of the Zener diode metal structure 42 is extended to contact the first P-type doping region 41P of the Zener diode doping structure 41 , and is not in contact with the first N-type doping region 41N.

[0088] Specifically, in the Zener diode 4, the potential of the metal pin 421 connected to the first P-type doping region 41P is "lower" than the potential of the metal pin 421 connected to the first N-type doping region 41N, thereby generating a "reverse bias" when the power component is powered on.

[0089] The normal diode metal structure 52 is located in the normal diode forming region B2, and the normal diode metal structure 52 is formed on the surface of the dielectric layer 7 opposite to the base layer 11, and sequentially penetrates the dielectric layer 7 and the covering insulating layer 23 to contact and electrically connect to the normal diode doping structure 51 covered by the covering insulating layer 23. The normal diode metal structure 52 and the normal diode doping structure 51 can be matched with each other to form a normal diode 5 (normal diode, VD). The normal diode 5 is configured to receive a forward bias, and the normal diode 5 can withstand a voltage between 0 volts and 0.7 volts.

[0090] In this embodiment, the conventional diode metal structure 52 includes two metal pins 521. The two metal pins 521 of the conventional diode metal structure 52 are spaced apart from each other and sequentially penetrate the dielectric layer 7 and the covering insulating layer 23 to be electrically connected to the second N-type doping region 51N and the second P-type doping region 51P of the conventional diode doping structure 51, respectively, so as to form the conventional diode 5.

[0091] More specifically, one of the metal pins 521 of the conventional diode metal structure 52 is extended to contact the second N-type doping region 51N of the conventional diode doping structure 51, and is not in contact with the second P-type doping region 51P. In other words, an extension depth of the metal pin 521 in contact with the second N-type doping region 51N preferably does not exceed a doping depth of the second N-type doping region 51N.

[0092] Furthermore, another metal pin 521 of the conventional diode metal structure 52 is extended to contact the second P-type doping region 51P of the conventional diode doping structure 51 , and is not in contact with the second N-type doping region 51N.

[0093] Furthermore, in the conventional diode 5, the potential of the metal pin 521 connected to the second P-type doping region 51P is "higher" than the potential of the metal pin 521 connected to the second N-type doping region 51N, thereby generating a "forward bias" when the power component is powered on.

[0094] It is worth mentioning that in the present embodiment, in the conventional diode 5, the metal pin 521 connected to the second P-type doping region 51P can be electrically connected to one of the gate filling structures 31 (such as gate filling structure 31) among the plurality of gate filling structures 31 through a wire (not shown). Figure 2Furthermore, the metal pin 521 connected to the second N-type doping region 51N can be electrically connected to the source metal structure 33 of the MOSFET 3 through a wire (not shown), but the present application is not limited thereto.

[0095] The resistor metal structure 62 is located in the resistor forming area B3, and is formed on the surface of the dielectric layer 7 opposite to the base layer 11, and partially penetrates the dielectric layer 7 to contact and electrically connect to the resistor doping structure 61 located on the surface of the coating insulating layer 23. The resistor metal structure 62 and the resistor doping structure 61 can be matched with each other to form a resistor 6 (resistor, R).

[0096] In this embodiment, the resistor metal structure 62 includes two metal pins 621. The two metal pins 621 of the resistor metal structure 62 are spaced apart from each other and partially penetrate the dielectric layer 7 to contact and electrically connect to the resistor doping structure 61 (e.g., P-type doped semiconductor). The doping concentration of the resistor doping structure 61 is lower than the doping concentration of the Zener diode doping structure 41 and the doping concentration of the conventional diode doping structure 51, so as to generate a resistor effect when the power component is powered on.

[0097] After implementing the above-mentioned steps S101 to S109, the following steps can be completed: Fig. 1I and Figure 2 The composite power device 100 (or trench power device) is shown.

[0098] The equivalent circuit diagram of the composite power component 100 of this embodiment is as follows: Figure 3 As shown. It should be emphasized that in actual application, each step does not exclude the possibility of replacing with a reasonable variation. Furthermore, it should be emphasized that the above steps are described from the perspective of a cross-sectional view. Under the premise of complying with the above steps, the possibility of implementing the present application with various design layouts is not excluded. In other words, if viewed from a top view, the composite power component 100 of this embodiment can have different design layout types.

[0099] According to the above configuration, the manufacturing method of the composite power component provided in the embodiment of the present application can integrate the formation of different electronic components (such as Zener diodes, conventional diodes, resistors) into the process of metal oxide semi-conductor field effect transistors to form the required power components without adding additional processes, thereby simplifying the process complexity.

[0100] In addition, the composite power component provided in the embodiment of the present application is based on a silicon structure in the design of the Zener diode and the conventional diode (that is, the Zener diode doping structure 41 and the conventional diode doping structure 51 are formed in the epitaxial layer 12). Accordingly, the composite power component provided in the embodiment of the present application can obtain a more stable output voltage and can be applied to a lower and wider input voltage range.

[0101] The above is a description of the manufacturing method of the composite power component of the embodiment of the present application, and the specific structure of the composite power component of the present embodiment is described below. It must be noted that although the composite power component of the present embodiment is manufactured by the above manufacturing method, the present application is not limited thereto. In other words, the composite power component of the present application can also be manufactured by other manufacturing methods.

[0102] like Fig. 1I Please match with Figure 2 and Figure 3 This embodiment further discloses a composite power component 100, which includes: a substrate structure 1, an insulating layer 2, a dielectric layer 7, a metal oxide semiconductor field effect transistor 3 (MOSFET), a Zener diode 4 (VZ), a conventional diode 5 (VD), and a resistor 6 (R).

[0103] The substrate structure 1 includes a base layer 11 and an epitaxial layer 12 formed on the base layer 11. The epitaxial layer 12 is recessed with at least one groove 13. The substrate structure 1 defines a transistor forming region A and a circuit component forming region B adjacent to the transistor forming region A along its length direction D, and the groove 13 is located in the transistor forming region A.

[0104] The insulating layer 2 is extendedly formed on the epitaxial layer 12 and the inner wall of the trench 13. The portion of the insulating layer 2 located on the inner wall of the trench 13 is defined as a trench insulating layer 21, which surrounds a groove 22, and the portion of the insulating layer 2 located on the surface of the epitaxial layer 12 is defined as a covering insulating layer 23. Furthermore, the dielectric layer 7 is formed on the covering insulating layer 23 of the insulating layer 2.

[0105] The MOSFET 3 is located in the transistor formation region A and includes: a gate filling structure 31, a base doping structure 32, a source metal structure 33, and a drain metal structure 34. The gate filling structure 31 is formed in the groove 22 of the trench insulating layer 21. The base doping structure 32 is formed in the epitaxial layer 12 and is located in the surrounding area of ​​the trench 13, and the base doping structure 32 is covered by the coating insulating layer 23. The source metal structure 33 is formed on the dielectric layer 7 and sequentially penetrates the dielectric layer 7 and the coating insulating layer 23 to contact and electrically connect the base doping structure 32. The drain metal structure 34 is formed on the bottom surface of the base layer 11.

[0106] The Zener diode 4 is located in the circuit component forming area B and includes: a Zener diode doping structure 41 and a Zener diode metal structure 42. The Zener diode doping structure 41 is formed in the epitaxial layer 12 and is covered by the capping insulating layer 23. The Zener diode doping structure 41 includes a first P-type doping region 41P and a first N-type doping region 41N.

[0107] The first P-type doping region 41P and the first N-type doping region 41N are both formed by doping downward from the top surface 101 of the epitaxial layer 12. The doping depth of the first P-type doping region 41P is greater than the doping depth of the first N-type doping region 41N. The doping range of the first P-type doping region 41P is greater than and covers the doping range of the first N-type doping region 41N. The first N-type doping region 41N is formed on the inner side of the first P-type doping region 41P. The top surface of the first N-type doping region 41N is coplanar with the top surface of the first P-type doping region 41P, and is aligned with the top surface 101 of the epitaxial layer 12. The first N-type doping region 41N is surrounded by the first P-type doping region 41P except for the outer edge of its top surface.

[0108] The Zener diode metal structure 42 includes two metal pins 421. The two metal pins 421 of the Zener diode metal structure 42 are spaced apart from each other and sequentially penetrate the dielectric layer 7 and the covering insulating layer 23 to be electrically connected to the first N-type doping region 41N and the first P-type doping region 41P of the Zener diode doping structure 41, respectively.

[0109] More specifically, one of the metal pins 421 of the Zener diode metal structure 42 is extended to contact the first N-type doping region 41N of the Zener diode doping structure 41, and is not in contact with the first P-type doping region 41P. Furthermore, another of the metal pins 421 of the Zener diode metal structure 42 is extended to contact the first P-type doping region 41P of the Zener diode doping structure 41, and is not in contact with the first N-type doping region 41N. In addition, the Zener diode 4 is configured to receive a reverse bias when the composite power device 100 is powered on.

[0110] The conventional diode 5 is also located in the circuit component forming area B and is spaced apart from the Zener diode 4. The conventional diode 5 includes: a conventional diode doping structure 51 and a conventional diode metal structure 52. The conventional diode doping structure 51 is formed in the epitaxial layer 12 and is covered by the coating insulating layer 23. The conventional diode doping structure 51 includes a second P-type doping region 51P and a second N-type doping region 51N. The conventional diode metal structure 52 includes two metal pins 521. The two metal pins 521 of the conventional diode metal structure 52 are spaced apart from each other and both sequentially penetrate the dielectric layer 7 and the coating insulating layer 23 to be electrically connected to the second N-type doping region 51N and the second P-type doping region 51P of the conventional diode doping structure 51, respectively. The structure of the conventional diode 5 is similar to that of the Zener diode 4, and will not be described in detail here. The difference is that the conventional diode 5 is configured to receive a forward bias when the composite power component 100 is powered on.

[0111] The resistor 6 is also located in the circuit component forming area B and is spaced apart from the Zener diode 4 and the conventional diode 5. The resistor 6 includes: a resistor doping structure 61 and a resistor metal structure 62. The resistor doping structure 61 is formed on the coating insulating layer 23 and is covered by the dielectric layer 7. The resistor doping structure 61 is a P-type doped semiconductor or an N-type doped semiconductor. The resistor metal structure 62 is formed on the dielectric layer and sequentially penetrates the dielectric layer 7 to be electrically connected to the resistor doping structure 61. Furthermore, the resistor 6 is configured to generate a resistance when the composite power component 100 is powered on.

[0112] [Second embodiment]

[0113] See also Figure 4A and Figure 4B As shown, the second embodiment of the present application also provides a composite power component 100 ′. Figure 4A is a partial schematic diagram of a composite power component according to a second embodiment of the present application, and Figure 4B FIG. 4 is an equivalent circuit diagram of a composite power component according to the second embodiment of the present application.

[0114] The structural design of the composite power component 100 ′ of the second embodiment of the present application is substantially the same as that of the first embodiment, except that the composite power component 100 ′ of this embodiment has a plurality of Zener diodes 4 ( VZ1 to VZN ) connected in series.

[0115] More specifically, in the present embodiment, the number of the Zener diodes 4 is plural, and the plurality of Zener diodes 4 (VZ1 to VZN) are arranged in series with each other and are located in the Zener diode forming region B1 of the circuit component forming region B. The number of the plurality of Zener diodes 4 may be, for example, two or more.

[0116] More specifically, the plurality of Zener diodes 4 connected in series are arranged in an alternating manner of "N-type doping region / P-type doping region / N-type doping region / P-type doping region..." Among any two adjacent Zener diodes 4 connected in series, the metal pin 421 of one of the Zener diodes 4 connected to the P-type doping region 41P is directly in contact with and electrically connected to the metal pin 421 of another of the Zener diodes 4 connected to the N-type doping region 41N. Furthermore, the Zener diode doping structure 41 of one of the Zener diodes 4 is not directly in contact with the Zener diode doping structure 41 of another of the Zener diodes 4.

[0117] like Figure 4B As shown, since the composite power component 100' of this embodiment has a plurality of Zener diodes 4 (VZ1 to VZN) connected in series, the number of Zener diodes 4 can be adjusted to change VG, thereby controlling the driving voltage of the composite power component 100' to achieve the feasibility of driving various power metal oxide semiconductor field effect transistors (Power MOSFET).

[0118] [Third embodiment]

[0119] See also Figure 5A and Figure 5B As shown, the third embodiment of the present application also provides a composite power component 100". Figure 5A is a partial schematic diagram of a composite power component according to the third embodiment of the present application, and Figure 5B FIG. 4 is an equivalent circuit diagram of a composite power component according to the third embodiment of the present application.

[0120] The structural design of the composite power component 100 ″ of the third embodiment of the present application is substantially the same as that of the first embodiment, except that the composite power component 100 ″ of this embodiment has a plurality of conventional diodes 5 ( VD1 to VDN ) connected in series.

[0121] More specifically, in this embodiment, the number of the conventional diodes 5 is plural, and the plurality of conventional diodes 5 (VD1 to VDN) are arranged in series with each other and are located in the conventional diode forming region B2 of the circuit component forming region B. The number of the plurality of conventional diodes 5 may be, for example, two or more.

[0122] More specifically, the plurality of conventional diodes 5 connected in series are arranged in an alternating manner of "N-type doping region / P-type doping region / N-type doping region / P-type doping region..." Among any two adjacent conventional diodes 5 connected in series, the metal pin 521 of one of the conventional diodes 5 connected to the P-type doping region 51P is directly in contact with and electrically connected to the metal pin 521 of another conventional diode 5 connected to the N-type doping region 51N. Furthermore, the conventional diode doping structure 51 of one of the conventional diodes 5 is not directly in contact with the conventional diode doping structure 51 of another conventional diode 5.

[0123] like Figure 5B As shown, since the composite power component 100" of this embodiment has a plurality of conventional diodes 5 (VD1 to VDN) connected in series with each other, the driving voltage of the composite power component 100" can be controlled by adjusting the number of conventional diodes 5 to achieve the feasibility of driving various power metal oxide semiconductor field effect transistors (Power MOSFET).

[0124] It is worth mentioning that in an embodiment not shown in the present application, the composite power component may also have a plurality of Zener diodes 4 (VZ1 to VZN) connected in series with each other and a plurality of conventional diodes 5 (VD1 to VDN) connected in series with each other, so that the composite power component has a wider range of applications.

[0125] [Beneficial Effects of Embodiments]

[0126] The beneficial effect of the present application is that the composite power component provided in the embodiment of the present application can form the required power component by integrating the formation of different electronic components (such as: Zener diodes, conventional diodes, resistors) into the structure of metal oxide semi-conductor field effect transistors, without adding additional processes, thereby simplifying the process complexity.

[0127] In addition, the composite power component provided in the embodiment of the present application is based on the silicon architecture in the design of the Zener diode and the conventional diode. Accordingly, the composite power component provided in the embodiment of the present application can obtain a more stable output voltage and can be applied to a lower and wider input voltage range.

[0128] Furthermore, since the composite power component of the present embodiment can be designed with a plurality of Zener diodes 4 (VZ1 to VZN) connected in series and / or a plurality of conventional diodes (VD1 to VDN) connected in series, the number of Zener diodes and conventional diodes can be adjusted to change VG, thereby controlling the driving voltage of the composite power component to achieve the feasibility of driving various power metal oxide semiconductor field effect transistors (Power MOSFET). In addition, the structural design of the composite power component of the present embodiment can reduce the number of electronic components required to be placed on the system circuit board, because some of its electronic components are integrated into the integrated component manufacturing process of the present application, thereby reducing the size of the terminal product.

[0129] The contents disclosed above are only preferred feasible embodiments of the present application, and are not intended to limit the scope of the present patent application. Therefore, all equivalent technical changes made using the description and drawings of the present application are included in the scope of the present patent application.

Claims

1. A composite power component, characterized in that: The composite power component comprises: A substrate structure, comprising a substrate layer and an epitaxial layer formed on the substrate layer; wherein the epitaxial layer is recessed with at least one groove, the substrate structure defines a transistor forming region and a circuit component forming region adjacent to the transistor forming region along its length direction, and the groove is located in the transistor forming region; an insulating layer, extendedly formed on the epitaxial layer and the inner wall of the trench; wherein the portion of the insulating layer located on the inner wall of the trench is defined as a trench insulating layer, which surrounds a groove, and the portion of the insulating layer located on the surface of the epitaxial layer is defined as a covering insulating layer; a dielectric layer formed on the coating insulating layer; A metal oxide semi-conductor field effect transistor is located in the transistor forming region and comprises: a gate filling structure formed in the groove of the trench insulating layer; A substrate doping structure is formed in the epitaxial layer and is located in the surrounding area of ​​the groove, and the substrate doping structure is covered by the coating insulating layer; the substrate doping structure includes a substrate P-type doping region and two substrate N-type doping regions formed on the substrate P-type doping region; the two substrate N-type doping regions and the substrate P-type doping region are stacked up and down with each other; the substrate P-type doping region is located at the lower side and abuts against the epitaxial layer; the two substrate N-type doping regions are located at the upper side, at both sides of the top of the substrate P-type doping region, and are formed at intervals from each other; and the two substrate N-type doping regions are both covered by the coating insulating layer; a source metal structure formed on the dielectric layer and sequentially penetrating the dielectric layer and the covering insulating layer to contact the base doping structure; the source metal structure comprises: a source metal conductive portion and at least one source metal contact plug connected to the source metal conductive portion, the source metal conductive portion is formed on the dielectric layer, the source metal contact plug sequentially penetrating the dielectric layer and the covering insulating layer to be electrically connected to the base doping structure; and a drain metal structure formed on a bottom surface of the base layer; wherein the source metal contact plug extends to a region between the two base N-type doping regions, and contacts the two base N-type doping regions and the base P-type doping region; wherein the extension depth of the source metal contact plug extending between the two base N-type doping regions does not exceed the two base N-type doping regions; and a Zener diode located in the circuit component forming area and comprising: a Zener diode doping structure formed in the epitaxial layer and covered by the capping insulating layer; wherein the Zener diode doping structure includes a first P-type doping region and a first N-type doping region; and A Zener diode metal structure is formed on the dielectric layer and sequentially penetrates the dielectric layer and the covering insulating layer to contact the first P-type doping region and the first N-type doping region of the Zener diode doping structure, so that the Zener diode receives a reverse bias when powered on; wherein the two substrate N-type doping regions of the substrate doping structure and the first N-type doping region of the Zener diode doping structure are both completed in the same ion implantation process and have substantially the same doping depth.

2. The composite power component according to claim 1, characterized in that: In the Zener diode, the first P-type doping region and the first N-type doping region are both formed by doping downward from a top surface of the epitaxial layer, a doping depth of the first P-type doping region is greater than a doping depth of the first N-type doping region, and a doping range of the first P-type doping region is greater than and covers a doping range of the first N-type doping region.

3. The composite power component according to claim 2, characterized in that: The first N-type doping region is formed on the inner side of the first P-type doping region, a top surface of the first N-type doping region is coplanar with a top surface of the first P-type doping region, and is flush with the top surface of the epitaxial layer, and the first N-type doping region is surrounded by the first P-type doping region except for the outer edge portion of its top surface.

4. The composite power component according to any one of claims 2 and 3, characterized in that: The Zener diode metal structure includes two metal pins, which are spaced apart from each other and sequentially penetrate the dielectric layer and the covering insulating layer to be electrically connected to the first N-type doping region and the first P-type doping region of the Zener diode doping structure respectively.

5. The composite power component according to claim 4, characterized in that: One of the metal pins of the Zener diode metal structure is extended to contact the first N-type doping region of the Zener diode doping structure and is not in contact with the first P-type doping region, and another one of the metal pins of the Zener diode metal structure is extended to contact the first P-type doping region of the Zener diode doping structure and is not in contact with the first N-type doping region; wherein, when the composite power component is powered on, the potential of the metal pin connected to the first P-type doping region is lower than the potential of the metal pin connected to the first N-type doping region, thereby generating the reverse bias.

6. The composite power component according to claim 1, characterized in that: The composite power component further includes: a conventional diode; wherein the conventional diode is also located in the circuit component formation area and is spaced apart from the Zener diode, and the conventional diode includes: a conventional diode doping structure and a conventional diode metal structure; wherein the conventional diode doping structure is formed in the epitaxial layer and is covered by the coating insulating layer, and the conventional diode doping structure includes a second P-type doping region and a second N-type doping region; the conventional diode metal structure includes two metal pins, and the two metal pins of the conventional diode metal structure are spaced apart from each other and both sequentially penetrate the dielectric layer and the coating insulating layer to be electrically connected to the second N-type doping region and the second P-type doping region of the conventional diode doping structure, respectively, so that the conventional diode receives a forward bias when powered on.

7. The composite power component according to claim 6, characterized in that: The composite power component further includes: a resistor; wherein the resistor is also located in the circuit component forming area and is spaced apart from the Zener diode and the conventional diode, and the resistor includes: a resistor doping structure and a resistor metal structure; wherein the resistor doping structure is formed on the coating insulating layer and is covered by the dielectric layer, the resistor doping structure is a P-type doped semiconductor or an N-type doped semiconductor, the resistor metal structure is formed on the dielectric layer and partially penetrates the dielectric layer to be electrically connected to the resistor doping structure; wherein the resistor generates a resistance when power is supplied.

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