Mask manufacturing method, semiconductor device manufactured using the mask, and method for manufacturing the same

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate including a first region, a second region, and a connection region placed between the first region and the second region; a plurality of first multi-channel active patterns placed in the first region of the substrate; a plurality of second multi-channel active patterns placed in the second region of the substrate; a first connection fin-type pattern placed in the connection region of the substrate and extending from the first region to the second region in a first direction; and a field insulating film placed on the substrate and covering an upper surface of the first connection fin-type pattern, wherein a width of the first connection fin-type pattern in a second direction decreases and then increases as it moves away from the first region, and the first direction is perpendicular to the second direction.

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a mask, a method for manufacturing a semiconductor device using the mask, and a semiconductor device manufactured using the mask. Background Technology

[0002] To manufacture highly integrated semiconductor devices, patterns are miniaturized. In manufacturing processes that integrate many components into a small area, the size of each component needs to be formed as small as possible, and the pitch, which is the sum of the width of each pattern to be formed and the spacing between patterns, also needs to be manufactured small.

[0003] Recently, the design rules for semiconductor devices have been drastically reduced. However, limitations exist in forming patterns with fine pitches for realizing these semiconductor devices due to the resolution limitations of available photolithography processes. Summary of the Invention

[0004] This disclosure provides a semiconductor device that can reduce chip area while ensuring the operating characteristics of transistors formed in different regions by preventing interference between transistors formed in different regions.

[0005] This disclosure also provides a method for manufacturing a mask that can reduce chip area while ensuring the operating characteristics of transistors formed in different regions by preventing interference between them.

[0006] This disclosure also provides a method for manufacturing a semiconductor device that can reduce chip area while ensuring the operating characteristics of transistors formed in different regions by preventing interference between transistors formed in different regions.

[0007] According to embodiments of the present disclosure, a semiconductor device is provided, comprising: a substrate including a first region, a second region, and a connection region disposed between the first region and the second region; a plurality of first multi-channel active patterns disposed in the first region of the substrate; a plurality of second multi-channel active patterns disposed in the second region of the substrate; a first connection fin pattern disposed in the connection region of the substrate and extending from the first region to the second region in a first direction; and a field insulating film disposed on the substrate and covering the upper surface of the first connection fin pattern, wherein the width of the first connection fin pattern in a second direction decreases and then increases as it moves away from the first region, and the first direction is perpendicular to the second direction.

[0008] According to embodiments of the present disclosure, a semiconductor device is provided, comprising: a substrate including a first region, a second region, and a connection region disposed between the first region and the second region; a plurality of first multi-channel active patterns disposed in the first region of the substrate; a plurality of second multi-channel active patterns disposed in the second region of the substrate; a first connection fin pattern disposed in the connection region of the substrate and extending from the first region to the second region in a first direction; and a field insulating film disposed on the substrate and covering the upper surface of the first connection fin pattern, wherein the first connection fin pattern includes a bridging portion and a first branch portion and a second branch portion protruding from the bridging portion toward the first region, and the first branch portion and the second branch portion are spaced apart from each other in a second direction perpendicular to the first direction.

[0009] According to embodiments of the present disclosure, a semiconductor device is provided, comprising: a substrate including a first region, a second region, and a connection region disposed between the first region and the second region; a plurality of first multi-channel active patterns disposed in the first region of the substrate; a plurality of second multi-channel active patterns disposed in the second region of the substrate; a first connection fin pattern disposed in the connection region of the substrate and extending from the first region to the second region in a first direction; a second connection fin pattern disposed in the connection region of the substrate and having a semi-annular upper surface; a third connection fin pattern disposed between the first connection fin pattern and the second connection fin pattern and extending along the contour of the outer sidewall of the first connection fin pattern in the first direction; a field insulating film disposed on the substrate and covering the upper surfaces of the first connection fin pattern, the upper surfaces of the second connection fin pattern, and the upper surfaces of the third connection fin pattern; a first gate electrode extending in a second direction perpendicular to the first direction on the first multi-channel active pattern; and a second gate electrode extending in the second direction on the second multi-channel active pattern, wherein the width of the first connection fin pattern in the second direction decreases and then increases as it moves away from the first region.

[0010] According to embodiments of this disclosure, a method for manufacturing a mask is provided, the method comprising: generating a virtual target pattern, a segment, and virtual evaluation points between a first target pattern and a second target pattern overlapping in a length direction; inputting first mask data into an OPC model to extract a first contour of the first target pattern and the second target pattern through simulation, the first mask data including the segment; calculating a first virtual EPE (edge ​​placement error) between the first contour and the virtual target pattern at the virtual evaluation points; moving the segment by the displacement after determining the displacement using the first virtual EPE; inputting second mask data including the moved segment into the OPC model to extract a second contour of the first target pattern and the second target pattern through simulation; calculating a second virtual EPE between the second contour and the virtual target pattern at the virtual evaluation points; and determining final mask data when the second virtual EPE is equal to or less than a set reference value, or when the number of simulations performed by the OPC model corresponds to a set reference number.

[0011] According to embodiments of this disclosure, a method for manufacturing a semiconductor device is provided. The method includes manufacturing a mask and performing a photolithography process on a substrate using the mask. The mask manufacturing step includes: generating a virtual target pattern, a fragment, and virtual evaluation points between a first target pattern and a second target pattern that overlap in a length direction; inputting first mask data into an OPC model to extract a first contour of the first and second target patterns through simulation, the first mask data including the fragment; calculating a first virtual EPE between the first contour and the virtual target pattern at the virtual evaluation points; moving the fragment by the displacement after determining the displacement using the first virtual EPE; inputting second mask data including the moved fragment into the OPC model to extract a second contour of the first and second target patterns through simulation; calculating a second virtual EPE between the second contour and the virtual target pattern at the virtual evaluation points; and determining final mask data when the second virtual EPE is equal to or less than a set reference value, or when the number of simulations performed by the OPC model corresponds to a set reference number. Attached Figure Description

[0012] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0013] Figure 1 This is an exemplary layout diagram used to explain the semiconductor device according to embodiments of the present disclosure;

[0014] Figure 2 It is used for explanation Figure 1 A diagram illustrating the first connecting fin-shaped pattern;

[0015] Figures 3 to 7 It is along Figure 1 Examples of screenshots of AA, BB, CC, DD, and EE;

[0016] Figure 8A , Figure 8B , Figure 9A , Figure 9B and Figure 10 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0017] Figure 11 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0018] Figure 12 and Figure 13 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0019] Figures 14 to 16 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0020] Figures 17 to 19 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0021] Figure 20 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0022] Figures 21 to 25 These are diagrams used to explain semiconductor devices according to embodiments of the present disclosure;

[0023] Figures 26 to 31 These are diagrams used to explain a method of manufacturing a mask according to embodiments of the present disclosure; and

[0024] Figure 32A , Figure 32B , Figure 33A , Figure 33B , Figure 34A and Figure 34B This is an intermediate stage diagram used to explain the method of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0025] because Figures 1 to 34B The accompanying drawings are for illustrative purposes, therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0026] Although the accompanying drawings of the semiconductor devices according to embodiments of the present disclosure illustrate fin transistors (fin field-effect transistors, FinFETs) including channel regions with fin-patterned shapes, transistors including nanowires or nanosheets, and multi-bridge channel field-effect transistors (MBCFETs)TM (This is an example, but the disclosure is not limited thereto.) For example, a semiconductor device according to an embodiment of the disclosure may include a tunneling transistor (tunneling FET) or a three-dimensional (3D) transistor. Of course, a semiconductor device according to an embodiment of the disclosure may include a planar transistor. Furthermore, a semiconductor device according to an embodiment of the disclosure may also include a bipolar junction transistor (BJT), a laterally diffused metal-oxide-semiconductor (LDMOS), etc.

[0027] Figure 1 This is an exemplary layout diagram used to explain the semiconductor device according to embodiments of the present disclosure. Figure 2 It is used for explanation Figure 1 The first connecting fin pattern is shown in the diagram. Figures 3 to 7 They are along Figure 1 Examples of screenshots of AA, BB, CC, DD, and EE.

[0028] In the semiconductor device described below, a fin transistor (FinFET) including a channel region with a fin pattern shape can be formed in a first element region DRG1 and a second element region DRG2.

[0029] Reference Figures 1 to 7 The semiconductor device according to embodiments of the present disclosure may include a plurality of first multi-channel active patterns AP1, a plurality of second multi-channel active patterns AP2, a first connecting fin pattern CF1, a second connecting fin pattern CF2, a third connecting fin pattern CF3, a first gate electrode 120, and a second gate electrode 220.

[0030] The substrate 100 may include a first element region DRG1, a second element region DRG2, and a connection region CRG. The connection region CRG may be placed between the first element region DRG1 and the second element region DRG2, and may separate the first element region DRG1 and the second element region DRG2 from each other. The first element region DRG1 and the second element region DRG2 may be spaced apart from each other in a first direction D1, and the connection region CRG is placed between them.

[0031] The first element region DRG1 and the second element region DRG2 can be one of an SRAM region, a logic region, and an I / O region, respectively. In embodiments of this disclosure, the first element region DRG1 and the second element region DRG2 can be the same region. In embodiments of this disclosure, the first element region DRG1 and the second element region DRG2 can be different regions. In embodiments of this disclosure, the first element region DRG1 can be an SRAM region, and the second element region DRG2 can be a logic region, but this disclosure is not limited thereto.

[0032] The connection region CRG can correspond to a buffer region, which is used to ensure the spacing distance to prevent the transistors in the first element region DRG1 and the second element region DRG2 from interfering with each other when they are operating.

[0033] Substrate 100 may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Alternatively, substrate 100 may include (but is not limited to) silicon germanium (SiGe), silicon germanium-on-insulator (SGOI), indium antimonide (InSb), lead telluride (PbTe) compound, indium arsenide (InAs), indium phosphide (InP), gallium arsenide (GaAs), gallium phosphide (GaP), gallium antimonide (GaSb), or indium gallium arsenide (InGaAs). Furthermore, substrate 100 may include one or more semiconductor layers or structures and may include active or operable portions of a semiconductor device. In the following description, substrate 100 will be described as a silicon (Si) substrate.

[0034] Multiple first multi-channel active patterns AP1 can be placed in the first element region DRG1 of the substrate 100. Each of the first multi-channel active patterns AP1 can protrude from the substrate 100.

[0035] The first multi-channel active pattern AP1 can extend relatively long along the first direction D1. For example, the first multi-channel active pattern AP1 can include a long side extending in the first direction D1 and a short side extending in the second direction D2. In the first element region DRG1, a plurality of first multi-channel active patterns AP1 can be arranged in the second direction D2 and can extend parallel to each other in the first direction D1. Here, the first direction D1 can intersect with the second direction D2 and the third direction D3. Furthermore, the second direction D2 can intersect with the third direction D3. The third direction D3 can be the thickness direction of the substrate 100. In embodiments of this disclosure, the first direction can be perpendicular to the second direction.

[0036] A first multi-channel active pattern AP1 can be defined by a first fin trench FT1 extending in a first direction D1. For example, the first multi-channel active pattern AP1 can correspond to a portion of the substrate defined by the first fin trench FT1. The first fin trench FT1 can be placed on either side of the first multi-channel active pattern AP1. For example, each of the first multi-channel active patterns AP1 can be a fin pattern. The sidewalls of the first multi-channel active pattern AP1 can be defined by the first fin trench FT1. Figure 6 In this configuration, the width of the first multi-channel active pattern AP1 in the second direction D2 can decrease as it moves away from the substrate 100 in the third direction D3. For example, the first multi-channel active pattern AP1 can have a sloping sidewall profile.

[0037] Multiple second multi-channel active patterns AP2 can be placed in the second element region DRG2 of the substrate 100. Each second multi-channel active pattern AP2 can protrude from the substrate 100.

[0038] The second multichannel active pattern AP2 can extend relatively long along the first direction D1. The second multichannel active pattern AP2 may include a long side extending in the first direction D1 and a short side extending in the second direction D2. In the second element region DRG2, a plurality of second multichannel active patterns AP2 can be arranged in the second direction D2 and can extend parallel to each other in the first direction D1.

[0039] The second multi-channel active pattern AP2 can be defined by a second fin trench FT2 extending in the first direction D1. For example, the second multi-channel active pattern AP2 can correspond to the portion of the substrate defined by the second fin trench FT2. The second fin trench FT2 can be placed on either side of the second multi-channel active pattern AP2. For example, each of the second multi-channel active patterns AP2 can be a fin pattern. The sidewalls of the second multi-channel active pattern AP2 can be defined by the second fin trench FT2. Figure 7 In this process, the width of the second multi-channel active pattern AP2 in the second direction D2 can decrease as it moves away from the substrate 100 in the third direction D3. For example, the second multi-channel active pattern AP2 can have a sloping sidewall profile.

[0040] The first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 may each be part of the substrate 100, and / or may include an epitaxial layer grown from the substrate 100. The first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 may include, for example, silicon (Si) or germanium (Ge) as elemental semiconductor materials. Furthermore, the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 may include compound semiconductor materials, and may include, for example, group IV-IV compound semiconductor materials or group III-V compound semiconductor materials.

[0041] For example, group IV-IV compound semiconductors may include binary or ternary compounds, including at least two of, for example, carbon (C), silicon (Si), germanium (Ge), and tin (Sn); or compounds obtained by doping these elements with group IV elements. Group IV-IV compound semiconductors may include, for example, silicon germanium (SiGe), silicon carbide (SiC), or silicon germanium carbide (SiGeC), but this disclosure is not limited thereto.

[0042] III-V compound semiconductors can be, for example, at least one of binary, ternary, and quaternary compounds formed by combining at least one of group III elements and at least one of group V elements. Group III elements can include, for example, boron (B), aluminum (Al), gallium (Ga), and indium (In), and group V elements can include, for example, nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb). III-V compound semiconductors can include, for example, gallium phosphide (GaP), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), gallium antimonide (GaSb), indium antimonide (InSb), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), or aluminum indium gallium phosphide (AlInGaP), but this disclosure is not limited thereto.

[0043] In a semiconductor device according to an embodiment of the present disclosure, the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 may be fin patterns, respectively.

[0044] The first connecting fin pattern CF1, the second connecting fin pattern CF2, and the third connecting fin pattern CF3 can be placed in the connecting regions CRG of the substrate 100, respectively. For example, the first connecting fin pattern CF1, the second connecting fin pattern CF2, and the third connecting fin pattern CF3 can be placed between the first element region DRG1 and the second element region DRG2, respectively.

[0045] The first connecting fin pattern CF1, the second connecting fin pattern CF2, and the third connecting fin pattern CF3 may each protrude from the substrate 100 and may be defined by fin cutting trenches FT_C. For example, in the manufacturing process, the first fin trench FT1, the second fin trench FT2, and the fin cutting trench FT_C ​​may be formed at the same level. Here, the term "at the same level" means that they are formed by the same manufacturing process.

[0046] A first connecting fin pattern CF1 may extend from a first element region DRG1 to a second element region DRG2 in a first direction D1. Furthermore, a second connecting fin pattern CF2 may extend from the first element region DRG1 to the second element region DRG2 in the first direction D1. A third connecting fin pattern CF3 protrudes from the first element region DRG1 in the first direction D1 but does not extend to the second element region DRG2. Alternatively, the third connecting fin pattern CF3 may protrude from the second element region DRG2 in the first direction D1 but does not extend to the first element region DRG1.

[0047] The first element region DRG1 and the connection region CRG can be distinguished based on the ends of the first connection fin pattern CF1, the end of the second connection fin pattern CF2, and the end of the third connection fin pattern CF3. For example, the boundary between the first element region DRG1 and the connection region CRG can be defined by the ends of the first connection fin pattern CF1, the second connection fin pattern CF2, and the third connection fin pattern CF3 that contact the first multi-channel active pattern AP1. Similarly, the second element region DRG2 and the connection region CRG can be distinguished based on the ends of the first connection fin pattern CF1, the end of the second connection fin pattern CF2, and the end of the third connection fin pattern CF3. For example, the boundary between the connection region CRG and the second element region DRG2 can be defined by the ends of the first connection fin pattern CF1, the second connection fin pattern CF2, and the third connection fin pattern CF3 that contact the second multi-channel active pattern AP2.

[0048] In a semiconductor device according to an embodiment of the present disclosure, the upper surface CF1_US of the first connection fin pattern may have an "X" shape. For example, the first connection fin pattern CF1 may include a bridging portion CF1_MP, a first branch portion to a fourth branch portion CF1_BP1, CF1_BP2, CF1_BP3 and CF1_BP4.

[0049] The first branch portion CF1_BP1 and the second branch portion CF1_BP2 may protrude from the bridging portion CF1_MP in the first direction D1. For example, the first branch portion CF1_BP1 and the second branch portion CF1_BP2 may protrude from the bridging portion CF1_MP toward the first element region DRG1, and may be spaced apart from each other in the second direction D2.

[0050] The third branch portion CF1_BP3 and the fourth branch portion CF1_BP4 may protrude from the bridging portion CF1_MP in the first direction D1. For example, the third branch portion CF1_BP3 and the fourth branch portion CF1_BP4 may protrude from the bridging portion CF1_MP toward the second element region DRG2, and may be spaced apart from each other in the second direction D2.

[0051] The first connecting fin pattern CF1 may include a first outer sidewall CF1_OSW1 and a second outer sidewall CF1_OSW2 extending in the first direction D1. For example, the first outer sidewall CF1_OSW1 and the second outer sidewall CF1_OSW2 may each be bent and flexed to slightly change the direction of extension, but generally extend in the first direction D1. The first outer sidewall CF1_OSW1 and the second outer sidewall CF1_OSW2 of the first connecting fin pattern may extend continuously from the first element region DRG1 to the second element region DRG2 in the first direction D1, respectively.

[0052] The first outermost wall CF1_OSW1 of the first connecting fin pattern can be the sidewall of the first branch portion CF1_BP1, the bridging portion CF1_MP, and the third branch portion CF1_BP3. The second outermost wall CF1_OSW2 of the first connecting fin pattern can be the sidewall of the second branch portion CF1_BP2, the bridging portion CF1_MP, and the fourth branch portion CF1_BP4.

[0053] The first branch portion CF1_BP1 may include a first sidewall and a second sidewall. The first sidewall of the first branch portion CF1_BP1 may be opposite to the second sidewall of the first branch portion CF1_BP1 in the second direction D2. When the first sidewall of the first branch portion CF1_BP1 faces the second branch portion CF1_BP2, the first outer sidewall CF1_OSW1 of the first connecting fin pattern includes the second sidewall of the first branch portion CF1_BP1. For example, the second branch portion CF1_BP2 is closer to the first sidewall of the first branch portion CF1_BP1 rather than closer to the first outer sidewall CF1_OSW1 of the first connecting fin pattern.

[0054] The width W1 of the first connecting fin pattern CF1 in the second direction D2 can decrease and then increase as it moves away from the first element region DRG1. The width W1 of the first connecting fin pattern CF1 in the second direction D2 can be the width in the second direction D2 between the first outer sidewall CF1_OSW1 and the second outer sidewall CF1_OSW2 of the first connecting fin pattern. For example, the width W1 of the first connecting fin pattern CF1 in the second direction D2 can be the width of the upper surface CF1_US of the first connecting fin pattern in the second direction D2.

[0055] To explain in another way, at a first point located at a first distance from either the first element region DRG1 or the second element region DRG2, the width W1 of the first connecting fin pattern CF1 in the second direction D2 can be a first width W12. For example, the first point can be located at a portion of the first connecting fin pattern CF1 having a first branch portion CF1_BP1 and a second branch portion CF1_BP2 that overlap each other in the second direction D2, or a portion of the first connecting fin pattern CF1 having a third branch portion CF1_BP3 and a fourth branch portion CF1_BP4 that overlap each other in the second direction D2. Furthermore, at a second point located further from either the first element region DRG1 or the second element region DRG2 than the first distance, the width W1 of the first connecting fin pattern CF1 in the second direction D2 can be a second width W11. For example, the second point can be located at the bridging portion CF1_MP of the first connecting fin pattern CF1. The first width W12 of the first connecting fin pattern CF1 at the first point in the second direction D2 is greater than the second width W11 of the first connecting fin pattern CF1 at the second point in the second direction D2.

[0056] In the bridging portion CF1_MP of the first connecting fin pattern CF1, the width W1 of the bridging portion CF1_MP of the first connecting fin pattern in the second direction D2 can decrease and then increase as it moves away from the first branch portion CF1_BP1 and the second branch portion CF1_BP2.

[0057] Multiple second connecting fin patterns CF2 can be placed in the connecting region CRG of the substrate 100. The second connecting fin patterns CF2 can be placed on either side of the first connecting fin pattern CF1. Alternatively, the first connecting fin pattern CF1 can be placed between the second connecting fin patterns CF2. Although Figure 1 The diagram illustrates a first connection fin pattern CF1 as an example, but this disclosure is not limited thereto. For example, a semiconductor device according to embodiments of this disclosure may include a plurality of first connection fin patterns CF1.

[0058] The second connecting fin pattern CF2, which is closest to the first connecting fin pattern CF1, can extend along the outline of the first connecting fin pattern CF1 in the first direction D1. For example, the second connecting fin pattern CF2 can be bent and flexed to slightly change the direction of extension, but in general, it can extend along the outline of the first connecting fin pattern CF1 in the first direction D1. That is, the second connecting fin pattern CF2, which is closest to the first connecting fin pattern CF1, is positioned along the outlines of the first outer sidewall CF1_OSW1 and the second outer sidewall CF1_OSW2 of the first connecting fin pattern.

[0059] The upper surface CF2_US of the second connecting fin pattern may have a line shape extending in the first direction D1. The line shape of the upper surface CF2_US of the second connecting fin pattern may not be a straight line, but may have bent or curved portions. The width W2 of the second connecting fin pattern CF2 in the second direction D2 is smaller than the width W1 of the first connecting fin pattern CF1 in the second direction D2. The second connecting fin pattern CF2 may have a substantially constant width W2 between the first element region DRG1 and the second element region DRG2. At the point where the width W1 of the first connecting fin pattern CF1 in the second direction D2 is minimum, the width W1 of the first connecting fin pattern CF1 in the second direction D2 is greater than the width W2 of the second connecting fin pattern CF2 in the second direction D2.

[0060] A pair of third connecting fin patterns CF3 protrude from either the first element region DRG1 or the second element region DRG2. For example, unlike the first connecting fin pattern CF1 and the second connecting fin pattern CF2, the end of each third connecting fin pattern CF3 may be located only at the boundary between the first element region DRG1 and the connecting region CRG, or only at the boundary between the connecting region CRG and the second element region DRG2. For example, the pair of third connecting fin patterns CF3 may include a third inner connecting fin pattern and a third outer connecting fin pattern. The third inner connecting fin pattern and the third outer connecting fin pattern may each protrude from the first element region DRG1 in a first direction D1. The third outer connecting fin pattern is positioned along the outer sidewall of the third inner connecting fin pattern and spaced apart from it.

[0061] Between the first connecting fin pattern CF1 and the third connecting fin pattern CF3, the second connecting fin pattern CF2 is placed along the outline of the outer wall of the first connecting fin pattern CF1. For example, a single second connecting fin pattern CF2 is placed between the first connecting fin pattern CF1 and the third connecting fin pattern CF3 that are closest to each other. Furthermore, when the first pair of third connecting fin patterns CF3 protrudes from the first element region DRG1, the second pair of third connecting fin patterns CF3 protrudes from the second element region DRG2. For example, the ends of the first pair of third connecting fin patterns CF3 may be located at the boundary between the first element region DRG1 and the connecting region CRG, and the ends of the second pair of third connecting fin patterns CF3 may be located at the boundary between the connecting region CRG and the second element region DRG2. The first pair of third connecting fin patterns CF3 may be closest to the second pair of third connecting fin patterns CF3.

[0062] The upper surface CF3_US of the third connecting fin pattern can have a semi-circular shape. Contrary to what is shown, the upper surface CF3_US of the third connecting fin pattern can have a semi-circular shape.

[0063] A single first connecting fin pattern CF1 can be directly connected to two or fewer first multichannel active patterns AP1. One or both of the first branch portion CF1_BP1 and the second branch portion CF1_BP2 can be directly connected to the first multichannel active pattern AP1. Furthermore, a single first connecting fin pattern CF1 can be directly connected to two or fewer second multichannel active patterns AP2. One or both of the third branch portion CF1_BP3 and the fourth branch portion CF1_BP4 can be directly connected to the second multichannel active pattern AP2.

[0064] Unlike the diagram shown, a single first connecting fin pattern CF1 may not be directly connected to the first multichannel active pattern AP1 and the second multichannel active pattern AP2. That is, the first branch portion CF1_BP1 and the second branch portion CF1_BP2 are not directly connected to the first multichannel active pattern AP1, respectively. Similarly, the third branch portion CF1_BP3 and the fourth branch portion CF1_BP4 are not directly connected to the second multichannel active pattern AP2, respectively.

[0065] In a semiconductor device according to an embodiment of the present disclosure, a first connecting fin pattern CF1 can be directly connected to two first multi-channel active patterns AP1 and two second multi-channel active patterns AP2. For example, a first branch portion CF1_BP1 and a second branch portion CF1_BP2 can each be directly connected to the first multi-channel active pattern AP1. A third branch portion CF1_BP3 and a fourth branch portion CF1_BP4 can each be directly connected to the second multi-channel active pattern AP2.

[0066] A single second connecting fin pattern CF2 can be directly connected to one or fewer first multichannel active patterns AP1. Furthermore, a single second connecting fin pattern CF2 can be directly connected to one or fewer second multichannel active patterns AP2.

[0067] In a semiconductor device according to an embodiment of the present disclosure, at least one second connection fin pattern CF2 can be directly connected to a single first multichannel active pattern AP1 and a single second multichannel active pattern AP2.

[0068] A single third-connection fin pattern CF3 can be directly connected to two or fewer first multichannel active patterns AP1. Alternatively, a single third-connection fin pattern CF3 can be directly connected to two or fewer second multichannel active patterns AP2.

[0069] In a semiconductor device according to an embodiment of the present disclosure, at least one third connection fin pattern CF3 can be directly connected to two first multi-channel active patterns AP1. At least one third connection fin pattern CF3 can be directly connected to two second multi-channel active patterns AP2. A single third connection fin pattern CF3 is directly connected to either a first multi-channel active pattern AP1 or a second multi-channel active pattern AP2.

[0070] exist Figure 1 In the diagram, at the boundary between the first element region DRG1 and the connection region CRG, the widths of the ends of the first connection fin pattern CF1, the second connection fin pattern CF2, and the third connection fin pattern CF3 in the second direction D2 are shown to be greater than the width of the first multi-channel active pattern AP1 in the second direction D2. Furthermore, at the boundary between the second element region DRG2 and the connection region CRG, the widths of the ends of the first connection fin pattern CF1, the second connection fin pattern CF2, and the third connection fin pattern CF3 in the second direction D2 are shown to be greater than the width of the second multi-channel active pattern AP2 in the second direction D2.

[0071] In this manufacturing process, by etching portions of the pre-patterned active pattern having the same shape as the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2, a first connecting fin pattern CF1, a second connecting fin pattern CF2, and a third connecting fin pattern CF3 can be formed. Figure 4 and Figure 5 In the above, the upper surface of the first multi-channel active pattern AP1 and the upper surface of the second multi-channel active pattern AP2 are higher than the upper surface CF1_US of the first connecting fin pattern.

[0072] The widths of the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 in the second direction D2 decrease as they move further away from the substrate 100 in the third direction D3. Therefore, the widths of the upper surfaces CF1_US of the first connecting fin pattern, CF2_US of the second connecting fin pattern, and CF3_US of the third connecting fin pattern are each greater than the widths of the upper surfaces of the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2. The first connecting fin pattern CF1 has two upper surfaces CF1_US adjacent to the first element region DRG1 (one for the first branch portion CF1_BP1 and one for the second branch portion CF1_BP2) and two upper surfaces CF1_US adjacent to the second element region DRG2 (one for the third branch portion CF1_BP3 and one for the fourth branch portion CF1_BP4). On the other hand, when the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 are measured at the same height as the upper surfaces of the first to third connecting fin patterns CF1, CF2 and CF3, the width of the upper surface CF1_US of the first connecting fin pattern, the width of the upper surface CF2_US of the second connecting fin pattern and the width of the upper surface CF3_US of the third connecting fin pattern can be the same as the width of the first multi-channel active pattern AP1 and the width of the second multi-channel active pattern AP2.

[0073] In embodiments of this disclosure, the boundary portion between the second connecting fin pattern CF2 and the first multi-channel active pattern AP1, and the boundary portion between the third connecting fin pattern CF3 and the first multi-channel active pattern AP1, can be similar to... Figure 4 Furthermore, the boundary portions between the second connecting fin pattern CF2 and the second multi-channel active pattern AP2, and the boundary portions between the third connecting fin pattern CF3 and the second multi-channel active pattern AP2, can be similar to... Figure 5 .

[0074] The point where a step appears between the first multi-channel active pattern AP1 and the connecting fin patterns CF1, CF2, and CF3 can be the boundary between the first element region DRG1 and the connecting region CRG. Similarly, the point where a step appears between the second multi-channel active pattern AP2 and the connecting fin patterns CF1, CF2, and CF3 can be the boundary between the second element region DRG2 and the connecting region CRG. In the manufacturing process, portions of the pre-patterned active patterns having the same shape as the first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 can be etched to form a step between the first multi-channel active pattern AP1 and one of the connecting fin patterns CF1, CF2, and CF3 as the boundary between the first element region DRG1 and the connecting region CRG, and a step between the second multi-channel active pattern AP2 and one of the connecting fin patterns CF1, CF2, and CF3 as the boundary between the second element region DRG2 and the connecting region CRG.

[0075] The field insulating film 105 can be placed on the substrate 100 and can be formed above the first element region DRG1, the second element region DRG2 and the connection region CRG.

[0076] The field insulating film 105 may fill a portion of the first fin trench FT1 and the second fin trench FT2, and may be formed on a portion of the sidewall of the first multi-channel active pattern AP1 and a portion of the sidewall of the second multi-channel active pattern AP2. The first multi-channel active pattern AP1 and the second multi-channel active pattern AP2 each protrude upward from the upper surface of the field insulating film 105.

[0077] The field insulating film 105 can be placed on the first connecting fin pattern CF1, the second connecting fin pattern CF2, and the third connecting fin pattern CF3, and can cover the upper surfaces CF1_US, CF2_US, and CF3_US of the first connecting fin pattern, the second connecting fin pattern, and the third connecting fin pattern. Furthermore, the field insulating film 105 can cover the sidewalls of the first connecting fin pattern CF1, the second connecting fin pattern CF2, and the third connecting fin pattern CF3. The first connecting fin pattern CF1, the second connecting fin pattern CF2, and the third connecting fin pattern CF3 do not protrude upwards from the upper surface of each field insulating film 105.

[0078] The field insulating film 105 may include, for example, an oxide film, a nitride film, a oxynitride film, or a combination thereof.

[0079] The first gate electrode 120 may be placed on the first element region DRG1 of the substrate 100 and may be placed on the field insulating film 105. The first gate electrode 120 may intersect with at least one first multi-channel active pattern AP1 and may extend relatively long in the second direction D2.

[0080] The second gate electrode 220 may be placed on the second element region DRG2 of the substrate 100 and may be placed on the field insulating film 105. The second gate electrode 220 may intersect with at least one second multi-channel active pattern AP2 and may extend relatively long in the second direction D2.

[0081] The first edge gate electrode 160 may be placed along the boundary between the first element region DRG1 and the connection region CRG, and may surround the end of the first multi-channel active pattern AP1. The first edge gate electrode 160 may intersect with a plurality of first multi-channel active patterns AP1. The first edge gate electrode 160 may extend relatively long in the second direction D2, and may be spaced apart from the first gate electrode 120 in the first direction D1.

[0082] The second edge gate electrode 260 may be placed along the boundary between the second element region DRG2 and the connection region CRG, and may surround the end of the second multi-channel active pattern AP2. The second edge gate electrode 260 may intersect with a plurality of second multi-channel active patterns AP2. The second edge gate electrode 260 may extend relatively long in the second direction D2, and may be spaced apart from the second gate electrode 220 in the first direction D1.

[0083] Unlike those shown, the semiconductor device according to embodiments of this disclosure may not include a first edge gate electrode 160 and a second edge gate electrode 260. While a single first edge gate electrode 160 is shown positioned along the boundary between the first element region DRG1 and the connection region CRG, this disclosure is not limited thereto. Similarly, while a single second edge gate electrode 260 is shown positioned along the boundary between the second element region DRG2 and the connection region CRG, this disclosure is not limited thereto.

[0084] exist Figure 1 The shapes in which the first gate electrode 120 and the second gate electrode 220 are placed are merely examples, and this disclosure is not limited thereto.

[0085] The first gate electrode 120, the second gate electrode 220, the first edge gate electrode 160, and the second edge gate electrode 260 may each comprise a conductive material, and may include, but are not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium tantalum nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), and titanium aluminum carbide (TiAlCN). TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0086] In addition to the conductive materials mentioned above, each of the first gate electrode 120, the second gate electrode 220, the first edge gate electrode 160, and the second edge gate electrode 260 may include conductive metal oxides, conductive metal oxynitrides, etc.

[0087] The first gate spacer 140 can be placed on the sidewall of the first gate electrode 120. The second gate spacer 240 can be placed on the sidewall of the second gate electrode 220. The first edge gate spacer 170 can be placed on the sidewall of the first edge gate electrode 160. The second edge gate spacer 270 can be placed on the sidewall of the second edge gate electrode 260. The first gate spacer 140, the second gate spacer 240, the first edge gate spacer 170, and the second edge gate spacer 270 can each extend in the second direction D2.

[0088] The first gate spacer 140, the second gate spacer 240, the first edge gate spacer 170, and the second edge gate spacer 270 may have a single-layer or multi-layer structure and may include at least one of, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0089] A first gate insulating film 130 may extend along the sidewalls and bottom surface of the first gate electrode 120. A second gate insulating film 230 may extend along the sidewalls and bottom surface of the second gate electrode 220. A first edge gate insulating film 165 may extend along the sidewalls and bottom surface of the first edge gate electrode 160. A second edge gate insulating film 265 may extend along the sidewalls and bottom surface of the second edge gate electrode 260. Figure 6 and Figure 7 In this process, the first gate insulating film 130 and the second gate insulating film 230 can extend along the upper surface of the field insulating film 105.

[0090] Taking the first gate insulating film 130 as an example, the first gate insulating film 130 may be formed along the outline of the first multi-channel active pattern AP1 protruding upward from the field insulating film 105 and along the upper surface of the field insulating film 105. In embodiments of this disclosure, the first gate insulating film 130 may include an interface film along the outline of the first multi-channel active pattern AP1 protruding upward from the field insulating film 105. For example, the interface film may include, but is not limited to, silicon oxide (SiO2). That is, the material of the interface film may be changed according to the material of the first multi-channel active pattern AP1.

[0091] The first gate insulating film 130, the second gate insulating film 230, the first edge gate insulating film 165, and the second edge gate insulating film 265 may each comprise, for example, silicon oxide (SiO2), silicon oxynitride (SiON), or a high dielectric constant material with a dielectric constant higher than that of silicon oxide (SiO2). For example, high dielectric constant materials can include, for example, boron nitride (BN), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium zirconium oxide (HfZrO4), hafnium tantalum oxide (Hf2Ta2O9), hafnium aluminum oxide (HfAlO3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTi2O6), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium oxide (Pb(Sc,Ta)O3), and lead zinc niobate (Pb(Zn) 1 / 3 Nb 2 / 3 One or more of the following can be selected from O3.

[0092] The semiconductor device according to embodiments of the present disclosure may include an NC (negative capacitance) FET using a negative capacitor. For example, the first gate insulating film 130, the second gate insulating film 230, the first edge gate insulating film 165, and the second edge gate insulating film 265 may each include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0093] Ferroelectric films can have negative capacitance, while paraelectric films can have positive capacitance. For example, when two or more capacitors are connected in series and each capacitor has a positive capacitance, the overall capacitance decreases from the capacitance of each of the individual capacitors. For example, the sum of the capacitances of two or more capacitors is less than the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the overall capacitance can be positive and can be greater than the absolute value of each of the individual capacitors.

[0094] When a ferroelectric film with negative capacitance and a paraelectric film with positive capacitance are connected in series, the overall capacitance of the two films connected in series can be increased. Utilizing this increased overall capacitance, a transistor including the ferroelectric film can exhibit a subthreshold swing (SS) of less than 60 mV / decade at room temperature. For example, in a non-capacitive FET (NC-FET), the insulating ferroelectric layer acts as a negative capacitor, allowing the channel surface potential to be amplified to be greater than the gate voltage; therefore, the device can operate at an SS of less than 60 mV / decade at room temperature.

[0095] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can include at least one of, for example, hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO4), barium strontium titanium oxide (BaSrTi2O6), barium titanium oxide (BaTiO3), and lead zirconium titanium oxide (Pb(Ti,Zr)O3). In each of the above ferroelectric materials, the ratio between the metals can vary, and the composition can be non-stoichiometric. For example, hafnium zirconium oxide can be a material obtained by doping hafnium oxide (HfO2) with zirconium (Zr). For example, hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O). In other words, hafnium zirconium oxide can be made from Hf with various combinations of values ​​of x, y, and z. x Zr y O z It is represented by HfZrO4, rather than by HfZrO4.

[0096] The ferroelectric material film may also include dopants. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film can vary depending on the type of ferroelectric material included in the film.

[0097] When the ferroelectric material film includes hafnium oxide (HfO2), the dopant included in the ferroelectric material film may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). However, this disclosure is not limited thereto. For example, other dopant such as strontium (Sr), lanthanum (La), titanium (Ti), and tantalum (Ta) may also be used to dope the ferroelectric material layer including hafnium oxide (HfO2).

[0098] When the dopant is aluminum (Al), the ferroelectric film may include 3 at% (atomic %) to 8 at% aluminum (Al). Here, the dopant ratio may be the ratio of aluminum (Al) to the sum of hafnium (Hf) and aluminum (Al).

[0099] When the dopant is silicon (Si), the ferroelectric film may comprise approximately 2 at% to approximately 10 at% silicon (Si). When the dopant is yttrium (Y), the ferroelectric film may comprise approximately 2 at% to approximately 10 at% yttrium (Y). When the dopant is gadolinium (Gd), the ferroelectric film may comprise approximately 1 at% to approximately 7 at% gadolinium (Gd). When the dopant is zirconium (Zr), the ferroelectric film may comprise approximately 50 at% to approximately 80 at% zirconium (Zr).

[0100] The paraelectric material film may possess paraelectric properties. The paraelectric material film may include, for example, silicon oxide (SiO2) and / or a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, but is not limited to, at least one of, for example, hafnium oxide (HfO2), barium strontium titanium oxide (BaSrTi2O6), zirconium oxide (ZrO2), and aluminum oxide (Al2O3).

[0101] Ferroelectric and paraelectric films can contain the same material. Ferroelectric films exhibit ferroelectric properties, but paraelectric films may not. For example, when both ferroelectric and paraelectric films contain hafnium oxide (HfO2), the crystal structure of the hafnium oxide (HfO2) in the ferroelectric film differs from that in the paraelectric film.

[0102] Ferroelectric material films can have a thickness that exhibits ferroelectric properties. The thickness of a ferroelectric material film can be, but is not limited to, for example, in the range of about 0.5 nm to about 10 nm. Since the critical thickness for exhibiting ferroelectric properties can vary for each ferroelectric material, the thickness of a ferroelectric material film can vary depending on the type of ferroelectric material.

[0103] In embodiments of this disclosure, the first gate insulating film 130, the second gate insulating film 230, the first edge gate insulating film 165, and the second edge gate insulating film 265 may each comprise a single ferroelectric material film, but this disclosure is not limited thereto. For example, the first gate insulating film 130, the second gate insulating film 230, the first edge gate insulating film 165, and the second edge gate insulating film 265 may each comprise a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film 130, the second gate insulating film 230, the first edge gate insulating film 165, and the second edge gate insulating film 265 may each have a stacked film structure of alternatingly stacked plurality of ferroelectric material films and plurality of paraelectric material films.

[0104] The first gate capping pattern 145, the second gate capping pattern 245, the first edge gate capping pattern 175, and the second edge gate capping pattern 275 can be respectively placed on the upper surfaces of the first gate electrode 120, the second gate electrode 220, the first edge gate electrode 160, and the second edge gate electrode 260. Taking the first gate capping pattern 145 as an example, the first gate capping pattern 145 can be placed on the upper surface of the first gate spacer 140. The first gate capping pattern 145, the second gate capping pattern 245, the first edge gate capping pattern 175, and the second edge gate capping pattern 275 can include at least one of, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), and combinations thereof.

[0105] Unlike what is shown, taking the first gate cap pattern 145 as an example, the first gate cap pattern 145 can be placed between the first gate spacers 140. In this case, the upper surface of the first gate cap pattern 145 can be placed on the same plane as the upper surface of the first gate spacers 140.

[0106] Unlike what is shown, the first gate cap pattern 145, the second gate cap pattern 245, the first edge gate cap pattern 175, and the second edge gate cap pattern 275 may not be placed on the first gate electrode 120, the second gate electrode 220, the first edge gate electrode 160, and the second edge gate electrode 260, respectively.

[0107] The first source / drain pattern 150 can be formed on the first multi-channel active pattern AP1 and can be placed on either side of the first gate electrode 120. The first source / drain pattern 150 may include p-type impurities or n-type impurities.

[0108] The second source / drain pattern 250 can be formed on the second multi-channel active pattern AP2 and can be placed on either side of the second gate electrode 220. The second source / drain pattern 250 may include p-type impurities or n-type impurities.

[0109] The first source / drain pattern 150 and the second source / drain pattern 250 may each include, but are not limited to, epitaxial patterns formed by epitaxial processes. For example, in embodiments of this disclosure, the first source / drain pattern 150 may be formed by performing an epitaxial growth process on both sides of the first gate electrode 120 in the recessed region of the first multi-channel active pattern AP1. The second source / drain pattern 250 may be formed by performing an epitaxial growth process on both sides of the second gate electrode 220 in the recessed region of the second multi-channel active pattern AP2. The first source / drain pattern 150 may be included in the source / drain of a transistor using the first multi-channel active pattern AP1 as the channel region, and the second source / drain pattern 250 may be included in the source / drain of a transistor using the second multi-channel active pattern AP2 as the channel region.

[0110] A lower interlayer insulating film 191 is formed on the field insulating film 105 and may cover the first source / drain pattern 150 and the second source / drain pattern 250. The lower interlayer insulating film 191 may be formed around the first gate electrode 120, the second gate electrode 220, the first edge gate electrode 160, and the second edge gate electrode 260. In embodiments of this disclosure, the upper surface of the lower interlayer insulating film 191 may be coplanar with the upper surfaces of the first gate capping pattern 145, the second gate capping pattern 245, the first edge gate capping pattern 175, and the second edge gate capping pattern 275, but this disclosure is not limited thereto.

[0111] The upper interlayer insulating film 192 can be placed on the lower interlayer insulating film 191. In embodiments of this disclosure, wiring patterns connected to the gate electrodes 120 and 220 and the source / drain patterns 150 and 250 can be placed inside the upper interlayer insulating film 192.

[0112] The upper interlayer insulating film 192 and the lower interlayer insulating film 191 may each include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and a low dielectric constant material. Low dielectric constant materials may include, but are not limited to, tetraethyl orthosilicate (FTEOS), silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), tri(trimethylsilyl)borate (TMSB), diacetoxydi-tert-butylsiloxane (DADBS), tri(trimethylsilyl)phosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen silazane (TOSZ), fluorosilicate glass (FSG), polyimide nanofoams such as polypropylene oxide, carbon-doped silica (CDO), organosilicon glass (OSG), SiLK, amorphous fluorinated carbon (a-CF), silica aerogel, silica dry gel, mesoporous silica, or combinations thereof.

[0113] Figures 8A to 10 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figures 1 to 7 The differences described.

[0114] For reference only. Figure 8A and Figure 8B It is along Figure 1 An example image captured by BB. Figure 9A and Figure 9B It is along Figure 1 An example image captured by CC. Figure 10 It is along Figure 1 An exemplary diagram of an EE cutoff. Along Figure 1 The cross-sectional view of DD can have the same Figure 10 The shapes are basically the same.

[0115] In the semiconductor device described below, transistors including nanosheets can be formed in a first element region DRG1 and a second element region DRG2.

[0116] Reference Figures 8A to 10 In a semiconductor device according to an embodiment of the present disclosure, a first multi-channel active pattern AP1 may include a first lower fin pattern BP1 and a first wafer pattern NS1. A second multi-channel active pattern AP2 may include a second lower fin pattern BP2 and a second wafer pattern NS2.

[0117] The first lower fin pattern BP1 may extend along a first direction D1. A first pattern NS1 may be placed on the first lower fin pattern BP1 and spaced apart from it. The first lower fin pattern BP1 may be formed by etching a portion of the substrate 100 and / or may include an epitaxial layer grown from the substrate 100. For example, the first lower fin pattern BP1 may be formed by partially removing the upper portion of the substrate 100 and thus may be integrally formed with the substrate 100, but this disclosure is not limited thereto.

[0118] The second lower fin pattern BP2 may extend along the first direction D1. A second pattern NS2 may be placed on the second lower fin pattern BP2 and spaced apart from it. The second lower fin pattern BP2 may be formed by etching a portion of the substrate 100, and / or may include an epitaxial layer grown from the substrate 100. For example, the second lower fin pattern BP2 may be formed by partially removing the upper portion of the substrate 100, and thus may be integrally formed with the substrate 100, but this disclosure is not limited thereto.

[0119] The first pattern NS1 and the second pattern NS2 may each include patterns of multiple sheets stacked on a third direction D3. Although the number of each of the first pattern NS1 and the second pattern NS2 is shown as three, this is only for ease of explanation, and their number is not limited thereto. For example, the number of the first pattern NS1 included in the first multichannel active pattern AP1 may be two or more.

[0120] The first pattern NS1 can be connected to the first source / drain pattern 150. The second pattern NS2 can be connected to the second source / drain pattern 250. The first pattern NS1 and the second pattern NS2 can be channel patterns used as channel regions for transistors. For example, the first pattern NS1 and the second pattern NS2 can be nanosheets or nanowires.

[0121] The first lower fin pattern BP1 and the second lower fin pattern BP2 each comprise at least one of elemental semiconductor materials, group IV-IV compound semiconductor materials, and group III-V compound semiconductor materials. The first pattern NS1 and the second pattern NS2 may each comprise one of elemental semiconductor materials, group IV-IV compound semiconductor materials, and group III-V compound semiconductor materials.

[0122] The second gate insulating film 230 may extend along the upper surface of the second lower fin pattern BP2 and the upper surface of the field insulating film 105. The second gate insulating film 230 may surround the second pattern NS2. The second gate insulating film 230 is shown as a single layer, but this is only for ease of description and the present disclosure is not limited thereto. The second gate insulating film 230 may include multiple layers. For example, in addition to the high dielectric constant insulating layer as described above, the second gate insulating film 230 may also include an interface film disposed between the second pattern NS2 and the second gate electrode 220. The first gate insulating film 130 may also be formed in a shape substantially the same as that of the second gate insulating film 230.

[0123] The second gate electrode 220 is placed on the second lower fin pattern BP2, and the second gate insulating film 230 is placed between the second gate electrode 220 and the second lower fin pattern BP2. The second gate electrode 220 intersects with the second lower fin pattern BP2. The second gate electrode 220 may surround the second pattern NS2, and the second gate insulating film 230 may be placed between the second gate electrode 220 and the second pattern NS2. The second gate electrode 220 may also be placed between the second lower fin pattern BP2 and the second pattern NS2, as well as between adjacent second patterns NS2. The first gate electrode 120 may also be formed with a shape substantially the same as that of the second gate electrode 220.

[0124] exist Figure 8A and Figure 9A In this configuration, the first gate spacer 140 is not placed between the first lower fin pattern BP1 and the first pattern NS1, nor between adjacent first patterns NS1. The second gate spacer 240 is not placed between the second lower fin pattern BP2 and the second pattern NS2, nor between adjacent second patterns NS2.

[0125] exist Figure 8B and Figure 9B In this configuration, a first gate spacer 140 is placed between a first lower fin pattern BP1 and a first pattern NS1, and between adjacent first patterns NS1. A second gate spacer 240 is placed between a second lower fin pattern BP2 and a second pattern NS2, and between adjacent second patterns NS2.

[0126] Figure 11 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figure 1 and Figures 8A to 10 The differences described.

[0127] For reference only. Figure 1 Description and reference of the second component region DRG2 Figures 9A to 10 The descriptions are basically the same.

[0128] In the semiconductor device described below, a fin-type transistor (FinFET) including a channel region with a fin pattern shape can be formed in a first element region DRG1, and a transistor including a nanosheet can be formed in a second element region DRG2.

[0129] Reference Figure 11 In a semiconductor device according to an embodiment of the present disclosure, the first multi-channel active pattern AP1 may include a first lower fin pattern BP1 and a first upper fin pattern UP1.

[0130] The first lower fin pattern BP1 may extend along the first direction D1. The first upper fin pattern UP1 may be directly connected to the first lower fin pattern BP1. The first upper fin pattern UP1 may include a first semiconductor molded pattern UP_A and a second semiconductor molded pattern UP_B alternately stacked on the first lower fin pattern BP1.

[0131] The first semiconductor molding pattern UP_A may include and Figures 9A to 10 The second pattern NS2 is made of the same material. If the second semiconductor molding pattern UP_B is removed during the manufacturing process, the first semiconductor molding pattern UP_A can be transformed into... Figure 8A and Figure 8B The first pattern is NS1.

[0132] The first semiconductor molding pattern UP_A can be a silicon (Si) pattern, and the second semiconductor molding pattern UP_B can be a silicon-germanium (SiGe) pattern, but this disclosure is not limited thereto.

[0133] The first upper fin pattern UP1 can be connected to the first source / drain pattern 150 and can be used as the channel region of the transistor.

[0134] Figure 12 and Figure 13 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figures 1 to 7 The differences described.

[0135] For reference only. Figure 12 This is an exemplary layout diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 13 It is used for explanation Figure 12 The first connecting fin pattern is shown in the diagram.

[0136] exist Figure 12 and Figure 13 In a semiconductor device according to an embodiment of the present disclosure, the bridging portion CF1_MP of the first connecting fin pattern CF1 can extend to the second element region DRG2.

[0137] For example, the upper surface of the first connecting fin pattern ( Figure 3 The CF1_US can have a “Y” shape.

[0138] The first outermost wall CF1_OSW1 of the first connecting fin pattern can be the sidewall of the first branch portion CF1_BP1 and the bridging portion CF1_MP. The second outermost wall CF1_OSW2 of the first connecting fin pattern can be the sidewall of the second branch portion CF1_BP2 and the bridging portion CF1_MP.

[0139] The width W1 of the bridging portion CF1_MP of the first connecting fin pattern in the second direction D2 can decrease and then increase as it moves away from the first branch portion CF1_BP1 and the second branch portion CF1_BP2.

[0140] In a semiconductor device according to an embodiment of the present disclosure, the bridging portion CF1_MP can be directly connected to two or fewer second multi-channel active patterns AP2. The first branch portion CF1_BP1 and the second branch portion CF1_BP2 can each be directly connected to two or fewer first multi-channel active patterns AP1.

[0141] Figures 14 to 16 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figures 1 to 7 The differences described.

[0142] For reference only. Figure 14 This is an exemplary layout diagram used to explain the semiconductor device according to embodiments of the present disclosure. Figure 15 It is used for explanation Figure 14 The first connecting fin pattern is shown in the diagram. Figure 16 It is along Figure 14 An example section cut by AA.

[0143] Reference Figures 14 to 16 In a semiconductor device according to an embodiment of the present disclosure, a bridging portion CF1_MP of a first connection fin pattern CF1 extends from a first element region DRG1 to a second element region DRG2. The first connection fin pattern CF1 does not include branch portions ( Figure 2 (CF1_BP1, CF1_BP2, CF1_BP3, and CF1_BP4). For example, the entire first connecting fin pattern CF1 is the bridging portion CF1_MP.

[0144] The first outermost wall CF1_OSW1 of the first connecting fin pattern can be the sidewall of the bridging portion CF1_MP. The second outermost wall CF1_OSW2 of the first connecting fin pattern can be the sidewall of the bridging portion CF1_MP.

[0145] The width W1 of the bridging portion CF1_MP of the first connecting fin pattern in the second direction D2 can decrease and then increase as it moves away from the first element region DRG1. The width W1 of the first connecting fin pattern CF1 in the second direction D2 can be the width in the second direction D2 between the first outer wall CF1_OSW1 and the second outer wall CF1_OSW2 of the first connecting fin pattern.

[0146] In a semiconductor device according to an embodiment of the present disclosure, the bridging portion CF1_MP can be directly connected to two or fewer first multi-channel active patterns AP1. Furthermore, the bridging portion CF1_MP can be directly connected to two or fewer second multi-channel active patterns AP2.

[0147] exist Figure 16 In the second direction D2, the width of the upper surface CF1_US of the first connecting fin pattern is greater than the width of the upper surface CF2_US of the second connecting fin pattern and the width of the upper surface CF3_US of the third connecting fin pattern. Second connecting fin patterns CF2, each having a width narrower than the width of the first connecting fin pattern CF1, are placed on either side of the first connecting fin pattern CF1. For example, one first connecting fin pattern CF1 is inserted between two second connecting fin patterns CF2.

[0148] Figures 17 to 19 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figures 1 to 7 The differences described.

[0149] For reference only. Figure 17 This is an exemplary layout diagram used to illustrate a semiconductor device according to an embodiment of the present disclosure. Figure 18 and Figure 19 They are along Figure 17 An example image captured by DD.

[0150] Reference Figures 17 to 19 In a semiconductor device according to an embodiment of the present disclosure, a first connection fin pattern CF1 may be directly connected to a single first multi-channel active pattern AP1 and two second multi-channel active patterns AP2. For example, a first branch portion CF1_BP1 of the first connection fin pattern CF1 may be directly connected to the single first multi-channel active pattern AP1, while a second branch portion CF1_BP2 may not be connected to any of the first multi-channel active patterns AP1.

[0151] The number of first multi-channel active patterns AP1 connected to the first connecting fin pattern CF1 is different from the number of second multi-channel active patterns AP2 connected to the first connecting fin pattern CF1.

[0152] exist Figure 18 In this process, a deep trench DT, deeper than the first fin trench FT1, can be formed between adjacent first multi-channel active patterns AP1 in the second direction D2. The deep trench DT can be formed during the process of removing unnecessary first multi-channel active patterns AP1.

[0153] exist Figure 19 In this process, at least one dummy fin pattern DPF can be placed between adjacent first multi-channel active patterns AP1 in the second direction D2. The dummy fin pattern DPF can extend relatively long in the first direction D1. The field insulating film 105 covers the upper surface DPF_US of the dummy fin pattern. The dummy fin pattern DPF does not protrude upward from the upper surface of the field insulating film 105. In the process of removing unnecessary first multi-channel active patterns AP1, when the etching depth is not deep enough, the lower portion of the first multi-channel active pattern AP1 may not be etched but can be retained as the dummy fin pattern DPF.

[0154] In embodiments of this disclosure, the cross-sectional view of the portion of the first connecting fin pattern CF1 that is not connected to the first multi-channel active pattern AP1, cut along the first direction D1 (e.g., cut through the end portion of the second branch portion CF1_BP2), can be similar to... Figure 22 or Figure 24 .exist Figure 22 or Figure 24 In the first connecting fin pattern CF1, the portion of the first connecting fin pattern CF1 that is not connected to the first multi-channel active pattern AP1 is cut off at the end portion of the first branch portion CF1_BP1 in the first direction D1.

[0155] At least one second connecting fin pattern CF2 may be directly connected to one of the first multichannel active pattern AP1 and the second multichannel active pattern AP2, rather than being connected to both. At least one third connecting fin pattern CF3 may be directly connected to a single first multichannel active pattern AP1.

[0156] Unlike what is shown, at least one third connecting fin pattern CF3 can be directly connected to a single second multichannel active pattern AP2.

[0157] Figure 20 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figures 17 to 19 The differences described.

[0158] Reference Figure 20In a semiconductor device according to an embodiment of the present disclosure, a first connection fin pattern CF1 can be directly connected to a single first multi-channel active pattern AP1 and a single second multi-channel active pattern AP2. For example, a first branch portion CF1_BP1 of the first connection fin pattern CF1 can be directly connected to the single first multi-channel active pattern AP1, while a second branch portion CF1_BP2 may not be connected to any of the first multi-channel active patterns AP1. A third branch portion CF1_BP3 of the first connection fin pattern CF1 can be directly connected to the single second multi-channel active pattern AP2, while a fourth branch portion CF1_BP4 may not be connected to any of the second multi-channel active patterns AP2.

[0159] Figures 21 to 25 This is a diagram used to explain a semiconductor device according to embodiments of the present disclosure. For ease of explanation, the main description will be based on references to... Figures 1 to 7 The differences described.

[0160] For reference only. Figure 21 This is an exemplary layout diagram used to illustrate a semiconductor device according to an embodiment of the present disclosure. Figure 22 and Figure 24 They are along Figure 21 An example image captured by BB. Figure 23 and Figure 25 They are along Figure 21 An example image captured by DD.

[0161] Reference Figures 21 to 25 In the semiconductor device according to embodiments of the present disclosure, the first connection fin pattern CF1 is directly connected to two second multi-channel active patterns AP2, but it may not be directly connected to the first multi-channel active pattern AP1. For example, the first branch portion CF1_BP1 and the second branch portion CF1_BP2 of the first connection fin pattern CF1 may not be connected to either of the first multi-channel active patterns AP1. The third branch portion CF1_BP3 and the fourth branch portion CF1_BP4 of the first connection fin pattern CF1 may each be directly connected to one of the second multi-channel active patterns AP2.

[0162] exist Figure 22 and Figure 23 In this process, a deep trench DT, which is deeper than the first fin trench FT1, can be formed at the boundary between the first element region DRG1 and the connection region CRG.

[0163] exist Figure 24 and Figure 25In this process, at the boundary between the first element region DRG1 and the connection region CRG, the first connecting fin pattern CF1 and the dummy fin pattern DPF can form a boundary. Although the height of the upper surface CF1_US of the first connecting fin pattern is shown to be different from the height of the upper surface DPF_US of the dummy fin pattern, this disclosure is not limited thereto. For example, in the manufacturing process according to an embodiment of this disclosure, when the fin cutting process and the process of removing unnecessary first multi-channel active patterns AP1 are performed simultaneously using the same process, the height of the upper surface CF1_US of the first connecting fin pattern can be the same as the height of the upper surface DPF_US of the dummy fin pattern. The fin cutting process can be a process for cutting the pre-active pattern into smaller segments and / or cutting the ring ends of the pre-active pattern.

[0164] Unlike the illustration, in embodiments of this disclosure, the first connecting fin pattern CF1 may be directly connected to a single second multichannel active pattern AP2. In embodiments of this disclosure, the first connecting fin pattern CF1 may not be directly connected to the second multichannel active pattern AP2.

[0165] Unlike what is shown, at least one second connecting fin pattern CF2 may not be directly connected to the first multichannel active pattern AP1 and the second multichannel active pattern AP2. Furthermore, at least one third connecting fin pattern CF3 may not be directly connected to the first multichannel active pattern AP1. At least one third connecting fin pattern CF3 may not be directly connected to the second multichannel active pattern AP2.

[0166] Figures 26 to 31 This is a diagram used to explain a method of manufacturing a mask according to embodiments of the present disclosure.

[0167] Reference Figure 26 The mask target layout is determined. The mask target layout may include a first layout group and a second layout group.

[0168] The first layout group may include first layout patterns to third layout patterns LO_11, LO_12 and LO_13 that extend elongatedly in the fourth direction D4. The first layout patterns to the third layout patterns LO_11, LO_12 and LO_13 may be spaced apart from each other in a fifth direction D5 perpendicular to the fourth direction D4.

[0169] The second layout group may include fourth to sixth layout patterns LO_21, LO_22 and LO_23 that extend elongatedly in the fourth direction D4. The fourth to sixth layout patterns LO_21, LO_22 and LO_23 may be spaced apart from each other in the fifth direction D5.

[0170] Next, the overlap run length (ORL) can be extracted between the first to third layout patterns LO_11, LO_12, and LO_13 and the fourth to sixth layout patterns LO_21, LO_22, and LO_23. The overlap run length (ORL) indicates the degree of overlap between the layout patterns of the first layout group and the layout patterns of the second layout group in the fourth direction D4. For example, Figure 26 The length of the overlap segment ORL between the second layout pattern LO_12 and the fifth layout pattern LO_22 is shown.

[0171] The overlap length ORL is used to determine the degree of merging between the layout patterns of the first layout group and the layout patterns of the second layout group that are facing each other in the fourth direction D4.

[0172] If the overlap length ORL is a% or less, the layout patterns of the first layout group and the second layout group are classified into the non-merged group. If the overlap length ORL exceeds a% and is b% or less, the layout patterns of the first and second layout groups are classified into the soft merged group. If the overlap length ORL exceeds b% and is 100% or less, the layout patterns of the first and second layout groups are classified into the hard merged group. Here, "a" and "b" are natural numbers less than 100, and "a" is less than "b". The values ​​of "a" and "b" can be defined by the actual printed image or by an image obtained through simulation using a set of provided layout patterns. The values ​​of "a" and "b" can vary depending on the resolution of the exposure tool used when printing the image and the size and proximity of the layout patterns of the mask used when printing the image.

[0173] The second layout pattern LO_12 and the fifth layout pattern LO_22 are classified into the soft merge group. The first layout pattern LO_11 and the fourth layout pattern LO_21 are classified into the hard merge group. The third layout pattern LO_13 and the sixth layout pattern LO_23 are classified into the non-merge group.

[0174] The following describes a method for manufacturing the mask layout used to implement the second layout pattern LO_12 and the fifth layout pattern LO_22. Furthermore, Figures 27 to 30 It corresponds to Figure 26 Part of P.

[0175] Reference Figure 27 A virtual target pattern V_TP is generated between the first target pattern TP1 and the second target pattern TP2, which overlap in the fourth direction D4 (the length direction). The first target pattern TP1 corresponds to... Figure 26 The fifth layout pattern LO_22 corresponds to the second target pattern TP2. Figure 26The second layout pattern is LO_12.

[0176] Fragments are generated in the first target pattern TP1, the second target pattern TP2, and the virtual target pattern V_TP. Each fragment includes a normal fragment N_frag and a virtual fragment V_frag. The normal fragment N_frag is generated in the first target pattern TP1 and the second target pattern TP2. The virtual fragment V_frag is generated in the virtual target pattern V_TP.

[0177] A virtual evaluation point V_EP is generated in the virtual target pattern V_TP.

[0178] Reference Figure 28 By inputting the first mask data into the optical proximity correction (OPC) model, the first contours TP1_C1 and TP2_C1 of the first target pattern TP1 and the second target pattern TP2 are extracted through simulation. The first mask data includes this segment.

[0179] Various basic data can be input into the OPC model as input data. Here, basic data can include mask data for fragments. Furthermore, basic data can include information such as the thickness, refractive index, and dielectric constant of the photoresist (PR), and can include data about the source pattern of the lighting system. However, basic data is not limited to the data exemplified above. On the other hand, mask data can include not only fragment data, but also data such as the pattern form, pattern location, type of pattern measurement (spacing or line measurement), and basic measurement values.

[0180] The outline of the target pattern is the output obtained through simulation using an OPC model and can correspond to the form of a pattern formed on the wafer using a photolithography process with a photomask. For example, the shapes of the first outline TP1_C1 of the first target pattern TP1 and the first outline TP2_C1 of the second target pattern TP2 can be transferred onto the wafer.

[0181] The first OPC pattern TP1_OPC1 of the first target pattern and the first OPC pattern TP2_OPC1 of the second target pattern can be OPC patterns used to extract the first outline TP1_C1 of the first target pattern TP1 and the first outline TP2_C1 of the second target pattern TP2. That is, when a photomask is generated based on the mask layout obtained by the first OPC pattern TP1_OPC1 of the first target pattern and the first OPC pattern TP2_OPC1 of the second target pattern, the shapes of the first outline TP1_C1 of the first target pattern TP1 and the first outline TP2_C1 of the second target pattern TP2 can be transferred onto the wafer.

[0182] Next, the edge placement error (EPE) is calculated. EPE can be the difference between the contour and the target pattern. A first normal EPE can be calculated between the first target pattern TP1, the second target pattern TP2, and the first contours TP1_C1 and TP2_C1. Additionally, a first virtual EPE (V_EPE) can be calculated between the virtual target pattern V_TP and the first contours TP1_C1 and TP2_C1. The first virtual EPE can be calculated at the virtual evaluation point V_EP.

[0183] The displacement of a segment is determined using a first virtual EPE. The displacement can be calculated by multiplying the first virtual EPE by the feedback. The feedback can be set by the user executing the OPC model. For example, while the feedback can be greater than 1 and less than 0, it is not limited to being greater than 1 and less than 0. Furthermore, the sign of the displacement (i.e., (-) and (+)) can indicate the direction of movement of the segment.

[0184] refer to Figure 28 and Figure 29 The first moved normal segment N_frag1 is located by moving it by one displacement from the normal segment N_frag, which is determined using the first virtual EPE. The second mask data can then be obtained.

[0185] By inputting the second mask data into the OPC model, the second contours TP1_C2 and TP2_C2 of the first target pattern TP1 and the second target pattern TP2 are extracted through simulation.

[0186] The first moving normal segment N_frag1 can be included in the second mask data.

[0187] The second contour TP1_C2 of the first target pattern TP1 and the second contour TP2_C2 of the second target pattern TP2 can be connected in the virtual target pattern V_TP area.

[0188] The second OPC pattern TP1_OPC2 of the first target pattern and the second OPC pattern TP2_OPC2 of the second target pattern can be OPC patterns used to extract the second contour TP1_C2 of the first target pattern TP1 and the second contour TP2_C2 of the second target pattern TP2.

[0189] Next, the second virtual EPE between the virtual target pattern V_TP and the second contours TP1_C2 and TP2_C2 can be calculated at the virtual evaluation point V_EP.

[0190] Repeat the aforementioned process until the virtual EPE is equal to or less than a set reference value, or the number of simulations performed by the aforementioned OPC model falls within the set reference number. For example, by repeating the aforementioned process, the second virtual EPE converges to 0 nm. If the second virtual EPE satisfies the above conditions, the second mask data can be determined as the final mask data.

[0191] If the second virtual EPE does not meet the above conditions, then the second virtual EPE is used to determine the segment's displacement. For example, the displacement can be calculated by multiplying the second virtual EPE by feedback. This feedback can be set by the user executing the OPC model.

[0192] Reference Figure 29 and Figure 30 The second moving normal segment N_frag2 is located by moving it by one displacement from the first moving normal segment N_frag1, which is determined using the second virtual EPE. The third mask data can then be obtained.

[0193] By inputting the third mask data into the OPC model, the third contours TP1_C3 and TP2_C3 of the first target pattern TP1 and the second target pattern TP2 are extracted through simulation.

[0194] The second moving normal fragment N_frag2 can be included in the third mask data.

[0195] The third contour TP1_C3 of the first target pattern TP1 and the third contour TP2_C3 of the second target pattern TP2 can be connected within the virtual target pattern V_TP region. Furthermore, the third virtual EPE between the virtual target pattern V_TP and the third contours TP1_C3 and TP2_C3 can be smaller than the set reference value at the virtual evaluation point V_EP.

[0196] The third OPC pattern TP1_OPC3 of the first target pattern and the third OPC pattern TP2_OPC3 of the second target pattern can be OPC patterns used to extract the third contour TP1_C3 of the first target pattern TP1 and the third contour TP2_C3 of the second target pattern TP2.

[0197] The third OPC pattern TP1_OPC3 of the first target pattern and the third OPC pattern TP2_OPC3 of the second target pattern can be determined as the final mask data.

[0198] Typically, the EPE obtained during contour extraction of the target pattern through the first OPC simulation, and subsequent EPE calculations, can deviate significantly from the reference value. Therefore, it can be determined that OPC simulations should not be performed after several to dozens of iterations. As a result, mask data, including fragment data that has been moved during the execution process of multiple OPC simulations, can be transformed into final mask data.

[0199] In the embodiments of this disclosure, during the process of determining the final mask data, a reference value for EPE (or V_EPE) and a reference number of simulations performed by the aforementioned OPC model can be set. The OPC simulation can be repeated until the set reference value for EPE (or V_EPE) or the set reference number of simulations performed by the aforementioned OPC model (whichever is reached earlier) is obtained to obtain the mask data as the final mask data.

[0200] Reference Figure 26 and Figure 31 A photomask can be created using the final mask data.

[0201] The photomask may include a first photomask pattern to a fifth photomask pattern M_LP11, M_LP21, M_LP22, M_LP31 and M_LP32.

[0202] The first photomask pattern M_LP11 can be fabricated based on the mask layout used to implement the fourth layout pattern LO_21 and the first layout pattern LO_11, which are classified into the hard-merging group. The first photomask pattern M_LP11 can be obtained from the simulated OPC pattern of the OPC model.

[0203] The second photomask pattern M_LP21 and the third photomask pattern M_LP22 can be fabricated based on the mask layout used to implement the fifth layout pattern LO_22 and the second layout pattern LO_12, which are classified into the soft merging group. This can be achieved through... Figures 27 to 30 The simulation of the OPC model describes the acquisition of the second photomask pattern M_LP21 and the third photomask pattern M_LP22.

[0204] The fourth photomask pattern M_LP31 and the fifth photomask pattern M_LP32 can be fabricated based on the mask layouts used to implement the sixth layout pattern LO_23 and the third layout pattern LO_13 classified into non-merged groups. The fourth photomask pattern M_LP31 and the fifth photomask pattern M_LP32 can be obtained from the simulated OPC pattern of the OPC model.

[0205] In executing the reference Figures 26 to 30Following the simulation of the described OPC model, Mask Threading (MTO) design data is transferred. Typically, MTO refers to the process of transferring the final mask data, after completing the OPC steps, to the mask manufacturing team to request mask fabrication. Therefore, the MTO design data can ultimately correspond to the final mask data on which the OPC simulation was performed. This MTO design data can have a graphical data format used in electronic design automation (EDA) software, etc. For example, the MTO design data can have a data format such as Graphical Data System II (GDSII) or Open Original Design System Interchange Standard (OASIS) and can describe the desired mask pattern to be manufactured.

[0206] After transmitting the MTO design data, mask data preparation (MDP) is performed. MDP may include, for example, format conversion called breakage, barcodes for mechanical reading, standard mask patterns for inspection, workgroup expansion, and verification in both automatic and manual methods. Here, workgroup may refer to a text file that creates a set of commands related to information such as the placement of multi-mask files, standard dose, lithography speed, and exposure method.

[0207] Format conversion (i.e., fragmentation) can refer to the process of dividing MTO design data into each region and changing its format to one suitable for electron beam lithography. For example, fragmentation can include data manipulation such as scaling, data resizing, data rotation, pattern reflection, and color inversion. In the conversion process via fragmentation, data containing a large number of systematic errors that may occur somewhere during the processing of images transferred from design data to the wafer can be corrected. This systematic error correction process is called Mask Process Correction (MPC) and can include, for example, linewidth adjustment known as CD adjustment, and work to improve pattern placement accuracy. Therefore, fragmentation can help improve the quality of the final mask and can be a pre-performed process for correcting the mask process. Here, systematic errors can be caused by distortions occurring in the lithography process, mask development and etching process, wafer imaging process, etc.

[0208] Mask data preparation may include MPC (Mechanical Process Control). As mentioned above, MPC refers to the process of correcting errors (i.e., systematic errors) that occur during the lithography process. Here, the lithography process can be a concept that typically includes electron beam writing, development, etching, baking, etc. For example, MPC can be applied to MTO (Mechanical Origin Tolerance) design data to adjust one or more of the size, shape, position, edge position of the pattern elements of the mask and / or the corresponding electron beam dose (or electron beam energy intensity) used when writing the mask. Furthermore, data processing can be performed before the lithography process. Data processing is a preprocessing procedure for the mask data and may include mask data syntax checking, lithography timing prediction, etc.

[0209] After preparing the mask data, the mask substrate is exposed based on the mask data. Here, photolithography can refer to, for example, electron beam writing. Electron beam writing can be performed, for example, using a multi-beam mask writer (MBMW) in grayscale writing mode. Alternatively, a variable shape beam (VSB) lithography machine can be used to perform electron beam writing.

[0210] After the mask data preparation step and before the photolithography process, a process can be performed to convert the mask data into pixel data. Pixel data is data directly used for actual photolithography and can include data about the shape of the photolithography target and data about the dose allocated to each of them. Here, the data about the shape can be bitmap data, where the shape data is converted into vector data through rasterization or the like. After generating the pixel data, an electron beam writing process can be performed by irradiating the mask substrate with an electron beam or multiple electron beams based on the pixel data.

[0211] Following the photolithography process, a series of processes are performed to complete the photomask. For example, this series of processes may include processes such as development, etching, and cleaning. Furthermore, the series of processes used to manufacture the photomask may include measurement processes, defect detection, and defect repair processes. Additionally, a thin-film coating process may be included. Here, a thin-film coating process can refer to a process in which a thin film is attached to the photomask surface to protect the photomask from subsequent contamination during transport and its usable lifetime, once the final cleaning and detection have revealed the absence of contaminating particles or chemical stains.

[0212] Figures 32A to 34B This is an intermediate stage diagram used to explain the method of manufacturing a semiconductor device according to embodiments of the present disclosure.

[0213] For reference only. Figure 32B , Figure 33B and Figure 34B They are along Figure 32A , Figure 33A and Figure 34A The cross-sectional view captured by FF. On the other hand, Figure 32B , Figure 33B and Figure 34B The images show cross-sectional views of the second mask transfer pattern PT_MP12, the second upper hard mask pattern PT_MP22, and the second lower hard mask pattern PT_MP32 cut along the second direction D2. Furthermore, cross-sectional views of the first mask transfer pattern PT_MP11, the first upper hard mask pattern PT_MP21, and the first lower hard mask pattern PT_MP31 cut along the second direction D2 can be compared with... Figure 32B , Figure 33B and Figure 34BEssentially the same. Furthermore, the cross-sectional views of the third mask transfer pattern PT_MP13, the third upper hard mask pattern PT_MP23, and the third lower hard mask pattern PT_MP33 cut along the second direction D2 can be compared with... Figure 32B , Figure 33B and Figure 34B They are basically the same.

[0214] Reference Figure 32A and Figure 32B A photolithography process can be performed on the substrate 100 using a photomask.

[0215] Can be referenced Figures 26 to 31 The method described herein is used to manufacture the photomask.

[0216] A first mask spacer film PT_SPL1 and a second mask spacer film PT_SPL2 are sequentially formed on the substrate 100.

[0217] The first mask transfer pattern to the third mask transfer pattern PT_MP11, PT_MP12 and PT_MP13 can be formed on the second mask spacer film PT_SPL2.

[0218] The first photomask pattern is formed by photolithography. Figure 31 The first photomask transfer pattern PT_MP11 is formed by transferring the second photomask pattern M_LP21 and the third photomask pattern M_LP22 onto the substrate 100 via photolithography. The second photomask transfer pattern PT_MP12 is formed by transferring the second photomask pattern M_LP21 and the third photomask pattern M_LP22 onto the substrate 100 via photolithography. The third photomask transfer pattern PT_MP13 is formed by transferring the fourth photomask pattern M_LP31 and the fifth photomask pattern M_LP32 onto the substrate 100 via photolithography. In embodiments of this disclosure, the first to third photomask transfer patterns PT_MP11, PT_MP12, and PT_MP13 can be used as a mandrel for a self-aligned quad patterning (SAQP) process.

[0219] Reference Figure 33A and Figure 33B An upper spacer pattern can be formed on the second mask spacer film PT_SPL2 along the outer walls of the first mask transfer pattern to the third mask transfer patterns PT_MP11, PT_MP12 and PT_MP13.

[0220] After the upper spacer pattern is formed, the first mask transfer pattern can be removed to the third mask transfer patterns PT_MP11, PT_MP12 and PT_MP13.

[0221] Next, the upper spacer pattern can be used as a mask to etch the second mask spacer film PT_SPL2. Therefore, the first upper hard mask pattern to the third upper hard mask pattern PT_MP21, PT_MP22 and PT_MP23 can be formed on the first mask spacer film PT_SPL1.

[0222] Reference Figure 34A and Figure 34B A lower spacer pattern can be formed on the first mask spacer film PT_SPL1 along the outer walls of the first upper hard mask pattern to the third upper hard mask patterns PT_MP21, PT_MP22 and PT_MP23.

[0223] After the lower spacer pattern is formed, the first upper hard mask pattern to the third upper hard mask pattern PT_MP21, PT_MP22 and PT_MP23 can be removed.

[0224] Next, the first mask spacer film PT_SPL1 can be etched using the lower spacer pattern as a mask. Therefore, the first to third lower hard mask patterns PT_MP31, PT_MP32 and PT_MP33 can be formed on the substrate 100.

[0225] Next, the substrate 100 can be etched using the first to third lower hard mask patterns PT_MP31, PT_MP32, and PT_MP33 as masks. A pre-multi-channel active pattern P_AP with a shape corresponding to the first to third lower hard mask patterns PT_MP31, PT_MP32, and PT_MP33 can be formed by the etching process.

[0226] Next, refer to Figure 1 By removing the portion of the pre-multichannel active pattern P_AP located in the connection region CRG, the first to third connection fin patterns CF1, CF2 and CF3 can be formed in the connection region CRG.

[0227] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the specific embodiments described without departing from the spirit and scope of this disclosure as defined in the appended claims. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device, comprising: A substrate comprising a first region, a second region, and a connection region disposed between the first region and the second region; Multiple first multi-channel active patterns are placed in a first region of the substrate; Multiple second multi-channel active patterns are placed in a second region of the substrate; A first connecting fin pattern is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction; as well as A field insulating film is placed on the substrate and covers the upper surface of the first connecting fin pattern. Wherein, the width of the first connecting fin pattern in the second direction decreases and then increases as it moves away from the first region, and The first direction is perpendicular to the second direction.

2. The semiconductor device according to claim 1, wherein, The first connecting fin pattern includes a bridging portion and a first branch portion and a second branch portion protruding from the bridging portion toward the first region, and The first branch portion and the second branch portion are spaced apart from each other in the second direction.

3. The semiconductor device according to claim 2, wherein, The first connecting fin pattern includes a third branch portion and a fourth branch portion protruding from the bridging portion toward the second region, and The third branch and the fourth branch are spaced apart from each other in the second direction.

4. The semiconductor device according to claim 2, wherein, The bridging portion extends into the second region.

5. The semiconductor device according to claim 1, wherein, The first connecting fin pattern is directly connected to two of the first multi-channel active patterns and two of the second multi-channel active patterns.

6. The semiconductor device according to claim 1, wherein, The first connecting fin pattern is directly connected to one of the first multi-channel active patterns and two of the second multi-channel active patterns.

7. The semiconductor device according to claim 1, wherein, The first connecting fin pattern is directly connected to one of the first multi-channel active patterns and one of the second multi-channel active patterns.

8. The semiconductor device according to claim 1, further comprising: A second connecting fin pattern is placed in the connecting area of ​​the substrate. The upper surface of the second connecting fin pattern has a semi-circular shape.

9. The semiconductor device according to claim 1, further comprising: A second connecting fin pattern is placed in the connecting region of the substrate and extends from the first region to the second region. Wherein, the width of the second connecting fin pattern in the second direction is smaller than the width of the first connecting fin pattern in the second direction.

10. The semiconductor device according to claim 1, wherein, Each of the first multi-channel active pattern and the second multi-channel active pattern is a fin-shaped pattern.

11. The semiconductor device according to claim 1, wherein, Each of the first multichannel active pattern and the second multichannel active pattern includes a lower fin pattern and a sheet pattern located on the lower fin pattern.

12. A semiconductor device, comprising: A substrate comprising a first region, a second region, and a connection region disposed between the first region and the second region; Multiple first multi-channel active patterns are placed in a first region of the substrate; Multiple second multi-channel active patterns are placed in a second region of the substrate; A first connecting fin pattern is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction; as well as A field insulating film is placed on the substrate and covers the upper surface of the first connecting fin pattern. The first connecting fin pattern includes a bridging portion and a first branch portion and a second branch portion protruding from the bridging portion toward the first region. The first branch portion and the second branch portion are spaced apart from each other in a second direction perpendicular to the first direction.

13. The semiconductor device according to claim 12, wherein, The bridging portion extends into the second region, and The width of the bridging portion in the second direction decreases and then increases as it moves away from the first branch portion and the second branch portion.

14. The semiconductor device according to claim 13, wherein, The bridging portion is directly connected to two or fewer of the second multichannel active patterns.

15. The semiconductor device according to claim 12, wherein, The first connecting fin pattern includes a third branch portion and a fourth branch portion protruding from the bridging portion toward the second region, and The third branch and the fourth branch are spaced apart from each other in the second direction.

16. The semiconductor device according to claim 15, wherein, One or both of the third and fourth branch portions are directly connected to the second multichannel active pattern.

17. The semiconductor device according to claim 12, wherein, One or both of the first branch portion and the second branch portion are directly connected to the first multichannel active pattern.

18. A semiconductor device, comprising: A substrate comprising a first region, a second region, and a connection region disposed between the first region and the second region; Multiple first multi-channel active patterns are placed in a first region of the substrate; Multiple second multi-channel active patterns are placed in a second region of the substrate; A first connecting fin pattern is placed in the connecting region of the substrate and extends from the first region to the second region in a first direction; A second connecting fin pattern is placed in the connecting area of ​​the substrate and has a semi-annular upper surface; A third connecting fin pattern is placed between the first connecting fin pattern and the second connecting fin pattern, and extends in the first direction along the outline of the outer wall of the first connecting fin pattern. A field insulating film is placed on the substrate and covers the upper surface of the first connecting fin pattern, the upper surface of the second connecting fin pattern, and the upper surface of the third connecting fin pattern; A first gate electrode extends on the first multi-channel active pattern in a second direction perpendicular to the first direction; as well as The second gate electrode extends in the second direction on the second multi-channel active pattern. The width of the first connecting fin pattern in the second direction decreases and then increases as it moves away from the first region.

19. The semiconductor device according to claim 18, wherein, The upper surface of the first connecting fin pattern has a Y shape.

20. The semiconductor device according to claim 18, wherein, The upper surface of the first connecting fin pattern has an X shape.

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