Access transistors in dual gate line configurations and methods of forming the same

Abstract

The present disclosure relates generally to access transistors in a dual gate line configuration and methods of forming the same. A semiconductor structure includes a two-dimensional array of unit cell structures over a substrate. Each unit cell structure includes an active layer, a gate dielectric under the active layer, two gate electrodes under the gate dielectric, and a drain electrode and two source electrodes over the active layer. Word lines are located under the active layer. Each unit cell structure includes portions of a respective set of four word lines, the set including two word lines electrically connected to two electrodes in the unit cell structure and two additional word lines electrically isolated from the two electrodes in the unit cell structure.

Description

Technical Field

[0001] This disclosure generally relates to access transistors in a dual-gate-line configuration and methods of forming thereof. Background Technology

[0002] Various transistor structures have been developed to meet diverse design criteria. Thin-film transistors (TFTs) made of oxide semiconductors are an attractive option for back-end process (BEOL) integration because TFTs can be processed at low temperatures and therefore do not damage previously manufactured devices. For example, manufacturing conditions and techniques do not damage previously manufactured front-end process (FEOL) and middle-end process (MEOL) devices. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor structure is provided, including a two-dimensional array of unit cell structures on a substrate, wherein each unit cell structure within the two-dimensional array of unit cell structures includes: an active layer comprising a semiconductor material; a gate dielectric beneath the active layer; a first gate electrode beneath a first portion of the gate dielectric; a second gate electrode beneath a second portion of the gate dielectric; a first source electrode contacting a first end portion of the active layer; a second source electrode contacting a second end portion of the active layer; and a drain electrode contacting a middle portion of the active layer; wherein the semiconductor structure further includes word lines beneath the active layer, the word lines being laterally spaced along a first horizontal direction and extending laterally along a second horizontal direction, wherein each unit cell structure within the two-dimensional array of unit cell structures includes portions of a set of four corresponding word lines selected from the word lines, and the set of four corresponding word lines includes two word lines electrically connected to the first gate electrode or the second gate electrode and two additional word lines electrically isolated from the first gate electrode and the second gate electrode.

[0004] According to another embodiment of this disclosure, a semiconductor structure is provided, comprising: an active layer comprising a semiconductor material and situated on a substrate; a gate dielectric below the active layer; a first gate electrode below a first portion of the gate dielectric; a second gate electrode below a second portion of the gate dielectric and laterally spaced from the first gate electrode; a first source electrode contacting a first end portion of the active layer; a second source electrode contacting a second end portion of the active layer; a drain electrode contacting a middle portion of the active layer; and at least four word lines having regions overlapping with and below the active layer in a plan view, wherein a first word line selected from the at least four word lines is electrically connected to the first gate electrode, a second word line selected from the at least four word lines is electrically connected to the second gate electrode, and all word lines selected from the at least four word lines other than the first and second word lines are electrically isolated from the first and second gate electrodes.

[0005] According to another embodiment of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming word lines on a substrate; forming word line connection via structures on the word lines; forming gate electrodes on the word line connection via structures; forming a two-dimensional array of stacked layers on the gate electrodes, each of the stacked layers including a gate dielectric and an active layer, wherein each active layer has a region overlapping and above: a set of two corresponding gate electrodes, a set of two corresponding word lines, and a set of two corresponding additional word lines, the set of two corresponding word lines being electrically connected to the set of two corresponding gate electrodes, and the set of two corresponding additional word lines being electrically isolated from the set of two corresponding gate electrodes; and forming a set of two source electrodes and a drain electrode on each active layer. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0007] In figures labeled with a combination of numbers and letter suffixes, figures with the same numbers correspond to the same processing steps. In figures labeled with numbers from 2 to 12, figures labeled with a combination of the number and the letter suffix "A" are top views. In figures labeled with numbers from 2 to 12, figures labeled with a combination of numbers and letter suffixes selected from "B", "C", "D", or "E" are vertical cross-sectional views along the vertical planes B-B', C-C', D-D', or E-E' of the structure shown in the figure labeled with the same number and letter index "A". In figures labeled with numbers from 2 to 12, vertical cross-sections B-B', C-C', D-D', and E-E' are shown in various top views and various vertical cross-sectional views (if applicable).

[0008] Figure 1 This is a vertical cross-sectional view of a first exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor, a first metal interconnect structure formed in a lower-level dielectric material layer, and an isolation dielectric layer, according to embodiments of the present disclosure.

[0009] Figures 2A to 2E These are various views of a portion of a memory array region of a first exemplary structure following the formation of an in-process insulating matrix layer and word line trenches, according to a first embodiment of this disclosure.

[0010] Figures 3A to 3E These are various views of a portion of a memory array region of a first exemplary structure following the formation of word lines, according to a first embodiment of the present disclosure.

[0011] Figures 4A to 4E These are various views of a portion of a memory array region in a first exemplary structure following the formation of a word line connection via structure, according to a first embodiment of the present disclosure.

[0012] Figures 5A to 5E Various views are taken of a portion of a memory array region of a first exemplary structure after the formation of the gate electrode, according to a first embodiment of the present disclosure.

[0013] Figures 6A to 6E These are various views of a portion of a memory array region of a first exemplary structure following the formation of a gate dielectric layer and a series of active layers, according to a first embodiment of the present disclosure.

[0014] Figures 7A to 7E These are various views of a portion of a memory array region of a first exemplary structure following the formation of a stack of gate dielectric and active layers, according to a first embodiment of the present disclosure.

[0015] Figures 8A to 8EThese are various views of a portion of a memory array region of a first exemplary structure following the formation of a dielectric layer and source and drain cavities, according to a first embodiment of the present disclosure.

[0016] Figures 9A to 9E Various views are taken of a portion of a memory array region of a first exemplary structure after the formation of source and drain electrodes, according to a first embodiment of the present disclosure.

[0017] Figures 10A to 10E These are various views of a portion of a memory array region of a first exemplary structure following the formation of a first higher-level dielectric material layer and a first higher-level metal interconnect structure, according to a first embodiment of the present disclosure.

[0018] Figures 11A to 11E These are various views of a portion of a memory array region of a first exemplary structure following the formation of a second higher-level dielectric material layer and a second higher-level metal interconnect structure, according to a first embodiment of the present disclosure.

[0019] Figures 12A to 12E These are various views of a portion of a memory array region in a first exemplary structure after the formation of the capacitor structure, according to a first embodiment of the present disclosure. For clarity, in Figure 12A The capacitor-level dielectric material layer is not shown.

[0020] Figure 13 This is a vertical cross-sectional view of a first exemplary structure after the formation of an additional higher-level dielectric material layer and an additional higher-level metal interconnect structure according to a first embodiment of the present disclosure.

[0021] Figure 14 This is a vertical cross-sectional view of an alternative configuration of a first exemplary structure according to a first embodiment of the present disclosure.

[0022] Figure 15A This is a schematic vertical cross-sectional view of a portion of the unit cells within a two-dimensional array of unit cells in a first exemplary structure according to a first embodiment of the present disclosure.

[0023] Figure 15B It is along Figure 15A A horizontal cross-sectional view of the horizontal plane B-B' in the diagram.

[0024] Figure 16A This is a schematic vertical cross-sectional view of a portion of a first exemplary structure according to a first embodiment of the present disclosure.

[0025] Figure 16B yes Figure 16A A schematic perspective view of a portion of the first exemplary structure.

[0026] Figure 17A This is a schematic vertical cross-sectional view of a portion of a first exemplary structure according to a first embodiment of the present disclosure.

[0027] Figure 17B yes Figure 17A A first plan view of a portion of a first exemplary structure, showing a first subset of structural elements. Vertical sections A-A' are... Figure 17A The plane of the vertical cross-section.

[0028] Figure 17C yes Figure 17A A first plan view of a portion of a first exemplary structure, showing a second subset of structural elements. Vertical sections A-A' are... Figure 17A The plane of the vertical cross-section.

[0029] Figure 18 This is a perspective view of a region of a first exemplary structure according to a first embodiment of the present disclosure.

[0030] Figures 19A to 19C This is a perspective view of a region of a first exemplary structure according to a first embodiment of the present disclosure.

[0031] Figure 20 This is a circuit diagram of a first exemplary structure according to a first embodiment of the present disclosure.

[0032] Figure 21A This is a plan view of a portion of a second exemplary structure according to a second embodiment of the present disclosure.

[0033] Figure 21B This is a plan view of a subset of components of a second exemplary structure at the level of word lines, word line connection via structures, and gate electrodes, according to a second embodiment of this disclosure.

[0034] Figures 22A to 22C This is a perspective view of a region of a second exemplary structure according to a second embodiment of the present disclosure.

[0035] Figure 23 This is a schematic diagram illustrating the configuration of word lines and bit lines in a first exemplary structure and a second exemplary structure according to embodiments of the present disclosure.

[0036] Figure 24 This is a flowchart illustrating the general processing steps for manufacturing the semiconductor device of this disclosure. Detailed Implementation

[0037] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] In addition, spatially related terms (e.g., "below," "below," "lower than," "above," "upper," etc.) may be used herein to facilitate the description of the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly. Elements with the same reference numerals denote the same elements and are assumed to have the same material composition and the same thickness range, unless otherwise expressly stated.

[0039] Generally, the structures and methods of this disclosure can be used to form embedded dynamic random access memory (DRAM) in back-end process (BEOL) structures at advanced nodes. Such embedded DRAM can offer advantages over static random access memory (SRAM) in terms of device density. The embedded DRAM of this disclosure can be formed in a folded bitline architecture that provides an improved differential sensing window by keeping the master bit line (BL) and the reference bit line (BL') (i.e., complementary bit lines used as references for the operation of sensing circuitry) close to each other. This disclosure uses transistors (e.g., thin-film transistors) that include a semiconductor metal-oxide active layer. Thus, the embedded DRAM of this disclosure can include a BEOL structure and, unlike single-crystal silicon-based field-effect transistors or fin field-effect transistors using single-crystal semiconductor fins, it does not occupy device regions at the front-end process (FEOL) stage.

[0040] Reference Figure 1This illustration shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 may include a semiconductor material layer 9 at least in its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 comprises a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 8 may comprise a single-crystal silicon substrate containing single-crystal silicon material.

[0041] A shallow trench isolation structure 720 comprising a dielectric material (e.g., silicon oxide) may be formed in the upper portion of the semiconductor material layer 9. Appropriately doped semiconductor wells (e.g., p-type and n-type wells) may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field-effect transistors 701 may be formed above the upper surface of the semiconductor material layer 9. For example, each field-effect transistor 701 may include a source electrode 732, a drain electrode 738, a semiconductor channel 735 including a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738, and a gate structure 750. The semiconductor channel 735 may comprise a single-crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 may be formed on each source electrode 732, and a drain-side metal-semiconductor alloy region 748 may be formed on each drain electrode 738.

[0042] The first exemplary structure may include a memory array region 100, in which a ferroelectric memory cell array may subsequently be formed. The first exemplary structure may also include a peripheral region 200 in which metal wiring for the ferroelectric memory device array is provided. Typically, field-effect transistors 701 in the CMOS circuit system 700 are electrically connected to the electrodes of the respective ferroelectric memory cells via a collection of corresponding metal interconnect structures.

[0043] Devices in peripheral region 200 (e.g., field-effect transistor 701) can function to operate the ferroelectric memory cell array subsequently formed. Specifically, devices in the peripheral region can be configured to control programming, erasing, and readout (read) operations of the ferroelectric memory cell array. For example, devices in the peripheral region may include readout circuitry and / or programming circuitry. Devices formed on the top surface of semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (e.g., resistors, diodes, capacitor structures, etc.), collectively referred to as CMOS circuitry system 700.

[0044] One or more field-effect transistors 701 in the CMOS circuit system 700 may include a semiconductor channel 735 that includes a portion of a semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 comprises a single-crystal semiconductor material (e.g., single-crystal silicon), then the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit system 700 may include a single-crystal semiconductor channel (e.g., a single-crystal silicon channel). In one embodiment, the plurality of field-effect transistors 701 in the CMOS circuit system 700 may include corresponding nodes that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently. For example, the plurality of field-effect transistors 701 in the CMOS circuit system 700 may include corresponding source electrodes 732 or corresponding drain electrodes 738 that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently.

[0045] In one embodiment, the CMOS circuit system 700 may include a programming control circuit configured to control the gate voltage of a set of field-effect transistors 701 for programming a respective ferroelectric memory cell, and configured to control the gate voltage of a transistor to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse to program a corresponding ferroelectric dielectric material layer in a selected ferroelectric memory cell to a first polarization state, in which the polarization in the ferroelectric dielectric material layer points to a first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse to program the ferroelectric dielectric material layer in a selected ferroelectric memory cell to a second polarization state, in which the polarization in the ferroelectric dielectric material layer points to a second electrode of the selected ferroelectric memory cell.

[0046] In one embodiment, substrate 8 may comprise a monocrystalline silicon substrate, and field-effect transistor 701 may comprise a corresponding portion of the monocrystalline silicon substrate as a semiconductor channel. As used herein, a "semiconductor" element refers to an element having a 1.0 × 10⁻⁶ ohm² / 40⁻¹² ... -6 S / cm up to 1.0×10 5 Elements with a conductivity of S / cm. As used herein, "semiconductor material" refers to materials that have a conductivity of 1.0 × 10⁻⁶ S / cm in the absence of electrical dopant. -6 S / cm up to 1.0×10 5 These materials exhibit electrical conductivity ranging from 1.0 S / cm to 1.0 × 10⁻⁶ when appropriately doped with electrical dopants. 5 Doped materials with an electrical conductivity of S / cm.

[0047] According to one aspect of this disclosure, a field-effect transistor 701 may subsequently be electrically connected to the drain and gate electrodes of an access transistor, the access transistor including a semiconductor metal-oxide plate to be formed above the field-effect transistor 701. In one embodiment, a subset of the field-effect transistor 701 may subsequently be electrically connected to at least one of the drain and gate electrodes. For example, the field-effect transistor 701 may include a first word line driver and a second word line driver, the first word line driver being configured to apply a first gate voltage to a first word line through a first subset of a lower-level metal interconnect structure to be formed subsequently, and the second word line driver being configured to apply a second gate voltage to a second word line through a second subset of the lower-level metal interconnect structure. Furthermore, the field-effect transistor 701 may include: a bit line driver configured to apply a bit line bias voltage to a bit line to be formed subsequently; and a sense amplifier configured to detect current flowing through the bit line during a read operation.

[0048] Various metal interconnect structures formed within the dielectric material layer can subsequently be formed on the substrate 8 and on the semiconductor device (e.g., field-effect transistor 701) on the substrate 8. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 601, a first interconnect level dielectric material layer 610, and a second interconnect level dielectric material layer 620. The first dielectric material layer 601 may be a layer surrounding contact structures connected to the source and drain (sometimes referred to as contact level dielectric material layer 601). The metal interconnect structures may include device contact via structures 612 formed in the first dielectric material layer 601 and contacting corresponding components of the CMOS circuit system 700, a first metal line structure 618 formed in the first interconnect level dielectric material layer 610, a first metal via structure 622 formed in the lower portion of the second interconnect level dielectric material layer 620, and a second metal line structure 628 formed in the upper portion of the second interconnect level dielectric material layer 620.

[0049] Each dielectric material layer (601, 610, 620) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each metal interconnect structure (612, 618, 622, 628) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, WC, and each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal fillers within the scope of this disclosure may also be used. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 may be formed as an integrated wire and via structure by a dual damascene process. The dielectric material layers (601, 610, 620) are referred to herein as lower-level dielectric material layers. The metal interconnect structures (612, 618, 622, 628) formed within the lower-level dielectric material layer are referred to herein as lower-level metal interconnect structures.

[0050] Although this disclosure uses an embodiment in which the memory cell array can be formed on the second line and via level dielectric material layer 620, it is clearly contemplated herein that an embodiment in which the memory cell array can be formed at different metal interconnect levels.

[0051] Transistor arrays and ferroelectric memory cell arrays can subsequently be deposited on dielectric material layers (601, 610, 620) on which metal interconnect structures (612, 618, 622, 628) have been formed. The collection of all dielectric material layers formed prior to the formation of the transistor array or ferroelectric memory cell array is collectively referred to as the lower-level dielectric material layers (601, 610, 620). The collection of all metal interconnect structures formed within the lower-level dielectric material layers (601, 610, 620) is referred to herein as the first metal interconnect structure (612, 618, 622, 628). Typically, the first metal interconnect structures (612, 618, 622, 628) formed within at least one lower-level dielectric material layer (601, 610, 620) can be formed on a semiconductor material layer 9 located in the substrate 8.

[0052] According to one aspect of this disclosure, transistors (e.g., thin-film transistors (TFTs)) can subsequently be formed in a metal interconnect layer above a metal interconnect layer comprising lower-level dielectric material layers (601, 610, 620) and first metal interconnect structures (612, 618, 622, 628). In one embodiment, a flat dielectric material layer having a uniform thickness can be formed above the lower-level dielectric material layers (601, 610, 620). This flat dielectric material layer is referred to herein as an in-process insulating substrate layer 635'. The in-process insulating substrate layer 635' comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and the in-process insulating substrate layer 635' can be deposited by chemical vapor deposition. The thickness of the in-process insulating substrate layer 635' can range from 20 nm to 300 nm, but smaller and larger thicknesses can also be used. In subsequent processing steps, additional insulating layers can be added, and the thickness of the insulating substrate layer 635 in the process can be increased.

[0053] Typically, an interconnect-level dielectric layer (e.g., a lower-level dielectric material layer (601, 610, 620)) containing a metal interconnect structure (e.g., a first metal interconnect structure (612, 618, 622, 628)) can be formed on the semiconductor device. An insulating substrate layer 635' can be formed on top of the interconnect-level dielectric layer.

[0054] In one embodiment, substrate 8 may include a single-crystal semiconductor material layer (e.g., semiconductor material layer 9), and field-effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) transistors) may include corresponding portions of the single-crystal semiconductor material layer, since corresponding channel regions may be formed on substrate 8.

[0055] It can be done later Figure 1 A memory array comprising a two-dimensional array of unit cell structures is formed on the first exemplary structure shown.

[0056] refer to Figures 2A to 2EA photoresist layer (not shown) can be applied over an insulating substrate layer 635' during the process, and this photoresist layer can be photolithographically patterned to form line and space patterns. Each line pattern in the patterned photoresist layer can be laterally spaced along a first horizontal direction hd1 and can extend laterally along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the line and space patterns in the patterned photoresist layer can be periodic patterns having periodicity along the first horizontal direction hd1. The area used to form the unit cell structure is marked with a dashed rectangle labeled "UC," and this area is referred to herein as the unit cell region UC. According to embodiments of the present disclosure, at least four space lateral extensions of the line and space patterns pass through each unit cell region UC. In other words, each unit cell region UC comprises at least four segments of space patterns.

[0057] An anisotropic etching process can be performed to transfer a spatial pattern into the upper portion of the insulating substrate layer 635' in the process. Line trenches (referred to herein as word trenches 19) can be formed in gaps from which material of the insulating substrate layer 635' is removed by the anisotropic etching process. The word trenches may extend laterally along a second horizontal direction hd2 and may be laterally spaced from each other along a first horizontal direction hd1. In one embodiment, the word trenches 19 may comprise pen-line trenches having straight sidewalls extending laterally along the second horizontal direction hd2. The word trenches 19 may have a periodicity along the first horizontal direction hd1, the periodicity being the same as the width of the unit cell region UC along the first horizontal direction hd1. In one embodiment, the word trenches 19 may have the same width along the first horizontal direction hd1 regardless of position. The depth of the word trenches 19 may range from 10 nm to 300 nm, for example, from 30 nm to 100 nm, but smaller and larger depths may also be used. After sequentially numbering the word line grooves 19 from 1 along a first horizontal direction using positive integers, the word line grooves 19 may include odd-numbered word line grooves 19 (referred to herein as first word line groove 19A) and even-numbered word line grooves 19 (referred to herein as second word line groove 19B). The patterned photoresist layer can then be removed, for example, by ashing.

[0058] See Figures 3A to 3EAt least one metallic material can be deposited in the word line trench 19. For example, a word line metal liner layer comprising a metal barrier material and a word line metal filler layer comprising a metal filler material can be sequentially deposited in the word line trench 19 and over the insulating substrate layer 635' during the process. The word line metal liner layer may comprise a metal barrier material (e.g., TiN, TaN, WN, TiC, TaC, WC, or stacks thereof) and can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the word line metal liner layer can range from 1 nm to 30 nm, but smaller and larger thicknesses can also be used. The word line metal filler layer may comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. The thickness of the word line metal filler layer can be selected such that each word line trench 19 is filled with a combination of the word line metal liner layer and the word line metal filler layer.

[0059] A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed to remove portions of the word line metal liner layer and the word line metal filler layer above a horizontal plane on the top surface of the insulating substrate layer 635' included in the process. Each remaining continuous portion of the word line metal liner layer and the word line metal filler layer filling the corresponding word line groove 19 constitutes a word line 3. Each word line 3 may include a word line metal liner 4 and a word line metal filler portion 5. Each word line metal liner 4 is the remaining portion of the word line metal liner layer after the planarization process. Each word line metal filler portion 5 is the remaining portion of the word line metal filler layer after the planarization process.

[0060] The character line 3 includes a first character line 3A filling a first character line groove 19A and a second character line 3B filling a second character line groove 19B. The first character line 3A and the second character line 3B alternate along a first horizontal direction hd1. Each unit cell UC includes at least four segments of different character lines 3, which include at least two first character lines 3A and at least two second character lines 3B.

[0061] Reference Figures 4A to 4B An insulating material layer (referred to herein as a via-level insulating layer) can be deposited on the insulating substrate layer 635' during the process, and this insulating material layer can be incorporated into the insulating substrate layer 635' during the process. The thickness of the insulating substrate layer 635' during the process can increase the thickness of the added insulating material layer, which can be, for example, in the range of 30 nm to 300 nm, such as 60 nm to 150 nm, but smaller and larger thicknesses can also be used.

[0062] A via cavity can be formed through the insulating substrate layer 635' in the process, such that the top surface of the word line 3 can be solidly exposed at the bottom of the via cavity. According to one aspect of the present disclosure, two via cavities can be formed within each unit cell region UC. In one embodiment, the top surfaces of the two first word lines 3A can be solidly exposed in the unit cell region UC, and the top surfaces of the two second word lines 3B can be solidly exposed in adjacent unit cell regions UC that are laterally offset relative to the unit cell region UC along the second horizontal direction hd2. Therefore, the type of word line 3 solidly exposed below the via cavity (i.e., the first word line 3A or the second word line 3B) can alternate along the second horizontal direction hd2. In one embodiment, the type of word line 3 solidly exposed below the via cavity can be the same along the first horizontal direction hd1, and can alternate between the first word line 3A and the second word line 3B along the second horizontal direction hd2. Thus, the positions of the via cavities can be offset along the second horizontal direction hd2.

[0063] At least one metallic material can be deposited in the via cavity. For example, a via metal liner layer comprising a metallic barrier material and a via metal filler layer comprising a metallic filler material can be sequentially deposited in the via cavity and on top of the insulating substrate layer 635' during the process. The via metal liner layer may include a metallic barrier material, such as TiN, TaN, WN, TiC, TaC, WC, or a stack thereof, and can be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the via metal liner layer can range from 1 nm to 30 nm, but smaller and larger thicknesses are also possible. The via metal filler layer may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. The thickness of the via metal filler layer can be selected such that each via cavity is filled with a combination of a via metal liner layer and a via metal filler layer.

[0064] A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed to remove portions of the via metal liner layer and via metal filler layer above a horizontal plane, including the top surface of the insulating substrate layer 635' in the process. Each remaining continuous portion of the via metal liner layer and via metal filler layer filling the corresponding via cavity constitutes a word line connection via structure 12. Each word line connection via structure 12 may include a via metal liner 13 and a via metal filler portion 14. Each via metal liner 13 is the remaining portion of the via metal liner layer after the planarization process. Each via metal filler portion 14 is the remaining portion of the via metal filler layer after the planarization process.

[0065] Each unit cell UC includes a pair of word line connection via structures 12. Typically, each word line connection via structure 12 can be formed on the top surface of a corresponding word line 3.

[0066] refer to Figures 5A to 5E An additional insulating material layer (referred to herein as a gate-level insulating layer) can be deposited on top of the insulating substrate layer 635' during the process, and this additional insulating material layer can be incorporated into the insulating substrate layer 635'. The thickness of the insulating substrate layer 635' can be increased by the thickness of the added insulating material layer, which can be, for example, in the range of 30 nm to 300 nm, such as 60 nm to 150 nm, but smaller and larger thicknesses can also be used. The insulating substrate layer 635' becomes the insulating substrate layer 635, which does not increase in thickness in subsequent processing steps.

[0067] A gate cavity (not shown) can be formed through the insulating substrate layer 635, such that the top surface of the word line connection via structure 12 is substantially exposed at the bottom of the gate cavity. According to one aspect of this disclosure, two gate cavities can be formed within each unit cell region UC. In one embodiment, the top surfaces of the two word line connection via structures 12 are substantially exposed in the unit cell region UC. The top surfaces of the word line connection via structures 12 are substantially exposed at the bottom of each gate cavity.

[0068] In one embodiment, each gate cavity may have its own rectangular horizontal cross-sectional shape. According to embodiments of this disclosure, each gate cavity may have a pair of first sidewalls parallel to a first horizontal direction hd1 and a pair of second sidewalls parallel to a second horizontal direction hd2. In one embodiment, each unit cell region UC may include two discrete gate cavities having a rectangular horizontal cross-sectional shape, and the regions of the two discrete gate cavities may be entirely located within the unit cell region UC. The two discrete gate cavities within each unit cell region UC may be laterally spaced from each other by a uniform spacing. Typically, the pair of first sidewalls of each gate cavity may or may not be parallel to the first horizontal direction hd1, and the pair of second sidewalls of each gate cavity may or may not be parallel to the second horizontal direction hd2.

[0069] At least one metallic material can be deposited in the gate cavity. For example, a gate metal liner layer comprising a metal barrier material and a gate metal filler layer comprising a metal filler material can be sequentially deposited in the gate cavity and over the insulating substrate layer 635. The gate metal liner layer may comprise a metal barrier material, such as TiN, TaN, WN, TiC, TaC, WC, or a stack thereof, and may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the gate metal liner layer may range from 1 nm to 30 nm, but smaller and larger thicknesses may also be used. The gate metal filler layer may comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. The thickness of the gate metal filler layer can be selected such that each gate cavity is filled with a combination of the gate metal liner layer and the gate metal filler layer.

[0070] A planarization process (e.g., chemical mechanical polishing (CMP)) can be performed to remove portions of the gate metal liner layer and gate metal filler layer above a horizontal plane including the top surface of the insulating substrate layer 635. Each remaining continuous portion of the gate metal liner layer and gate metal filler layer filling the respective gate cavity constitutes a gate electrode 15. Each gate electrode 15 may include a gate metal liner 16 and a gate metal filler portion 17. Each gate metal liner 16 is the remaining portion of the gate metal liner layer after the planarization process. Each gate metal filler portion 17 is the remaining portion of the gate metal filler layer after the planarization process.

[0071] A pair of gate electrodes 15 can be formed within each unit cell region UC. This pair of gate electrodes 15 may include a first gate electrode 15A and a second gate electrode 15B. Each word line connection via structure contacting the bottom surface of the first gate electrode 15A is referred to herein as a first word line connection via structure 12, and it contacts the top surface of one of the two word lines (3A, 3B) below the first gate electrode 15A. Each word line connection via structure contacting the bottom surface of the second gate electrode 15B is referred to herein as a second word line connection via structure 12, and it contacts the top surface of one of the two word lines (3A, 3B) below the second gate electrode 15B. Typically, the first word line 3A and the second word line 3B may be located below the first gate electrode 15A in the unit cell region UC, and additional first word line 3A and additional second word line 3B may be located below the second gate electrode 15B in the unit cell region UC.

[0072] In one embodiment, two first word lines 3A selected from the four word lines 3 extending through the unit cell region UC may be electrically connected to a corresponding one of the first gate electrode 15A and the second gate electrode 15B within the unit cell region UC. In another embodiment, two second word lines 3B selected from the four word lines 3 extending through the unit cell region UC may be electrically connected to a corresponding one of the first gate electrode 15A and the second gate electrode 15B within the unit cell region UC. In one embodiment, for each pair of adjacent unit cell regions UC that are adjacent to each other and laterally spaced apart from each other along the second horizontal direction hd2, the gate electrode 15 in one unit cell region UC may be electrically connected to two first word lines 3A, and the gate electrode 15 in the other unit cell region UC may be electrically connected to two second word lines 3B.

[0073] In one embodiment, each unit cell region UC may include a first gate electrode 15A and a second gate electrode 15B, and four word lines 3 may extend below the two gate electrodes (15A, 15B). Two of the four word lines 3 (3A or 3B) may be active word lines electrically connected to the two gate electrodes (15A, 15B) of the first unit cell region UC, and the other two word lines 3 (3B or 3A) may be passing word lines of the first unit cell region UC electrically isolated from the two gate electrodes (15A, 15B). In a second unit cell region UC that is adjacent to the first unit cell UC and laterally spaced from the first unit cell region UC along the second horizontal direction hd2, two word lines (3A or 3B) electrically connected to the gate electrodes (15A, 15B) in the first unit cell region UC become through word lines electrically isolated from any gate electrode (15A, 15B) in the second unit cell UC, and two word lines (3B or 3A) electrically floating in the first unit cell region UC become active word lines of the second unit cell region UC electrically connected to the two gate electrodes (15A, 15B) in the second unit cell region UC.

[0074] Within each unit cell region UC, the first word line connection via structure 12 can contact the bottom surface of the first gate electrode 15A and the top surface of one of the two active word lines (which can be two first word lines 3A or two second word lines 3B), and the second word line connection via structure 12 can contact the bottom surface of the second gate electrode 15B and the top surface of the other of the two active word lines.

[0075] refer to Figures 6A to 6EA gate dielectric layer 10C and a continuous active layer 20C can be sequentially deposited over an insulating substrate layer 635 and a gate electrode 15. The gate dielectric layer 10C can be formed over the insulating substrate layer 635 and the gate electrode 15 by depositing at least one gate dielectric material. The gate dielectric material may include (but is not limited to) silicon oxide, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or stacks thereof. Other suitable dielectric materials are within the scope of this disclosure. The gate dielectric material can be deposited by atomic layer deposition or chemical vapor deposition. The thickness of the gate dielectric layer 10C can range from 1 nm to 100 nm, for example, from 3 nm to 30 nm, but smaller and larger thicknesses can also be used.

[0076] A continuous active layer 20C comprising a semiconductor material can be deposited over the gate dielectric layer 10C. The continuous active layer 20C can be an unpatterned (i.e., blanket) semiconductor material layer. In one embodiment, the continuous active layer 20C may comprise a compound semiconductor material. In one embodiment, the semiconductor material comprises, after appropriate doping with an electrically conductive dopant (which may be a p-type or n-type dopant), a dielectric constant of 1.0 S / m to 1.0 × 10⁻¹⁰. 5 Materials with conductivity in the S / m range. Exemplary semiconductor materials that can be used for the continuous active layer 20C include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Typically, the continuous active layer 20C may comprise an oxide of at least one metal, such as at least two and / or at least three metals selected from In, Zn, Ga, Sn, Pb, Zr, Sr, Ru, Mn, Mg, Nb, Ta, Hf, Al, La, Sc, Ti, V, Cr, Mo, W, Fe, Co, Ni, Pd, Ir, Ag, and any combination thereof. Some metal elements may be present at a dopant concentration, for example, at an atomic percentage of less than 1.0%. Other suitable semiconductor materials are within the scope of this disclosure. In one embodiment, the semiconductor material of the continuous active layer 20C may include indium gallium zinc oxide.

[0077] The continuous active layer 20C may comprise a polycrystalline semiconductor material, or an amorphous semiconductor material that may subsequently be annealed to a polycrystalline semiconductor material having a larger average grain size. The continuous active layer 20C can be deposited via physical vapor deposition, but other suitable deposition processes may also be used. The thickness of the continuous active layer 20C can range from 1 nm to 300 nm, for example from 2 nm to 100 nm and / or from 4 nm to 50 nm, but smaller and larger thicknesses may also be used.

[0078] refer to Figures 7A to 7E A photoresist layer 43 can be applied over a continuous active layer 20C, and the photoresist layer 43 can be photolithographically patterned to form discrete patterned photoresist material portions. Each patterned portion of the photoresist layer 43 can be located within the area of ​​a corresponding unit cell region UC. A single discrete patterned photoresist material portion can be formed within each unit cell region UC. The area of ​​each patterned portion of the photoresist layer 43 can define the area of ​​a semiconductor metal oxide portion to be subsequently patterned from the continuous active layer 20C. In one embodiment, each patterned portion of the photoresist layer 43 can have a rectangular or rounded rectangular horizontal cross-sectional shape.

[0079] By performing an anisotropic etching process, the pattern in the photoresist layer 43 can be transferred through the continuous active layer 20C and the gate dielectric layer 10C. The patterned portion of the continuous active layer 20C includes a two-dimensional array of active layers 20. The patterned portion of the gate dielectric layer 10C includes a two-dimensional array of gate dielectrics 10. A two-dimensional array of stacked layers of gate dielectrics 10 and active layers 20 can be formed. The sidewalls of the gate dielectrics 10 and active layers 20 within each stack can be vertically overlapped, i.e., they can be located in the same vertical plane. The photoresist layer 43 can then be removed, for example, by ashing.

[0080] In one embodiment, each active layer 20 may have a rectangular or rounded rectangular horizontal cross-sectional shape. In one embodiment, the lateral dimension of each active layer 20 along the first horizontal direction hd1 may be in the range of 60 nm to 1000 nm, for example, from 100 nm to 300 nm, but smaller and larger lateral dimensions may also be used. In one embodiment, the lateral dimension of each active layer 20 along the second horizontal direction hd2 may be in the range of 20 nm to 500 nm, for example, from 40 nm to 250 nm, but smaller and larger lateral dimensions may also be used. The ratio of the lateral dimension along the first horizontal direction hd1 to the lateral dimension along the second horizontal direction hd2 in each active layer 20 may be in the range of 0.5 to 4, for example, 1 to 2, but smaller and larger ratios may also be used.

[0081] Typically, semiconductor material layers such as a continuous active layer 20C and a gate dielectric layer 10C can be patterned as a two-dimensional array of layer stacks (10, 20). Each layer stack includes a gate dielectric 10 and an active layer 20. The active layer 20 may include a semiconductor metal oxide material, and / or be substantially composed of a semiconductor metal oxide material. Each active layer 20 may include a pair of longitudinal sidewalls extending along the channel direction (i.e., the current direction between the source electrode and the drain electrode) and a pair of lateral sidewalls extending in a direction perpendicular to the channel direction. In one embodiment, the pair of lateral sidewalls may be parallel to the longitudinal direction of the word line 3, and the pair of longitudinal sidewalls may be perpendicular to the longitudinal direction of the word line 3.

[0082] According to one aspect of this disclosure, a two-dimensional array of layer stacks (10, 20) can be formed over a two-dimensional array of gate electrodes 15. Each layer stack (10, 20) may include a gate dielectric 10 and an active layer 20. Each active layer 20 has a region that overlaps with or is above: a set of corresponding two gate electrodes (15A, 15B), a set of corresponding two word lines (3A or 3B), and a set of corresponding two additional word lines (3B or 3A). The set of corresponding two word lines (3A or 3B) may be electrically connected to the set of corresponding two gate electrodes (15A, 15B), and the set of corresponding two additional word lines (3B or 3A) may be electrically isolated from the set of corresponding two gate electrodes (15A, 15B). In approximately 50% of the first type of unit cell region UC, which comprises approximately all unit cell regions UC, a set of two first word lines 3A is electrically connected to a set of corresponding two gate electrodes (15A, 15B), and a set of corresponding two second word lines 3B is electrically isolated from the set of corresponding two gate electrodes (15A, 15B). In approximately 50% of the second type of unit cell region UC, a set of two second word lines 3B is electrically connected to a set of corresponding two gate electrodes (15A, 15B), and a set of corresponding two first word lines 3A is electrically isolated from the set of corresponding two gate electrodes (15A, 15B).

[0083] The structure within each unit cell region UC includes: an active layer 20 comprising a semiconductor material (which may be a compound semiconductor material, such as a semiconductor metal oxide material); a gate dielectric 10 beneath the active layer 20; a first gate electrode 15A beneath a first portion of the gate dielectric 10; a second gate electrode 15B beneath a second portion of the gate dielectric 10; and at least four word lines (3A, 3B) having regions overlapping with and beneath the active layer 20 in a plan view. A first word line (3A or 3B) selected from the at least four word lines (3A, 3B) is electrically connected to the first gate electrode 15A, a second word line (3A or 3B) selected from the at least four word lines is electrically connected to the second gate electrode 15B, and all word lines selected from the at least four word lines (3A, 3B) other than the first word line (3A or 3B) and the second word line (3A or 3B) are electrically isolated from the first gate electrode 15A and the second gate electrode 15B. In an embodiment where the two first word lines 3A are electrically connected to the first gate electrode 15A and the second gate electrode 15B in the unit cell region UC, the two second word lines 3B are electrically isolated from the first gate electrode 15A and the second gate electrode 15B in the unit cell region UC.

[0084] In one embodiment, each of the first gate electrode 15A and the second gate electrode 15B may have a width along the channel direction (i.e., the current direction in the active layer 20), which is the same as the lateral separation direction between adjacent pairs of subsequently formed source and drain electrodes. In one embodiment, the width of each of the first gate electrode 15A and the second gate electrode 15B may be twice the width of each word line 3 along the first horizontal direction hd1.

[0085] refer to Figures 8A to 8E A dielectric layer 40 can be deposited on a two-dimensional array of stacked layers of gate dielectric 10 and active layer 20. The dielectric layer 40 is also referred to as a thin-film transistor-level (TFT-level) dielectric layer, i.e., a dielectric layer located at the thin-film transistor level. The dielectric layer 40 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a stack thereof. Optionally, the dielectric layer 40 can be planarized to provide a flat top surface. The thickness of the dielectric layer 40, measured from its interface with the insulating substrate layer 635, can range from 100 nm to 1000 nm, for example, 200 nm to 500 nm, but smaller and larger thicknesses are also possible.

[0086] A photoresist layer 47 may be applied over the dielectric layer 40, and the photoresist layer 47 may be photolithographically patterned to form discrete openings therein. In one embodiment, three rectangular openings may be formed in the photoresist layer 47 within each unit cell region UC. The three rectangular openings include two source openings and one drain opening, the source openings defining the lateral extent of a source electrode subsequently formed within the unit cell region UC, and the drain opening defining the lateral extent of a drain electrode subsequently formed within the unit cell region UC.

[0087] The pattern of line trenches and discrete openings in the photoresist layer 47 can be transferred through the dielectric layer 40 to form source cavities 51 and drain cavities 59. A pair of source cavities 51 can be formed over each active layer 20. Specifically, a pair of source cavities 51 can be formed at the end portions of a corresponding active layer 20 that are laterally spaced along the first horizontal direction hd1. The area of ​​each source cavity 51 can be entirely within the area of ​​the underlying active layer 20. A portion of the top surface of the active layer 20 can be solidly exposed at the bottom of each source cavity 51. Drain cavities 59 can be formed over each active layer 20 between the corresponding pair of source cavities 51. A portion of the top surface of the active layer 20 can be solidly exposed at the bottom of each drain cavity 59. The photoresist layer 47 can then be removed, for example, by ashing.

[0088] refer to Figures 9A to 9E At least one conductive material may be deposited in the cavities (51, 59) and on the dielectric layer 40. This at least one conductive material may include a metal liner material and a metal filler material. The metal liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the scope of this disclosure may also be used.

[0089] Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the dielectric layer 40 using a planarization process, which may employ CMP and / or recess etching processes. Other suitable planarization processes may also be used. Each remaining portion of the at least one conductive material filling the source cavity 51 constitutes a source electrode 52. Each remaining portion of the at least one conductive material filling the drain cavity 59 constitutes a drain electrode 56.

[0090] In one embodiment, each source electrode 52 may include a source metal liner 53 as the remainder of a metal liner material and a source metal filler portion 54 as the remainder of a metal filler material. Each drain electrode 56 may include a drain metal liner 57 as the remainder of a metal liner material and a drain metal filler portion 58 as the remainder of a metal filler material. Each top word line 3 may include a gate metal liner 4 as the remainder of a metal liner material and a gate metal filler portion 5 as the remainder of a metal filler material. Typically, the first source electrode 52, the drain electrode 56, and the second source electrode 52 may be formed on corresponding portions of the top surface of each active layer 20. The drain electrode 56 is formed between the first source electrode 52 and the second source electrode 52.

[0091] Typically, a first transistor and a second transistor can be formed in each unit cell region UC. The first and second transistors include an active layer 20 as a continuous material portion located above the substrate 8, and an assembly of electrode structures (52, 15, 56) located on the active layer 20, which may include a first source electrode 52, a first gate electrode 15A, a drain electrode 56, a second gate electrode 15B, and a second source electrode 52 along a first horizontal direction hd1 from one side to the other. A first portion of the active layer 20 extending laterally between the first source electrode 52 and the drain electrode 56 may include a first semiconductor channel, and a second portion of the active layer 20 extending laterally between the second source electrode 52 and the drain electrode 56 may include a second semiconductor channel. The top surfaces of the first source electrode 52, the drain electrode 56, and the second source electrode 52 may lie in a horizontal plane including the top surface of the dielectric layer 40 (i.e., coplanar).

[0092] Typically, a combination of two source electrodes 52 and a drain electrode 56 are located on each active layer 20. The first source electrode 52 contacts a first end portion of the active layer 20, and the second source electrode 52 contacts a second end portion of the active layer 20. The drain electrode 56 contacts a middle portion of the active layer 20. In one embodiment, the separation direction between the first source electrode 52 and the second source electrode 52 may be the same as the first horizontal direction hd1.

[0093] refer to Figures 10A to 10EAt least one first higher-level dielectric material layer 70 and a first higher-level metal interconnect structure (72, 74, 76, 78) can be formed on the dielectric layer 40. The at least one first higher-level dielectric material layer 70 may include a first via-level dielectric material layer and a first line-level dielectric material layer. The first via-level dielectric material layer has a source contact via structure 72 and a drain contact via structure 76 formed therein. The first line-level dielectric material layer has an embedded first source connection pad 74 and a bit line 78. In this embodiment, the first via-level dielectric material layer may be formed first, and the source contact via structure 72 and the drain contact via structure 76 may be formed through the first via-level dielectric material layer. The first line-level dielectric material layer may then be formed on the first via-level dielectric material layer, and the first source connection pad 74 and the bit line 78 may then be formed through the first line-level dielectric material layer on one of the source contact via structure 72 and the drain contact via structure 76.

[0094] Alternatively, the first via-level dielectric material layer and the first line-level dielectric material layer can be formed as a single dielectric material layer, and a dual damascene process can be performed to form an integrated line and via structure. The integrated line and via structure includes source-side integrated line and via structures and drain-side integrated line and via structures. The source-side integrated line and via structure includes a corresponding combination of a source contact via structure 72 and a first source connection pad 74. The drain-side integrated line and via structure includes a corresponding combination of a drain contact via structure 76 and bit lines 78 integrally formed within the drain contact via structure 76. In one embodiment, each bit line 78 extends laterally along a first horizontal direction hd1 and can be electrically connected to an assembly of drain electrodes 56 disposed along the first horizontal direction hd1.

[0095] Typically, a source contact via structure 72 may be formed on the source electrode 52, and a drain contact via structure 76 may be formed on the drain electrode 56. Bit lines 78 may be formed on the drain contact via structure 76, such that each bit line 78 extends laterally along a horizontal direction perpendicular to the length direction of the word line 3. The bit lines 78 may extend laterally along a horizontal direction different from the second horizontal direction hd2 (e.g., the first horizontal direction hd1). In one embodiment, each active layer 20 may have a rectangular horizontal cross-sectional shape having a first side parallel to the first horizontal direction hd1 and a second side parallel to the second horizontal direction hd2.

[0096] refer to Figures 11A to 11EAt least one second higher-level dielectric material layer 80 and a second higher-level metal interconnect structure (82, 84) can be formed over at least one first higher-level dielectric material layer 70. The at least one second higher-level dielectric material layer 80 may include a second via-level dielectric material layer in which a source connection via structure 82 is formed, and a second line-level dielectric material layer in which a second source connection pad 84 is formed. In this embodiment, a second via-level dielectric material layer can be formed, and the source contact via structure 82 can be formed through the second via-level dielectric material layer. Subsequently, a second line-level dielectric material layer can be formed over the second via-level dielectric material layer, and subsequently, a second source connection pad 84 can be formed through the second line-level dielectric material layer over the corresponding source connection via structure 82.

[0097] Alternatively, the second via-level dielectric material layer and the second line-level dielectric material layer can be formed as a single dielectric material layer, and a dual damascene process can be performed to form an integrated line and via structure. This integrated line and via structure includes a source-side integrated line and via structure comprising a corresponding combination of a source connection via structure 82 and a second source connection pad 84.

[0098] Typically, a higher-level dielectric material layer (70, 80) can be formed above the dielectric layer 40. Source connection metal interconnect structures (72, 74, 82, 84) can be formed within the higher-level dielectric material layers (70, 80). These source connection metal interconnect structures (72, 74, 82, 84) can be used to electrically connect each source electrode 52 to a conductive node of a corresponding capacitor structure to be formed subsequently. Within each unit cell region UC, a first source connection metal interconnect structure (72, 74, 82, 84) can be used to provide an electrical connection between the first source electrode 52 and a first conductive node of a first capacitor structure to be formed subsequently, and a second source connection metal interconnect structure (72, 74, 82, 84) can be used to provide an electrical connection between the second source electrode 52 and a second conductive node of a second capacitor structure to be formed subsequently.

[0099] refer to Figures 12A to 12EA capacitor structure 98 can be formed within the capacitor-level dielectric material layer 90. For example, a source-side electrode 92 (also referred to as a first capacitor electrode) can be formed on the top surface of the second source connection pad 84 by depositing and patterning a first conductive material, which can be a metallic material or a heavily doped semiconductor material. Optionally, a dielectric etch stop layer 89 can be formed on the top surface of the second higher-level dielectric material layer 80. A node dielectric 94 can be formed on each source-side electrode 92 by depositing a node dielectric material (e.g., silicon oxide and / or dielectric metal oxides (e.g., aluminum oxide, lanthanum oxide, and / or hafnium oxide)). A ground-side electrode 96 (also referred to as a second capacitor electrode) can be formed on the solid exposed surface of the node dielectric by depositing and patterning a second conductive material, which can be a metallic material or a heavily doped semiconductor material. Note that the area of ​​the unit cell UC at the level of capacitor structure 98 is offset relative to the area of ​​the unit cell UC at the level of the higher-level dielectric material layers (70, 80), such that each unit cell UC comprises a pair of capacitor structures 98 as a continuous structure. The two-dimensional periodicity of the unit cell UC is the same, regardless of the level that defines the area of ​​the unit cell UC.

[0100] Each consecutive combination of the source-side electrode 92, the node dielectric 94, and the ground-side electrode 96 can constitute a capacitor structure 98. A pair of capacitor structures 98 can be formed within each unit cell region UC. Therefore, a first capacitor structure 98 and a second capacitor structure 98 can be formed within each unit cell region UC. The first conductive node of the first capacitor structure 98 (e.g., the source-side electrode 92) is electrically connected to the underlying first source electrode 52, and the second conductive node of the second capacitor structure 98 (e.g., another source-side electrode 92) is electrically connected to the underlying second source electrode 52.

[0101] Typically, the field-effect transistor 701 located on the substrate 8 can be electrically connected to various nodes of the transistor formed within the dielectric layer 40. A subset of the field-effect transistor 701 can be electrically connected to at least one of the drain electrode 56, the first gate electrode 15A, and the second gate electrode 15B. The bottom surface of the first conductive node of the first capacitor structure 98 can contact the top surface of a corresponding first source-connected metal interconnect structure (72, 74, 82, 84). The bottom surface of the second conductive node of the second capacitor structure 98 can contact the top surface of a corresponding second source-connected metal interconnect structure (72, 74, 82, 84).

[0102] A capacitor-level dielectric material layer 90 may be formed on the capacitor structure 98. Each capacitor structure 98 may be formed within and laterally surrounded by the capacitor-level dielectric material layer 90, which is one of the higher-level dielectric material layers (70, 80, 90).

[0103] In one embodiment, each source-side electrode 92 may be electrically connected to (i.e., electrically short-circuited to) a corresponding source electrode 52. Each ground-side electrode 96 may be electrically grounded, for example, by forming an array of conductive via structures (not shown) that contact the ground-side electrode 96 and connect to an overlying metal electrode (not shown). Typically, the capacitor structure 98 may be formed above a horizontal plane including a top surface of bit lines 78. Each capacitor structure 98 includes a node electrically connected to a corresponding source electrode 52.

[0104] A unit cell structure is formed within a volume laterally defined by the unit cell region UC. A first exemplary structure may include a two-dimensional array of unit cell structures. In one embodiment, each unit cell structure within the two-dimensional array of unit cell structures may include: a first capacitor structure 98, which may include a first source-side electrode 92 electrically connected to a first source electrode 52; and a second capacitor structure 98, which may include a second source-side electrode 92 electrically connected to a second source electrode 52.

[0105] In one embodiment, each unit cell structure within the two-dimensional array of unit cell structures may include: a first source-side metal interconnect structure (72, 74, 82, 84), which may include at least one first conductive via structure (72, 82) and provides an electrical connection between the first source electrode 52 and the first source-side plate 92; and a second source-side metal interconnect structure (72, 74, 82, 84), which may include at least one second conductive via structure (72, 82) and provides an electrical connection between the second source electrode 52 and the second source-side plate 92.

[0106] In one embodiment, each unit cell structure within a two-dimensional array of unit cell structures may include a bit line contact structure 76 that contacts the top surface of the drain electrode 56 and the bottom surface of a corresponding bit line 78. In one embodiment, a field-effect transistor 701 may be located beneath at least four word lines 3 within each unit cell structure. The field-effect transistor 701 may include a portion of a substrate (which may include a single-crystal semiconductor material) as a corresponding channel region.

[0107] Reference Figure 13This illustrates a first exemplary structure following the formation of a two-dimensional array of memory cells 99 on an insulating substrate layer 635. Various additional metal interconnect structures (632, 668) can be formed in the insulating substrate layer 635, the dielectric layer 40, and higher-level dielectric material layers (70, 80, 90). The additional metal interconnect structures (632, 668) may include, for example, a second metal via structure 632 formed through the insulating substrate layer 635 and the dielectric layer 40 on the top surface of a corresponding second metal line structure 628. Furthermore, the additional metal interconnect structures (632, 668) may include, for example, metal line structures formed in the upper portion of the capacitor-level dielectric material layer 90, referred herein as a sixth metal line structure 668.

[0108] Subsequently, additional interconnect-level dielectric material layers and additional metal interconnect structures can be formed. For example, a seventh interconnect-level dielectric material layer 670, incorporating a seventh metal wire structure 678 and a sixth metal via structure 672, can be formed over the capacitor-level dielectric material layer 90. Although this disclosure is described using an embodiment in which seven levels of metal wire structures are used, embodiments using fewer or more interconnect layers are expressly contemplated herein.

[0109] Reference Figure 14 Through multiple two-dimensional arrays of vertically stacked memory cells 99, it is possible to obtain from Figure 13 Alternative configurations of the first exemplary structure according to the first embodiment of this disclosure are derived from the first exemplary structure shown. Although in Figure 14 The document illustrates a configuration of four two-dimensional arrays of vertically stacked memory cells 99, but additional configurations of two, three, five, or more two-dimensional arrays of vertically stacked memory cells 99 are explicitly anticipated herein.

[0110] exist Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figures 17A to 17C , Figure 18 and Figures 19A to 19C It shows Figures 12A to 12C Various additional views of the first exemplary structure. Figure 15A This is a schematic vertical cross-sectional view of a portion of the unit cells within a two-dimensional array of unit cells in a first exemplary structure according to a first embodiment of the present disclosure. Figure 15B It is along Figure 15A A horizontal cross-sectional view of the horizontal plane B-B' in the diagram. Figure 16A This is a schematic vertical cross-sectional view of a portion of a first exemplary structure according to a first embodiment of the present disclosure. Figure 16B yes Figure 16AA schematic perspective view of a portion of the first exemplary structure. Figure 17A This is a schematic vertical cross-sectional view of a portion of a first exemplary structure according to a first embodiment of the present disclosure. Figure 17B yes Figure 17A A first plan view of a portion of a first exemplary structure, showing a first subset of structural elements. Vertical sections A-A' are... Figure 17A The plane of the vertical cross-section. Figure 17C yes Figure 17A A first plan view of a portion of a first exemplary structure, showing a second subset of structural elements. Vertical sections A-A' are... Figure 17A The plane of the vertical cross-section. Figure 18 This is a perspective view of a region of a first exemplary structure according to a first embodiment of the present disclosure. Figures 19A to 19C This is a perspective view of a region of a first exemplary structure according to a first embodiment of the present disclosure.

[0111] refer to Figure 20 This diagram illustrates a circuit schematic of a portion of a first exemplary structure according to a first embodiment of the present disclosure. The circuit schematic shows eight thin-film transistors formed within four adjacent unit cell regions UC arranged along a second horizontal direction hd2 in the first exemplary structure described above. A pair of bit lines (BL, BL') (including a pair of bit lines 78 in the first exemplary structure described above) can be connected to a sense amplifier SA. Each word line (WL1, WL2, WL3, WL4) can be connected along the length of the word line (WL1, WL2, WL3, WL4) to the gate electrode 15 of every other transistor. Regarding the four word lines, word lines WL1 and WL3 correspond to the first word line 3A, and word lines WL2 and WL4 correspond to the second word line 3B.

[0112] Bit line pairs (BL, BL') consist of a major bit line BL and a complementary bit line BL'. During a read operation on each memory cell connected to the major bit line BL, the complementary bit line BL' acts as a reference bit line. During a read operation on each memory cell connected to the complementary bit line BL', the major bit line BL acts as a reference bit line. Figure 20 The folded bit line configuration shown enhances the noise immunity of the memory cell array and increases the signal-to-noise ratio of the memory cell array during readout, since most of the noise present during readout is common-mode noise.

[0113] Reference Figure 21A , Figure 21B and Figures 22A to 22CA second exemplary structure according to a second embodiment of the present disclosure is shown. The second exemplary structure can be derived from the first exemplary structure by azimuthally rotating the element about a vertical axis perpendicular to the top surface of the substrate 8 with a rotation angle that is not a multiple of π / 2 (i.e., 90 degrees) between a first horizontal plane including the bottom surface of the gate electrode 15 and a second horizontal plane including the top surface of the source electrode 52 and the drain electrode 56. In other words, the rotation angle can be greater than 0 degrees and less than 90 degrees, greater than 90 degrees and less than 180 degrees, greater than 180 degrees and less than 270 degrees, or greater than 270 degrees and less than 360 degrees. In one embodiment, the rotation angle can be in the range of 1 degree to 89 degrees, in the range of 91 degrees to 179 degrees, in the range of 181 degrees to 269 degrees, or in the range of 271 degrees to 359 degrees. In one embodiment, the rotation angle can be in the range of 5 to 85 degrees, 95 to 175 degrees, 185 to 265 degrees, or 275 to 355 degrees. In another embodiment, the rotation angle can be in the range of 10 to 80 degrees, 100 to 170 degrees, 190 to 260 degrees, or 280 to 350 degrees. In yet another embodiment, the rotation angle can be in the range of 20 to 70 degrees, 110 to 160 degrees, 200 to 250 degrees, or 290 to 340 degrees. In yet another embodiment, the rotation angle can be in the range of 30 to 60 degrees, 120 to 150 degrees, 210 to 240 degrees, or 300 to 330 degrees.

[0114] The position of the word line connection via structure 12 can be rearranged as necessary to provide an electrical connection between the word line 3 and the gate electrode 15. The electrical connection between the word line 3 and the gate electrode 15 can have the same circuit diagram as in the first exemplary structure. The positions of the source contact via structure 72 and the drain contact via structure 76 can be rearranged as necessary to provide electrical connections between the source electrode 52 and the source connection pad 74, and between the drain electrode 56 and the bit line 78. The electrical connection between the source electrode 52 and the source connection pad 74 can have the same circuit diagram as in the first exemplary structure. The electrical connection between the drain electrode 56 and the bit line 78 can have the same circuit diagram as in the first exemplary structure.

[0115] In some embodiments, the source contact via structure 72 may be vertically elongated. In this embodiment, the source connection pad 74 and the source connection via structure 82 may be omitted, and the second source connection pad 84 may be formed on the top surface of the second contact via structure 72.

[0116] Typically, a gate dielectric layer 10C and a semiconductor material layer (e.g., a continuous active layer 20C) can be deposited over the gate electrode 15. The semiconductor material layer and the gate dielectric layer 10C can be patterned as a two-dimensional array of layer stacks (10, 20). Each layer stack (10, 20) may include a gate dielectric 10 and an active layer 20. In one embodiment, each active layer 20 may include two sidewalls that are not perpendicular to and not parallel to the length direction (e.g., the second horizontal direction hd2) of the word line 3, and may include two additional sidewalls perpendicular to the two sidewalls. In one embodiment, each active layer 20 may have a rectangular horizontal cross-sectional shape having two pairs of parallel sidewalls that are not parallel to and not perpendicular to the first horizontal direction hd1 or the second horizontal direction hd2. The two pairs of parallel sidewalls may include two first sidewalls that are parallel to each other and two second sidewalls that are parallel to each other and perpendicular to the two first sidewalls. In one embodiment, the bit line 78 may extend laterally along the first horizontal direction hd1, and the word line 3 may extend laterally along the second horizontal direction hd2. In one embodiment, the second horizontal direction hd2 can be perpendicular to the first horizontal direction hd1.

[0117] In one embodiment, the separation direction between the first source electrode 52 and the second source electrode 52 (i.e., the channel direction that serves as the current flow direction within the active layer 20) is not parallel to the first horizontal direction hd1 and not parallel to the second horizontal direction hd2.

[0118] In one embodiment, the active layer 20 in the two-dimensional array of the unit cell structure is arranged with a first periodicity along a third horizontal direction hd3 and a second periodicity along a fourth horizontal direction hd4, wherein the third horizontal direction hd3 is not parallel to the first horizontal direction hd1 and not parallel to the second horizontal direction hd2, and the fourth horizontal direction hd4 is perpendicular to the third horizontal direction.

[0119] refer to Figure 23 The schematic diagram illustrates the configuration of word lines (WL1, WL2, WL3, WL4) and bit lines (BL, BL') in a first exemplary structure and a second exemplary structure according to embodiments of the present disclosure. The folded bit line configuration uses electrical connections of each word line 3 along the length direction of the word line 3 to every other gate electrode 15, thus providing an enhanced signal-to-noise ratio.

[0120] refer to Figure 24 The flowchart illustrates the general processing steps for manufacturing the semiconductor device of this disclosure.

[0121] Refer to step 2410 and Figure 1 , Figures 2A to 2E , Figures 3A to 3E , Figure 21A , Figure 21B and Figures 22A to 22CWord lines 3 are formed on substrate 8.

[0122] Refer to step 2420 and Figures 4A to 4E , Figure 21A , Figure 21B and Figures 22A to 22C A character line connection via structure 12 is formed on the character line 3.

[0123] Refer to step 2430 and Figures 5A to 5E , Figure 21A , Figure 21B and Figures 22A to 22C A gate electrode 15 is formed on the word line connection via structure 12.

[0124] Refer to step 2440 and Figures 6A to 6E , Figures 7A to 7E , Figure 21A , Figure 21B and Figures 22A to 22C A two-dimensional array of stacked layers (10, 20) can be formed over the gate electrode 15. Each stacked layer (10, 20) may include a gate dielectric 15 and an active layer 20. Each active layer 20 has a region that overlaps with and is above the following: a set of two corresponding gate electrodes (15A, 15B), a set of two corresponding word lines (3A or 3B), and a set of two corresponding additional word lines (3B or 3A). The set of two corresponding word lines (3A or 3B) may be electrically connected to the set of two corresponding gate electrodes (15A, 15B), and the set of two corresponding additional word lines (3B or 3A) may be electrically isolated from the set of two corresponding gate electrodes (15A, 15B).

[0125] Refer to step 2450 and Figures 8A to 19C , Figure 21A and Figure 21B as well as Figures 22A to 22C Two sets of source electrodes 52 and drain electrodes 56 can be formed on each active layer 20.

[0126] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor structure is provided that may include a two-dimensional array of unit cell structures on a substrate 8. Each unit cell structure within the two-dimensional array of unit cell structures may include: an active layer 20 comprising a semiconductor material; a gate dielectric 10 beneath the active layer 20; a first gate electrode 15A beneath a first portion of the gate dielectric 10; a second gate electrode 15B beneath a second portion of the gate dielectric 10; a first source electrode 52 contacting a first end portion of the active layer 20; a second source electrode 52 contacting a second end portion of the active layer 20; and a drain electrode 56 contacting a middle portion of the active layer 20. The semiconductor device may also include word lines 3 beneath the active layer 20, which are laterally spaced along a first horizontal direction hd1 and extend laterally along a second horizontal direction hd2. Each unit cell structure within the two-dimensional array of unit cell structures may include a portion of a set of four corresponding word lines 3 selected from these word lines 3, and the set of four corresponding word lines 3 may include two word lines (3A or 3B) electrically connected to the first gate electrode 15A or the second gate electrode 15B and two additional word lines (3B or 3A) electrically isolated from the first gate electrode 15A and the second gate electrode 15B.

[0127] In one embodiment, each unit cell structure within a two-dimensional array of unit cell structures may include: a first word line connection via structure 12 that contacts the bottom surface of the first gate electrode 15A and the top surface of one of the two word lines (3A or 3B); and a second word line connection via structure 12 that contacts the bottom surface of the second gate electrode 15B and the top surface of the other of the two word lines (3A or 3B).

[0128] In one embodiment, each of the first gate electrode 15A and the second gate electrode 15B has a width along the separation direction between the first source electrode 52 and the second source electrode 52; and the width of each of the first gate electrode 15A and the second gate electrode 15B is twice the width of each word line 3 along the first horizontal direction hd1. This configuration ensures sufficient coverage tolerance for forming the word line connection via structure 12.

[0129] In one embodiment, the separation direction between the first source electrode 52 and the second source electrode 52 is the same as that of the first horizontal direction hd1 (as in the first exemplary structure).

[0130] In one embodiment, the separation direction between the first source electrode 52 and the second source electrode 52 is not parallel to the first horizontal direction hd1 and not parallel to the second horizontal direction hd2 (as in the second exemplary structure).

[0131] In one embodiment, each unit cell structure within the two-dimensional array of unit cell structures may include: a first capacitor structure 98, which includes a first source-side plate 92 electrically connected to the first source electrode 52; and a second capacitor structure 98, which includes a second source-side plate 92 electrically connected to the second source electrode 52. In one embodiment, each unit cell structure within the two-dimensional array of unit cell structures may include: a first source-side metal interconnect structure (72, 74, 82, 84), which includes at least one first conductive via structure (72, 82) and provides an electrical connection between the first source electrode 52 and the first source-side plate 92; and a second source-side metal interconnect structure (72, 74, 82, 84), which includes at least one second conductive via structure (72, 82) and provides an electrical connection between the second source electrode 52 and the second source-side plate 92.

[0132] In one embodiment, the semiconductor structure may include bit lines 78 extending laterally along a horizontal direction different from the second horizontal direction hd1 (e.g., the first horizontal direction hd1), wherein each unit cell structure within the two-dimensional array of unit cell structures may include a bit line contact structure 76 that contacts the top surface of the drain electrode 56 and the bottom surface of a corresponding bit line 78.

[0133] In one embodiment, bit line 78 extends laterally along a first horizontal direction hd1; and each active layer 20 has a rectangular horizontal cross-sectional shape having a first side parallel to the first horizontal direction hd1 and a second side parallel to the second horizontal direction hd2 (as in the first exemplary structure).

[0134] In one embodiment, bit line 78 extends laterally along a first horizontal direction hd1; each active layer 20 has a rectangular horizontal cross-sectional shape having a first side that is not parallel to the first horizontal direction hd1 and not parallel to the second horizontal direction hd2; and the active layers in the two-dimensional array of the unit cell structure are arranged with a first periodicity along a third horizontal direction hd3 that is not parallel to the first horizontal direction hd1 and not parallel to the second horizontal direction hd2 and with a second periodicity along a fourth horizontal direction hd4 that is perpendicular to the third horizontal direction hd3 (as shown in the second exemplary structure).

[0135] In one embodiment, the active layer 20 comprises a semiconductor metal oxide material; the substrate 8 may include a single-crystal semiconductor material layer (such as semiconductor material layer 9); and a field-effect transistor 701 comprising a single-crystal semiconductor material layer as a corresponding portion of a corresponding channel region is located on the substrate 8 and below a two-dimensional array of unit cell structures.

[0136] According to another aspect of this disclosure, a semiconductor structure is provided, which may include: an active layer 20 comprising a semiconductor material and on a substrate 8; a gate dielectric 10 below the active layer 20; a first gate electrode 15A below a first portion of the gate dielectric 10; a second gate electrode 15B below a second portion of the gate dielectric 10 and laterally spaced from the first gate electrode 15A; a first source electrode 52 contacting a first end portion of the active layer 20; a second source electrode 52 contacting a second end portion of the active layer 20; and a drain electrode 56. The active layer 20 is in contact with the middle portion of the active layer 20; and at least four word lines 3 having regions that overlap with and are below the active layer 20 in a plan view, wherein a first word line (3A or 3B) selected from the at least four word lines 3 is electrically connected to a first gate electrode 15A, a second word line (3A or 3B) selected from the at least four word lines 3 is electrically connected to a second gate electrode 15B, and all word lines 3 selected from the at least four word lines 3 except for the first word line (3A or 3B) and the second word line (3A or 3B) are electrically isolated from the first gate electrode 15A and the second gate electrode 15B.

[0137] In one embodiment, the semiconductor structure may include: a drain contact via structure 76 that contacts the top surface of the drain electrode 56; and a bit line 78 that contacts the drain contact via structure 76 and extends laterally over the first source electrode 52 and the second source electrode 52.

[0138] In one embodiment, the semiconductor structure may include: a first capacitor structure 98, which includes a first source-side plate 92 electrically connected to the first source electrode 52; and a second capacitor structure 98, which includes a second source-side plate 92 electrically connected to the second source electrode 52.

[0139] In one embodiment, the semiconductor structure may include: a first source-side metal interconnect structure (72, 74, 82, 84) including at least one first conductive via structure (72, 82) and providing an electrical connection between a first source electrode 52 and a first source-side plate 92; a second source-side metal interconnect structure (72, 74, 82, 84) including at least one second conductive via structure (72, 82) and providing an electrical connection between a second source electrode 52 and a second source-side plate 92; and a field-effect transistor 701, which is below the at least four word lines 3 and includes a corresponding portion of the substrate 8 as a corresponding channel region.

[0140] In one embodiment, the semiconductor structure may include a sense amplifier SA, which includes a field-effect transistor 701 and has an input node electrically connected to a bit line 78. The field-effect transistor 701 may be located on a substrate 8 and may include a corresponding channel region containing a single-crystal semiconductor material. This channel region may be a portion of the single-crystal semiconductor material of a semiconductor material layer 9 within the substrate, or may include the same single-crystal material as the single-crystal semiconductor material of the semiconductor material layer 9 within the substrate 8 (as in embodiments using a gate-all-around field-effect transistor).

[0141] Typically, it is difficult to scale down semiconductor devices or embed additional devices in advanced nodes. For example, it is difficult to scale and embed DRAM devices in sub-20nm device nodes. Folded bitline architectures can effectively improve the signal-to-noise ratio, but when incorporated into standard logic processes, they result in area loss and sometimes wiring patterns that violate design rules.

[0142] The structures and methods of this disclosure use transistors (e.g., BEOL thin-film transistors (TFTs)) as access transistors in the DRAM capacitor structure and are compatible with CMOS-under-array (CuA) configurations (i.e., configurations that provide field-effect transistors using single-crystal channels within a memory array). Folded bitline architectures can be used in the DRAM arrays of this disclosure without area loss.

[0143] A compact common-drain configuration of a pair of thin-film transistors sharing a drain electrode can be used to provide an area efficiency layout comparable to SRAM arrays in advanced nodes. Alternatively, when using a folded bitline architecture that provides a high signal-to-noise ratio, jumper wiring and / or tilted asymmetric pair designs can be used to further reduce the cell device area.

[0144] The structures and methods disclosed herein provide all-BEOL 1T1C DRAM arrays compatible with under-array CMOS (CuA) configurations to minimize FEOL device area usage. The BEOL DRAM arrays of this disclosure can be vertically stacked to provide multi-level BEOL DRAM arrays.

[0145] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of this disclosure.

[0146] Example 1 is a semiconductor structure comprising a two-dimensional array of unit cell structures on a substrate, wherein each unit cell structure within the two-dimensional array of unit cell structures comprises: an active layer comprising a semiconductor material; a gate dielectric beneath the active layer; a first gate electrode beneath a first portion of the gate dielectric; a second gate electrode beneath a second portion of the gate dielectric; a first source electrode contacting a first end portion of the active layer; a second source electrode contacting a second end portion of the active layer; and a drain electrode contacting a middle portion of the active layer; wherein the semiconductor structure further comprises word lines beneath the active layer, the word lines being laterally spaced along a first horizontal direction and extending laterally along a second horizontal direction, wherein each unit cell structure within the two-dimensional array of unit cell structures comprises portions of a set of four corresponding word lines selected from the word lines, and the set of four corresponding word lines comprises two word lines electrically connected to the first gate electrode or the second gate electrode and two additional word lines electrically isolated from the first gate electrode and the second gate electrode.

[0147] Example 2 is the semiconductor structure described in Example 1, wherein each unit cell structure within the two-dimensional array of the unit cell structure includes: a first word line connection via structure that contacts the bottom surface of the first gate electrode and the top surface of one of the two word lines; and a second word line connection via structure that contacts the bottom surface of the second gate electrode and the top surface of the other of the two word lines.

[0148] Example 3 is the semiconductor structure described in Example 1, wherein: each of the first gate electrode and the second gate electrode has a width along the separation direction between the first source electrode and the second source electrode; and the width of each of the first gate electrode and the second gate electrode is twice as large as the width of each word line along the first horizontal direction.

[0149] Example 4 is the semiconductor structure described in Example 3, wherein the separation direction between the first source electrode and the second source electrode is the same as the first horizontal direction.

[0150] Example 5 is the semiconductor structure described in Example 3, wherein the separation direction between the first source electrode and the second source electrode is not parallel to the first horizontal direction and not parallel to the second horizontal direction.

[0151] Example 6 is the semiconductor structure described in Example 1, wherein each unit cell structure within the two-dimensional array of the unit cell structure includes: a first capacitor structure including a first source-side plate electrically connected to the first source electrode; and a second capacitor structure including a second source-side plate electrically connected to the second source electrode.

[0152] Example 7 is the semiconductor structure described in Example 6, wherein each unit cell structure within the two-dimensional array of the unit cell structure includes: a first source-side metal interconnect structure including at least one first conductive via structure and providing an electrical connection between the first source electrode and the first source-side plate; and a second source-side metal interconnect structure including at least one second conductive via structure and providing an electrical connection between the second source electrode and the second source-side plate.

[0153] Example 8 is the semiconductor structure described in Example 1, further comprising: bit lines extending laterally along a horizontal direction different from the second horizontal direction, wherein each unit cell structure within the two-dimensional array of the unit cell structures includes a bit line contact structure that contacts the top surface of the drain electrode and the bottom surface of a corresponding bit line among the bit lines.

[0154] Example 9 is the semiconductor structure described in Example 8, wherein: the bit lines extend laterally along the first horizontal direction; and each active layer in the active layers has a rectangular horizontal cross-sectional shape having a first side parallel to the first horizontal direction and a second side parallel to the second horizontal direction.

[0155] Example 10 is the semiconductor structure described in Example 8, wherein: the bit lines extend laterally along the first horizontal direction; each active layer in the active layers has a rectangular horizontal cross-sectional shape having a first side that is not parallel to the first horizontal direction and not parallel to the second horizontal direction; and the active layers in the two-dimensional array of the unit cell structure are arranged in a first periodicity along a third horizontal direction and in a second periodicity along a fourth horizontal direction, the third horizontal direction being neither parallel to the first horizontal direction nor parallel to the second horizontal direction, and the fourth horizontal direction being perpendicular to the third horizontal direction.

[0156] Example 11 is the semiconductor structure described in Example 1, wherein: the active layer comprises a semiconductor metal oxide material; the substrate comprises a single-crystal semiconductor material layer; and a field-effect transistor comprising the single-crystal semiconductor material layer as a corresponding portion of a corresponding channel region is located on the substrate and below a two-dimensional array of the unit cell structure.

[0157] Example 12 is a semiconductor structure comprising: an active layer comprising a semiconductor material and situated on a substrate; a gate dielectric beneath the active layer; a first gate electrode beneath a first portion of the gate dielectric; a second gate electrode beneath a second portion of the gate dielectric and laterally spaced from the first gate electrode; a first source electrode contacting a first end portion of the active layer; a second source electrode contacting a second end portion of the active layer; a drain electrode contacting a middle portion of the active layer; and at least four word lines having regions overlapping with and beneath the active layer in a plan view, wherein a first word line selected from the at least four word lines is electrically connected to the first gate electrode, a second word line selected from the at least four word lines is electrically connected to the second gate electrode, and all word lines selected from the at least four word lines, except for the first and second word lines, are electrically isolated from the first and second gate electrodes.

[0158] Example 13 is the semiconductor structure described in Example 12, further comprising: a drain contact via structure in contact with the top surface of the drain electrode; and a bit line in contact with the drain contact via structure and extending laterally over the first source electrode and the second source electrode.

[0159] Example 14 is the semiconductor structure described in Example 12, further comprising: a first capacitor structure including a first source-side plate electrically connected to the first source electrode; and a second capacitor structure including a second source-side plate electrically connected to the second source electrode.

[0160] Example 15 is the semiconductor structure described in Example 14, further comprising: a sense amplifier including a field-effect transistor and having an input node electrically connected to the bit line, wherein the field-effect transistor is located on the substrate and includes a corresponding channel region containing a single-crystal semiconductor material.

[0161] Example 16 is a method of forming a semiconductor structure, comprising: forming word lines on a substrate; forming word line connection via structures on the word lines; forming gate electrodes on the word line connection via structures; forming a two-dimensional array of stacked layers on the gate electrodes, each of the stacked layers including a gate dielectric and an active layer, wherein each active layer has a region overlapping and above: a set of two corresponding gate electrodes, a set of two corresponding word lines, and a set of two corresponding additional word lines, the set of two corresponding word lines being electrically connected to the set of two corresponding gate electrodes, and the set of two corresponding additional word lines being electrically isolated from the set of two corresponding gate electrodes; and forming a set of two source electrodes and a drain electrode on each active layer.

[0162] Example 17 is the method of Example 16, further comprising: forming a source contact via structure on the set of the two source electrodes, and forming a drain contact via structure on the drain electrode; and forming a bit line on the drain electrode, wherein each of the bit lines extends laterally along a horizontal direction perpendicular to the length direction of the word line.

[0163] Example 18 is the method of Example 17, further comprising: forming capacitor structures on a horizontal plane including the top surface of the bit line, wherein each capacitor structure in the capacitor structures includes a node electrically connected to a corresponding source electrode in the source electrodes.

[0164] Example 19 is the method of Example 16, further comprising: depositing a gate dielectric layer and a semiconductor material layer on the gate electrode; patterning the semiconductor material layer and the gate dielectric layer into a two-dimensional array of the stacked layers, wherein each of the active layers includes two sidewalls parallel to the length direction of the word line and two additional sidewalls perpendicular to the length direction of the word line.

[0165] Example 20 is the method of Example 16, further comprising: depositing a gate dielectric layer and a semiconductor material layer on the gate electrode; patterning the semiconductor material layer and the gate dielectric layer into a two-dimensional array of the layer stack, wherein each of the active layers includes two sidewalls that are not perpendicular to and not parallel to the length direction of the word line and two additional sidewalls that are perpendicular to the two sidewalls.

Claims

1. A semiconductor structure comprising a two-dimensional array of unit cell structures on a substrate, wherein, Each unit cell structure within the two-dimensional array of the unit cell structure includes: Active layer, including semiconductor materials; Gate dielectric, below the active layer; The first gate electrode is located below the first portion of the gate dielectric; The second gate electrode is located below the second portion of the gate dielectric; The first source electrode is in contact with the first end portion of the active layer; The second source electrode is in contact with the second end portion of the active layer; and The drain electrode is in contact with the middle portion of the active layer; The semiconductor structure further includes word lines beneath the active layer, the word lines being laterally spaced along a first horizontal direction and extending laterally along a second horizontal direction. Each unit cell structure within the two-dimensional array of the unit cell structure includes a portion of a set of four corresponding word lines selected from the word lines, and the set of four corresponding word lines includes a first word line electrically connected to the first gate electrode via a first word line connection via structure, a second word line electrically connected to the second gate electrode via a second word line connection via structure, and two additional word lines electrically isolated from the first gate electrode and the second gate electrode.

2. The semiconductor structure according to claim 1, wherein: The first word line connection via structure contacts the bottom surface of the first gate electrode and the top surface of the first word line; as well as The second word line connection via structure contacts the bottom surface of the second gate electrode and the top surface of the second word line.

3. The semiconductor structure according to claim 1, wherein: Each of the first gate electrode and the second gate electrode has a width along the separation direction between the first source electrode and the second source electrode; and The width of each of the first gate electrode and the second gate electrode is twice as large as the width of each word line along the first horizontal direction.

4. The semiconductor structure according to claim 3, wherein, The separation direction between the first source electrode and the second source electrode is the same as that of the first horizontal direction.

5. The semiconductor structure according to claim 3, wherein, The separation direction between the first source electrode and the second source electrode is not parallel to the first horizontal direction and not parallel to the second horizontal direction.

6. The semiconductor structure according to claim 1, wherein, Each unit cell structure within the two-dimensional array of the unit cell structure includes: A first capacitor structure includes a first source-side plate electrically connected to the first source electrode; and... The second capacitor structure includes a second source-side plate electrically connected to the second source electrode.

7. The semiconductor structure according to claim 6, wherein, Each unit cell structure within the two-dimensional array of the unit cell structure includes: A first source-side metal interconnect structure includes at least one first conductive via structure and provides an electrical connection between the first source electrode and the first source-side plate; and The second source-side metal interconnect structure includes at least one second conductive via structure and provides an electrical connection between the second source electrode and the second source-side plate.

8. The semiconductor structure according to claim 1, further comprising: Bit lines extending laterally along a horizontal direction different from the second horizontal direction, wherein each unit cell structure within the two-dimensional array of the unit cell structures includes a bit line contact structure that contacts the top surface of the drain electrode and the bottom surface of a corresponding bit line.

9. The semiconductor structure according to claim 8, wherein: The bit line extends laterally along the first horizontal direction; and Each of the active layers has a rectangular horizontal cross-sectional shape, the rectangular horizontal cross-sectional shape having a first side parallel to the first horizontal direction and a second side parallel to the second horizontal direction.

10. The semiconductor structure according to claim 8, wherein: The bit line extends laterally along the first horizontal direction; Each of the active layers has a rectangular horizontal cross-sectional shape, the rectangular horizontal cross-sectional shape having a first side that is not parallel to the first horizontal direction and not parallel to the second horizontal direction; and The active layer within the two-dimensional array of the unit cell structure is arranged with a first periodicity along a third horizontal direction and a second periodicity along a fourth horizontal direction, wherein the third horizontal direction is not parallel to the first horizontal direction and not parallel to the second horizontal direction, and the fourth horizontal direction is perpendicular to the third horizontal direction.

11. The semiconductor structure according to claim 1, wherein: The active layer comprises a semiconductor metal oxide material; The substrate includes a single-crystal semiconductor material layer; and Field-effect transistors, comprising portions of the corresponding channel regions of the single-crystal semiconductor material layer, are located on the substrate and below the two-dimensional array of the unit cell structure.

12. A semiconductor structure, comprising: An active layer, comprising semiconductor material and situated on a substrate; Gate dielectric, below the active layer; The first gate electrode is located below the first portion of the gate dielectric; The second gate electrode is located below the second portion of the gate dielectric and is laterally spaced from the first gate electrode. The first source electrode is in contact with the first end portion of the active layer; The second source electrode is in contact with the second end portion of the active layer; The drain electrode is in contact with the middle portion of the active layer; as well as At least four word lines, the at least four word lines having regions overlapping with and below the active layer in a plan view, wherein a first word line selected from the at least four word lines is electrically connected to the first gate electrode through a first word line connection via structure, a second word line selected from the at least four word lines is electrically connected to the second gate electrode through a second word line connection via structure, and all word lines selected from the at least four word lines except for the first word line and the second word line are electrically isolated from the first gate electrode and the second gate electrode.

13. The semiconductor structure according to claim 12, further comprising: The drain contact via structure contacts the top surface of the drain electrode; as well as Bit lines are in contact with the drain contact via structure and extend laterally over the first source electrode and the second source electrode.

14. The semiconductor structure according to claim 12, further comprising: The first capacitor structure includes a first source-side plate electrically connected to the first source electrode. as well as The second capacitor structure includes a second source-side plate electrically connected to the second source electrode.

15. The semiconductor structure according to claim 13, further comprising: A sense amplifier comprising a field-effect transistor and having an input node electrically connected to the bit line, wherein the field-effect transistor is located on the substrate and includes a corresponding channel region containing a single-crystal semiconductor material.

16. A method for forming a semiconductor structure, comprising: Word lines are formed on the substrate; A character line connection via structure is formed on the character line; A gate electrode is formed on the word line connection via structure; A two-dimensional array of stacked layers is formed on the gate electrode, each of the stacked layers including a gate dielectric and an active layer, wherein each active layer has a region overlapping and above the following: a set of two corresponding gate electrodes, a set of two corresponding word lines, and a set of two corresponding additional word lines, wherein a first word line in the set of two corresponding word lines is electrically connected to a first gate electrode in the set of two corresponding gate electrodes through a first word line connection via structure in the word line connection via structure, a second word line in the set of two corresponding word lines is electrically connected to a second gate electrode in the set of two corresponding gate electrodes through a second word line connection via structure in the word line connection via structure, and the set of two corresponding additional word lines is electrically isolated from the set of two corresponding gate electrodes; as well as Two sets of source electrodes and a drain electrode are formed on each of the active layers.

17. The method of claim 16, further comprising: A source contact via structure is formed on the assembly of the two source electrodes, and a drain contact via structure is formed on the drain electrode; as well as Bit lines are formed on the drain electrode, wherein each bit line extends laterally along a horizontal direction perpendicular to the length direction of the word line.

18. The method of claim 17, further comprising: A capacitor structure is formed on a horizontal plane including the top surface of the bit line, wherein each capacitor structure includes a node electrically connected to a corresponding source electrode in the source electrode.

19. The method of claim 16, further comprising: A gate dielectric layer and a semiconductor material layer are deposited on the gate electrode; The semiconductor material layer and the gate dielectric layer are patterned into a two-dimensional array of the stacked layers. Each of the active layers includes two sidewalls parallel to the length direction of the word line and two additional sidewalls perpendicular to the length direction of the word line.

20. The method of claim 16, further comprising: A gate dielectric layer and a semiconductor material layer are deposited on the gate electrode; The semiconductor material layer and the gate dielectric layer are patterned into a two-dimensional array of the stacked layers. Each of the active layers includes two sidewalls that are neither perpendicular to nor parallel to the length direction of the word line, and two additional sidewalls that are perpendicular to the two sidewalls.

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