Variable resistance memory device

Abstract

A variable resistance memory device includes a substrate, memory cell structures on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction being parallel to a top surface of the substrate and crossing each other, and a dummy cell structure surrounding each memory cell structure when viewed in a plan view, the dummy cell structure being a single body structure continuously extending between all of the memory cell structures, wherein each memory cell structure includes a first conductive line, a second conductive line on and intersecting the first conductive line, and a memory cell between the first conductive line and the second conductive line, wherein the dummy cell structure includes a first dummy conductive line, a second dummy conductive line on and intersecting the first dummy conductive line, and a dummy memory cell between the first dummy conductive line and the second dummy conductive line.

Description

Technical Field

[0001] The implementation methods relate to semiconductor devices, and more specifically, to variable resistance storage devices. Background Technology

[0002] Semiconductor memory devices can be categorized into volatile memory devices and non-volatile memory devices. Volatile memory devices may lose their stored data when their power supply is interrupted. For example, volatile memory devices can include dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices. Conversely, non-volatile memory devices can retain their stored data even when their power supply is interrupted. For example, non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory devices.

[0003] Furthermore, next-generation semiconductor memory devices, such as magnetic random access memory (MRAM) devices and phase-change random access memory (PRAM) devices, have been developed to provide high-performance and low-power semiconductor memory devices. The materials of these next-generation semiconductor memory devices can have resistance values ​​that vary depending on the current or voltage applied to them, and can retain their resistance values ​​even when the current or voltage is interrupted. Summary of the Invention

[0004] In one aspect, a variable resistance memory device may include: a substrate; a plurality of memory cell structures spaced apart from each other in a first direction and a second direction, the first and second directions being parallel to the top surface of the substrate and intersecting each other; and a dummy cell structure extending integrally around each of the plurality of memory cell structures in a plan view and between the plurality of memory cell structures. Each of the plurality of memory cell structures may include a first conductive line, a second conductive line disposed on and intersecting the first conductive line, and a memory cell between the first conductive line and the second conductive line. The dummy cell structure may include a first dummy conductive line, a second dummy conductive line disposed on and intersecting the first dummy conductive line, and a dummy memory cell between the first dummy conductive line and the second dummy conductive line.

[0005] In another aspect, a variable resistive storage device may include: a substrate; a plurality of memory cell structures spaced apart from each other in a first direction and a second direction, the first and second directions being parallel to the top surface of the substrate and intersecting each other; and a single dummy cell structure disposed between the plurality of memory cell structures. The single dummy cell structure may extend between the memory cell structures spaced apart from each other in the first direction and between the memory cell structures spaced apart from each other in the second direction. Each of the plurality of memory cell structures may include a first conductive line, a second conductive line disposed on and intersecting the first conductive line, and a memory cell between the first and second conductive lines. The single dummy cell structure may include a first dummy conductive line, a second dummy conductive line disposed on and intersecting the first dummy conductive line, and a dummy memory cell between the first and second dummy conductive lines. Attached Figure Description

[0006] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 This is a conceptual diagram of a variable resistance storage device based on some implementation methods.

[0008] Figure 2 yes Figure 1 The circuit diagram of the memory cell array.

[0009] Figure 3 This is a plan view of a variable resistance storage device according to some implementation methods.

[0010] Figure 4 yes Figure 3 An enlarged view of a portion of a variable resistance storage device.

[0011] Figure 5A and Figure 5B They are respectively along Figure 3 Sectional views of lines I-I' and II-II'.

[0012] Figure 6 This is a cross-sectional view of a storage unit according to some implementation methods.

[0013] Figures 7A to 7C This is a cross-sectional view of a virtual storage unit according to some implementation methods.

[0014] Figure 8A and Figure 8B They correspond to respectively Figure 3 The cross-sectional views along lines I-I' and II-II' are shown to illustrate a variable resistance storage device according to some embodiments.

[0015] Figure 9A and Figure 9B This is a plan view of a method for manufacturing a variable resistance storage device according to some embodiments.

[0016] Figure 10 This is a plan view of a variable resistance storage device according to some implementation methods.

[0017] Figure 11 yes Figure 10 An enlarged view of a portion of a variable resistance storage device.

[0018] Figure 12A and Figure 12B They are respectively along Figure 10 Sectional views of lines I-I' and II-II'. Detailed Implementation

[0019] Figure 1 This is a conceptual diagram of a variable resistance storage device based on some implementation methods.

[0020] Reference Figure 1 The variable resistance storage device 1000 may include a plurality of memory cell arrays (MCAs) stacked sequentially on a substrate 100. Each of the plurality of memory cell arrays (MCAs) may include a plurality of memory cells arranged two-dimensionally in a direction parallel to the top surface 100U of the substrate 100. The variable resistance storage device 1000 may also include a plurality of conductive layers, and the conductive layers and the memory cell arrays (MCAs) may be alternately stacked on the substrate 100. Each of the plurality of memory cell arrays (MCAs) may be disposed between mutually perpendicular conductive layers. Each conductive layer may include a plurality of conductive lines for write, read, and erase operations of the plurality of memory cells. Figure 1 The diagram shows a four-cell array (MCA). However, the implementation is not limited to this.

[0021] Figure 2 yes Figure 1 The circuit diagram of the memory cell array MCA.

[0022] Reference Figure 2 , Figure 1 The storage cell array (MCA) may include a first storage cell array (MCA1), a second storage cell array (MCA2), a third storage cell array (MCA3), and a fourth storage cell array (MCA4).

[0023] A first memory cell array MCA1 may be disposed between a first conductive line CL1 and a second conductive line CL2, wherein the second conductive line CL2 may intersect the first conductive line CL1. The first memory cell array MC1 may include first memory cells MC1 respectively disposed at the intersection points of the first conductive line CL1 and the second conductive line CL2. Each first memory cell MC1 may include a first variable resistor pattern and a first switch pattern connected in series between a corresponding line in the first conductive line CL1 and a corresponding line in the second conductive line CL2.

[0024] The second memory cell array MCA2 can be disposed between the second conductive line CL2 and the third conductive line CL3, and the third conductive line CL3 can intersect the second conductive line CL2. The second memory cell array MCA2 can include second memory cells MC2 respectively disposed at the intersection points of the second conductive line CL2 and the third conductive line CL3. Each second memory cell MC2 can include a second variable resistor pattern and a second switch pattern connected in series between a corresponding line in the second conductive line CL2 and a corresponding line in the third conductive line CL3. In some embodiments, the first memory cell array MCA1 and the second memory cell array MCA2 can share the second conductive line CL2.

[0025] The third memory cell array MCA3 can be disposed between the third conductive line CL3 and the fourth conductive line CL4, and the fourth conductive line CL4 can intersect the third conductive line CL3. The third memory cell array MCA3 can include third memory cells MC3 respectively disposed at the intersection points of the third conductive line CL3 and the fourth conductive line CL4. Each third memory cell MC3 can include a third variable resistor pattern and a third switch pattern connected in series between a corresponding line in the third conductive line CL3 and a corresponding line in the fourth conductive line CL4. In some embodiments, the second memory cell array MCA2 and the third memory cell array MCA3 can share the third conductive line CL3.

[0026] The fourth memory cell array MCA4 can be disposed between the fourth conductive line CL4 and the fifth conductive line CL5, and the fifth conductive line CL5 can intersect the fourth conductive line CL4. The fourth memory cell array MCA4 can include fourth memory cells MC4 respectively disposed at the intersection points of the fourth conductive line CL4 and the fifth conductive line CL5. Each fourth memory cell MC4 can include a fourth variable resistor pattern and a fourth switch pattern connected in series between a corresponding line in the fourth conductive line CL4 and a corresponding line in the fifth conductive line CL5. In some embodiments, the third memory cell array MCA3 and the fourth memory cell array MCA4 can share the fourth conductive line CL4.

[0027] The first to fourth memory cell arrays MCA1, MCA2, MCA3 and MCA4 are as follows: Figure 2 As shown. However, the implementation is not limited to this. Additional memory cell arrays and additional conductive lines may be stacked on the fourth memory cell array MCA4. The additional memory cell arrays may be substantially the same as the first to fourth memory cell arrays MCA1, MCA2, MCA3 and MCA4, and the additional conductive lines may be substantially the same as the first to fifth conductive lines CL1, CL2, CL3, CL4 and CL5.

[0028] Figure 3 This is a plan view of a variable resistance storage device according to some implementation methods. Figure 4 yes Figure 3 An enlarged view of a portion of a variable resistance storage device. Figure 5A and Figure 5B They are respectively along Figure 3 The cross-sectional views are taken along lines I-I' and II-II'. In this embodiment, for ease of explanation, a memory cell array (MCA) will be primarily described.

[0029] Reference Figure 3 , Figure 4 , Figure 5A and Figure 5B A substrate 100 may be provided, comprising a plurality of cell regions CR and a core region COR between the plurality of cell regions CR. The substrate 100 may be a semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The plurality of cell regions CR may be arranged in a first direction D1 and a second direction D2 parallel to the top surface 100U of the substrate 100, the first direction D1 and the second direction D2 may intersect each other. The core region COR may extend between the plurality of cell regions CR in the first direction D1 and the second direction D2, and may surround each of the plurality of cell regions CR when viewed in a plan view. For example, the core region COR may be a single grid-like structure extending continuously between all the cell regions CR in the first direction D1 and the second direction D2 to separate every two adjacent cell regions CR from each other.

[0030] Multiple memory cell structures (MCS) can be disposed on the multiple cell regions CR. The multiple memory cell structures (MCS) can be spaced apart from each other in a first direction D1 and a second direction D2. Each of the multiple memory cell structures (MCS) may include a first conductive line CL1, a second conductive line CL2 disposed on and intersecting the first conductive line CL1, and a memory cell MC between the first conductive line CL1 and the second conductive line CL2. The first conductive line CL1 may extend in the first direction D1 (e.g., longitudinally) and may be spaced apart from each other in the second direction D2. The second conductive line CL2 may extend in the second direction D2 (e.g., longitudinally) and may be spaced apart from each other in the first direction D1. The memory cells MC can be disposed at the intersection of the first conductive line CL1 and the second conductive line CL2. Each memory cell MC may include a switch pattern SW and a variable resistor pattern VR stacked on a third direction D3 perpendicular to the top surface 100U of the substrate 100. In some embodiments, the switch pattern SW may be disposed below the variable resistor pattern VR. However, the embodiments are not limited to this; for example, the variable resistor pattern VR may be disposed below the switch pattern SW.

[0031] According to some embodiments, a first conductive line CL1 may extend from each of the plurality of unit regions CR to the core region COR in a first direction D1. The ends CL1E of the first conductive line CL1 may be aligned with each other in the core region COR in a second direction D2. A second conductive line CL2 may extend from each of the plurality of unit regions CR to the core region COR in a second direction D2. The ends CL2E of the second conductive line CL2 may be aligned with each other in the core region COR in the first direction D1.

[0032] The plurality of memory cell structures (MCS) may include a pair of memory cell structures (MCS) adjacent to each other in the second direction D2. The pair of memory cell structures (MCS) may be respectively disposed on a pair of cell regions CR that are adjacent to each other in the second direction D2 among the plurality of cell regions CR. In some embodiments, the pair of memory cell structures (MCS) may share a second conductive line CL2. In this case, the second conductive line CL2 may (e.g., continuously) extend from one of the pair of cell regions CR to a core region COR provided between the pair of cell regions CR, and may extend (e.g., continuously) across the core region COR provided between the pair of cell regions CR to the other of the pair of cell regions CR.

[0033] like Figure 3As shown, a dummy cell structure (DCS) can be disposed on the core region (COR). The DCS can surround each of the plurality of memory cell structures (MCS) in a plan view and can extend between the plurality of memory cell structures (MCS) to form a (e.g., continuous) body. The DCS can have a single body structure disposed between the plurality of memory cell structures (MCS), for example, a single and continuous structure extending continuously along the core region (COR) adjacent to each of the plurality of cell structures (MCS). A single dummy cell structure (DCS) can extend between a first pair of memory cell structures (MCS) spaced apart from each other along a first direction D1 and between a second pair of memory cell structures (MCS) spaced apart from each other along the first direction D1, and can extend between a third pair of memory cell structures (MCS) spaced apart from each other along a second direction D2 and between a fourth pair of memory cell structures (MCS) spaced apart from each other along the second direction D2. In other words, as... Figure 3 As shown, the same single dummy unit structure DCS ( Figure 3 The gray area in the diagram can extend (e.g., continuously) between a first pair of memory cell structures (MCS) spaced apart from each other along a first direction D1 and between a second pair of memory cell structures (MCS) spaced apart from each other along a first direction D1, and can extend between a third pair of memory cell structures (MCS) spaced apart from each other along a second direction D2 and between a fourth pair of memory cell structures (MCS) spaced apart from each other along a second direction D2. When viewed in a plan view, the single dummy cell structure (DCS) can surround each of the plurality of memory cell structures (MCS).

[0034] The dummy cell structure DCS may include a first dummy conductive line DCL1, a second dummy conductive line DCL2 disposed on and intersecting the first dummy conductive line DCL1, and a dummy storage cell DMC between the first dummy conductive line DCL1 and the second dummy conductive line DCL2. Note that the term "dummy" refers to a configuration within the variable resistive storage device 1000 that has the same or similar structure and shape as other components but does not actually function (e.g., does not function electrically). Therefore, electrical signals are not applied to the "dummy" component, or the "dummy" component does not perform a specific electrical function.

[0035] The first dummy conductive lines DCL1 may extend in a first direction D1 (e.g., longitudinally) and may be spaced apart from each other in a second direction D2. Each of the plurality of memory cell structures MCS (in the cell region CR) may be disposed between a pair of first dummy conductive lines DCL1 spaced apart from each other in the second direction D2. The first dummy conductive lines DCL1 may be disposed on the core region COR. Some of the first dummy conductive lines DCL1 may overlap with the edges of each of the plurality of cell regions CR and may extend into the core region COR. In some embodiments, the end DCL1E of the first dummy conductive line DCL1 adjacent to the first conductive line CL1 may be aligned with the end CL1E of the first conductive line CL1 in the second direction D2 on the core region COR.

[0036] The first conductive line CL1 and the first dummy conductive line DCL1 may have widths in the second direction D2. For example, the lengths of the first conductive line CL1 and the first dummy conductive line DCL1 in the first direction D1 may be longer than their corresponding widths in the second direction D2. In some embodiments, the first width W1 of each first conductive line CL1 may be equal to the second width W2 of each first dummy conductive line DCL1. The first dummy conductive line DCL1 may comprise the same material as the first conductive line CL1. For example, the first dummy conductive line DCL1 and the first conductive line CL1 may comprise at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), and a metal semiconductor compound (e.g., a metal silicide). The first dummy conductive line DCL1 may be electrically levitated. For example, the first conductive line CL1 and the first dummy conductive line DCL1 may comprise the same material, have the same dimensions, and be spaced at equal intervals, except that the first dummy conductive line DCL1 is electrically levitated.

[0037] The second dummy conductive lines DCL2 may extend in a second direction D2 (e.g., longitudinally) and may be spaced apart from each other in a first direction D1. Each of the plurality of memory cell structures MCS (in the core region CR) may be disposed between a pair of second dummy conductive lines DCL2 spaced apart from each other in the first direction D1. The second dummy conductive lines DCL2 may be disposed on the core region COR. Some of the second dummy conductive lines DCL2 may overlap with the edges of each of the plurality of cell regions CR and may extend into the core region COR. In some embodiments, the end DCL2E of the second dummy conductive line DCL2 adjacent to the second conductive line CL2 may be aligned with the end CL2E of the second conductive line CL2 in the first direction D1 on the core region COR. For example, as Figure 3 and Figure 4 As shown, some of the second dummy conductive lines DCL2 can extend continuously along multiple unit regions CR arranged in a row along the second direction D2.

[0038] The second conductive line CL2 and the second dummy conductive line DCL2 may have widths in the first direction D1. For example, the lengths of the second conductive line CL2 and the second dummy conductive line DCL2 in the second direction D2 may be longer than their corresponding widths in the first direction D1. In some embodiments, the third width W3 of each second conductive line CL2 may be equal to the fourth width W4 of each second dummy conductive line DCL2. The second dummy conductive line DCL2 may comprise the same material as the second conductive line CL2. For example, the second dummy conductive line DCL2 and the second conductive line CL2 may comprise at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), and a metal semiconductor compound (e.g., a metal silicide). The second dummy conductive line DCL2 may be electrically levitated. For example, the second conductive line CL2 and the second dummy conductive line DCL2 may comprise the same material, have the same dimensions, and be spaced apart at equal intervals, except that the second dummy conductive line DCL2 is electrically levitated.

[0039] In some embodiments, the second dummy conductor DCL2 may intersect with the first dummy conductor DCL1 and the first conductor CL1. The dummy memory cell DMC may be located at the intersections of the second dummy conductor DCL2 and the first dummy conductor DCL1, the intersection of the second dummy conductor DCL2 and the first conductor CL1, and the intersection of the second conductor CL2 and the first dummy conductor DCL1. The dummy memory cell DMC may have the same components as the memory cell MC. Each dummy memory cell DMC may include a switch pattern SW and a variable resistor pattern VR stacked on a third-direction D3.

[0040] The dummy memory cell (DMC) can be arranged around each of the plurality of memory cell structures (MCS) in a plan view, and can be arranged two-dimensionally on the core region (COR) between the plurality of memory cell structures (MCS). For example, as Figure 3 and Figure 4 As shown, the dummy storage cell (DMC) can be arranged around each cell region (CR), that is, around the periphery of each storage cell structure (MCS). Figure 3 and Figure 4 (Represented by dashed lines) around, as shown in the plan view. For example, as... Figure 3 and Figure 4As shown, dummy memory cells (DMCs) can be arranged two-dimensionally on the core region COR between adjacent memory cell structures in a memory cell structure MCS, for example, between adjacent dashed structures in the dashed structure of the cell region CR. The dummy memory cells (DMCs) can be connected to a first dummy conductive line (DCL1) and a second dummy conductive line (DCL2). The dummy memory cells (DMCs), the first dummy conductive line (DCL1), and the second dummy conductive line (DCL2) can be connected to each other to form a single dummy cell structure (DCS).

[0041] like Figure 3 As shown, the core region (COR) may include a first contact region R1 and a second contact region R2. For example, each first contact region R1 may be provided between memory cell structures (MCS) spaced apart from each other along a second direction D2, and each second contact region R2 may be provided between memory cell structures (MCS) spaced apart from each other along a first direction D1. Figure 4 As shown, conductive contact CTs can be disposed on the first contact area R1 and the second contact area R2, and can be electrically connected to transistors on the substrate 100. The conductive contact CTs can include conductive materials. In some embodiments, when a pair of memory cell structures MCSs adjacent to each other in the second direction D2 share a second conductive line CL2, the second conductive line CL2 can be respectively connected to the conductive contact CTs on the first contact area R1 between the pair of memory cell structures MCSs.

[0042] In addition to the first contact region R1 and the second contact region R2, the dummy unit structure DCS can be disposed on the core region COR. The dummy unit structure DCS can extend along the core region COR, excluding the first contact region R1 and the second contact region R2, to form a main body. For example, as... Figure 4 As shown, apart from the first contact area R1 and the second contact area R2, the dummy unit structure DCS can be on and overlap with the core area COR (when viewed in a plan view). For example, in a plan view, the dummy unit structure DCS can have a non-overlapping relationship with the first contact area R1 and the second contact area R2.

[0043] like Figure 5A and Figure 5BAs shown, an interlayer insulating layer 150 can be disposed on the substrate 100 and can cover the plurality of memory cell structures (MCS) and dummy cell structures (DCS). For example, the interlayer insulating layer 150 can cover the sidewalls of the first conductive line CL1, the first dummy conductive line DCL1, the sidewalls of the memory cell MC, the sidewalls of the dummy memory cell DMC, the sidewalls of the second conductive line CL2, and the sidewalls of the second dummy conductive line DCL2. Conductive contacts (CTs) can penetrate the interlayer insulating layer 150 to be electrically connected to the transistors on the substrate 100. For example, the interlayer insulating layer 150 can include at least one of silicon oxide, silicon nitride, and silicon oxide nitride.

[0044] For example, if a memory cell structure (MCS) is to be formed without a dummy cell structure (DCS), the outermost memory cell (MC) of each of the plurality of memory cell structures (MCS) will become vulnerable during the manufacturing process (e.g., step difference between the cell region CR and the core region COR after planarization, etch load effect between the cell region CR and the core region COR during the etching process, etc.) due to the difference in pattern density between each of the plurality of cell regions CR and the core region COR. Therefore, this may lead to operational failure of the outermost memory cell (MC).

[0045] However, according to an implementation, the dummy cell structure DCS can be disposed on the core region COR to surround each of the plurality of memory cell structures MCS, and can extend along the core region COR between the plurality of memory cell structures MCS to form a body. The dummy cell structure DCS can have the same stacking structure as the plurality of memory cell structures MCS. In other words, the dummy cell structure DCS may include a first dummy conductive line DCL1, a second dummy conductive line DCL2 intersecting the first dummy conductive line DCL1, and dummy memory cells DMC between the first dummy conductive line DCL1 and the second dummy conductive line DCL2. In this case, the difference in pattern density between each cell region CR and the core region COR can be minimized, thus suppressing or preventing defects in the outermost memory cell MC of each memory cell structure MCS during the manufacturing process. Furthermore, since the dummy cell structure DCS is formed to have the same stacking structure as the plurality of memory cell structures MCS, the plurality of memory cell structures MCS and the dummy cell structure DCS can be easily formed. As a result, a variable resistance memory device that minimizes defects in memory cells and is easy to manufacture can be realized or provided.

[0046] Figure 6 This is a cross-sectional view showing a storage unit according to some embodiments. Figures 7A to 7C This is a cross-sectional view showing a virtual storage unit according to some embodiments.

[0047] Reference Figure 6 Each memory cell MC can be disposed between a corresponding line in the first conductive line CL1 and a corresponding line in the second conductive line CL2. Each memory cell MC may include a variable resistor pattern VR and a switch pattern SW connected in series between the corresponding first conductive line CL1 and the corresponding second conductive line CL2. Each memory cell MC may also include a first electrode pattern EL1 between the corresponding first conductive line CL1 and the switch pattern SW, a second electrode pattern EL2 between the switch pattern SW and the variable resistor pattern VR, a third electrode pattern EL3 between the variable resistor pattern VR and the corresponding second conductive line CL2, a first metallic pattern MB1 between the variable resistor pattern VR and the second electrode pattern EL2, and a second metallic pattern MB2 between the variable resistor pattern VR and the third electrode pattern EL3.

[0048] The first to third electrode patterns EL1, EL2, and EL3 may include conductive materials. For example, the first to third electrode patterns EL1, EL2, and EL3 may be carbon electrodes comprising carbon. In some embodiments, the first to third electrode patterns EL1, EL2, and EL3 may include metals and / or metal nitrides. The first metallic pattern MB1 and the second metallic pattern MB2 may cover the bottom and top surfaces (e.g., the entire bottom and top surfaces) of the variable resistance pattern VR to prevent material diffusion of the variable resistance pattern VR. Furthermore, the first metallic pattern MB1 may be provided between the variable resistance pattern VR and the switch pattern SW to improve contact resistance. For example, the first metallic pattern MB1 and the second metallic pattern MB2 may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

[0049] The variable resistance pattern VR can include materials capable of storing data using changes in their resistance. In some embodiments, the variable resistance pattern VR can include materials whose phase can reversibly change between crystalline and amorphous states by temperature. For example, the variable resistance pattern VR can include compounds comprising at least one of Te and Se (i.e., chalcogens) and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, and Ga.

[0050] For some examples, the variable resistance pattern VR may include at least one of GeTe, GeSe, GeS, SbSe, SbTe, SbS, SbSe, SnSb, InSe, InSb, AsTe, AlTe, GaSb, AlSb, BiSb, ScSb, YSb, CeSb, DySb, and NdSb. For some examples, the variable resistance pattern VR may include at least one of GeSbSe, AlSbTe, AlSbSe, SiSbSe, SiSbTe, GeSeTe, InGeTe, GeSbTe, GeAsTe, SnSeTe, GeGaSe, BiSbSe, GaSeTe, InGeSb, GaSbSe, GaSbTe, InSbSe, InSbTe, SnSbSe, SnSbTe, ScSbTe, ScSbSe, ScSbS, YSbTe, YSbSe, YSbS, CeSbTe, CeSbSe, CeSbS, DySbTe, DySbSe, DySbS, NdSbTe, NdSbSe, and NdSbS. For some examples, the variable resistance pattern VR may include GeSbTeS, BiSbTeSe, AgInSbTe, GeSbSeTe, GeSnSbTe, SiGeSbTe, SiGeSbSe, SiGeSeTe, BiGeSeTe, BiSiGeSe, BiSiGeTe, GeSbTeBi, GeSbSeBi, GeSbSeIn, GeSbSeGa, GeSbSeAl, GeSbSeTl, GeSbSeSn, GeSbSeZn At least one of GeSbTeIn, GeSbTeGa, GeSbTeAl, GeSbTeTl, GeSbTeSn, GeSbTeZn, ScGeSbTe, ScGeSbSe, ScGeSbS, YGeSbTe, YGeSbSe, YGeSbS, CeGeSbTe, CeGeSbSe, CeGeSbS, DyGeSbTe, DyGeSbSe, DyGeSbS, NdGeSbTe, NdGeSbSe and NdGeSbS.For some examples, the variable resistance pattern VR may include InSbTeAsSe, GeScSbSeTe, GeSbSeTeS, GeScSbSeS, GeScSbTeS, GeScSeTeS, GeScSbSeP, GeScSbTeP, GeSbSeTeP, GeScSbSeIn, GeScSbSeGa, GeScSbSeAl, GeScSb SeTl, GeScSbSeZn, GeScSbSeSn, GeScSbTeIn, GeScSbTeGa, GeSbAsTeAl, GeScSbTeTl, GeSc SbTeZn, GeScSbTeSn, GeSbSeTeIn, GeSbSeTeGa, GeSbSeTeAl, GeSbSeTeTl, GeSbSeTeZn, Ge SbSeTeSn, GeSbSeSIn, GeSbSeSGa, GeSbSeSAl, GeSbSeSTl, GeSbSeSZn, GeSbSeSSn, GeSbTe SIn, GeSbTeSGa, GeSbTeSAl, GeSbTeSTl, GeSbTeSZn, GeSbTeSSn, GeSbSeInGa, GeSbSeInAl , GeSbSeInTl, GeSbSeInZn, GeSbSeInSn, GeSbSeGaAl, GeSbSeGaTl, GeSbSeGaZn, GeSbSeGa At least one of Sn, GeSbSeAlTl, GeSbSeAlZn, GeSbSeAlSn, GeSbSeTlZn, GeSbSeTlSn and GeSbSeZnSn. The variable resistance pattern VR may also include at least one of B, C, N, O, P, Cd, W, Ti, Hf, and Zr.

[0051] In some embodiments, the variable resistance pattern VR can have a single-layer structure or a multilayer structure comprising multiple stacked layers. In some embodiments, the variable resistance pattern VR can have a superlattice structure comprising layers of Ge and layers excluding Ge that are repeatedly and alternately stacked. For example, the variable resistance pattern VR can have a structure in which GeTe layers and SbTe layers are repeatedly and alternately stacked.

[0052] In some embodiments, the variable resistance pattern VR may include at least one of a perovskite compound and a conductive metal oxide. For example, the variable resistance pattern VR may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr,Ca)MnO3 (PCMO), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, and barium strontium zirconium oxide. When the variable resistance pattern VR includes a transition metal oxide, the dielectric constant of the variable resistance pattern VR may be greater than that of silicon oxide.

[0053] In some embodiments, the variable resistance pattern VR can have a two-layer structure of a conductive metal oxide layer and a tunnel insulating layer, or a three-layer structure of a first conductive metal oxide layer, a tunnel insulating layer, and a second conductive metal oxide layer. In this case, the tunnel insulating layer can include, for example, aluminum oxide, hafnium oxide, or silicon oxide.

[0054] In some embodiments, the switch pattern SW may include a silicon diode or oxide diode with rectification characteristics. In this case, the switch pattern SW may include silicon diodes of P-type silicon and N-type silicon, or it may include P-type NiO. x and N-type TiO x Oxide diodes or P-type CuO x and N-type TiO x The oxide diode. In some embodiments, the switch pattern SW may include oxide (e.g., ZnO). x MgO x AlO x (etc.), which has high resistance below a certain voltage to interrupt current, and low resistance at a certain voltage or higher to allow current to flow.

[0055] In some embodiments, the switch pattern SW can be a bidirectional threshold switch (OTS) element with bidirectional characteristics. In this case, the switch pattern SW can include a substantially amorphous chalcogenide material. Here, the term "substantially amorphous" can include amorphous, but can also include cases where grain boundaries or crystalline portions are locally present in a part of a component. In this case, the switch pattern SW can include a compound comprising chalcogen elements (e.g., Te and / or Se) and at least one of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P.

[0056] For some examples, the switch pattern SW may include at least one of GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, and SnTe. For some examples, the switch pattern SW may include at least one of GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, and SnAsTe. For some examples, the switching pattern SW may include GeSiAsTe, GeSiAsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi , at least one of GeAsSeBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn and GeAsTeZn.For some examples, switch patterns SW can include GeSiAsseTe, GeSisSeTeS, GeSiAsseS, GeSiAsTeS, GeSiSeTeS, GeSiAsseP, GeSiAsTeP, GeAsseTeP, GeSiAsseIn, GeSiAsSeGa, GeSiAsseAl, GeSiAsseTl, GeSi AsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl, GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTe At least one of Sn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSeAlSn, GeAsSeTlZn, GeAsSeTlSn, and GeAsSeZnSn.For some examples, the switching pattern SW may include GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeT eZn, GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, G eSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeT ePIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl The switch pattern SW may include at least one of the following: GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl, GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, and GeAsSeSAlSn. The switch pattern SW can have a single-layer structure or a multi-layer structure including multiple stacked layers.

[0057] Each memory cell MC may further include a spacer structure SS. The spacer structure SS may cover the sidewalls of the first metallic pattern MB1, the second metallic pattern MB2, the variable resistance pattern VR, and the third electrode pattern EL3. The bottom surface of the spacer structure SS may contact the top surface of the second electrode pattern EL2. The spacer structure SS may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxide nitride layer. For example, the spacer structure SS may include a first spacer SS1 and a second spacer SS2, which comprise different materials. The first spacer SS1 may fill the recessed portion of the variable resistance pattern VR. The second spacer SS2 may cover the sidewall of the first spacer SS1.

[0058] Reference Figures 7A to 7C Each dummy memory cell (DMC) can be disposed between a corresponding line in the first dummy conductive line DCL1 and a corresponding line in the second conductive line CL2, or between a corresponding line in the first conductive line CL1 and a corresponding line in the second dummy conductive line DCL2, or between a corresponding line in the first dummy conductive line DCL1 and a corresponding line in the second dummy conductive line DCL2. Each dummy memory cell (DMC) can have the same components as each memory cell (MC). Each dummy memory cell (DMC) can include a variable resistor pattern VR and a switch pattern SW connected in series with each other. Each dummy memory cell (DMC) can also include a first electrode pattern EL1 between the corresponding first dummy conductive line DCL1 (or the corresponding first conductive line CL1) and the switch pattern SW, a second electrode pattern EL2 between the switch pattern SW and the variable resistor pattern VR, a third electrode pattern EL3 between the variable resistor pattern VR and the corresponding second dummy conductive line DCL2 (or the corresponding second conductive line CL2), a first metallic pattern MB1 between the variable resistor pattern VR and the second electrode pattern EL2, and a second metallic pattern MB2 between the variable resistor pattern VR and the third electrode pattern EL3. Each virtual memory cell (DMC) may also include a spacer structure SS, and the spacer structure SS may include a first spacer SS1 and a second spacer SS2 containing different materials.

[0059] The first to third electrode patterns EL1, EL2 and EL3, switch pattern SW, variable resistor pattern VR, first metallic pattern MB1 and second metallic pattern MB2, and spacer structure SS of each dummy memory cell DMC can be the same as the first to third electrode patterns EL1, EL2 and EL3, switch pattern SW, variable resistor pattern VR, first metallic pattern MB1 and second metallic pattern MB2, and spacer structure SS of each memory cell MC.

[0060] Figure 8A and Figure 8BThey correspond to respectively Figure 3 The figures are cross-sectional views along lines I-I' and II-II' to illustrate a variable resistor storage device according to some embodiments. In the following description, for ease of explanation, this embodiment will be primarily described in conjunction with... Figure 3 , Figure 4 , Figure 5A and Figure 5B Differences between implementation methods.

[0061] Reference Figure 3 , Figure 8A and Figure 8B The peripheral circuit structure PCS can be disposed on the substrate 100. The peripheral circuit structure PCS may include a device isolation pattern ST disposed in the substrate 100 to define an active region ACT and a peripheral transistor PTR disposed on the active region ACT. The device isolation pattern ST may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxide nitride.

[0062] Each peripheral transistor (PTR) may include a gate electrode GE on each active region ACT, a gate insulating pattern GI between each active region ACT and the gate electrode GE, a gate cover pattern CAP on the top surface of the gate electrode GE, gate spacers GSP on the two sidewalls of the gate electrode GE, and source / drain regions SD disposed on both sides of the gate electrode GE in each active region ACT. The gate electrode GE may include at least one of, for example, a doped semiconductor material, a conductive metal nitride, and a metal. The gate insulating pattern GI may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and a high-k dielectric layer. The high-k dielectric layer may include a material whose dielectric constant is higher than that of the silicon oxide layer. For example, the high-k dielectric layer may include a hafnium oxide (HfO) layer, an aluminum oxide (AlO) layer, or a tantalum oxide (TaO) layer. Each of the gate cover pattern CAP and the gate spacer GSP may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, and a silicon oxide nitride layer.

[0063] The peripheral circuit structure PCS may further include source / drain contacts 10 connected to the source / drain regions SD of each peripheral transistor PTR, interconnect lines 20 disposed on the peripheral transistor PTR, and interconnect contacts 22 connected to the interconnect lines 20. The source / drain regions SD of each peripheral transistor PTR can be connected to the corresponding interconnect lines in the interconnect lines 20 through the source / drain contacts 10. The source / drain contacts 10, interconnect lines 20, and interconnect contacts 22 may include conductive materials (e.g., metals).

[0064] The peripheral circuit structure PCS may further include a lower interlayer insulating layer 30 disposed on the substrate 100 and covering the peripheral transistor PTR, source / drain contacts 10, interconnects 20, and interconnect contacts 22. The lower interlayer insulating layer 30 may cover the peripheral transistor PTR. The source / drain contacts 10, interconnects 20, and interconnect contacts 22 may be disposed within the lower interlayer insulating layer 30. For example, the lower interlayer insulating layer 30 may include at least one of silicon oxide, silicon nitride, and silicon oxide nitride.

[0065] The multiple memory cell structures (MCS) and dummy cell structures (DCS) can be disposed on the peripheral circuit structure (PCS). The first conductive line CL1 and the first dummy conductive line DCL1 can be disposed on the lower interlayer insulating layer 30. The first conductive line CL1 can be connected to the corresponding interconnect contact in the interconnect contact 22. Each first conductive line CL1 can be electrically connected to the terminal (i.e., the corresponding source / drain region SD) of the corresponding peripheral transistor PTR through the corresponding interconnect contact 22 and the corresponding interconnect line 20. The first dummy conductive line DCL1 can be electrically floated instead of being connected to the interconnect contact 22.

[0066] The second conductive line CL2 and the second dummy conductive line DCL2 can be disposed on the first conductive line CL1 and the first dummy conductive line DCL1, and can cross the first conductive line CL1 and the first dummy conductive line DCL1. Each second conductive line CL2 can be connected to a corresponding one of the conductive contacts CT. Each second conductive line CL2 can be connected to the corresponding interconnect contact 22 and the corresponding interconnect line 20 through the corresponding conductive contact CT, and can be electrically connected to the terminal (i.e., the corresponding source / drain region SD) of the corresponding peripheral transistor PTR through the corresponding interconnect contact 22 and the corresponding interconnect line 20. The second dummy conductive line DCL2 can be not connected to the conductive contact CT and the interconnect contact 22, but can be electrically floated.

[0067] The first storage cell MC1 can be disposed at the intersection of the first conductive line CL1 and the second conductive line CL2. The first dummy storage cell DMC1 can be disposed at the intersection of the second dummy conductive line DCL2 and the first dummy conductive line DCL1, the intersection of the second dummy conductive line DCL2 and the first conductive line CL1, and the intersection of the second conductive line CL2 and the first dummy conductive line DCL1. The first storage cell MC1 and the first dummy storage cell DMC1 can be connected to a reference... Figure 3 , Figure 4 , Figure 5A and Figure 5B The described storage unit MC is the same as the virtual storage unit DMC.

[0068] In some embodiments, the third conductive line CL3 and the third dummy conductive line DCL3 may be disposed above and intersect with the second conductive line CL2 and the second dummy conductive line DCL2. The third conductive line CL3 and the third dummy conductive line DCL3 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. The third conductive line CL3 and the third dummy conductive line DCL3 may have a width in the second direction D2. In some embodiments, the fifth width W5 of each third conductive line CL3 may be equal to the sixth width W6 of each third dummy conductive line DCL3. The third dummy conductive line DCL3 may comprise the same material as the third conductive line CL3. For example, the third dummy conductive line DCL3 and the third conductive line CL3 may comprise at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, aluminum, titanium, or tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), and a metal semiconductor compound (e.g., a metal silicide).

[0069] Each third conductive line CL3 can be connected to a corresponding conductive contact CT. Each third conductive line CL3 can be connected to the corresponding interconnect contact 22 and the corresponding interconnect line 20 through the corresponding conductive contact CT, and can be electrically connected to the terminal (i.e., the corresponding source / drain region SD) of the corresponding peripheral transistor PTR through the corresponding interconnect contact 22 and the corresponding interconnect line 20. The third dummy conductive line DCL3 can be left unconnected to the conductive contact CT and the interconnect contact 22, and can instead be electrically floated.

[0070] The plurality of memory cell structures (MCS) may include a pair of memory cell structures (MCS) adjacent to each other in the first direction D1. The pair of memory cell structures (MCS) may be respectively disposed on a pair of cell regions CR that are adjacent to each other in the first direction D1 among the plurality of cell regions CR. In some embodiments, the pair of memory cell structures (MCS) may share a third conductive line CL3. In this case, the third conductive line CL3 may extend from one of the cell regions CR to a core region COR provided between the cell regions CR, and may extend across the core region COR provided between the cell regions CR to the other of the cell regions CR.

[0071] The second storage cell MC2 can be disposed at the intersection of the second conductive line CL2 and the third conductive line CL3. The second dummy storage cell DMC2 can be disposed at the intersection of the third dummy conductive line DCL3 and the second dummy conductive line DCL2, the intersection of the third dummy conductive line DCL3 and the second conductive line CL2, and the intersection of the third conductive line CL3 and the second dummy conductive line DCL2. The second storage cell MC2 and the second dummy storage cell DMC2 can be related to a reference... Figure 3 , Figure 4 , Figure 5A and Figure 5B The described storage unit MC and the virtual storage unit DMC are essentially the same.

[0072] Interlayer insulation layer 150 can be disposed on peripheral circuit structure PCS. Interlayer insulation layer 150 can cover the sidewall of first conductive line CL1, the sidewall of first dummy conductive line DCL1, the sidewall of first memory cell MC1, the sidewall of first dummy memory cell DMC1, the sidewall of second conductive line CL2, the sidewall of second dummy conductive line DCL2, the sidewall of second memory cell MC2, the sidewall of second dummy memory cell DMC2, the sidewall of third conductive line CL3, and the sidewall of third dummy conductive line DCL3.

[0073] Figure 9A and Figure 9B This is a plan view of a method for manufacturing a variable resistance storage device according to some embodiments. In the following text, for ease of explanation and convenience, details regarding... Figure 3 , Figure 4 , Figure 5A and Figure 5B The same technical features are described in the implementation methods.

[0074] Reference Figure 9A The first conductive line CL1 ( Figure 9A The white line in the middle) and the first dummy conductive line DCL1 ( Figure 9A The gray lines (in the diagram) can be formed on the substrate 100. For example, the formation of the first conductive line CL1 and the first dummy conductive line DCL1 can include forming a first conductive layer on the substrate 100 and patterning the first conductive layer. The first conductive line CL1 and the first dummy conductive line DCL1 can be formed simultaneously, that is, simultaneously formed by the same patterning process of the first conductive layer.

[0075] The first conductive line CL1 and the first dummy conductive line DCL1 may extend elongatedly (e.g., longitudinally) in a first direction D1 and may be spaced apart from each other in a second direction D2. According to some embodiments, the first conductive line CL1 may extend from each of the plurality of unit regions CR to the core region COR in the first direction D1. The first dummy conductive line DCL1 may be formed on the core region COR. Some of the first dummy conductive lines DCL1 may overlap with the edges of each of the plurality of unit regions CR and may extend to the core region COR.

[0076] The first dummy conductive line DCL1 adjacent to the first conductive line CL1 can be connected to the first conductive line CL1 along the second direction D2 in the core region COR adjacent to the second contact region R2. Some of the first dummy conductive lines DCL1 can be connected to each other along the second direction D2 in the core region COR adjacent to the first contact region R1. When the first conductive line CL1 and the first dummy conductive line DCL1 are formed as lines extending long in the first direction D1, collapse of the first conductive line CL1 and the first dummy conductive line DCL1 may occur. However, according to the embodiment, at least some of the first conductive line CL1 and the first dummy conductive line DCL1 can be formed to be connected to each other along the second direction D2 in the core region COR. Therefore, collapse of the first conductive line CL1 and the first dummy conductive line DCL1 can be minimized or prevented.

[0077] The connection portion between the first conductive line CL1 and the first dummy conductive line DCL1 can be removed by the first trimming process. As a result, see reference... Figure 3 , Figure 4 , Figure 5A and Figure 5B The ends CL1E of the first conductive line CL1 can be aligned with each other in the second direction D2 on the core region COR adjacent to the second contact region R2, and the ends DCL1E of the first dummy conductive line DCL1 adjacent to the first conductive line CL1 can be aligned with the ends CL1E of the first conductive line CL1 in the second direction D2 on the core region COR adjacent to the second contact region R2. Furthermore, some ends of the first dummy conductive lines DCL1 can be aligned with each other in the second direction D2 on the core region COR adjacent to the first contact region R1.

[0078] Refer again Figure 3 , Figure 4 , Figure 5A and Figure 5B The memory cell MC and the dummy memory cell DMC can be formed on the first conductive line CL1 and the first dummy conductive line DCL1. The memory cell MC and the dummy memory cell DMC can be arranged along the top surfaces of the first conductive line CL1 and the first dummy conductive line DCL1 in a first direction D1, and can be spaced apart from each other in a second direction D2. For example, the formation of the memory cell MC and the dummy memory cell DMC can include sequentially forming a switch layer and a variable resistor layer on the first conductive line CL1 and the first dummy conductive line DCL1, and then sequentially etching the variable resistor layer and the switch layer. The variable resistor pattern VR and the switch pattern SW of each of the memory cell MC and the dummy memory cell DMC can be formed by etching the variable resistor layer and the switch layer. By etching the variable resistor layer and the switch layer, the memory cell MC and the dummy memory cell DMC can be formed simultaneously.

[0079] Reference Figure 9B The second conductive line CL2 and the second dummy conductive line DCL2 can be formed on the substrate 100. The second conductive line CL2 and the second dummy conductive line DCL2 can be formed on the substrate 100 having the first conductive line CL1, the first dummy conductive line DCL1, the memory cell MC, and the dummy memory cell DMC. However, for ease of explanation and convenience, in... Figure 9B The components other than the second conductive line CL2 and the second dummy conductive line DCL2 are omitted. For example, the formation of the second conductive line CL2 and the second dummy conductive line DCL2 may include forming a second conductive layer on the substrate 100 and patterning the second conductive layer. The second conductive line CL2 and the second dummy conductive line DCL2 may be formed simultaneously, for example, by the same patterning process of the second conductive layer.

[0080] The second conductive line CL2 and the second dummy conductive line DCL2 may extend elongatedly (e.g., longitudinally) in the second direction D2 and may be spaced apart from each other in the first direction D1. According to some embodiments, the second conductive line CL2 may extend from each of the plurality of unit regions CR to the core region COR in the second direction D2. The second dummy conductive line DCL2 may be formed on the core region COR. Some of the second dummy conductive lines DCL2 may overlap with the edges of each of the plurality of unit regions CR and may extend to the core region COR.

[0081] The second dummy conductive line DCL2 adjacent to the second conductive line CL2 can be connected to the second conductive line CL2 along the first direction D1 in the core region COR adjacent to the first contact region R1. Some of the second dummy conductive lines DCL2 can be connected to each other along the first direction D1 in the core region COR adjacent to the second contact region R2. When the second conductive line CL2 and the second dummy conductive line DCL2 are formed as lines extending long in the second direction D2, collapse of the second conductive line CL2 and the second dummy conductive line DCL2 may occur. However, according to the embodiment, at least some of the second conductive line CL2 and the second dummy conductive line DCL2 can be formed to be connected to each other along the first direction D1 in the core region COR. Therefore, collapse of the second conductive line CL2 and the second dummy conductive line DCL2 can be minimized or prevented.

[0082] The connection between the second conductive line CL2 and the second dummy conductive line DCL2 can be removed by the second trimming process. As a result, see reference... Figure 3 , Figure 4 , Figure 5A and Figure 5BThe ends CL2E of the second conductive line CL2 can be aligned with each other in the first direction D1 on the core region COR adjacent to the first contact region R1, and the ends DCL2E of the second dummy conductive line DCL2 adjacent to the second conductive line CL2 can be aligned with the ends CL2E of the second conductive line CL2 in the first direction D1 on the core region COR adjacent to the first contact region R1. Furthermore, some ends of the second dummy conductive lines DCL2 can be aligned with each other in the first direction D1 on the core region COR adjacent to the second contact region R2.

[0083] Refer again Figure 3 , Figure 4 , Figure 5A and Figure 5B The memory cells MC can be disposed at the intersections of the first conductive line CL1 and the second conductive line CL2. The dummy memory cells DMC can be disposed at the intersections of the second dummy conductive line DCL2 and the first dummy conductive line DCL1, the intersection of the second dummy conductive line DCL2 and the first conductive line CL1, and the intersection of the second conductive line CL2 and the first dummy conductive line DCL1. The interlayer insulating layer 150 can be formed on the substrate 100 and can cover the sidewalls of the first conductive line CL1, the first dummy conductive line DCL1, the memory cell MC, the dummy memory cell DMC, the second conductive line CL2, and the second dummy conductive line DCL2. Conductive contacts CT can be formed on the first contact area R1 and the second contact area R2. The conductive contacts CT can penetrate the interlayer insulating layer 150 and can be electrically connected to the transistors on the substrate 100.

[0084] Figure 10 This is a plan view of a variable resistance storage device according to some implementation methods. Figure 11 yes Figure 10 An enlarged view of a portion of a variable resistance storage device. Figure 12A and Figure 12B They are respectively along Figure 10 The cross-sectional views are taken along lines I-I' and II-II'. In the following description, for ease of explanation, this embodiment will be primarily described. Figure 3 , Figure 4 , Figure 5A and Figure 5B Differences between implementation methods.

[0085] Reference Figure 10 , Figure 11 , Figure 12A and Figure 12BMultiple memory cell structures (MCS) can be respectively disposed on the multiple cell regions (CR). The multiple memory cell structures (MCS) can be spaced apart from each other in a first direction (D1) and a second direction (D2). Each of the multiple memory cell structures (MCS) may include a first conductive line (CL1), a second conductive line (CL2) disposed on and intersecting the first conductive line (CL1), and a memory cell (MC) between the first conductive line (CL1) and the second conductive line (CL2). The first conductive line (CL1) can extend in the first direction (D1) and can be spaced apart from each other in the second direction (D2). The second conductive line (CL2) can extend in the second direction (D2) and can be spaced apart from each other in the first direction (D1). The memory cells (MC) can be respectively disposed at the intersection of the first conductive line (CL1) and the second conductive line (CL2).

[0086] In some embodiments, the first conductive line CL1 may be partially disposed on each of the plurality of unit regions CR. In other words, the first conductive line CL1 may not extend to the core region COR. The ends CL1E of the first conductive line CL1 may be aligned with each other in a second direction D2 on each of the plurality of unit regions CR. The ends CL2E of the second conductive line CL2 may be aligned with each other in a first direction D1 on each of the plurality of unit regions CR.

[0087] The plurality of memory cell structures (MCS) may include a pair of memory cell structures (MCS) adjacent to each other in the second direction D2. This pair of memory cell structures (MCS) may be respectively disposed on a pair of adjacent cell regions CR in the second direction D2 among the plurality of cell regions CR. In some embodiments, the pair of memory cell structures (MCS) may share a second conductive line CL2. In this case, the second conductive line CL2 may extend from one of the pair of cell regions CR to a core region COR provided between the pair of cell regions CR, and may extend across the core region COR provided between the pair of cell regions CR to the other of the pair of cell regions CR.

[0088] A dummy cell structure (DCS) can be disposed on the core region (COR). The DCS can surround each of the plurality of memory cell structures (MCS) in a plan view and can extend between the plurality of MCS to form a single entity. The DCS can also be a single dummy cell structure disposed between the plurality of MCS. The DCS may include a first dummy conductive line (DCL1), a second dummy conductive line (DCL2) disposed on and intersecting the first dummy conductive line (DCL1), and dummy memory cells (DMCs) between the first dummy conductive line (DCL1) and the second dummy conductive line (DCL2).

[0089] The first dummy conductive lines DCL1 may extend in a first direction D1 and may be spaced apart from each other in a second direction D2. In some embodiments, some of the first dummy conductive lines DCL1 may be spaced apart from the end CL1E of the first conductive line CL1 in the first direction D1. The second dummy conductive lines DCL2 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. In some embodiments, some of the second dummy conductive lines DCL2 may be spaced apart from the end CL2E of the second conductive line CL2 in the second direction D2.

[0090] In some embodiments, the second dummy conductive line DCL2 may intersect with the first dummy conductive line DCL1, and the second conductive line CL2 may intersect with both the first conductive line CL1 and the first dummy conductive line DCL1. The dummy memory cell DMC may be located at the intersection of the second dummy conductive line DCL2 and the first dummy conductive line DCL1, and at the intersection of the second conductive line CL2 and the first dummy conductive line DCL1, respectively.

[0091] According to an implementation, a dummy cell structure DCS can be disposed on a core region COR to surround each of the plurality of memory cell structures MCS, and can extend along the core region COR between the plurality of memory cell structures MCS to form a body. The dummy cell structure DCS can have the same stacking structure as the plurality of memory cell structures MCS. In this case, the difference in pattern density between each of the cell regions CR and the core region COR can be minimized, thus suppressing or preventing defects in the outermost memory cell MC of each memory cell structure MCS during the manufacturing process. Furthermore, since the dummy cell structure DCS is formed with the same stacking structure as the plurality of memory cell structures MCS, the plurality of memory cell structures MCS and the dummy cell structure DCS can be easily (e.g., simultaneously) formed. As a result, a variable resistance memory device capable of minimizing memory cell defects and being easy to manufacture can be realized or provided.

[0092] According to an embodiment, a dummy cell structure can be disposed on a core region of a substrate. The dummy cell structure can surround each of the plurality of spaced-apart memory cell structures and can extend between the plurality of memory cell structures to form a body. The dummy cell structure can have the same stacking structure as the plurality of memory cell structures. In this case, the difference in pattern density between the core region on which the dummy cell structure is disposed and the cell region on which the memory cell structure is disposed can be minimized, thus suppressing or preventing defects in the outermost memory cell of each memory cell structure during the manufacturing process. Furthermore, since the dummy cell structure has the same stacking structure as the memory cell structure, both the memory cell structure and the dummy cell structure can be easily formed. As a result, a variable resistance memory device that minimizes memory cell defects and is easy to manufacture can be realized or provided.

[0093] By summarizing and reviewing, the implementation methods can provide variable resistance memory devices capable of minimizing defects in memory cells. The implementation methods can also provide variable resistance memory devices that are easy to manufacture.

[0094] Exemplary embodiments have been disclosed herein. Although specific terms are used, they are used and interpreted in a general and descriptive sense only and not for limiting purposes. In some instances, as will be apparent to those skilled in the art at the time of filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described with respect to other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0095] This application claims priority to Korean Patent Application No. 10-2021-0032764, filed on March 12, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A variable resistance storage device, comprising: substrate; The memory cell structure on the substrate is spaced apart from each other in a first direction and a second direction, the first direction and the second direction being parallel to the top surface of the substrate and intersecting each other; as well as A dummy cell structure, when viewed in a plan view, surrounds each of the said memory cell structures; the dummy cell structure is a single main structure that extends continuously between all said memory cell structures. Each of the aforementioned storage cell structures includes: First conductive line; A second conductive line, which lies on and intersects the first conductive line; and The storage unit between the first conductive line and the second conductive line, and The virtual unit structure mentioned above includes: First, a fictitious conductive line; A second dummy conductive line is on the first dummy conductive line and intersects with the first dummy conductive line; and A virtual storage unit between the first virtual conductive line and the second virtual conductive line.

2. The variable resistance storage device according to claim 1, wherein: The first conductive lines extend in the first direction and are spaced apart from each other in the second direction, and The first dummy conductive line extends in the first direction and is spaced apart from each other in the second direction.

3. The variable resistance storage device of claim 2, wherein each of the storage cells is structured between a pair of first dummy conductive lines spaced apart from each other along the second direction.

4. The variable resistance storage device according to claim 3, wherein: Each of the first conductive lines has a first width in the second direction, and Each of the first dummy conductive lines has a second width in the second direction, the second width being equal to the first width.

5. The variable resistance storage device according to claim 3, wherein: The second conductive wires extend in the second direction and are spaced apart from each other in the first direction, and The second dummy conductive line extends in the second direction and is spaced apart from each other in the first direction.

6. The variable resistance storage device of claim 5, wherein each of the storage cells is structured between a pair of second dummy conductive lines spaced apart from each other along the first direction.

7. The variable resistance storage device according to claim 6, wherein: Each of the second conductive lines has a third width in the first direction, and Each of the second dummy conductive lines has a fourth width in the first direction, and the third width is equal to the fourth width.

8. The variable resistance storage device according to claim 6, wherein: The substrate includes cell regions on which the memory cell structure is located and core regions between the cell regions. The first conductive line extends from each of the unit regions to the core region in the first direction, and The ends of the first conductive wire are aligned with each other in the second direction in the core region.

9. The variable resistance storage device according to claim 8, wherein: The second conductive line extends from each of the unit regions to the core region in the second direction, and The ends of the second conductive wire are aligned with each other in the first direction in the core region.

10. The variable resistance storage device according to claim 9, wherein: Some intersections between the second conductive line and the first dummy conductive line, and Some of the second dummy conductive lines intersect with the first conductive line.

11. The variable resistance storage device according to claim 10, wherein the dummy storage cells are located at the intersection of the second dummy conductive line and the first dummy conductive line, the intersection of the second dummy conductive line and the first conductive line, and the intersection of the second conductive line and the first dummy conductive line.

12. The variable resistance storage device according to claim 6, wherein: The substrate includes cell regions on which the memory cell structure is located and core regions between the cell regions. The ends of the first conductive wire are aligned with each other in the second direction in each of the unit regions, and The ends of the second conductive wire are aligned with each other in the first direction in each of the unit regions.

13. The variable resistance storage device according to claim 1, wherein: The substrate includes cell regions on which the memory cell structure is located and core regions between the cell regions, and The dummy unit structure is located on the core region and is formed as a single main structure that extends continuously along the core region.

14. The variable resistance storage device according to claim 13, wherein: The core region includes a contact area on which conductive contacts are located, and The dummy unit structure extends along the core region, excluding the contact area.

15. The variable resistance storage device according to claim 14, further comprising a peripheral circuit structure on the substrate. The storage cell structure, the dummy cell structure, and the conductive contact are located on the peripheral circuit structure, and The conductive contact therein is electrically connected to the peripheral transistor of the peripheral circuit structure.

16. The variable resistance storage device of claim 1, wherein each of the storage cell and the dummy storage cell comprises a variable resistance pattern and a switch pattern stacked upwards on a third side perpendicular to the top surface of the substrate.

17. A variable resistance storage device, comprising: substrate; The storage cell structure is spaced apart from each other in a first direction and a second direction on the substrate, the first direction and the second direction being parallel to the top surface of the substrate and intersecting each other; as well as A single dummy cell structure between the storage cell structures, The individual dummy cell structure extends between adjacent memory cell structures spaced apart from each other in the first direction within the memory cell structure, and also extends between adjacent memory cell structures spaced apart from each other in the second direction within the memory cell structure. Each of the aforementioned storage cell structures includes: First conductive line; A second conductive line that intersects the first conductive line; and The storage unit between the first conductive line and the second conductive line, and The single dummy unit structure mentioned above includes: First, a fictitious conductive line; A second dummy conductive line is on the first dummy conductive line and intersects with the first dummy conductive line; and A dummy storage unit is set between the first dummy conductive line and the second dummy conductive line.

18. The variable resistance storage device of claim 17, wherein, when viewed in a plan view, the individual dummy cell structure surrounds each of the storage cell structures.

19. The variable resistance storage device according to claim 17, wherein: The first dummy conductive line comprises the same material as the first conductive line, and The second dummy conductive line comprises the same material as the second conductive line.

20. The variable resistance storage device of claim 17, wherein each of the storage cell and the dummy storage cell comprises a variable resistance pattern and a switch pattern stacked upwards on a third side perpendicular to the top surface of the substrate.

Images