Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a substrate, comprising a first device region and a second device region, the first device region comprising a channel region, a preset region located on both sides of the channel region, and a well region contact region surrounding the channel region and the preset region; a first isolation structure located in the substrate between the preset region and the well region contact region, and between the well region contact region and the adjacent second device region; a polysilicon gate covering the channel region; a first source-drain doped region located in the preset region on both sides of the polysilicon gate; a metal gate located on the substrate of the second device region; a support structure located on the top of the first isolation structure; and an interlayer dielectric layer covering the polysilicon gate, the metal gate, and the sidewalls of the support structure. The support structure can improve the problem of the top surface depression of the interlayer dielectric layer above the first isolation structure, prevent the interlayer dielectric layer and the metal gate from contacting the first source-drain doped region and the well region contact region during the flattening process, and improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor technology, even as device dimensions continue to shrink, it is still desirable to further improve transistor performance and to manufacture integrated circuit semiconductor devices that combine low, medium, and high voltage application ranges.

[0003] For example, an integrated circuit (hereinafter referred to as a driver IC) used to drive image sensors, LCDs, and printed heads, etc., is composed of a drive output unit with a high-voltage MOS transistor with a strong voltage resistance between the drain and the source that operates at a power supply voltage of more than 3.3V, and a logic unit of a control drive output unit with a low-voltage MOS transistor with a poor drain voltage resistance that can be used at a power supply voltage of several volts or less. Such integrated circuits are usually called system-on-chips. Although such integrated circuits include logic transistors that operate with very low voltages (such as 1.8V or 2.5V), other transistors on the same integrated circuit are designed for high voltage applications and therefore operate with high voltages, and often the voltage difference between the drain and the source may be as high as 30V or even 40V. High-voltage transistor elements are capable of carrying more current than logic transistors or peripheral transistors in logic circuits.

[0004] Among them, compared with low voltage (LV) devices, high voltage devices (HV) and medium voltage devices (MV) have higher operating voltages, and the sizes of high voltage devices and medium voltage devices are correspondingly larger. High voltage devices and medium voltage devices still use polysilicon gates (Poly Gate), while low voltage devices use metal gates (Metal Gate).

[0005] However, the performance of the devices formed so far is poor. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the problem of the top surface depression of the interlayer dielectric layer above the first isolation structure, preventing the top surface of the first source / drain doping region and the well region contact region from being contacted during the planarization process of forming the interlayer dielectric layer and the metal gate, thereby improving the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device is greater than the channel length of the second device, and the substrate of the first device region includes a channel region, preset regions located on both sides of the channel region along the length direction of the channel region, and a well region contact region surrounding the channel region and the preset region; a first isolation structure, located in the substrate between the preset region and the well region contact region, and between the well region contact region and the adjacent second device region; a polysilicon gate, covering the substrate of the channel region; a first source-drain doped region, located in the substrate of the preset region on both sides of the polysilicon gate; a metal gate, located on the substrate of the second device region; a second source-drain doped region, located in the substrate on both sides of the metal gate; a support structure, located on the top of the first isolation structure; an interlayer dielectric layer, located on the substrate and covering the polysilicon gate, the metal gate and the sidewalls of the support structure.

[0008] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first device region for forming a first device and a second device region for forming a second device, the channel length of the first device being greater than the channel length of the second device, the substrate of the first device region comprising a channel region, preset regions located on both sides of the channel region along the length direction of the channel region and used to form a first source-drain doping region, and a well region contact region surrounding the channel region and the preset region, a first isolation structure is formed in the substrate between the preset region and the well region contact region, and between the well region contact region and an adjacent second device region, forming a polysilicon gate separated from the first device region and the second device region on the substrate, located The polysilicon gate of the first device area covers the channel area; a first source-drain doped region is formed in a preset area on both sides of the polysilicon gate of the first device area; a second source-drain doped region is formed in the substrate on both sides of the polysilicon gate of the second device area; a support structure is formed on the first isolation structure exposed by the polysilicon gate; after forming the first source-drain doped region and the second source-drain doped region and the support structure, an interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the side walls of the polysilicon gate and the support structure, and exposes the top of the polysilicon gate of the second device area; the polysilicon gate of the second device area is removed, and a gate opening is formed in the interlayer dielectric layer; a metal gate is formed in the gate opening.

[0009] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0010] The semiconductor structure provided by the embodiment of the present invention also includes a support structure, which is located on the top of the first isolation structure; forming an interlayer dielectric layer includes a process of flattening the dielectric material layer, and forming a metal gate includes a process of flattening the metal gate material. The support structure can play a supporting role in the process of flattening the interlayer dielectric layer and the metal gate, so as to avoid over-polishing of the interlayer dielectric layer above the first isolation structure, which is not only conducive to improving the top surface dipping (Dishing) and thickness reduction problems of the interlayer dielectric layer above the first isolation structure, but also the support structure can protect the first source and drain doping region and the well region contact region, which is conducive to preventing the flattening treatment from contacting the top surface of the first source and drain doping region and the well region contact region. The top surface of the first source and drain doping region and the well region contact region is usually formed with a metal silicide layer, which is correspondingly conducive to preventing the flattening treatment from contacting the metal silicide layer located on the top surface of the first source and drain doping region and the well region contact region, thereby improving the performance of the semiconductor structure.

[0011] In the method for forming a semiconductor structure provided by an embodiment of the present invention, before forming the interlayer dielectric layer, a support structure is also formed on the first isolation structure exposed by the polysilicon gate; forming the interlayer dielectric layer includes a process of flattening the dielectric material layer, and forming the metal gate includes a process of flattening the metal gate material. The support structure can play a supporting role in the process of flattening the interlayer dielectric layer and the metal gate to avoid over-grinding the interlayer dielectric layer above the first isolation structure, which is not only conducive to improving the top surface depression and thickness reduction of the interlayer dielectric layer above the first isolation structure, but also, due to the first source leakage doping The substrate around the doped area and the well area contact area has the support structure that can play a supporting role. The support structure can also protect the first source and drain doped area and the well area contact area, which is beneficial to prevent the planarization treatment from contacting the top surface of the first source and drain doped area and the well area contact area. The top surface of the first source and drain doped area and the well area contact area is usually also formed with a metal silicide layer, which is correspondingly beneficial to prevent the planarization treatment from contacting the metal silicide layer located on the top surface of the first source and drain doped area and the well area contact area, and further helps to avoid metal contamination of the planarization processing machine; in summary, the embodiments of the present invention are beneficial to improving the performance of semiconductor structures and production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0013] Figure 6 and Figure 7is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0014] Figures 8 to 23 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0015] As can be seen from the background technology, the performance of the current semiconductor structure needs to be improved. Now, in combination with a method for forming a semiconductor structure, the reasons why the performance of the semiconductor structure needs to be improved are analyzed. Figures 1 to 5 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 , providing a substrate 10, including a first device region 10H for forming a first device and a second device region 10L for forming a second device, the channel length of the first device is greater than the channel length of the second device, the substrate 10 of the first device region 10H includes a channel region 10C, preset regions 10S located on both sides of the channel region 10C along the length direction of the channel region 10C for forming first source and drain doping regions, and a well region contact region 10P surrounding the channel region 10C and the preset region 10S, an isolation structure 11 is formed in the substrate 10 between the channel region 10C and the preset region 10S, between the preset region 10S and the well region contact region 10P, between the channel region 10C and the well region contact region 10P, and between the well region contact region 10P and the adjacent second device region 10L.

[0017] Continue to refer Figure 1 , forming a polysilicon gate 20 separately on the substrate 10 of the first device region 10H and the second device region 10L, and the polysilicon gate 20 of the first device region 10H covers the substrate 10 of the channel region 10C.

[0018] refer to Figure 2 , a first source-drain doped region 21 is formed in a preset area 10S on both sides of the polysilicon gate 20 of the first device region 10H; and a second source-drain doped region 22 is formed in the substrate 10 on both sides of the polysilicon gate 20 of the second device region 10L.

[0019] refer to Figure 3 A metal silicide layer 30 is formed on top surfaces of the first source / drain doping region 21 , the well contact region 10P and the second source / drain doping region 22 .

[0020] refer to Figure 4, an interlayer dielectric layer 40 is formed on the substrate 10 at the side of the polysilicon gate 20, covering the metal silicide layer 30 and the isolation structure 11, and exposing the top of the polysilicon gate 20 of the second device area 10L. The step of forming the interlayer dielectric layer 40 generally includes: forming a dielectric material layer (not shown) covering the sidewall and top of the polysilicon gate 20 on the substrate 10; performing a planarization process on the dielectric material layer, removing the dielectric material layer higher than the top surface of the polysilicon gate 20 of the second device area 10L, and the remaining dielectric material layer is used as the interlayer dielectric layer 40.

[0021] refer to Figure 5 , remove the polysilicon gate 20 of the second device region 10L, form a gate opening (not shown) in the interlayer dielectric layer 40 of the second device region; and form a metal gate 50 in the gate opening. The step of forming the metal gate 50 generally includes: filling the gate opening with a metal gate material (not shown), the metal gate material also being formed on the interlayer dielectric layer 40; performing a planarization process on the metal gate material, removing the metal gate material on the top surface of the interlayer dielectric layer 40, and the remaining metal gate material in the gate opening is used as the metal gate 50.

[0022] In the method, since the polysilicon gate 20 is not formed on the substrate 10 around the first source / drain doped region 21 and the well contact region 10P, the pattern density of the polysilicon gate 20 around the first source / drain doped region 21 and the well contact region 10P is low, and no structure capable of playing a supporting role is formed around the first source / drain doped region 21 and the well contact region 10P, it is easy to flatten the first source / drain doped region 21 and the well contact region 10P in the process of flattening the dielectric material layer and the metal gate material. The interlayer dielectric layer 40 above P is over-polished, resulting in a serious top surface depression problem of the interlayer dielectric layer 40 above the first source and drain doping regions 21 and the well contact region 10P. The thickness of the interlayer dielectric layer 40 above the first source and drain doping regions 21 and the well contact region 10P is reduced, and even the planarization process contacts the metal silicide layer 30 located on the top surface of the first source and drain doping regions 21 and the well contact region 10P, which makes the planarization process machine susceptible to metal contamination, resulting in poor performance of the formed device and reduced production yield.

[0023] In particular, the channel length of the first device is greater than the channel length of the second device, and the operating voltage of the first device is greater than the operating voltage of the second device. In order to better isolate the first device from the second device, the area of ​​the isolation structure 11 located between the well region contact area 10P and the adjacent second device area 10L is relatively large. In the process of planarizing the interlayer dielectric layer 40 and the metal gate 50, the problem of over-grinding of the interlayer dielectric layer 40 above the first source and drain doped region 21 and the well region contact region 10P is serious, and the planarizing process is very likely to contact the metal silicide layer 30 located on the top surface of the first source and drain doped region 21 and the well region contact region 10P.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including a support structure, located on the top of the first isolation structure; the support structure can play a supporting role in the process of flattening the interlayer dielectric layer and the metal gate to avoid over-grinding the interlayer dielectric layer above the first isolation structure, which is not only beneficial to improving the top surface depression and thickness reduction problems of the interlayer dielectric layer above the first isolation structure, but also the support structure can protect the first source and drain doping region and the well region contact region, which is beneficial to prevent the flattening treatment from contacting the top surface of the first source and drain doping region and the well region contact region. The top surface of the first source and drain doping region and the well region contact region is usually formed with a metal silicide layer, which is correspondingly beneficial to prevent the metal silicide layer from being flattened, thereby improving the performance of the semiconductor structure.

[0025] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 6 and Figure 7 , Figure 6 is a top view, Figure 7 for Figure 6 The local cross-sectional view along the length direction of the channel region shows a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0026] In this embodiment, the semiconductor structure includes: a substrate 100, including a first device region 100H for forming a first device and a second device region 100L for forming a second device, the channel length of the first device is greater than the channel length of the second device, the channel length of the first device is greater than the channel length of the second device, the substrate 100 of the first device region 100H includes a channel region 100C, a channel region 100C along the length direction (such as Figure 6The first device region 100L is provided with a first isolation structure 110, which is located in the substrate 100 between the preset region 100S and the well region contact region 100P, and between the well region contact region 100P and the adjacent second device region 100L; a polysilicon gate 200, which covers the substrate 100 of the channel region 100C; a first source / drain doped region 100S, which is located on both sides of the channel region 100C and is used to form a first source / drain doped region; and a well region contact region 100P surrounding the channel region 100C and the preset region 100S. The doped region 130 is located in the substrate 100 of the preset area 100S on both sides of the polysilicon gate 200; the metal gate 360 ​​is located on the substrate 100 of the second device area 100L; the second source and drain doped region 240 is located in the substrate 100 on both sides of the metal gate 360; the support structure 300 is located on the top of the first isolation structure 110; the interlayer dielectric layer 340 is located on the substrate 100 and covers the polysilicon gate 200, the metal gate 360 ​​and the side wall of the support structure 300.

[0027] The metal gate 360 ​​is used as a first metal gate 360 ​​.

[0028] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0029] In this embodiment, taking the formation of a planar field effect transistor as an example, the substrate 100 is a planar substrate. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0030] In some other embodiments, the substrate may also be a three-dimensional substrate according to the type of transistor actually formed.

[0031] A channel length of the first device is greater than a channel length of the second device, and an operating voltage of the first device is higher than an operating voltage of the second device.

[0032] In this embodiment, the first device includes one or both of a medium voltage device and a high voltage device, and the second device is a low voltage device. The operating voltages of the low voltage device, the medium voltage device, and the high voltage device increase in sequence. As an example, the operating voltage of the low voltage device is less than 1.5V, the operating voltage of the medium voltage device is 1V to 10V, and the operating voltage of the high voltage device is greater than 10V.

[0033] In this embodiment, the first device is a high voltage device and the second device is a low voltage device. Specifically, the second device is a core device.

[0034] It should be noted that the first device may be an NMOS transistor or a PMOS transistor. Similarly, the second device may also be an NMOS transistor or a PMOS transistor. As an example, the first device is an NMOS transistor, and the second device is a PMOS transistor.

[0035] In this embodiment, a well region (not shown) is formed in the substrate 100, and the well region has a different conductivity type from the channel of the transistor. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.

[0036] As an example, the first device is an NMOS transistor, and the well region of the first device region 100H is a P-type doped deep well region (P well). Specifically, the well region of the first device region 100H is a high voltage device P-type doped deep well region (High Voltage P well), so that the first device can withstand a larger operating voltage.

[0037] As an example, the second device is a PMOS transistor, and the well region of the second device region 100L is an N-type doped well region.

[0038] The substrate 100 of the first device region 100H includes a channel region 100C. When the first device is in operation, a conductive channel is formed in the substrate 100 of the channel region 100C. Specifically, the channel region 100C is located in the well region.

[0039] In this embodiment, the direction of the length of the channel region 100C refers to: the direction of movement of carriers in the conductive channel when the device is working. Specifically, the first source-drain doped region 130 includes a source region and a drain region located on both sides of the polysilicon gate 200, respectively, and the direction from the drain region to the source region is the direction of the length of the channel region 100C. In this embodiment, the length direction of the channel region 100C is as follows: Figure 6 The direction perpendicular to the length direction of the channel region 100C is the width direction of the channel region 100C (as shown in FIG. Figure 6 shown in the Y direction).

[0040] The preset region 100S is used to form the first source-drain doping region 130. The preset region 100S is located at both sides of the channel region 100C along the length direction of the channel region 100C, and the preset region 100S is a long strip structure extending along the width direction of the channel region 100C.

[0041] The well region contact area 100P is used to realize the electrical connection between the well region and the external circuit or other interconnection structure. Specifically, the semiconductor structure generally further includes a contact hole plug located above the well region contact area 100P and in contact with the well region contact area 100P, so as to provide a substrate potential for the substrate 100 through the contact hole plug.

[0042] In this embodiment, the well contact region 100P is a closed ring structure, and is also used as a guard ring (GuardRing) to isolate external coupling noise.

[0043] In this embodiment, the substrate 100 further includes a third device region (not shown) for forming a third device, and the channel conductivity type of the third device is different from that of the second device. In this embodiment, the third device is also a low voltage device, and the channel length of the third device is less than the channel length of the first device. In this embodiment, the second device is a PMOS transistor, and the third device is correspondingly an NMOS transistor.

[0044] In this embodiment, the substrate 100 further includes a functional area (not shown) for forming a functional structure. The functional structure includes a resistor structure, a capacitor structure, a diode, a triode, etc. As an example, the functional area is used to form a resistor structure.

[0045] The first isolation structure 110 is used to isolate the well contact region 100P from the first source-drain doped region 130, and is also used to achieve isolation between the well contact region 100P and adjacent devices. In this embodiment, the first isolation structure 110 located outside the well contact region 100P surrounds the well contact region 100P. Accordingly, the first isolation structure 110 located outside the well contact region 100P is also a ring structure.

[0046] In this embodiment, a second isolation structure 120 is further formed in the substrate 100 between the channel region 100C and the preset region 100S. The second isolation structure 120 is used to increase the moving path between the carriers and the conductive channel, thereby improving the withstand voltage capability of the first device.

[0047] Specifically, in this embodiment, a first groove (not marked) is formed in the substrate 100 between the well region contact area 100P and the channel region 100C, and between the well region contact area 100P and the adjacent second device region 100L, a second groove (not marked) is formed in the substrate 100 between the channel region 100C and the preset area 100S, the first isolation structure 110 is located in the first groove, and the second isolation structure 120 is located in the second groove.

[0048] Accordingly, the first trench and the second trench are used to define an active area in the first device area 100H of the substrate 100 , that is, the substrate 100 of the first device area 100H isolated by the first trench and the second trench is an active area.

[0049] Specifically, in this embodiment, the channel region 100C, the preset region 100S, and the well region contact region 100P isolated by the first isolation structure 110 and the second isolation structure 120 are active areas (Active Area, AA).

[0050] In this embodiment, the first isolation structure 110 and the second isolation structure 120 are both shallow trench isolation (STI) structures. The first isolation structure 110 and the second isolation structure 120 are made of insulating materials, such as silicon oxide, silicon nitride or silicon oxynitride.

[0051] The semiconductor structure further includes a liner layer 105 located between the first isolation structure 110 and the sidewall and bottom of the first trench, and between the second isolation structure 120 and the sidewall and bottom of the second trench.

[0052] The liner layer 105 is used to improve the interface quality of the bottom surface and the sidewall of the first trench and the second trench, thereby improving the formation quality of the first isolation structure 110 and the second isolation structure 120. As an example, the material of the liner layer 105 is silicon oxide.

[0053] The polysilicon gate 200 is used as a device gate structure of the first device, so as to control the opening or closing of the conductive channel of the first device.

[0054] Since the first device region 100H is used to form the first device, the channel length of the first device is greater than the channel length of the second device, and the gate size of the first device is correspondingly larger. Therefore, by making the first device adopt a polysilicon gate 200, it is avoided to adopt a metal gate in the first device, thereby avoiding the problem of top surface depression of the metal gate caused by the larger gate size in the first device region 100H.

[0055] In this embodiment, the material of the polysilicon gate 200 is polysilicon.

[0056] In this embodiment, the polysilicon gate 200 covers the substrate 100 in the channel region 100C, and also extends to cover a portion of the second isolation structure 120 .

[0057] The first source-drain doped region 130 is used as a source region or a drain region of the first device.

[0058] In this embodiment, the first device is an NMOS transistor, and the first source-drain doping region 130 is N-type doped. In other embodiments, when a PMOS transistor is formed, the first source-drain doping region is P-type doped.

[0059] The first metal gate 360 ​​is used to control the opening and closing of the conductive channel of the second device.

[0060] The material of the metal gate 360 ​​is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the metal gate 360 ​​is Al.

[0061] The second source-drain doped region 240 is used as a source region or a drain region of the second device. In this embodiment, the second source-drain doped region 240 includes a source-drain epitaxial layer doped with ions, thereby providing stress for the channel to improve the mobility of carriers.

[0062] In this embodiment, the second device is a PMOS transistor, the second source and drain doping region 240 is P-type doped, the second source and drain doping region 240 is doped with P-type ions, and the material of the source and drain epitaxial layer is SiGe, thereby providing compressive stress for the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor channel.

[0063] In this embodiment, the substrate 100 also includes a third device region; the semiconductor structure also includes: a second metal gate (not shown), located on the substrate 100 in the third device region; and a third source-drain doped region (not shown), located in the substrate 100 on both sides of the second metal gate.

[0064] The third source-drain doped region is used as a source region or a drain region of a third device. In this embodiment, the channel conductivity type of the third device is different from the channel conductivity type of the second device, and accordingly, the doping type of the third source-drain doped region is different from that of the second source-drain doped region. In this embodiment, the third device is an NMOS transistor, and the third source-drain doped region is correspondingly N-type doped.

[0065] In this embodiment, the semiconductor structure further includes: a stacked structure (not shown) located between the polysilicon gate 200 and the substrate 100 , and between the first metal gate 360 ​​and the substrate 100 .

[0066] In this embodiment, the stacked structure includes a high-k gate dielectric layer 202 and a metal barrier layer 203 stacked in sequence from bottom to top.

[0067] In this embodiment, the material of the high-k gate dielectric layer 202 is a high-k dielectric material. As an example, the material of the high-k gate dielectric layer 202 is HfO2.

[0068] In this embodiment, the metal barrier layer 203 is used to isolate the high-k gate dielectric layer 202 from the polysilicon gate 200, and to isolate the high-k gate dielectric layer 202 from the metal gate 360, so as to protect the high-k gate dielectric layer 202. Moreover, the metal barrier layer 203 is also used to prevent the easily diffusible ions in the metal gate 360 ​​from diffusing into the high-k gate dielectric layer 202. The metal barrier layer 203 also has a certain influence on the gate work function of the second device.

[0069] The material of the metal barrier layer 203 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 203 is titanium nitride.

[0070] The semiconductor structure further includes: a gate oxide layer 201 located between the stacked structure and the substrate 100 of the first device region 100H; an interface buffer layer 204 located between the stacked structure and the substrate 100 of the second device region 100L, and the thickness of the interface buffer layer 204 is less than the thickness of the gate oxide layer 201 .

[0071] The gate oxide layer 201 is used to isolate the polysilicon gate 200 from the channel of the first device, and the interface buffer layer 204 is used as an interface buffer layer between the high-k gate dielectric layer 202 and the second device region 100L substrate 100, which is beneficial to improving electron mobility, interface stability and device reliability.

[0072] The gate oxide layer 201 and the interface buffer layer 204 are made of silicon oxide or silicon oxynitride. In this embodiment, the gate oxide layer 201 and the interface buffer layer 204 are made of silicon oxide.

[0073] The support structure 300 can play a supporting role during the planarization process of forming the interlayer dielectric layer 340 and the metal gate 360, so as to avoid over-grinding of the interlayer dielectric layer above the first isolation structure 110, which is not only beneficial to improve the top surface depression and thickness reduction problems of the interlayer dielectric layer 340 above the first isolation structure 110, but also the support structure 300 can play a protective role for the first source and drain doped region 130 and the well region contact region 100P, which is beneficial to prevent the planarization process from contacting the top surface of the first source and drain doped region 130 and the well region contact region 100P. The top surfaces of the first source and drain doped region 130 and the well region contact region 100P are usually also formed with a metal silicide layer, which is correspondingly beneficial to prevent the metal silicide layer from being ground, thereby improving the performance of the semiconductor structure.

[0074] The support structure 300 is made of a material with relatively high hardness, so as to ensure that the support structure 300 can play a supporting and polishing blocking role in the planarization process of forming the interlayer dielectric layer 340 and forming the metal gate 360. In this embodiment, the material of the support structure 300 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride and boron carbonitride.

[0075] It should be noted that, in this embodiment, the top surface of the support structure 300 is flush with the top surface of the metal gate 360 ​​, or the top surface of the support structure 300 is lower than the top surface of the metal gate 360 ​​.

[0076] The steps of forming the interlayer dielectric layer 340 and the metal gate 360 ​​include: forming an interlayer dielectric layer 340 on the substrate 100 on the side of the polysilicon gate 200 to expose the polysilicon gate 200 in the second device area 100L; removing the polysilicon gate 200 located in the second device area 100L, forming a gate opening in the interlayer dielectric layer 340, and forming the metal gate 360 ​​in the gate opening.

[0077] The formation of the interlayer dielectric layer 340 includes a process of planarizing the dielectric material layer, and the formation of the metal gate 360 ​​includes a process of planarizing the metal gate material layer. In this embodiment, the top surface of the support structure 300 is not higher than the top surface of the metal gate 360, so as to prevent adverse effects on the planarization process of forming the interlayer dielectric layer 340 and forming the metal gate 360.

[0078] In this embodiment, the top surface of the supporting structure 300 is lower than the top surface of the metal gate 360 ​​as an example for description.

[0079] It should be noted that, along the direction of the surface normal of the substrate 100, the height difference between the top surface of the support structure 300 and the top surface of the metal gate 360 ​​should not be too large. When the top surface of the support structure 300 is lower than the metal gate 360, the excessive height difference will result in a correspondingly small thickness of the support structure 300, which will easily increase the risk of the support structure 300 being removed during the planarization process of forming the interlayer dielectric layer 340 and the metal gate 360, and thus easily lead to poor support of the support structure 300. For this reason, in this embodiment, along the direction of the surface normal of the substrate 100, the height difference between the top surface of the support structure 300 and the top surface of the metal gate 360 ​​is less than or equal to

[0080] As an example, along the direction of the surface normal of the substrate 100, the height difference between the top surface of the support structure 300 and the top surface of the metal gate 360 ​​is to

[0081] It should also be noted that, in the present embodiment, along the width direction of the first isolation structure 110, the sidewall of the support structure 300 is indented relative to the sidewall on the same side of the first isolation structure 110. The sidewall of the support structure 300 is indented relative to the sidewall on the same side of the first isolation structure 110, thereby reserving process space for the overlay shift of the photolithography process for forming the support structure 300, so as to prevent the support structure 300 from being formed on the first source-drain doped region 130 and the well contact region 100P due to the overlay shift, and correspondingly ensure that during the metal silicide process, the metal layer can contact the entire top surface of the first source-drain doped region 130 and the well contact region 100P, thereby increasing the process window of the photolithography process for forming the support structure 300.

[0082] In order to ensure that the distance by which the side wall of the support structure 300 is retracted relative to the side wall on the same side of the first isolation structure 110 can compensate for the overlay offset of the photolithography process, and to ensure that the area of ​​the support structure 300 is not too small so that the support structure 300 can play a sufficient supporting role, in this embodiment, along the width direction of the first isolation structure 110, the side wall of the support structure 300 is retracted by 0.3μm to 0.4μm relative to the side wall on the same side of the first isolation structure 110.

[0083] The support structure 300 includes any one of a first support layer 310 and a second support layer 320 ; or, the support structure 300 includes a first support layer 310 and a second support layer 320 located on the first support layer 310 .

[0084] In this embodiment, the support structure 300 includes a first support 310 and a second support layer 320 located on the first support layer 310. In this embodiment, the material of the first support layer 310 is silicon nitride. Silicon nitride has high hardness and density, so it can provide high mechanical strength to improve the support function of the support structure 300.

[0085] In this embodiment, the semiconductor structure also includes: a first inner sidewall 210, located on the sidewall of the first metal gate 360; a second inner sidewall 220, located on the sidewall of the polysilicon gate 200, the second inner sidewall 220 is made of the same material as the first inner sidewall 210 and the first supporting layer 310; and an outer sidewall 230, located on the sidewalls of the first inner sidewall 210 and the second inner sidewall 220.

[0086] The first inner sidewall 210 is used to define the formation position of the source / drain epitaxial layer and is also used to protect the sidewall of the first metal gate 360. The second inner sidewall 220 is used to protect the sidewall of the polysilicon gate 200.

[0087] In the process of forming the semiconductor structure, before forming the first source-drain doping region 130 and the second source-drain doping region 240, polysilicon gates are formed on the substrate 100 of the first device region 100H and the second device region 100L; the step of forming the source-drain epitaxial layer includes: in the first device region 100H, forming a hard mask layer on the top and sidewalls of the polysilicon gate and the top surface of the substrate 100, wherein the hard mask layer exposes the polysilicon gate of the second device region 100L and the top surface of the substrate 100; The source and drain epitaxial layers are formed in the substrate 100 on both sides of the polysilicon gate; the step of forming the first supporting layer 310 includes: after forming the source and drain epitaxial layers, before ion doping the source and drain epitaxial layers to form the second source and drain doping area 240, in the first device area 100H, removing the hard mask layer located on the top of the polysilicon gate and the top surface of the preset area 100S and the well area contact area 100P, and retaining the hard mask layer located on the first isolation structure 110 for use as the first supporting layer 310.

[0088] The first inner sidewall 210 and the first supporting layer 310 are made of the same material because, in the step of forming the hard mask layer, a first inner sidewall is formed on the sidewall of the polysilicon gate located in the second device area 100L; and, the second inner sidewall 220, the first inner sidewall 210 and the first supporting layer 310 are made of the same material because, in the first device area, in the step of removing the hard mask layer located on the top of the polysilicon gate and the top surface of the preset area 100S and the well area contact area 100P in the first device area 100H, the remaining hard mask layer on the sidewall of the polysilicon gate 200 located in the first device area 100H is retained to serve as the second inner sidewall 220.

[0089] As an example, the material of the outer wall 230 is silicon nitride.

[0090] In this embodiment, the supporting structure 300 includes a second supporting layer 320; the substrate 100 also includes a functional area for forming a functional structure; the semiconductor structure also includes: a silicide blocking layer (not shown), located on a partial area of ​​the substrate 100 in the functional area, and the material of the silicide blocking (salicide block, SAB) layer is the same as the material of the second supporting layer 320.

[0091] The material of the silicide blocking layer is the same as that of the second supporting layer 320. This is because the silicide blocking layer is formed simultaneously with the step of forming the second supporting layer 320, thereby integrating the process steps of forming the second supporting layer 320 with the process steps of forming the silicide blocking layer, thereby improving process integration and compatibility.

[0092] The silicide barrier layer exposes the area where the metal silicide layer is desired to be formed, and is used to protect the area where the metal silicide layer is not desired to be formed. Specifically, in this embodiment, the silicide barrier layer is used to protect the functional area to prevent the metal silicide layer from being formed on part of the functional area.

[0093] In this embodiment, the material of the silicide barrier layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the silicide barrier layer is the same as the material of the second supporting layer 320, that is, silicon nitride.

[0094] Correspondingly, the semiconductor structure also includes: a metal silicide layer 330, located between the top surface of the first source / drain doped region 130 exposed by the silicide blocking layer and the interlayer dielectric layer 340, between the top surface of the well contact region 100P and the interlayer dielectric layer 340, and between the top surface of the second source / drain doped region 240 and the interlayer dielectric layer 340.

[0095] The semiconductor structure generally further includes: contact hole plugs (not shown) located on the top surfaces of the first source / drain doping region 130, the second source / drain doping region 240 and the well contact region 100P, respectively; the metal silicide layer 330 is used to reduce the contact resistance between the first source / drain doping region 130, the second source / drain doping region 240 and the well contact region 100P and the corresponding contact hole plugs, thereby correspondingly improving the performance of the semiconductor structure.

[0096] In this embodiment, the material of the metal silicide layer 330 may be a nickel silicon compound, a cobalt silicon compound or a titanium silicon compound.

[0097] The interlayer dielectric layer 340 is used to isolate adjacent devices.

[0098] In this embodiment, the support structure 300 can play a supporting role during the planarization process of forming the interlayer dielectric layer 340, so as to avoid over-grinding of the interlayer dielectric layer 340 above the first isolation structure 110, which is beneficial to improving the problems of top surface depression and thickness reduction of the interlayer dielectric layer 340 above the first isolation structure 110. Therefore, the top surface flatness and height consistency of the interlayer dielectric layer 340 are relatively high, which is beneficial to improving the performance of the semiconductor structure.

[0099] In this embodiment, the material of the interlayer dielectric layer 340 is silicon oxide.

[0100] In this embodiment, for the convenience of illustration and description, only the interlayer dielectric layer 340 is illustrated in the cross-sectional view. In addition, in this embodiment, for the convenience of illustrating the specific structure of the first device area 100H, only the position of the second device area 100L is illustrated in the top view. For the specific structure of the second device area 100L, please refer to the corresponding cross-sectional view.

[0101] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 23 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0102] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0103] refer to Figures 8 to 9 , Figure 8 is a top view, Fig. 9 for Figure 8 A partial cross-sectional view along the length direction of the channel region, providing a substrate 100, including a first device region 100H for forming a first device and a second device region 100L for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device, and the substrate 100 of the first device region 100H includes a channel region 100C, a channel region 100C along the length direction (such as Figure 8 A first isolation structure 110 is formed in the substrate 100 between the preset region 100S and the well region contact region 100P, and between the well region contact region 100P and the adjacent second device region 100L.

[0104] The substrate 100 is used to provide a platform for subsequent process steps.

[0105] In this embodiment, the substrate 100 is used to form a planar field effect transistor as an example, and the substrate 100 is a planar substrate. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0106] In some other embodiments, the substrate may also be a three-dimensional substrate according to the type of transistor actually formed.

[0107] A channel length of the first device is greater than a channel length of the second device, and an operating voltage of the first device is higher than an operating voltage of the second device.

[0108] In this embodiment, the first device includes one or both of a medium voltage device and a high voltage device, and the second device is a low voltage device. The operating voltages of the low voltage device, the medium voltage device, and the high voltage device increase in sequence. As an example, the operating voltage of the low voltage device is less than 1.5V, the operating voltage of the medium voltage device is 1V to 10V, and the operating voltage of the high voltage device is greater than 10V.

[0109] In this embodiment, the first device is a high voltage device and the second device is a low voltage device. Specifically, the second device is a core device.

[0110] It should be noted that the first device may be an NMOS transistor or a PMOS transistor. Similarly, the second device may also be an NMOS transistor or a PMOS transistor. As an example, the first device is an NMOS transistor, and the second device is a PMOS transistor.

[0111] In this embodiment, a well region (not shown) is formed in the substrate 100, and the well region has a different conductivity type from the channel of the transistor. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.

[0112] As an example, the first device is an NMOS transistor, and the well region of the first device region 100H is a P-type doped deep well region. Specifically, the well region of the first device region 100H is a high voltage device P-type doped deep well region, so that the first device can withstand a larger operating voltage.

[0113] As an example, the second device is a PMOS transistor, and the well region of the second device region 100L is an N-type doped well region.

[0114] The substrate 100 of the first device region 100H includes a channel region 100C. When the first device is in operation, a conductive channel is formed in the substrate 100 of the channel region 100C. Specifically, the channel region 100C is located in the well region.

[0115] In this embodiment, the direction of the length of the channel region 100C refers to: the direction of movement of carriers in the conductive channel when the device is working. Specifically, a first source-drain doped region is subsequently formed in the preset area 100S, and the first source-drain doped region includes a source region and a drain region respectively located on both sides of the polysilicon gate, and the direction from the drain region to the source region is the direction of the length of the channel region 100C. In this embodiment, the length direction of the channel region 100C is as follows: Figure 8 The direction perpendicular to the length direction of the channel region 100C is the width direction of the channel region 100C (as shown in FIG. Figure 8 shown in the Y direction).

[0116] The preset region 100S is used to form a first source-drain doping region. The preset region 100S is located at both sides of the channel region 100C along the length direction of the channel region 100C, and the preset region 100S is a long strip structure extending along the width direction of the channel region 100C.

[0117] The well contact region 100P is used to realize electrical connection between the well region and an external circuit or other interconnection structure. Specifically, a contact hole plug in contact with the well contact region 100P is subsequently formed above the well contact region 100P to provide a substrate potential for the substrate through the contact hole plug.

[0118] In this embodiment, the well contact region 100P is a closed ring structure, and is also used as a guard ring (GuardRing) for isolating external coupling noise.

[0119] The first isolation structure 110 is used to isolate the well contact region 100P from the first source-drain doped region formed subsequently, and is also used to achieve isolation between the well contact region 100P and adjacent devices. In this embodiment, the first isolation structure 110 located outside the well contact region 100P surrounds the well contact region 100P, and accordingly, the first isolation structure 110 located outside the well contact region 100P is also a ring structure.

[0120] In this embodiment, a second isolation structure 120 is further formed in the substrate 100 between the channel region 100C and the preset region 100S. The second isolation structure 120 is used to increase the moving path between the carriers and the conductive channel, thereby improving the withstand voltage capability of the first device.

[0121] Specifically, a first trench (not marked) is formed in the substrate 100 between the well region contact area 100P and the channel region 100C, and between the well region contact area 100P and the adjacent second device region 100L, a second trench (not marked) is formed in the substrate 100 between the channel region 100C and the preset area 100S, the first isolation structure 110 is located in the first trench, and the second isolation structure 120 is located in the second trench.

[0122] Accordingly, the first trench and the second trench are used to define an active area in the first device area 100H of the substrate 100 , that is, the substrate 100 of the first device area 100H isolated by the first trench and the second trench is an active area.

[0123] Specifically, in this embodiment, the channel region 100C, the preset region 100S, and the well region contact region 100P isolated by the first isolation structure 110 and the second isolation structure 120 are active areas (Active Area, AA).

[0124] In this embodiment, the first isolation structure 110 and the second isolation structure 120 are both shallow trench isolation (STI) structures. The first isolation structure 110 and the second isolation structure 120 are made of insulating materials, such as silicon oxide, silicon nitride or silicon oxynitride.

[0125] In this embodiment, a liner layer 105 is further formed between the first isolation structure 110 and the sidewall and bottom of the first trench, and between the second isolation structure 120 and the sidewall and bottom of the second trench.

[0126] The liner layer 105 is used to improve the interface quality of the bottom surface and the sidewall of the first trench and the second trench, thereby improving the formation quality of the first isolation structure 110 and the second isolation structure 120. As an example, the material of the liner layer 105 is silicon oxide.

[0127] In this embodiment, the substrate 100 further includes a third device region (not shown) for forming a third device, and the channel conductivity type of the third device is different from that of the second device. In this embodiment, the third device is also a low-voltage device, and the channel length of the third device is less than the channel length of the first device.

[0128] In this embodiment, the second device is a PMOS transistor, and the third device is a NMOS transistor accordingly.

[0129] In this embodiment, the substrate 100 further includes a functional area (not shown) for forming a functional structure. The functional structure includes a resistor structure, a capacitor structure, a diode, a triode, etc. As an example, the functional area is used to form a resistor structure.

[0130] refer to Fig.10 and Fig.11 , Fig.10 is a top view, Fig.11 for Fig.10 A local cross-sectional view along the length direction of the channel region shows that the polysilicon gate 200 is formed separately on the substrate 100 in the first device region 100H and the second device region 100L. The polysilicon gate 200 in the first device region 100H covers the channel region 100C.

[0131] The polysilicon gate 200 of the first device region 100H is used as a device gate structure of the first device, thereby controlling the opening or closing of the conductive channel of the first device. The polysilicon gate 200 of the second device region 100L is used as a dummy gate, thereby occupying a space position for the subsequent formation of a metal gate.

[0132] After forming an interlayer dielectric layer on the substrate 100 at the side of the polysilicon gate 200, the polysilicon gate 200 of the second device area 100L is removed to form a gate opening, and a metal gate is formed in the gate opening. The process of forming the metal gate generally includes a step of flattening the metal gate material, and the larger the size of the metal gate, the higher the probability of a depression problem on the top surface of the metal gate during the flattening process. Since the first device area 100H is used to form the first device, the channel length of the first device is greater than the channel length of the second device, and the gate size of the first device is correspondingly larger. Therefore, by making the first device adopt the polysilicon gate 200, avoiding the use of the metal gate in the first device, it is helpful to prevent the top surface depression of the metal gate caused by the larger gate size in the first device area 100H.

[0133] In this embodiment, the material of the polysilicon gate 200 is polysilicon.

[0134] In this embodiment, the polysilicon gate 200 located in the first device region 100H covers the substrate 100 in the channel region 100C, and also extends to cover a portion of the second isolation structure 120 .

[0135] In this embodiment, the steps of forming the polysilicon gate 200 include: forming a polysilicon gate material layer (not shown) on the substrate 100; forming a gate mask layer 205 on the polysilicon gate material layer; using the gate mask layer 205 as a mask, patterning the polysilicon gate material layer, retaining the polysilicon gate material layer on the substrate 100 located in the channel area 100C, and a portion of the polysilicon gate material layer on the substrate 100 located in the second device area 100L for use as the polysilicon gate 200.

[0136] The gate mask layer 205 is used as a mask for patterning the polysilicon gate material layer. In this embodiment, the material of the gate mask layer 105 is silicon nitride.

[0137] It should be noted that, in this embodiment, before forming the polysilicon gate material layer, the formation method further includes: forming a high-k gate dielectric material layer and a metal barrier material layer stacked sequentially from bottom to top on the substrate 100. Accordingly, in the process of patterning the polysilicon gate material layer, the high-k gate dielectric material layer and the metal barrier material layer are also patterned to form a high-k gate dielectric layer 202 and a metal barrier layer 203.

[0138] In this embodiment, the material of the high-k gate dielectric layer 202 is a high-k dielectric material. As an example, the material of the high-k gate dielectric layer 202 is HfO2.

[0139] In this embodiment, the metal barrier layer 203 is used to isolate the high-k gate dielectric layer 202 from the polysilicon gate 200, and to isolate the high-k gate dielectric layer 202 from the subsequently formed metal gate, so as to protect the high-k gate dielectric layer 202. At the same time, in the subsequent process of removing the polysilicon gate 200 of the second device region 100L, the metal barrier layer 203 is also used as an etching stop layer to reduce the probability of damage to the high-k gate dielectric layer 202. Moreover, after the metal gate is subsequently formed on the second device region 100L, the metal barrier layer 203 is also used to block the easily diffusible ions in the metal gate from diffusing into the high-k gate dielectric layer 202. Among them, the metal barrier layer 203 also has a certain influence on the gate work function of the second device.

[0140] The material of the metal barrier layer 203 includes one or both of titanium nitride (TiN) and silicon-doped titanium nitride (TiSiN). In this embodiment, the material of the metal barrier layer 203 is titanium nitride.

[0141] It should also be noted that, in the present embodiment, during the process of forming the polysilicon gate 200, a gate oxide layer 201 is also formed between the high-k gate dielectric layer 202 of the first device region 100H and the substrate 100, and an interface buffer layer 204 is also formed between the high-k gate dielectric layer 202 of the second device region 100H and the substrate 100, and the thickness of the interface buffer layer 204 is less than the thickness of the gate oxide layer 201.

[0142] The gate oxide layer 201 is used to isolate the polysilicon gate 200 from the channel of the first device, and the interface buffer layer 204 is used as an interface buffer layer between the high-k gate dielectric layer 202 and the second device region 100L substrate 100, which is beneficial to improving electron mobility, interface stability and device reliability.

[0143] The gate oxide layer 201 and the interface buffer layer 204 are made of silicon oxide or silicon oxynitride. In this embodiment, the gate oxide layer 201 and the interface buffer layer 204 are made of silicon oxide.

[0144] In this embodiment, for the convenience of illustration and description, only the interface buffer layer 204 and the gate mask layer 205 are illustrated in the cross-sectional view. In addition, in this embodiment, for the convenience of illustrating the device structure of the first device area 100H, only the position of the second device area 100L is illustrated in the top view. For the specific structure of the second device area 100L, please refer to the corresponding cross-sectional view.

[0145] refer to Figures 12 to 15 , a first source-drain doped region 130 (eg, Fig.15); forming a second source-drain doped region 240 (as shown in FIG. 1 ) in the substrate 100 on both sides of the polysilicon gate 200 of the second device region 100L; Fig.15 shown).

[0146] Combined with reference Figures 12 to 18 A support structure 300 (eg, Fig.18 shown).

[0147] Subsequent steps also include: forming an interlayer dielectric layer on the substrate 100 on the side of the polysilicon gate 200 to expose the top of the polysilicon gate 200 in the second device area 100L; removing the polysilicon gate 200 in the second device area 100L to form a gate opening in the interlayer dielectric layer; and forming a metal gate in the gate opening.

[0148] By forming a support structure 300 on the first isolation structure 110 exposed by the polysilicon gate 200, the support structure 300 can play a supporting role in the process of flattening the interlayer dielectric layer and the metal gate, so as to avoid over-grinding of the interlayer dielectric layer above the first isolation structure 110, which is not only conducive to improving the top surface depression and thickness reduction of the interlayer dielectric layer above the top surface of the preset area 100S and the well contact area 100P, but also, because the substrate 100 around the first source and drain doping area 130 and the well contact area 100P has the support structure 300 that can play a supporting role, the support The structure 300 can also protect the first source-drain doped region 130 and the well contact region 100P, which is beneficial to prevent the planarization treatment from contacting the top surface of the first source-drain doped region 130 and the well contact region 100P. The top surfaces of the first source-drain doped region 130 and the well contact region 100P are usually also formed with a metal silicide layer, which is correspondingly beneficial to prevent the planarization treatment from contacting the metal silicide layer located on the top surfaces of the first source-drain doped region 130 and the well contact region 100P, thereby helping to avoid metal contamination of the planarization processing machine; in summary, this embodiment is beneficial to improving the performance of the semiconductor structure and the production yield.

[0149] The support structure 300 is made of a material with relatively high hardness, so as to ensure that the support structure 300 can play a supporting and grinding blocking role in the subsequent flattening process of forming an interlayer dielectric layer and forming a metal gate. In this embodiment, the material of the support structure 300 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride and boron carbonitride.

[0150] It should be noted that, in this embodiment, the top surface of the support structure 300 is flush with the top surface of the polysilicon gate 200 of the second device region 100L, or the top surface of the support structure 300 is lower than the top surface of the polysilicon gate 200 of the second device region 100L.

[0151] In the process of planarization of forming the interlayer dielectric layer, it is usually necessary to expose the top surface of the polysilicon gate 200 of the second device area 100L, so as to facilitate the subsequent removal of the polysilicon gate 200 of the second device area 100L. In addition, the subsequent process of forming a metal gate in the second device area 100L includes: planarizing the metal gate material layer and removing the metal gate material layer located on the top surface of the interlayer dielectric layer. In this embodiment, the top surface of the support structure 300 is not higher than the top surface of the polysilicon gate 200 of the second device area 100L, so as to prevent adverse effects on the subsequent planarization process of forming the interlayer dielectric layer and forming the metal gate.

[0152] In this embodiment, an example is taken in which the top surface of the supporting structure 300 is lower than the top surface of the polysilicon gate 200 for description.

[0153] Along the direction of the normal line of the surface of the substrate 100, the height difference between the top surface of the support structure 300 and the top surface of the polysilicon gate 200 of the second device area 100L should not be too large. When the top surface of the support structure 300 is lower than the top surface of the polysilicon gate 200 of the second device area 100L, the excessive height difference will result in a correspondingly small thickness of the support structure 300, which will easily increase the risk of the support structure 300 being removed during the flattening process of forming the interlayer dielectric layer and forming the metal gate, and thus easily lead to poor support of the support structure 300. For this reason, in this embodiment, along the direction of the normal line of the surface of the substrate 100, the height difference between the top surface of the support structure 300 and the top surface of the polysilicon gate 200 of the second device area 100L is less than or equal to

[0154] As an example, along the direction of the surface normal of the substrate 100, the height difference between the top surface of the support structure 300 and the top surface of the polysilicon gate 200 of the second device region 100L is to

[0155] Specifically, in this embodiment, the thickness of the support structure 300 is 280 nm.

[0156] In this embodiment, along the width direction of the first isolation structure 110, the sidewall of the support structure 300 is indented relative to the sidewall on the same side of the first isolation structure 110. The sidewall of the support structure 300 is indented relative to the sidewall on the same side of the first isolation structure 110, thereby reserving process space for the overlay shift of the photolithography process for forming the support structure 300, so as to prevent the support structure 300 from being formed on the first source-drain doped region 130 and the well contact region 100P due to the overlay shift, and correspondingly ensure that in the subsequent metal silicide process, the metal layer can contact the entire top surface of the first source-drain doped region 130 and the well contact region 100P, thereby increasing the process window of the photolithography process for forming the support structure 300.

[0157] In order to ensure that the distance by which the side wall of the support structure 300 is retracted relative to the side wall on the same side of the first isolation structure 110 can compensate for the overlay offset of the photolithography process, and to ensure that the area of ​​the support structure 300 is not too small so that the support structure 300 can play a sufficient supporting role, in this embodiment, along the width direction of the first isolation structure 110, the side wall of the support structure 300 is retracted by 0.3μm to 0.4μm relative to the side wall on the same side of the first isolation structure 110.

[0158] The support structure 300 includes any one of a first support layer 310 and a second support layer 320 ; or, the support structure 300 includes a first support layer 310 and a second support layer 320 located on the first support layer 310 .

[0159] In this embodiment, the support structure 300 includes a first support 310 and a second support layer 320 located on the first support layer 310 as an example for description.

[0160] The steps of forming the first source-drain doping region 130 , the second source-drain doping region 240 , and the support structure 300 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0161] refer to Fig.12 , a source-drain epitaxial layer 140 is formed in the substrate 100 on both sides of the polysilicon gate 200 of the second device region 100L. The source-drain epitaxial layer 140 is used to form a second source-drain doped region through subsequent ion doping. The source-drain epitaxial layer 140 is also used to provide stress for the channel of the second device, thereby improving the mobility of carriers. In this embodiment, the source-drain epitaxial layer 140 is also doped with ions.

[0162] In this embodiment, the second device region 100L is used to form a PMOS transistor. The source-drain epitaxial layer 140 includes a stress layer doped with P-type ions. The material of the stress layer is SiGe. The stress layer provides compressive stress for the channel region of the PMOS transistor, thereby improving the carrier mobility of the PMOS transistor channel.

[0163] In this embodiment, the step of forming the source-drain epitaxial layer 140 includes: in the first device area 100H, forming a hard mask layer 150 on the top and side walls of the polysilicon gate 200 and the top surface of the substrate 100, the hard mask layer 150 exposing the polysilicon gate 200 and the top surface of the substrate 100 of the second device area 100L; forming the source-drain epitaxial layer 140 in the substrate 100 on both sides of the polysilicon gate 200 exposed by the hard mask layer 150.

[0164] In this embodiment, the substrate 100 also includes a third device region for forming a third device, the channel length of the third device is smaller than the channel length of the first device, and the channel conductivity type of the third device is different from the channel conductivity type of the second device; in the step of forming the hard mask layer 150, the hard mask layer 150 is also formed on the top surface and side wall of the polysilicon gate 200 in the third device region and the top surface of the substrate 100.

[0165] The hard mask layer 150 is used to protect the substrate 100 of the first device region 100H and the third device region to prevent the substrate 100 of the first device region 100H and the third device region from being affected by the formation of the source-drain epitaxial layer 140. In this embodiment, the process of forming the source-drain epitaxial layer 140 also includes a process of etching the substrate 100 on both sides of the polysilicon gate 200 of the second device region 100L to form a groove, and the hard mask layer 150 is also used as an etching mask for forming the groove.

[0166] In this embodiment, the material of the hard mask layer 150 is silicon nitride or silicon oxynitride.

[0167] In this embodiment, the method for forming the semiconductor structure further includes: in the step of forming the hard mask layer 150, forming a first inner sidewall 210 located on the sidewall of the polysilicon gate 200 of the second device region 100L. The first inner sidewall 210 is used to protect the sidewall of the polysilicon gate 200 of the second device region 100L, and is also used to define the formation position of the source and drain epitaxial layer 140.

[0168] In this embodiment, the steps of forming the hard mask layer 150 and the first inner sidewall 210 include: forming a hard mask material layer (not shown) on the top and sidewalls of the polysilicon gate 200 and the top surface of the substrate 100; removing the hard mask material layer on the top of the polysilicon gate 200 and the top surface of the substrate 100 located in the second device area 100L, and retaining the remaining hard mask material layer on the sidewall of the polysilicon gate 200 located in the second device area 100L for use as the first inner sidewall 210.

[0169] The hard mask material layer of the second device region 100L is etched by an anisotropic etching process until the top of the polysilicon gate 200 located in the second device region 100L and the hard mask material layer on the top surface of the substrate 100 on both sides of the polysilicon gate 200 are removed. Since the anisotropic etching process has a low etching rate in a direction perpendicular to the side wall of the polysilicon gate 200, a portion of the hard mask material layer located on the side wall of the polysilicon gate 200 in the second device region 100L is retained and used as the first inner sidewall 210.

[0170] Specifically, the step of forming the source-drain epitaxial layer 140 in the substrate 100 on both sides of the polysilicon gate 200 exposed by the hard mask layer 150 includes: using the hard mask layer 150 as a mask, forming grooves (not shown) in the substrate 100 on both sides of the polysilicon gate 200 of the second device area 100L; and forming the source-drain epitaxial layer 140 in the grooves.

[0171] In this embodiment, an epitaxial process is adopted to form a stress layer in the groove, and in the process of forming the stress layer, ions are self-doped in situ to form the source-drain epitaxial layer 140 .

[0172] refer to Fig.13 and Fig.14 , Fig.13 is a top view, Fig.14 for Fig.13 In the local cross-sectional view along the length direction of the channel region, a first supporting layer 310 is formed on the first isolation structure 110 exposed from the polysilicon gate 200 .

[0173] The subsequent step further includes performing ion doping on the source / drain epitaxial layer 140 , so that the source / drain epitaxial layer 140 doped with ions is used as the second source / drain doping region.

[0174] In this embodiment, the step of forming the first supporting layer 310 includes: after forming the source and drain epitaxial layer 140 and before ion doping the source and drain epitaxial layer 140, in the first device area 100H, removing the hard mask layer 150 located on the top of the polysilicon gate 200 and the top surface of the preset area 100S and the well area contact area 100P, and retaining the hard mask layer 150 located on the first isolation structure 110 for use as the first supporting layer 310.

[0175] By retaining the hard mask layer 150 on the first isolation structure 110 as the first supporting layer 310 , it is beneficial to improve the integration of the steps of forming the first supporting layer 310 with the existing process, thereby improving process compatibility and reducing costs.

[0176] In the present embodiment, in the first device area 100H, during the process of removing the hard mask layer 150 located on the top of the polysilicon gate 200 and the top surface of the preset area 100S and the well area contact area 100P, the formation method also includes: removing the hard mask layer 150 located on the polysilicon gate 200 and the top surface of the substrate 100 in the third device area, exposing the substrate 100 on both sides of the polysilicon gate 200 in the third device area.

[0177] The substrate 100 on both sides of the polysilicon gate 200 of the third device region is exposed, so as to form a third source-drain doped region in the substrate 100 on both sides of the polysilicon gate 200 of the third device region later.

[0178] In this embodiment, the step of removing the hard mask layer 150 on the top surface of the polysilicon gate 200 and the substrate 100 located in the third device area, and the top surface of the polysilicon gate 200 located in the first device area 100H, the preset area 100S and the top surface of the well contact area 100P includes: using a mask to form a mask layer to cover the polysilicon gate 200 and the source-drain epitaxial layer 140 of the second device area 100L and the preset area 100S and the well contact area 100P, and expose the hard mask layer 150 located on the top of the first isolation structure 110; using the mask layer as a mask, anisotropic etching process is adopted to etch the hard mask layer 150 until the polysilicon gate 200 and the top surface of the substrate 100 located in the third device area, and the hard mask layer 150 on the top surface of the polysilicon gate 200 located in the first device area 100H, the preset area 100S and the top surface of the well contact area 100P are removed.

[0179] In the present embodiment, in the process of forming the first supporting layer 310, the hard mask layer 150 on the top surface of the polysilicon gate 200 and the top surface of the substrate 100 located in the third device area, and the top surface of the polysilicon gate 200 located in the first device area 100H, the preset area 100S and the top surface of the well contact area 100P are removed. Therefore, in the process of forming the first supporting layer 310, only the pattern of the mask forming the mask layer needs to be adjusted. Accordingly, the process of forming the first supporting layer 310 does not require the use of an additional mask, which not only improves the integration and compatibility of the process of forming the first supporting layer 310 with the existing technology, but also helps to save costs and simplify the process flow.

[0180] It should be noted that, in this embodiment, the formation method also includes: in the first device area 100H, in the step of removing the hard mask layer 150 located on the top of the polysilicon gate 200 and the top surface of the preset area 100S and the well area contact area 100P, retaining the remaining hard mask layer 150 on the side wall of the polysilicon gate 200 located in the first device area 100H for use as a second inner sidewall.

[0181] The second inner sidewall 220 is used to protect the sidewall of the polysilicon gate 200 .

[0182] Specifically, the hard mask layer 150 is etched using an anisotropic etching process with the mask layer as a mask. Since the anisotropic etching process has a low etching rate in a direction perpendicular to the side wall of the polysilicon gate 200, a portion of the hard mask layer 150 located on the side wall of the polysilicon gate 200 in the first device area 100H and the third device area is retained to serve as the second inner sidewall 220.

[0183] refer to Fig.15 The formation method further includes: forming an outer sidewall 230 on the sidewalls of the first inner sidewall 210 and the second inner sidewall 220. The outer sidewall 230 is used to define the formation positions of the subsequent first source-drain doping region and the third source-drain doping region. As an example, the material of the outer sidewall 230 is silicon nitride.

[0184] Continue to refer Fig.15 , a first source-drain doped region 130 is formed in a preset area 100S on both sides of the polysilicon gate 200 of the first device region 100H; and a second source-drain doped region 240 is formed in the substrate 100 on both sides of the polysilicon gate 200 of the second device region 100.

[0185] In this embodiment, in the first device area 100H, after removing the hard mask layer 150 located on the top of the polysilicon gate 200 and the top surface of the preset area 00S and the well area contact area 100P, the first source and drain doping area 130 and the second source and drain doping area 240 are formed.

[0186] The first source-drain doped region 130 is used as a source region or a drain region of the first device. In this embodiment, the first device is an NMOS transistor, and the first source-drain doped region 130 is N-type doped. In other embodiments, when a PMOS transistor is formed, the first source-drain doped region is P-type doped.

[0187] In this embodiment, after forming the first supporting layer 310 , the forming method further includes: forming a third source-drain doped region (not shown) in the substrate 100 on both sides of the polysilicon gate 200 in the third device region.

[0188] The third source-drain doping region is used as a source region or a drain region of a third device. In this embodiment, the channel conductivity type of the third device is different from that of the second device, and accordingly, the doping type of the third source-drain doping region is different from that of the second source-drain doping region 240 .

[0189] Specifically, the third device is an NMOS device, and the third source and drain doping regions are correspondingly N-type doped.

[0190] In this embodiment, the channel conductivity type of the third device is the same as that of the first device, and therefore, the first source-drain doping region 130 and the third source-drain doping region are formed in the same step.

[0191] In this embodiment, ion doping is performed on the substrate 100 in the preset area 100S and the substrate 100 on both sides of the polysilicon gate 200 in the third device area to form the first source and drain doping area 130 and the third source and drain doping area respectively. Specifically, the ion doping is performed by an ion implantation process.

[0192] The second source-drain doped region 240 is used as a source region or a drain region of the second device. Specifically, the source-drain epitaxial layer 140 is ion-doped, so that the ion-doped source-drain epitaxial layer 140 is used as the second source-drain doped region 240. In this embodiment, the second device is a PMOS transistor, and the source-drain epitaxial layer 140 is doped with P-type ions.

[0193] In this embodiment, the channel conductivity types of the second device and the first device are different, and therefore, the first source-drain doped region 130 and the second source-drain doped region 240 are formed in different steps.

[0194] refer to Figures 16 to 18 In this embodiment, the support structure 300 includes a second support layer 320; after the first source-drain doping region 130 and the second source-drain doping region 240 are formed, the second support layer 320 is formed.

[0195] Specifically, in this embodiment, the second supporting layer 320 is formed on the first supporting layer 310 .

[0196] In this embodiment, the forming method further includes: in the step of forming the second supporting layer 320 , forming a silicide blocking layer (not shown) on the substrate 100 in the functional area.

[0197] By forming the silicide blocking layer simultaneously during the step of forming the second supporting layer 320 , the process steps of forming the second supporting layer 320 and the process steps of forming the silicide blocking layer are integrated, thereby improving process integration and process compatibility.

[0198] By forming a silicide barrier layer, the area where the metal silicide layer is desired to be formed is exposed, and the area where the metal silicide layer is not desired to be formed is protected. Specifically, in this embodiment, the silicide barrier layer is used to protect a portion of the functional area to prevent the metal silicide layer from being formed on a portion of the functional area.

[0199] In this embodiment, the material of the silicide barrier layer includes one or more of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the silicide barrier layer is the same as the material of the second supporting layer 320, that is, silicon nitride.

[0200] Specifically, the steps of forming the second supporting layer 320 and the silicide barrier layer include:

[0201] like Fig.16 As shown, a barrier material layer 160 is formed on the top and sidewalls of the polysilicon gate 200 and the top surface of the substrate 100. In this embodiment, the process of forming the barrier material layer 160 includes a chemical vapor deposition process or a furnace process. The chemical vapor deposition process and the furnace process are low in cost and simple to operate.

[0202] like Fig.17 and Fig.18 As shown, Fig.17 is a top view, Fig.18 for Fig.17 In the local cross-sectional view along the length direction of the channel region, the blocking material layer 160 located on the top and side walls of the polysilicon gate 200, the first source and drain doping region 130 and the well region contact region 100P, and the top surface of the second source and drain doping region 240 are removed, and the blocking material layer 160 located on the first isolation structure 110 is retained to serve as the second supporting layer 320, and the blocking material layer 160 located on a partial area of ​​the functional area is retained to serve as the silicide blocking layer.

[0203] The step of removing the blocking material layer 160 located on the top and sidewalls of the polysilicon gate 200, the first source / drain doping region 130 and the well contact region 100P, and the top surface of the second source / drain doping region 100L includes a process of forming a mask layer using a photomask. In the process of removing the blocking material layer 160 located on the top and sidewalls of the polysilicon gate 200, the first source / drain doping region 130 and the well contact region 100P, and the top surface of the second source / drain doping region 100L, the blocking material layer 160 located on the first isolation structure 110 is retained to serve as the second supporting layer 320. Therefore, only the pattern of the photomask needs to be adjusted so that the formed mask layer can cover the blocking material layer 160 located on the first isolation structure 110. This is not only conducive to integrating the step of forming the second supporting layer 320 with the step of forming the silicide blocking layer, but also does not require the use of an additional photomask, which is conducive to cost saving. In addition, compared with the prior art, no additional step of forming the second supporting layer 320 is performed, which is conducive to significantly improving process compatibility and process integration.

[0204] refer to Fig.19 and Fig. 20 , Fig.19 is a top view, Fig. 20 for Fig.19 A local cross-sectional view along the length direction of the channel region shows that after forming the second supporting layer 320 and the silicide blocking layer, a metal silicide layer 330 is formed on the top surfaces of the first source / drain doped region 130, the second source / drain doped region 240 and the well contact region 100P exposed by the silicide blocking layer.

[0205] Subsequently, contact hole plugs are formed on the top surfaces of the first source / drain doping region 130, the second source / drain doping region 240 and the well contact region 100P respectively. The metal silicide layer 330 is used to reduce the contact resistance between the first source / drain doping region 130, the second source / drain doping region 240 and the well contact region 100P and the corresponding contact hole plugs, thereby improving the performance of the semiconductor structure accordingly.

[0206] In this embodiment, the material of the metal silicide layer 330 may be a nickel silicon compound, a cobalt silicon compound or a titanium silicon compound.

[0207] refer to Fig.21 After forming the first source-drain doping region 130 and the second source-drain doping region 240 and the supporting structure 300, an interlayer dielectric layer 340 is formed on the substrate 100, and the interlayer dielectric layer 340 covers the side walls of the polysilicon gate 200 and the supporting structure 300, and exposes the top of the polysilicon gate 200 of the second device region 100L.

[0208] During the planarization process of forming the interlayer dielectric layer 340, the support structure 300 can play a supporting role to avoid over-grinding of the interlayer dielectric layer 340 above the first isolation structure 110, which is beneficial to improving the top surface depression and thickness reduction problems of the interlayer dielectric layer 340 above the first isolation structure 110, thereby improving the top surface flatness and height consistency of the interlayer dielectric layer 350. Moreover, the support structure 300 can also protect the first source and drain doping area 130 and the well area contact area 100P, which is beneficial to prevent the top surfaces of the first source and drain doping area 130 and the well area contact area 100P from being contacted during the planarization process, and correspondingly helps prevent the metal silicide layer 330 from being ground, and further helps avoid metal contamination of the planarization processing machine.

[0209] The interlayer dielectric layer 340 is used to isolate adjacent devices and exposes the top of the polysilicon gate 200 of the second device region 100L to facilitate removal of the polysilicon gate 200 of the second device region 100L.

[0210] In this embodiment, the interlayer dielectric layer 340 also exposes the top of the polysilicon gate 200 of the third device region, so as to facilitate the subsequent removal of the polysilicon gate 200 of the third device region.

[0211] The material of the interlayer dielectric layer 340 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 340 is silicon oxide.

[0212] In this embodiment, the step of forming the interlayer dielectric layer 340 includes: forming a dielectric material layer (not shown) on the substrate 100 to cover the top surface and side walls of the polysilicon gate 200 and the top surface and side walls of the support structure 300; and planarizing the dielectric material layer to remove the dielectric material layer on the top of the polysilicon gate 200 located in the second device area 100L.

[0213] In this embodiment, a deposition process is used to form the dielectric material layer. The deposition process includes a chemical vapor deposition process. In this embodiment, the planarization process includes a chemical mechanical planarization (CMP) process.

[0214] In this embodiment, during the process of planarizing the dielectric material layer, the gate mask layer 205, the first inner side wall 210, the second inner side wall 220 and the outer side wall 230 are also planarized. After the dielectric material layer is planarized, the top surface of the polysilicon gate 200 is exposed.

[0215] In this embodiment, for the convenience of illustration and description, only the interlayer dielectric layer 340 is illustrated in the cross-sectional view.

[0216] refer to Fig. 22 , the polysilicon gate 200 of the second device region 100L is removed, and a gate opening 350 is formed in the interlayer dielectric layer 340. The gate opening 350 is used as a first gate opening 350.

[0217] The first gate opening 350 is used to provide a space for forming a first metal gate. In this embodiment, the metal barrier layer 203 is used as a stop layer to remove the polysilicon gate 200 of the second device region 100L.

[0218] refer to Fig.23 , a metal gate 360 ​​is formed in the first gate opening 350. The metal gate 360 ​​is used as the first metal gate 360. The high-k gate dielectric layer 202, the metal barrier layer 203 and the first metal gate 360 ​​in the second device region 100L are used to form a metal gate structure. Since the channel length of the second device is small, the operating voltage of the second device is small. As the critical size of the device continues to shrink, the use of a metal gate structure is conducive to improving the short channel effect.

[0219] The first metal gate 360 ​​is used to control the opening and closing of the conductive channel of the second device. The material of the first metal gate 360 ​​is Al, Cu, Ag, Au, Pt, Ni, Ti or W. In this embodiment, the material of the first metal gate 360 ​​is Al.

[0220] In this embodiment, the step of forming the first metal gate 360 ​​includes: filling a metal gate material layer (not shown) in the first gate opening 350, and the metal gate material layer is also formed on the top of the interlayer dielectric layer 340; planarizing the metal gate material layer, and retaining the remaining metal gate material layer located in the first gate opening 350 for use as the first metal gate 360.

[0221] In this embodiment, the process of forming the metal gate material layer includes one or more of an atomic layer deposition process, a physical vapor deposition process, and an electrochemical plating process.

[0222] In this embodiment, the support structure 300 can play a supporting role during the planarization process of the metal gate material layer to avoid over-grinding of the interlayer dielectric layer 340 above the first isolation structure 110, which is beneficial to improving the top surface depression and thickness reduction problems of the interlayer dielectric layer 340 above the first source and drain doping regions 130 and the well region contact region 100P, and is also beneficial to preventing the planarization process from contacting the top surfaces of the first source and drain doping regions 130 and the well region contact region 100P, which is correspondingly beneficial to preventing the metal silicide layer 330 from being contacted by the planarization process, and further beneficial to avoiding metal contamination of the planarization process machine, thereby improving the performance of the semiconductor structure and the production yield.

[0223] In this embodiment, the planarization process includes a chemical mechanical planarization process.

[0224] In this embodiment, the silicide barrier layer located in the functional area still retains a portion of its thickness during the planarization process of forming the interlayer dielectric layer 340 and the first metal gate 360 ​​as an example. In other embodiments, the silicide barrier layer located in the functional area may be completely removed during the planarization process of forming the interlayer dielectric layer and the first metal gate.

[0225] In this embodiment, after forming the interlayer dielectric layer 340, the semiconductor structure forming method further includes: removing the polysilicon gate 200 located in the third device region, forming a second gate opening (not shown) in the interlayer dielectric layer 340 in the third device region; and forming a second metal gate in the second gate opening. The second metal gate is used to control the opening and closing of the conductive channel of the third device.

[0226] In the present embodiment, the channel conductivity types of the first device and the second device are different, and the work function material types contained in the first metal gate 360 ​​and the second metal gate are different. Therefore, the polysilicon gate 200 of the second device area 100L is removed and the polysilicon gate 200 of the third device area is removed in different steps, and the first metal gate 360 ​​and the second metal gate are formed in different steps, which helps to prevent the steps of forming the first metal gate 360 ​​and the second metal gate from affecting each other.

[0227] For the detailed description of the material and formation steps of the second metal gate, reference may be made to the corresponding description of the first metal gate 360 ​​, which will not be repeated here.

[0228] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a first device region for forming a first device and a second device region for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device, and the substrate of the first device region comprises a channel region, preset regions located at both sides of the channel region along the length direction of the channel region, and a well region contact region surrounding the channel region and the preset region; A first isolation structure is located in the substrate between the preset area and the well region contact area, and between the well region contact area and the adjacent second device area; A polysilicon gate covering the substrate in the channel region; A first source-drain doped region is located in the substrate in the preset area on both sides of the polysilicon gate; a metal gate, located on the substrate of the second device region; A second source-drain doped region is located in the substrate on both sides of the metal gate; a support structure located on top of the first isolation structure; An interlayer dielectric layer is located on the substrate and covers the polysilicon gate, the metal gate and the sidewall of the support structure.

2. The semiconductor structure according to claim 1, wherein: The supporting structure includes any one of a first supporting layer and a second supporting layer; or, the supporting structure includes a first supporting layer and a second supporting layer located on the first supporting layer.

3. The semiconductor structure according to claim 2, wherein: The support structure includes a first support layer; the second source-drain doped region includes a source-drain epitaxial layer.

4. The semiconductor structure according to claim 3, characterized in that The semiconductor structure further includes: a first inner sidewall located on the sidewall of the metal gate; a second inner sidewall located on the sidewall of the polysilicon gate; the second inner sidewall is made of the same material as the first inner sidewall and the first supporting layer.

5. The semiconductor structure according to claim 2, wherein: The support structure includes a second support layer; the substrate also includes a functional area for forming a functional structure; The semiconductor structure also includes: a silicide blocking layer, located on a partial area of ​​the functional area, the material of the silicide blocking layer is the same as the material of the second supporting layer; a metal silicide layer, located between the top surface of the first source and drain doped area exposed by the silicide blocking layer and the interlayer dielectric layer, between the top surface of the well area contact area and the interlayer dielectric layer, and between the top surface of the second source and drain doped area and the interlayer dielectric layer.

6. The semiconductor structure according to claim 1, wherein: Along the width direction of the first isolation structure, the sidewall of the support structure is retracted relative to the sidewall on the same side of the first isolation structure.

7. The semiconductor structure according to claim 6, wherein: Along the width direction of the first isolation structure, the sidewall of the support structure is retracted by 0.3 μm to 0.4 μm relative to the sidewall on the same side of the first isolation structure.

8. The semiconductor structure according to claim 1, wherein: The material of the support structure includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride oxycarbon, boron nitride and boron carbonitride.

9. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a second isolation structure located in the substrate between the channel region and the first source-drain doping region; the polysilicon gate covers the substrate of the channel region and also extends to cover a portion of the second isolation structure.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, comprising a first device region for forming a first device and a second device region for forming a second device, wherein the channel length of the first device is greater than the channel length of the second device, the substrate of the first device region comprises a channel region, preset regions located on both sides of the channel region along the length direction of the channel region and used to form first source and drain doping regions, and a well region contact region surrounding the channel region and the preset region, wherein a first isolation structure is formed in the substrate between the preset region and the well region contact region and between the well region contact region and an adjacent second device region; Forming a polysilicon gate on the substrate separately in the first device region and the second device region, wherein the polysilicon gate located in the first device region covers the channel region; forming a first source-drain doped region in a preset area on both sides of the polysilicon gate of the first device region; forming a second source-drain doped region in the substrate on both sides of the polysilicon gate of the second device region; forming a supporting structure on the first isolation structure exposed by the polysilicon gate; After forming the first source-drain doped region and the second source-drain doped region and the support structure, forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the sidewalls of the polysilicon gate and the support structure and exposes the top of the polysilicon gate of the second device region; removing the polysilicon gate of the second device region and forming a gate opening in the interlayer dielectric layer; A metal gate is formed in the gate opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: The supporting structure includes any one of a first supporting layer and a second supporting layer; or, the supporting structure includes a first supporting layer and a second supporting layer located on the first supporting layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The support structure includes the first support layer; The step of forming the second source-drain doped region includes: forming a source-drain epitaxial layer in the substrate on both sides of the polysilicon gate of the second device region; ion doping the source-drain epitaxial layer so that the source-drain epitaxial layer doped with ions is used as the second source-drain doped region; The step of forming the source-drain epitaxial layer comprises: forming a hard mask layer on the top and sidewalls of the polysilicon gate and the top surface of the substrate in the first device region, wherein the hard mask layer exposes the polysilicon gate and the top surface of the substrate in the second device region; forming the source-drain epitaxial layer in the substrate on both sides of the polysilicon gate exposed by the hard mask layer; The step of forming the first supporting layer comprises: after forming the source and drain epitaxial layer and before ion doping the source and drain epitaxial layer, in the first device region, removing the hard mask layer located on the top of the polysilicon gate and the top surface of the preset region and the well region contact region, and retaining the hard mask layer located on the first isolation structure to serve as the first supporting layer; In the first device region, after removing the hard mask layer located on the top of the polysilicon gate and the top surface of the preset region and the well region contact region, the first source and drain doping region is formed in the substrate of the preset region.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming a semiconductor structure further comprises: in the step of forming the hard mask layer, forming a first inner sidewall located on the sidewall of the polysilicon gate of the second device region; The steps of forming the hard mask layer and the first inner sidewall include: forming a hard mask material layer on the top and sidewalls of the polysilicon gate and the top surface of the substrate; removing the hard mask material layer on the top of the polysilicon gate and the top surface of the substrate located in the second device area, and retaining the remaining hard mask material layer on the sidewall of the polysilicon gate located in the second device area for use as the first inner sidewall.

14. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the semiconductor structure also includes: in the first device area, in the step of removing the hard mask layer located on the top of the polysilicon gate and the top surface of the preset area and the well area contact area, retaining the remaining hard mask layer on the side wall of the polysilicon gate located in the first device area for use as a second inner sidewall.

15. The method for forming a semiconductor structure according to claim 12, wherein: In the step of providing a substrate, the substrate further comprises a functional area for forming a functional structure; The support structure includes the second support layer; after forming the first source-drain doping region and the second source-drain doping region, the second support layer is formed; The method for forming a semiconductor structure further comprises: in the step of forming the second supporting layer, forming a silicide blocking layer on a partial area of ​​the functional area; After forming the second supporting layer and the silicide blocking layer and before forming the interlayer dielectric layer, a metal silicide layer is formed on the top surfaces of the first source / drain doped region, the second source / drain doped region and the well contact region exposed by the silicide blocking layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of forming the second supporting layer and the silicide barrier layer comprises: forming a barrier material layer on the top and sidewalls of the polysilicon gate and on the top surface of the substrate; The blocking material layer located on the top and sidewall of the polysilicon gate, the first source and drain doping region and the well region contact region, and the top surface of the second source and drain doping region is removed, and the blocking material layer located on the first isolation structure is retained to serve as the second supporting layer, and the blocking material layer located on a partial area of ​​the substrate of the functional area is retained to serve as the silicide blocking layer.

17. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing a substrate, a second isolation structure is further formed in the substrate between the channel region and the preset region; In the step of forming the polysilicon gate, the polysilicon gate located in the first device region covers the substrate of the channel region and also extends to cover a portion of the second isolation structure.

18. The method for forming a semiconductor structure according to claim 10, wherein: The top surface of the support structure is lower than the top surface of the polysilicon gate of the second device region, or the top surface of the support structure is flush with the top surface of the polysilicon gate of the second device region.

19. The method for forming a semiconductor structure according to claim 18, wherein: Along the direction of the substrate surface normal, the height difference between the top surface of the support structure and the top surface of the polysilicon gate of the second device region is to 20. The method for forming a semiconductor structure according to claim 10, wherein: Along the width direction of the first isolation structure, the sidewall of the support structure is retracted relative to the sidewall on the same side of the first isolation structure.

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