Semiconductor device with sti region

Abstract

This application relates to semiconductor devices with STI regions. Disclosed herein is an apparatus including a semiconductor substrate including: first and second circuit regions; a first trench extending in a first direction and formed between the first and second circuit regions, wherein the first trench includes a first inner wall positioned on a side of the first circuit region and a second inner wall positioned on a side of the second circuit region; and a plurality of second trenches extending in a second direction different from the first direction and formed in the first circuit region such that the second trenches communicate with the first trench at the first inner wall; and a first insulating film formed on the first and second inner walls such that the second inner wall is covered with the first insulating film without being exposed.

Description

Technical Field

[0001] Generally, this application relates to semiconductor devices. More specifically, this application relates to semiconductor devices having an STI region. Background Technology

[0002] In semiconductor devices such as DRAM (Dynamic Random Access Memory), there are cases where the memory cell array region and the peripheral circuit region are separated by STI (Shallow Trench Isolation). The STI is filled with an insulating material such as silicon oxide. It is desirable that the horizontal difference between the surface of the STI, formed from the insulating material such as silicon oxide, and the surface of the memory cell array region be small. Furthermore, it is preferable that the surface of the STI extends beyond the surface of the peripheral circuit region. This is because the top portion of the inner wall of the STI located on the side of the peripheral circuit region is exposed. If the surface of the STI does not extend beyond the surface of the peripheral circuit region, then due to the pretreatment used to form the gate dielectric film in the peripheral circuit region, the conductive material constituting the wiring pattern accumulates in the exposed portion. Summary of the Invention

[0003] In one aspect, this application provides an apparatus comprising: a semiconductor substrate including: first and second circuit regions; a first trench extending in a first direction and formed between the first and second circuit regions, wherein the first trench includes a first inner wall positioned on the side of the first circuit region and a second inner wall positioned on the side of the second circuit region; and a plurality of second trenches extending in a second direction different from the first direction and formed in the first circuit region such that each of the plurality of second trenches contacts the first trench at a first inner wall; and a first insulating film formed on the first and second inner walls such that the height of the first insulating film is equal to or greater than that of the second inner wall.

[0004] In another aspect, this application provides an apparatus comprising: a semiconductor substrate having a first trench formed between a memory cell array region and a peripheral circuit region, wherein a plurality of memory cells are formed on the memory cell array region and peripheral circuits are formed on the peripheral circuit region; and a first insulating film covering the inner wall and bottom surface of the first trench, wherein the peripheral circuit region does not contain the first insulating film.

[0005] In another aspect, this application provides a method comprising: forming a first insulating film on a semiconductor substrate over a first region, a second region, and a third region positioned between the first and second regions, and subsequently forming a second insulating film; reducing the thickness of the second insulating film over the first region such that the thickness of the second insulating film over the first region is less than the thickness of the second insulating film over the second region; removing the second insulating film over the third region; etching a trench in the semiconductor substrate in the third region using the second insulating film as a mask; removing the second insulating film over the first region so as to leave the second insulating film over the second region; and forming a third insulating film on the semiconductor substrate over the first region, the second region, and the trench formed in the third region such that the third insulating film covers the first insulating film without the second insulating film inserted therebetween in the first region, and such that the third insulating film covers the first insulating film while the second insulating film is inserted therebetween in the second region. Attached Figure Description

[0006] Figure 1A This is a partial schematic plan view of a semiconductor device according to the present disclosure, and Figure 1B It is along Figure 1A A schematic cross-section of line AA shown in the diagram;

[0007] Figure 2A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 2B It is along Figure 2A A schematic cross-section of line AA shown in the diagram;

[0008] Figure 3A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 3B It is along Figure 3A A schematic cross-section of line AA shown in the diagram;

[0009] Figure 4A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 4B It is along Figure 4A A schematic cross-section of line AA shown in the diagram;

[0010] Figure 5A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 5B It is along Figure 5A A schematic cross-section of line AA shown in the diagram;

[0011] Figure 6A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 6B It is along Figure 6A A schematic cross-section of line AA shown in the diagram;

[0012] Figure 7A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 7B It is along Figure 7A A schematic cross-section of line AA shown in the diagram;

[0013] Figure 8A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 8B It is along Figure 8A A schematic cross-section of line AA shown in the diagram;

[0014] Figure 9A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 9B It is along Figure 9A A schematic cross-section of line AA shown in the diagram;

[0015] Figure 10A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 10B It is along Figure 10A A schematic cross-section of line AA shown in the diagram;

[0016] Figure 11A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 11B It is along Figure 11A A schematic cross-section of line AA shown in the diagram;

[0017] Figure 12A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 12B It is along Figure 12A A schematic cross-section of line AA shown in the diagram;

[0018] Figure 13A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 13B It is along Figure 13A A schematic cross-section of line AA shown in the diagram;

[0019] Figure 14A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 14B It is along Figure 14A A schematic cross-section of line AA shown in the diagram;

[0020] Figure 15A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 15B It is along Figure 15A A schematic cross-section of line AA shown in the diagram;

[0021] Figure 16A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 16B It is along Figure 16A A schematic cross-section of line AA shown in the diagram;

[0022] Figure 17A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 17B It is along Figure 17A A schematic cross-section of line AA shown in the diagram;

[0023] Figure 18A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 18B It is along Figure 18A A schematic cross-section of line AA shown in the diagram;

[0024] Figure 19A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 19B It is along Figure 19A The schematic cross-section of line AA shown; and

[0025] Figure 20A This is a partial schematic plan view of the manufacturing process of the semiconductor device according to the present disclosure, and Figure 20B It is along Figure 20A The schematic cross-section of line AA shown is illustrated. Detailed Implementation

[0026] Various embodiments of the invention will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the invention that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of the invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0027] The semiconductor device according to this disclosure is, for example, a semiconductor memory device such as DRAM and includes a semiconductor substrate 10, said semiconductor substrate being divided into a memory cell array region 1, a peripheral circuit region 2, and an STI region 3, such as Figure 1BAs shown in the diagram, the STI region 3 has insulating films 23 to 25 embedded in trenches 11 formed on the semiconductor substrate 10. Insulating film 23 may comprise silicon oxide, insulating film 24 may comprise silicon nitride, and insulating film 25 may comprise SOG (spin-on glass) material. The STI region 3 extends in the y-direction and is positioned between the memory cell array region 1 and the peripheral circuit region 2. Different trenches 12 and 13 are also formed on the semiconductor substrate 10. Trench 12 extends in the x-direction above the memory cell array region 1 and the STI region 3. Although in Figure 1B The cross-section shown illustrates only one trench 12, but in practice, multiple trenches 12 extending in the x-direction are arranged in the y-direction. Word lines 31 are partially embedded in an associated trench 12. The top portion of each word line 31 is covered with an insulating film 32. An insulating film 21 comprising silicon oxide is embedded in the inner portion of the trench 13 and acts as an STI region for the unit transistor. Figure 1B In the cross-section shown, an insulating film 33 covers the surface of the semiconductor substrate 10 in the peripheral circuit region 2. The insulating film 33 is the gate dielectric film of the transistor formed in the peripheral circuit region 2.

[0028] Trench 11 has inner walls 11a and 11b, and a bottom surface 11c. Inner wall 11a is located on the boundary between memory cell array region 1 and STI region 3. Inner wall 11b is located on the boundary between peripheral circuit region 2 and STI region 3. Figure 1B As shown, the inner walls 11a and 11b are in contact with the insulating film 23. Specifically, the entire inner wall 11b, located on the side of the peripheral circuit area 2, is covered by the insulating film 23 and is not exposed.

[0029] The method for manufacturing a semiconductor device according to this embodiment will now be explained.

[0030] First, a hard mask 41 is formed on the semiconductor substrate 10, and the hard mask 41 is patterned to form an opening 41a on the hard mask 41, such as... Figure 2A and 2B As shown in the diagram. A hard mask 41 is then used as a mask to etch the semiconductor substrate 10, thereby forming a plurality of trenches 13 in the memory cell array region 1. Next, as shown in the diagram... Figure 3A and 3B As shown, after the removal of the hard mask 41, insulating films 21 and 22 are formed sequentially on the surface of the semiconductor substrate 10, as illustrated. Figure 4A and 4BAs shown in the diagram, insulating films 21 and 22 comprise silicon oxide and silicon nitride, respectively, and can be deposited using a CVD (chemical vapor deposition) method. The thickness of insulating film 22 can be greater than that of insulating film 21. The interior portion of trench 13 is thus filled with insulating film 22 comprising silicon oxide. DRAM cell transistors are formed in regions separated by trench 13.

[0031] Next, as Figure 5A and 5B As shown, a portion of the insulating film 22 located in the peripheral circuit region 2 is covered with resist 42, and the resist 42 is used as a mask to etch the insulating film 22, thereby reducing the film thickness of a portion of the insulating film 22 located in the memory cell array region 1. Therefore, the film thickness of the insulating film 22 on the memory cell array region 1 is less than the film thickness of the insulating film 22 on the peripheral circuit region 2. The edge of the resist 42 is located in the STI region 3, and steps are correspondingly formed in the insulating film 22 on the STI region 3. Next, after removing the resist 42, another resist 43 is formed covering the memory cell array region 1 and the peripheral circuit region 2, as shown. Figure 6A and 6B As shown in the diagram. Then, using resist 43 as a mask, the insulating film 22 is etched, thereby removing a portion of the insulating film 22 covering the STI region 3 to expose the insulating film 21. Next, after removing the resist 43, the insulating film 21 and the semiconductor substrate 10 are etched using the insulating film 22 as a mask, thereby forming trenches 11 in the STI region 3, as shown in the diagram. Figure 7A and 7B As shown in the diagram. Therefore, the inner wall 11a located on the side of the memory cell array region 1, the inner wall 11b located on the side of the peripheral circuit region 2, and the bottom surface 11c are exposed in the trench 11. Subsequently, silicon nitride is wet-etched to remove the insulating film 22 on the memory cell array region 1. Thus, the insulating film 21 is exposed on the memory cell array region 1, as shown in the diagram. Figure 8A and 8B As shown in the diagram. At this time, the wet etching conditions are set to prevent the insulating film 22 on the peripheral circuit area 2 from being completely removed.

[0032] Next, insulating films 23 and 24 are formed sequentially over the entire semiconductor substrate 10, as follows: Figure 9A and 9BAs shown in the diagram. Insulating films 23 and 24 comprise silicon oxide and silicon nitride, respectively, and can be deposited using a CVD method. The film thicknesses of insulating films 23 and 24 are set such that they do not completely fill the trench 11. Therefore, the memory cell array region 1, the peripheral circuit region 2, and the inner walls of the trench 11 are covered with stacked films comprising insulating films 23 and 24. Since insulating film 22 has already been removed from the memory cell array region 1, insulating films 23 and 21 are stacked directly without insulating film 22 inserted between them. Conversely, since insulating film 22 remains on the peripheral circuit region 2, insulating films 21 and 23 are stacked with insulating film 22 inserted between them. Next, an insulating film 25 comprising SOG material is formed over the entire semiconductor substrate 10, as shown in the diagram. Figure 10A and 10B As shown in the diagram, the thickness of the insulating film 25 is set to be sufficient to fill the trench 11. Next, the insulating film 25 is polished using a CMP (chemical mechanical polishing) method to expose the insulating film 23 on the peripheral circuit area 2, as shown. Figure 11A and 11B As shown in the diagram. Specifically, after performing CMP using an insulating film 24 containing silicon nitride as a stop on the peripheral circuit region 2, CMP is performed in a state where there is no selectivity between silicon nitride and silicon oxide, and the CMP ends when the insulating film 23 containing silicon oxide is exposed. Therefore, a state is obtained where the insulating film 24 is removed from the peripheral circuit region 2 and left on the memory cell array region 1.

[0033] Next, dry etching is performed under conditions of high etching rate for silicon oxide, such as... Figure 12A and 12B As shown in the diagram, the insulating film 25 on the memory cell array region 1 is removed to expose the insulating film 24 containing silicon nitride, and the insulating film 23 on the peripheral circuit region 2 is removed to expose the insulating film 22 containing silicon nitride. At this time, the etching conditions are set such that the top surface 23t of the insulating film 23 covering the inner wall 11b of the trench 11 is higher than the upper surface of the insulating film 21. Next, dry etching is performed under conditions of a high etching rate for silicon nitride, such as... Figure 13A and 13BAs shown in the diagram, the insulating film 24 on the memory cell array region 1 is removed to expose the silicon oxide-containing insulating film 23, and the insulating film 22 on the peripheral circuit region 2 is removed to expose the silicon oxide-containing insulating film 21. Therefore, the insulating film 23 covering the inner wall 11b of the trench 11 is introduced to a state where the top surface 23t extends from the surface of the insulating film 21. A portion of the top surface 24tb of the insulating film 24 covering the inner wall 11b is lower than a portion of the top surface 24ta of the insulating film 24 covering the inner wall 11a. The upper surface of the insulating film 23 on the memory cell array region 1 and the upper surface of the insulating film 25 on the STI region 3 are substantially in the same plane.

[0034] Next, in such Figure 14A and 14B After the hard mask 44 shown is formed over the entire semiconductor substrate 10, openings are formed on the hard mask 44 in the form of strips. Next, the hard mask 44 formed on the peripheral circuit region 2 is covered with a photoresist 45, such as... Figure 15A and 15B As shown in the diagram, the hard mask 44 formed on the memory cell array region 1 is exposed without being covered by the resist 45. The edges of the resist 45 are positioned on the STI region 3. Next, after removing the resist 45, dry etching is performed in this state using the hard mask 44 as a mask, thereby forming multiple trenches 12 in the memory cell array region 1, as shown in the diagram. Figure 16A and 16B As shown in the diagram. This dry etching is performed under conditions where the selectivity difference between silicon, silicon oxide, and silicon nitride is small. Therefore, the insulating films 21 and 23 containing silicon oxide and the insulating film 24 containing silicon nitride are also etched, and trench 12 contacts trench 11 at the inner wall 11a. Because as Figure 13B As shown, the upper surfaces of the insulating film 23 on the memory cell array region 1 and the upper surfaces of the insulating film 25 on the STI region 3 form substantially the same plane, so the widths of the trenches 12 formed in the memory cell array region 1 and the STI region 3 will be substantially uniform. That is, if there is a difference between the height of the upper surface of the insulating film 23 on the memory cell array region 1 and the height of the upper surface of the insulating film 25 on the STI region 3, the width of the trenches 12 will unfavorably change at the boundary between the memory cell array region 1 and the STI region 3. However, when the heights of the upper surfaces of the insulating film 23 on the memory cell array region 1 and the upper surfaces of the insulating film 25 on the STI region 3 are substantially equal, such changes in the width of the trenches 12 can be prevented.

[0035] Next, in such Figure 17A and 17BAs shown, after the hard mask 44 is removed, the semiconductor substrate 10 exposed on the inner wall of the trench 12 is thermally oxidized to form a silicon oxide film 26. This silicon oxide film 26 serves as the gate electrode of the unit transistor. Word lines 31 are then embedded in the trench 12. Next, the upper portion of the word lines 31 is covered with an insulating film 32, as shown... Figure 18A and 18B As shown in the diagram. Because the width of each of the trenches 12 is substantially uniform, damage to the word lines 31 or similar issues due to a reduction in the width of the trenches 12 relative to the design value will not occur. Next, the memory cell array region 1 is covered with resist 46, as shown in the diagram. Figure 19A and 19B As shown in the diagram, the peripheral circuit region 2 is exposed without being covered by resist 46. The edges of resist 46 are positioned on the STI region 3. Next, etching is performed using resist 46 as a mask, thereby removing the insulating films 21 and 32 formed on the peripheral circuit region 2, as shown in the diagram. Figure 20A and 20B As shown in the diagram, the semiconductor substrate 10 is therefore exposed in the peripheral circuit region 2. At this point, over-etching is required to prevent the insulating film 21 from remaining on the surface of the semiconductor substrate 10. However, because in embodiments of the invention, the insulating film 23 covering the inner wall 11b of the trench 11 is in a state where the top surface 23t protrudes from the surface of the insulating film 21, the inner wall 11b of the trench 11 is not exposed and can remain covered with the insulating film 21, even when over-etching is performed to remove the insulating film 21.

[0036] Subsequently, during the thermal oxidation process, the semiconductor substrate 10 exposed in the peripheral circuit region 2 is oxidized and an insulating film 33 is formed, such as... Figure 1A and Figure 1B As shown in the diagram. Subsequently, wiring patterns and the like are formed. Because the inner wall 11b of the trench 11, as described above, is not exposed and remains covered with the insulating film 21, the metallic material constituting the wiring pattern and the like does not accumulate on the inner wall 11b of the trench 11.

[0037] While the invention has been disclosed in certain preferred embodiments and examples, those skilled in the art will understand that the invention extends beyond the specifically disclosed embodiments to other alternative embodiments and / or the invention and its obvious modifications and equivalents. Furthermore, other modifications within the scope of the invention will be apparent to those skilled in the art based on this disclosure. Various combinations or sub-combinations of specific features and aspects of the embodiments are also contemplated and will still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form different modes of the disclosed invention. Therefore, it is intended that the scope of at least some of the invention disclosed herein should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor memory device, comprising: A semiconductor substrate having a first trench formed between a memory cell array region and a peripheral circuit region, wherein a plurality of memory cells are formed on the memory cell array region and peripheral circuits are formed on the peripheral circuit region; as well as A first insulating film covers the inner wall and bottom surface of the first trench, wherein the peripheral circuit area does not contain the first insulating film. The inner wall includes a first inner wall positioned on the boundary between the memory cell array region and the first trench, and a second inner wall positioned on the boundary between the peripheral circuit region and the first trench. The first insulating film continuously covers the second inner wall, the bottom surface, the first inner wall, and the memory cell array area, wherein the top surface of the first insulating film covering the second inner wall is higher than the top surface of the first insulating film covering the first inner wall.

2. The semiconductor memory device of claim 1, further comprising a second insulating film formed in the first trench to cover the first and second inner walls and the bottom surface of the first trench such that the first insulating film is located between the second insulating film and the first and second inner walls and the bottom surface of the first trench.

3. The semiconductor memory device according to claim 2, The first insulating film comprises silicon oxide, and The second insulating film comprises silicon nitride.

4. The semiconductor memory device according to claim 3, The second insulating film includes a first segment covering the first inner wall and a second segment covering the second inner wall, and The top end of the second segment of the second insulating film is positioned below the top end of the first segment of the second insulating film.

5. The semiconductor memory device of claim 4, further comprising a plurality of signal lines, The semiconductor substrate further has a plurality of second trenches extending over the memory cell array region and the first trench, and Each of the signal lines is at least partially embedded in an associated one of the second trenches.

6. The semiconductor memory device of claim 5, wherein the signal lines are word lines for accessing the memory cells.

7. The semiconductor memory device of claim 5, wherein the top portion of each of the signal lines is covered with a third insulating film, and wherein the peripheral circuit area is covered with a fourth insulating film.

8. The semiconductor memory device of claim 1, wherein the first inner wall of the first trench is in direct contact with the memory cell array region, and the second inner wall of the first trench is in direct contact with the peripheral circuit region.

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