Semiconductor device and driving method thereof

Abstract

Embodiments provide a semiconductor device capable of reducing loss and a driving method thereof. The semiconductor device of the embodiments includes a first electrode, a first semiconductor layer provided on the first electrode in a diode region, a second semiconductor layer provided on the first electrode in an IGBT region, a third semiconductor layer provided on the first semiconductor layer and the second semiconductor layer across the diode region, a boundary region, and the IGBT region, a fourth semiconductor layer provided on the third semiconductor layer in the boundary region and the IGBT region, a fifth semiconductor layer provided on the third semiconductor layer and the fourth semiconductor layer, a second electrode provided in the diode region, a third electrode provided in the IGBT region, and a fourth electrode extending from an upper surface of the fifth semiconductor layer toward the third semiconductor layer in the boundary region and electrically insulated from the third electrode.

Description

[0001] This application enjoys priority to Japanese Patent Application No. 2021-38456 (filed March 10, 2021) and U.S. Patent Application No. 17 / 470692 (filed September 9, 2021). This application incorporates the entire contents of the aforementioned basic applications by reference. Technical Field

[0002] The implementation methods relate to semiconductor devices and driving methods thereof. Background Technology

[0003] Previously, RC-IGBTs (Reverse Conducting IGBTs) with diode and IGBT (Insulated Gate Bipolar Transistor) regions were known. In RC-IGBTs, the return current from the emitter side to the collector side of the IGBT region can flow into the diode region.

[0004] In an RC-IGBT diode region where return current flows through it (i.e., the diode region is conducting), the greater the injection of charge carriers (electrons or holes) into the base layer, the lower the forward voltage of the diode region. A lower forward voltage results in lower constant losses in the diode region. Conversely, more charge carriers in the base layer lead to greater recovery losses during diode recovery. Thus, the constant losses and recovery losses in the diode region represent a trade-off. Summary of the Invention

[0005] The embodiments provide a semiconductor device and a driving method thereof that can reduce losses.

[0006] The semiconductor device according to the relevant technical solution is a semiconductor device having a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, comprising: a first electrode disposed throughout the diode region, the boundary region, and the IGBT region; a first semiconductor layer of a first conductivity type disposed on the first electrode in the diode region; a second semiconductor layer of a second conductivity type disposed on the first electrode in the IGBT region; and a third semiconductor layer of a first conductivity type disposed throughout the diode region, the boundary region, and the IGBT region, located on the first semiconductor layer in the diode region and in the IGBT region. The impurity concentration of the third semiconductor layer is lower than that of the first semiconductor layer, located on the second semiconductor layer. The fourth semiconductor layer, of the first conductivity type, is disposed on the third semiconductor layer in the boundary region and the IGBT region, and has a higher impurity concentration than the upper portion of the third semiconductor layer. The fifth semiconductor layer, of the second conductivity type, is disposed on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region. The sixth semiconductor layer, of the first conductivity type, is disposed on the upper portion of the fifth semiconductor layer in the IGBT region. The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region. The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region, and is adjacent to the sixth, fifth, fourth, and third semiconductor layers in the first direction; the fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the boundary region, and is adjacent to the fifth, fourth, and third semiconductor layers in the first direction, and is electrically insulated relative to the third electrode; the fifth electrode is provided with... On the aforementioned fifth semiconductor layer: a first insulating film is disposed between the aforementioned second electrode and the aforementioned fifth semiconductor layer, and between the aforementioned second electrode and the aforementioned third semiconductor layer; a second insulating film is disposed between the aforementioned third electrode and the aforementioned fifth electrode, between the aforementioned third electrode and the aforementioned sixth semiconductor layer, between the aforementioned third electrode and the aforementioned fifth semiconductor layer, between the aforementioned third electrode and the aforementioned fourth semiconductor layer, and between the aforementioned third electrode and the aforementioned third semiconductor layer; and a third insulating film is disposed between the aforementioned fourth electrode and the aforementioned fifth electrode, between the aforementioned fourth electrode and the aforementioned fifth semiconductor layer, between the aforementioned fourth electrode and the aforementioned fourth semiconductor layer, and between the aforementioned fourth electrode and the aforementioned third semiconductor layer.

[0007] The driving method of the relevant technical solution is the driving method of the aforementioned semiconductor device. The first conductivity type is n-type, and the second conductivity type is p-type. In the conducting state of the diode region, a negative voltage relative to the second electrode is applied to the fourth electrode within the boundary region. Before the diode region recovers, a positive voltage relative to the second electrode is applied to the fourth electrode. During the reverse recovery current flowing through the diode region, a negative voltage relative to the second electrode is applied to the fourth electrode.

[0008] The driving method of the relevant technical solution is the driving method of the aforementioned semiconductor device. The first conductivity type is p-type, and the second conductivity type is n-type. In the conducting state of the diode region, a positive voltage relative to the second electrode is applied to the fourth electrode within the boundary region. Before the diode region recovers, a negative voltage relative to the second electrode is applied to the fourth electrode. During the reverse recovery current flowing through the diode region, a positive voltage relative to the second electrode is applied to the fourth electrode. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0010] Figure 2 This is a circuit diagram showing a half-bridge circuit incorporating the semiconductor device of the first embodiment.

[0011] Figure 3 (a) represents time on the horizontal axis and voltage on the vertical axis. Figure 2 The graph shows the time-varying voltage between the gate electrode and emitter electrode of the IGBT region in the first semiconductor device. Figure 3 (b) is a graph showing the time variation of the voltage between the gate electrode and the emitter electrode in the boundary region of the first semiconductor device, with time on the horizontal axis and voltage on the vertical axis. Figure 3 (c) represents time on the horizontal axis and voltage on the vertical axis. Figure 2 The graph shows the time-varying voltage between the gate electrode and emitter electrode of the IGBT region in the second semiconductor device. Figure 3 (d) is a graph showing the time variation of the voltage between the gate electrode and the emitter electrode in the boundary region of the second semiconductor device, with time on the horizontal axis and voltage on the vertical axis. Figure 3 (e) is a graph showing the time-varying voltage between the collector and emitter electrodes and the time-varying collector current of the first semiconductor device, with time on the horizontal axis and voltage and current on the vertical axis. Figure 3(f) is a graph showing the time variation of the voltage between the collector electrode and the emitter electrode of the second semiconductor device, with time on the horizontal axis and voltage and current on the vertical axis.

[0012] Figure 4 (a)~ Figure 4 (c) is a schematic diagram representing the action of the boundary region.

[0013] Figure 5 (a) is a graph showing the relationship between the time-varying current flowing through the diode region and the boundary region and the time-varying voltage between the gate and emitter electrodes in the boundary region, with time on the horizontal axis and voltage and current on the vertical axis. Figure 5 (b) takes time on the horizontal axis and current on the vertical axis. Figure 5 (a) is an enlarged portion enclosed by the dashed line A, showing the time variation of the current flowing through the diode region and the boundary region in the first embodiment and the time variation of the current flowing through the diode region and the boundary region in the reference example.

[0014] Figure 6 This is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment.

[0015] Figure 7 This is a cross-sectional view showing a second variation of the semiconductor device according to the first embodiment.

[0016] Figure 8 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0017] Figure 9A This is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment.

[0018] Figure 9B This is a top view showing a first modified example of the semiconductor device according to the second embodiment.

[0019] Figure 10 This is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment.

[0020] Figure 11 This is a cross-sectional view showing the semiconductor device according to the third embodiment.

[0021] Figure 12 This is a cross-sectional view showing the semiconductor device according to the fourth embodiment.

[0022] Figure 13 This is a cross-sectional view showing the semiconductor device according to the fifth embodiment. Detailed Implementation

[0023] The following is a reference to the appendix. Figure 1 Each embodiment will be described below. Furthermore, the accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc., may not necessarily be the same as in reality. Moreover, even when representing the same part, there may be cases where the dimensions or ratios are represented differently depending on the accompanying drawings. Furthermore, in this specification and in each drawing, the same reference numerals are assigned to the same elements as those described in the previously shown figures, and detailed descriptions are appropriately omitted.

[0024] Furthermore, to facilitate understanding, an orthogonal XYZ coordinate system will be used to illustrate the configuration and structure of each part. The X-axis, Y-axis, and Z-axis are mutually orthogonal. Additionally, the direction in which the X-axis extends is designated as the "X direction," the direction in which the Y-axis extends is designated as the "Y direction," and the direction in which the Z-axis extends is designated as the "Z direction." Furthermore, to facilitate understanding, the direction of the arrow in the Z-direction is designated upwards, and its opposite direction is designated downwards; however, these directions are independent of the direction of gravity.

[0025] Furthermore, in the following descriptions, + and - indicate the relative levels of impurity concentration for each conductivity type. Specifically, descriptions with "+" indicate a relatively higher impurity concentration compared to descriptions with "-". Furthermore, descriptions without "+" or "-" indicate a relatively higher impurity concentration compared to descriptions with "+", and a relatively lower impurity concentration compared to descriptions with "-". Here, in cases where each region includes both donor and acceptor impurities, "impurity concentration" refers to the net impurity concentration after these impurities cancel each other out.

[0026] <First Implementation>

[0027] First, the first embodiment will be described.

[0028] Figure 1 This is a cross-sectional view showing the semiconductor device according to this embodiment.

[0029] The semiconductor device 100 in this embodiment is an RC-IGBT. In the semiconductor device 100, a diode region S1, an IGBT region S3, and a boundary region S2 located between the diode region S1 and the IGBT region S3 are provided.

[0030] In this embodiment, the semiconductor device 100 includes a lower electrode 110 and an n + Type 111, p + The n-type collector layer 112, the n-type layer 113, the n-type barrier layer 115, the p-type layer 116, and the n-type barrier layer 117 are all present in the n-type collector layer. +The semiconductor device 100 includes an emitter layer 117, an internal electrode 122, a gate electrode 131, an internal electrode 132, a gate electrode 141, an upper electrode 150, and multiple insulating films 161, 162, 163, and 164. The various parts of the semiconductor device 100 will be described in detail below.

[0031] The lower electrode 110 is made of a conductive material such as a metal. The lower electrode 110 is provided over approximately the entire area of ​​the lower surface of the semiconductor device 100. That is, the lower electrode 110 is provided throughout the diode region S1, the boundary region S2, and the IGBT region S3. The lower electrode 110 functions as a cathode electrode in the diode region S1 and as a collector electrode in the IGBT region S3.

[0032] n + In this embodiment, the cathode layer 111 is disposed in the portion of the lower electrode 110 where the diode region S1 and the boundary region S2 are located.

[0033] p + In this embodiment, the collector layer 112 is disposed in the portion of the lower electrode 110 where the IGBT region S3 is located, and is not disposed in the diode region S1 and the boundary region S2. In other words, in this embodiment, from n + Type 111 cathode layer and p + The boundary of the collector layer 112 of the type faces the diode region S1 and is a certain region, which is the boundary region S2.

[0034] The length D1 of the boundary region S2 in the X direction from the diode region S1 toward the IGBT region S3 is not particularly limited, but it is preferably shorter than the distance D2 between the upper electrode 150 and the lower electrode 110.

[0035] An n-type layer 113 is disposed throughout the diode region S1, the boundary region S2, and the IGBT region S3. Furthermore, in this embodiment, the n-type layer 113 is disposed in the diode region S1 and the boundary region S2 in an n-type configuration. + On the cathode layer 111 of the type, a p is configured in the IGBT region. + On the collector layer 112 of the type.

[0036] The n-type layer 113 has n-type buffer regions 114a and n － The base region 114b of the type.

[0037] An n-type buffer region 114a is provided throughout the diode region S1, the boundary region S2, and the IGBT region S3. Furthermore, in this embodiment, the n-type buffer region 114a is disposed in the diode region S1 and the boundary region S2. +On the cathode layer 111 of the type, a p is configured in the IGBT region. + On the n-type collector layer 112. The impurity concentration of the n-type buffer region 114a is higher than that of the n-type. + The n-type cathode layer 111 has a low impurity concentration. However, it is also possible to omit the n-type buffer region in the semiconductor device.

[0038] n － The base region 114b of the n-type diode is disposed on the buffer region 114a within the diode region S1, the boundary region S2, and the IGBT region S3. － The impurity concentration in the base region 114b of the n-type is lower than that in the buffer region 114a of the n-type.

[0039] The n-type barrier layer 115 is disposed in the boundary region S2 and the IGBT region S3. － The upper part of the base region 114b of the n-type diode. In this embodiment, the n-type blocking layer 115 is not provided in the diode region S1. The impurity concentration of the n-type blocking layer 115 is higher than that of the n-type diode. － The base region 114b of the n-type layer has a high impurity concentration. That is, the impurity concentration of the n-type barrier layer 115 is higher than the impurity concentration of the upper part of the n-type layer 113.

[0040] A p-type layer 116 is disposed in the diode region S1, the boundary region S2, and the IGBT region S3. The p-type layer 116 is configured in the diode region S1 at n... － On the base region 114b of the type, with n － The base region 114b of the n-type layer is connected to the base region 114b. In addition, the p-type layer 116 is disposed on the n-type barrier layer 115 in the boundary region S2 and the IGBT region S3, and is connected to the n-type barrier layer 115.

[0041] p-type layer 116 has a p-type region 116a and multiple p-type regions. + Type 116b. Type 116a is configured in diode region S1 at n － On the base region 114b of the type, with n － The p-type region 116a is connected to the base region 114b of the diode. Furthermore, the p-type region 116a is disposed on the n-type barrier layer 115 in the boundary region S2 and the IGBT region S3, and is connected to the n-type barrier layer 115. The p-type region 116a functions as the anode layer of the p-type diode in the diode region S1 and as the base layer of the p-type diode in the IGBT region S3.

[0042] Each p + Region 116b of type p is located above region 116a of type p. Multiple p... + Regions 116b of type 116b are separated from each other in the X direction.+ Region 116b of type 116b serves as p in diode region S1 + The anode layer of the type functions as a p in the IGBT region S3. + The contact layer of this type performs its function.

[0043] In this embodiment, each p in the boundary region S2 is set as follows: + The length L1 of region 116b in the X direction and the p in diode region S1 + The length L2 in the X direction of region 116b of type S2 is approximately equal. Furthermore, in this embodiment, each p in the boundary region S2 is provided... + The length of region 116b in the Y direction of type is the same as that of each p in diode region S1. + The lengths of region 116b in the Y direction are approximately equal. Therefore, when viewed from above, i.e., in the direction from the upper electrode 150 toward the lower electrode 110, each p in the boundary region S2... + The area of ​​region 116b of type and each p in diode region S1 + The areas of region 116b of type 116b are approximately equal. However, suppose that each p in the boundary region... + The length of the region in the X direction of the type is related to the p-values ​​in the diode region. + The relationship between the lengths of the region in the X direction and the p values ​​in the boundary region. + The length of the region in the Y direction of the type is related to the p-values ​​in the diode region. + The length relationship of the region in the Y direction is not limited to the above.

[0044] n + The emitter layer 117 is disposed on the upper part of the p-type layer 116 in the IGBT region S3, and is not disposed in the diode region S1 and the boundary region S2.

[0045] p + Type 112 collector layer, type n buffer region 114a, n － The base region 114b of the n-type, the barrier layer 115 of the n-type, the layer 116 of the p-type, and the n-type layer + The emitter layer 117 of the type contains semiconductor materials such as silicon.

[0046] Multiple trenches T1 are formed in the diode region S1. The multiple trenches T1 are arranged in the X direction. Each trench T1 extends from the upper surface of the p-type layer 116, more specifically from each p-type layer 116... + The upper surface of region 116b of type extends to n － The base region 114b of the type. The lower end of each trench T1 is located at a ratio of n －The lower surface of the base region 114b of the type is located at the top.

[0047] An internal electrode 122 is disposed within each trench T1. Each internal electrode 122 is made of a conductive material such as a metal. Each internal electrode 122 extends from the upper surface of the p-type layer 116, more specifically from each p-type layer 116. + The upper surface of region 116b of type extends to n － The base region 114b of the type. The lower end of each internal electrode 122 is located at a position greater than n. － The lower surface of the base region 114b of the type is located at the top. Each internal electrode 122 is connected to the p-type layer 116 and the n-type layer. － The base regions 114b of the type are adjacent in the X direction.

[0048] Multiple trenches T2a are provided in the IGBT region S3. Additionally, in Figure 1 The text represents one of a plurality of trenches T2a. The trenches T2a are arranged in the X direction. Each trench T2a starts from n... + The upper surface of the emitter layer 117 extends to n － The base region 114b of the type. The lower end of each trench T2a is located at a ratio of n － The lower surface of the base region 114b of the type is located at the top.

[0049] A gate electrode 131 is disposed within each trench T2a. Each gate electrode 131 is formed of a conductive material such as a metal. Each gate electrode 131 is located from n + The upper surface of the emitter layer 117 extends to n － The base region 114b of the type. The lower end of each gate electrode 131 is located at a ratio of n － The lower surface of the base region 114b of the type is located at the top. Each gate electrode 131 and n + The emitter layer 117, p-type layer 116, n-type blocking layer 115 and n-type... － The base regions 114b of the type are adjacent in the X direction.

[0050] Furthermore, a trench T2b is provided in the IGBT region S3. The trench T2b is located on the boundary region S2 side, which is closer to the multiple trenches T2. The trench T2b extends from the upper surface of the p-type layer 116 to the n-type layer. － The base region 114b of the type. The lower end of the trench T2b is located at a ratio of n. － The lower surface of the base region 114b of the type is located at the top.

[0051] An internal electrode 132 is disposed within the trench T2b. The internal electrode 132 is formed of a conductive material such as a metal. The internal electrode 132 extends from the upper surface of the p-type layer 116, more specifically from the p-type layer 116. + The upper surface of region 116b of type extends to n－ The base region 114b of the type. The lower end of the internal electrode 132 is located at a position greater than n. － The lower surface of the base region 114b of the n-type electrode is located at the top. The internal electrode 132 is connected to the p-type layer 116, the n-type barrier layer 115, and the n-type... － The base regions 114b of the type are adjacent in the X direction.

[0052] Multiple trenches T3 are provided in the boundary region S2. The multiple trenches T3 are arranged in the X direction. Each trench T3 extends from the upper surface of the p-type layer 116, more specifically from each p-type layer 116. + The upper surface of region 116b of type extends to n － The base region 114b of the type. The lower end of each trench T3 is located at a ratio of n － The lower surface of the base region 114b of the type is located at the top.

[0053] A gate electrode 141 is disposed within each trench T3. Each gate electrode 141 is formed of a conductive material such as a metal. Each gate electrode 141 extends from the upper surface of the p-type layer 116 to the n-type layer. － The base region 114b of the type. The lower end of each gate electrode 141 is located at a position greater than n. － The lower surface of the base region 114b is located at the top. Each gate electrode 141 is connected to the p-type layer 116, the n-type barrier layer 115, and the n... － The base regions 114b of the n-type are adjacent in the X direction. Therefore, in this embodiment, the region in the semiconductor device 100 that has an n-type barrier layer 115 adjacent to the gate electrode 141 corresponds to the boundary region S2.

[0054] In addition, Figure 1 The example shown is that the number of gate electrodes 141 in the boundary region S2 is two, but the number of gate electrodes 141 in the boundary region S2 is not limited to two.

[0055] The upper electrode 150 is formed of a conductive material such as a metal. The upper electrode 150 is disposed on the p-type layer 116 in the diode region S1, the boundary region S2, and the IGBT region S3. Furthermore, the upper electrode 150 is disposed on the inner electrode 122 in the diode region S1, on the gate electrode 141 in the boundary region S2, and on both the gate electrode 131 and the inner electrode 132 in the IGBT region S3. The upper electrode 150 functions as an anode electrode in the diode region S1 and as an emitter electrode in the IGBT region S3.

[0056] Each insulating film 161 is disposed in the diode region S1 between each internal electrode 122 and the upper electrode 150, between each internal electrode 122 and the p-type layer 116, and between each internal electrode 122 and the n-type layer 116.－ Between the base region 114b of the type.

[0057] Each insulating film 162 is disposed in the IGBT region S3 between each gate electrode 131 and the upper electrode 150, and between each gate electrode 131 and n + Between the emitter layer 117, between each gate electrode 131 and the p-type layer 116, between each gate electrode 131 and the n-type barrier layer 115, and between each gate electrode 131 and the n-type barrier layer 115. － Between the base region 114b of the type.

[0058] The insulating film 163 is disposed in the IGBT region S3 between the internal electrode 132 and the upper electrode 150, between the internal electrode 132 and the p-type layer 116, and between the internal electrode 132 and the n-type layer 116. － Between the base region 114b of the type.

[0059] Each insulating film 164 is disposed in the boundary region S2 between each gate electrode 141 and the upper electrode 150, between each gate electrode 141 and the p-type layer 116, between each gate electrode 141 and the n-type barrier layer 115, and between each gate electrode 141 and the n-type barrier layer 115. － Between the base regions 114b of the n-type. In this embodiment, each insulating film 164 is in contact with the barrier layer 115 of the n-type.

[0060] Each insulating film 161, 162, 163, and 164 is formed of an insulating material such as silicon oxide or silicon nitride.

[0061] In this embodiment, trenches T1, T2a, T2b, and T3 are arranged at approximately a certain interval in the X direction. Therefore, in the boundary region S2, the distance L3 in the X direction between two adjacent gate electrodes 141 is approximately equal to the distance L4 in the X direction between two adjacent internal electrodes 122 in the diode region S1. However, the relationship between distance L3 and distance L4 is not limited to the above.

[0062] Internal electrodes 122 and 132 are electrically connected to the upper electrode 150 within the semiconductor device 100. Gate electrode 131 is not electrically connected to internal electrodes 122 and 132 or the upper electrode 150 within the semiconductor device 100. That is, gate electrode 131 is electrically insulated relative to internal electrodes 122 and 132 and the upper electrode 150. Gate electrode 141 is not electrically connected to internal electrodes 122 and 132, the upper electrode 150, or gate electrode 131 within the semiconductor device 100. That is, gate electrode 141 is electrically insulated relative to internal electrodes 122 and 132, the upper electrode 150, and gate electrode 131. However, all internal electrodes 122 may be electrically insulated relative to the upper electrode 150 and gate electrode 131, but electrically connected relative to gate electrode 141. Alternatively, one of the plurality of internal electrodes 122 may be electrically insulated relative to the upper electrode 150 and gate electrode 131, but electrically connected relative to gate electrode 141.

[0063] Next, an example of the use of the semiconductor device 100 in this embodiment will be described.

[0064] Figure 2 This is a circuit diagram showing a half-bridge circuit incorporating the semiconductor device of this embodiment.

[0065] Two semiconductor devices 100 can be installed in a half-bridge circuit C. Hereinafter, one of the two semiconductor devices 100 installed in the half-bridge circuit C will be referred to as "first semiconductor device 100A" and the other as "second semiconductor device 100B".

[0066] The lower electrode 110, i.e., the collector electrode, of the first semiconductor device 100A is electrically connected to the upper electrode 150, i.e., the emitter electrode, of the second semiconductor device 100B. A terminal of the load L, such as a motor, is electrically connected to the connection point CP between the lower electrode 110 of the first semiconductor device 100A and the upper electrode 150 of the second semiconductor device 100B.

[0067] Furthermore, the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A is electrically connected to the first signal source SG1 via a resistor R1, etc. The gate electrode 141 of the boundary region S2 of the first semiconductor device 100A is electrically connected to a second signal source SG2, which is different from the first signal source SG1, via a resistor R2, etc. The gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B is electrically connected to a third signal source SG3 via a resistor R3, etc. The gate electrode 141 of the boundary region S2 of the second semiconductor device 100B is electrically connected to a fourth signal source SG4, which is different from the third signal source SG3, via a resistor R4, etc.

[0068] Figure 3 (a) represents time on the horizontal axis and voltage on the vertical axis. Figure 2 The graph shows the time-varying voltage between the gate electrode and the emitter electrode of the IGBT region in the first semiconductor device.

[0069] Figure 3 (b) is a graph showing the time variation of the voltage between the gate electrode and the emitter electrode in the boundary region of the first semiconductor device, with time on the horizontal axis and voltage on the vertical axis.

[0070] Figure 3 (c) represents time on the horizontal axis and voltage on the vertical axis. Figure 2 The graph shows the time-varying voltage between the gate electrode and emitter electrode of the IGBT region in the second semiconductor device.

[0071] Figure 3 (d) is a graph showing the time variation of the voltage between the gate electrode and the emitter electrode in the boundary region of the second semiconductor device, with time on the horizontal axis and voltage on the vertical axis.

[0072] Figure 3 (e) is a graph showing the time variation of the voltage between the collector electrode and the emitter electrode of the first semiconductor device, with time on the horizontal axis and voltage and current on the vertical axis.

[0073] Figure 3 (f) is a graph showing the time variation of the voltage between the collector electrode and the emitter electrode of the second semiconductor device, with time on the horizontal axis and voltage and current on the vertical axis.

[0074] Figure 4 (a)~ Figure 4 (c) is a schematic diagram representing the action of the boundary region.

[0075] In addition, Figure 4 (a)~ Figure 4 In diagram (c), holes are represented by a circle enclosing "h", and electrons are represented by a circle enclosing "e". Furthermore, the directions of movement of holes and electrons are indicated by arrows. Additionally, the following describes applying a voltage between the gate electrodes 131 and 141 and the upper electrode 150 such that the potentials of the gate electrodes 131 and 141 are higher than the potential of the upper electrode 150, which functions as either the emitter or anode electrode; this is also referred to as "applying a positive voltage to the gate electrodes 131 and 141". Similarly, applying a voltage between the gate electrodes 131 and 141 and the upper electrode 150 such that the potentials of the gate electrodes 131 and 141 are lower than the potential of the upper electrode 150 is also referred to as "applying a negative voltage to the gate electrodes 131 and 141".

[0076] First, let's explain the states that precede time t1.

[0077] like Figure 3 As shown in (a), the first signal source SG1 applies a voltage V11 to the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A before time t1. Here, the voltage V11 is a potential lower than the threshold voltage at which an n-type channel is formed in the p-type layer 116 of the IGBT region S3, for example, a negative voltage. Therefore, before time t1, the IGBT region S3 of the first semiconductor device 100A is as follows: Figure 3 As shown in (e), it is in the off state.

[0078] In addition, such as Figure 3 As shown in (b), the second signal source SG2 applies a voltage V21 to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A before time t1. Here, the voltage V21 is a voltage lower than the threshold required to form a p-type inversion layer in the n-type barrier layer 115 of the boundary region S2, for example, a negative voltage. Therefore, a p-type inversion layer is formed in the portion of the n-type barrier layer 115 near the gate electrode 141.

[0079] In addition, such as Figure 3 As shown in (c), the third signal source SG3 applies a voltage V12 to the gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B before time t1. Here, the voltage V12 is a voltage higher than the threshold voltage required to form an n-type channel in the p-type layer 116 of the IGBT region S3, for example, a positive voltage. Therefore, before time t1, the IGBT region S3 of the second semiconductor device 100B is as follows: Figure 3 (f) shows the on state.

[0080] In addition, such as Figure 3 As shown in (d), the fourth signal source SG4 applies a voltage V21 to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B before time t1. Therefore, a p-type inversion layer is formed in the n-type barrier layer 115 at a portion near the gate electrode 141.

[0081] Next, as Figure 3 As shown in (c), at time t1, the third signal source SG3 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B from voltage V12 to voltage V11. Thus, as... Figure 3As shown in (f), the IGBT region S3 of the second semiconductor device 100B switches from the on state to the off state. Furthermore, a return current begins to flow in the diode region S1 and the boundary region S2 of the first semiconductor device 100A. That is, the diode region S1 and the boundary region S2 of the first semiconductor device 100A become on.

[0082] At this time, the second signal source SG2 is as follows Figure 3 As shown in (b), a voltage V21 continues to be applied to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A. Therefore, as Figure 4 As shown in (a), a p-type inversion layer continues to be formed in the portion of the n-type barrier layer 115 near the gate electrode 141. Therefore, in the portion of the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 in the boundary region S2 surrounding the gate electrode 141, a p-type channel ch1 containing this inversion layer is formed. Through the p-type channel ch1, it is easy to move from the p-type layer 116, particularly from the p+ type region 116b, towards the n-type barrier layer 116. － Holes are injected into the base layer 114. Therefore, n － The amount of charge carriers in the base layer 114 increases. This reduces the on-resistance of the diode region S1 and the boundary region S2 of the first semiconductor device 100A. Consequently, the constant losses in the diode region S1 and the boundary region S2 of the first semiconductor device 100A are reduced.

[0083] Next, as Figure 3 As shown in (d), at time t2 before the recovery of the diode region S1 and boundary region S2 of the second semiconductor device 100B begins, the fourth signal source SG4 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B from voltage V21 to voltage V22. Here, voltage V22 is a voltage higher than the threshold voltage for forming a p-type channel in the n-type barrier layer 115, for example, a positive voltage. Therefore, as Figure 4 As shown in (b), an n-type channel ch2 is formed in the portion of the n-type barrier layer 115 and n-type layer 113 located around the gate electrode 141 in the boundary region S2. In particular, the portion of the n-type barrier layer 115 located near the gate electrode 141 functions as an n-type accumulation layer. As a result, it is difficult to transfer energy from the p-type layer 116, especially from the p+ type region 116b, to the n-type layer. － Holes are injected into the base layer 114 of the p-type layer. Furthermore, the voltage V22 can also be a higher voltage than the threshold voltage for forming an n-type channel in the p-type layer 116. In this case, an n-type channel is also formed in the p-type layer 116, making it less likely for holes to be injected into the n-type channel. －Holes are injected into the base layer 114 of the type. This suppresses the injection of holes in the diode region S1 and boundary region S2 of the second semiconductor device 100B before recovery begins. － The amount of charge carriers in the base region 114b of the type increases. As a result, the recovery loss of the second semiconductor device 100B can be reduced.

[0084] Next, as Figure 3 As shown in (a), at time t3, the first signal source SG1 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A from voltage V11 to voltage V12. Thus, as... Figure 3 As shown in (e), the IGBT region S3 of the first semiconductor device 100A switches from the off state to the on state.

[0085] Figure 5 (a) is a graph showing the relationship between the time variation of the current flowing through the diode region and the boundary region and the time variation of the voltage between the gate electrode and the emitter electrode in the boundary region, with time on the horizontal axis and current and voltage on the vertical axis. Figure 5 (b) takes time on the horizontal axis and current on the vertical axis. Figure 5 (a) is an enlarged portion enclosed by the dashed line A, showing the time variation of the current flowing through the diode region and the boundary region in this embodiment and the time variation of the current flowing through the diode region and the boundary region in the reference example.

[0086] like Figure 5 As shown in (a), at time t3, the IGBT region S3 of the first semiconductor device 100A switches from an off state to an on state, and recovery begins in the diode region S1 and boundary region S2 of the second semiconductor device 100B. The current flowing through the diode region S1 and boundary region S2 of the second semiconductor device 100B gradually decreases after time t3, and after time t4, a reverse recovery current begins to flow from the lower electrode 110 to the upper electrode 150. Up to time t4 when the reverse recovery current flows, the fourth signal source SG4 applies a voltage V22 to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B. Therefore, up to time t4, an n-type channel ch2 is formed in the portion of the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 of the boundary region S2 around the gate electrode 141. Therefore, hole injection is suppressed up to time t4. As a result, the peak value Ir of the reverse recovery current can be reduced. As a result, the recovery loss of the diode region S1 and the boundary region S2 of the first semiconductor device 100A can be reduced.

[0087] exist Figure 5In the reference example shown in (b), at time t2, the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B is not switched from voltage V21 to voltage V22. That is, the fourth signal source SG4 continues to apply voltage V21 to the gate electrode 141. In this case, the peak value of the reverse recovery current in this embodiment is higher than the peak value Ir of the reverse recovery current in the reference example.

[0088] Next, as Figure 3 (d) and Figure 5 As shown in (a), the fourth signal source SG4 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B from voltage V22 to voltage V21 at time t4. Thus, as... Figure 4 As shown in (c), a p-type channel ch1 is formed again in the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 in the boundary region S2. Through the p-type channel ch1, from the n... － The base layer 114 promotes hole discharge into the p-type layer 116. As a result, the recovery loss of the diode region S1 and the boundary region S2 of the second semiconductor device 100B can be reduced.

[0089] Next, as Figure 3 As shown in (a), the first signal source SG1 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the first semiconductor device 100A from voltage V12 to voltage V11 at time t5. As a result, as... Figure 3 As shown in (e), the IGBT region S3 of the first semiconductor device 100A switches from the on state to the off state. Furthermore, a return current begins to flow in the diode region S1 and the boundary region S2 of the second semiconductor device 100B. That is, the diode region S1 and the boundary region S2 of the second semiconductor device 100B become on.

[0090] At this time, the fourth signal source SG4 is as follows Figure 3 As shown in (d), a voltage V21 continues to be applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B. Therefore, as Figure 4 As shown in (a), a p-type channel ch1 is formed in the portion of the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 in the boundary region S2 surrounding the gate electrode 141. Holes can easily travel from the p-type layer 116, particularly from the p+ type region 116b, to the n-type layer 113 via the p-type channel ch1. － Base layer 114 is implanted. Therefore, the on-resistance of diode region S1 and boundary region S2 of the second semiconductor device 100B can be reduced. As a result, the constant loss of diode region S1 and boundary region S2 of the second semiconductor device 100B can be reduced.

[0091] Next, as Figure 3 As shown in (b), at time t6 before the recovery of the diode region S1 and boundary region S2 of the first semiconductor device 100A begins, the second signal source SG2 switches the voltage of the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A from voltage V21 to voltage V22. Therefore, as Figure 4 As shown in (b), an n-type channel ch2 is formed in the portion of the n-type barrier layer 115 and n-type layer 113 surrounding the gate electrode 141 in the boundary region S2. Therefore, holes are less likely to migrate from the p-type layer 116, particularly from the p+ type region 116b, to the n-type layer. － The base layer 114 is implanted with an n-type channel. Furthermore, the voltage V22 can also be a higher voltage than the threshold voltage for forming an n-type channel on the p-type layer 116. In this case, an n-type channel is also formed in the p-type layer 116, making it less likely for n-type channels to be implanted. － Holes are injected into the base layer 114 of the first semiconductor device 100A. As a result, the recovery loss of the diode region S1 and the boundary region S2 of the first semiconductor device 100A can be reduced.

[0092] Next, as Figure 3 As shown in (c), the third signal source SG3 switches the voltage applied to the gate electrode 131 of the IGBT region S3 of the second semiconductor device 100B from voltage V11 to voltage V12 at time t7. Thus, as... Figure 3 As shown in (f), the IGBT region S3 of the second semiconductor device 100B switches from the off state to the on state. This initiates the recovery of the diode region S1 and the boundary region S2 of the first semiconductor device 100A.

[0093] Next, as Figure 3 As shown in (b), at the moment t8 when the reverse recovery current begins to flow in the diode region S1 and the boundary region S2 of the first semiconductor device 100A, the second signal source SG2 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A from voltage V22 to voltage V21. Thus, as... Figure 4 As shown in (c), a p-type channel ch1 is formed again in the portion of the p-type layer 116, the n-type barrier layer 115, and the n-type layer 113 in the boundary region S2, located around the gate electrode 141. Holes can easily pass through the p-type channel ch1 from the n-type layer 141. － The base layer 114 is discharged into the p-type layer 116. As a result, the recovery loss of the diode region S1 and the boundary region S2 of the first semiconductor device 100A can be reduced.

[0094] The upper electrode 150 is electrically connected to the inner electrode 122. Therefore, when the diode region S1 is in the on state, a negative voltage relative to the inner electrode 122 is applied to the gate electrode 141 within the boundary region S2. Before the diode region S1 recovers, a positive voltage relative to the inner electrode 122 is applied to the gate electrode 141. During the period when a reverse recovery current flows through the diode region S1, a negative voltage relative to the inner electrode 122 is applied to the gate electrode 141.

[0095] Through the above, the trade-off between constant loss and recovery loss in the diode region S1 and boundary region S2 of the first semiconductor device 100A and the second semiconductor device 100B can be improved. Furthermore, the driving method of the semiconductor device 100 described above is only one example, and the driving method of the semiconductor device 100 is not particularly limited to the method described above. For example, the moment when the fourth signal source SG4 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the second semiconductor device 100B from voltage V22 to voltage V21 is not limited to the moment t4 when the reverse recovery current begins to flow. Similarly, the moment when the second signal source SG2 switches the voltage applied to the gate electrode 141 of the boundary region S2 of the first semiconductor device 100A from voltage V22 to voltage V21 is not limited to the moment t8 when the reverse recovery current begins to flow.

[0096] Next, the effects of this implementation method will be explained.

[0097] In the semiconductor device 100 of this embodiment, an n-type barrier layer 115 and a gate electrode 141 adjacent to the n-type barrier layer 115 and electrically insulated from the gate electrode 131 of the IGBT region S3 are provided in the boundary region S2. Therefore, by adjusting the voltage applied to the gate electrode 141 of the boundary region S2 independently of the gate electrode 131 of the IGBT region S3, the trade-off between constant loss and recovery loss in the diode region S1 and the boundary region S2 of the semiconductor device 100 can be improved. As a result, the losses in the diode region S1 and the boundary region S2 of the semiconductor device 100 can be reduced.

[0098] Furthermore, compared to the diode region S1, the boundary region S2 is more prone to current concentration during recovery and is more easily damaged during recovery. In contrast, in this embodiment, an n-type blocking layer 115 and a gate electrode 141 are provided in the boundary region S2. Therefore, before recovery begins, the voltage applied to the gate electrode 141 can be adjusted so that the n-type blocking layer 115 functions as an n-type accumulation layer. Thus, before recovery begins, the n-type current concentration in the boundary region S2 can be suppressed. － The amount of charge carriers in the base region 114b of the semiconductor device increases. As a result, the destruction of the boundary region S2 of the semiconductor device 100 during recovery is suppressed.

[0099] Furthermore, in this embodiment, the n-type blocking layer 115 and the gate electrode 141 are not provided in the diode region S1. Therefore, in the diode region S1, the amount of charge carriers is reduced compared to the amount of charge carriers in the boundary region S2. As a result, the increase in the forward voltage of the diode region S1 can be suppressed.

[0100] <First Variation of the First Embodiment>

[0101] Next, a variation of the first embodiment will be described.

[0102] Figure 6 This is a cross-sectional view showing a first modified example of the semiconductor device according to the first embodiment.

[0103] Furthermore, in the following description, only the differences from the first embodiment will be explained in principle. Everything else described below is the same as the first embodiment. The same applies to other variations and embodiments described below.

[0104] In the first embodiment, it is described that n is provided on the lower electrode 110 in the boundary region S2. + An example of type 111 cathode layer. However, it can also be as follows: Figure 6 As shown, n is not set in the boundary region S2. + A cathode layer of type 111. Furthermore, p... + The collector layer 112 is also provided in the boundary region S2, where a p-type electrode is disposed between the lower electrode 110 and the n-type layer 113. + Type 112 collector layer. In this case, from n + Type 111 cathode layer and p + The boundary of the collector layer 112 of the type faces the IGBT region S3 and becomes a certain region, which is the boundary region S2.

[0105] This structure also improves the trade-off between constant loss and recovery loss in diode region S1 and boundary region S2. Furthermore, this structure suppresses the destruction of boundary region S2 during recovery. Additionally, this structure suppresses the decrease in carrier quantity in diode region S1.

[0106] <Second variation of the first embodiment>

[0107] Next, a second variation of the first embodiment will be described.

[0108] Figure 7 This is a cross-sectional view showing a second variation of the semiconductor device according to the first embodiment.

[0109] It can also be n+ Type 111 cathode layer and p + Both the current collector layer 112 and the n-type layer 113 are disposed in the boundary region S2. In the boundary region S2, an n-type current collector layer 112 is disposed between the lower electrode 110 and the n-type layer 113. + Type 111 cathode layer and p + Both of these are type 112 collector layers.

[0110] This structure also improves the trade-off between constant loss and recovery loss in diode region S1 and boundary region S2. Furthermore, this structure suppresses the disruption of boundary region S2 during recovery. Additionally, this structure also prevents the amount of charge carriers in diode region S1 from decreasing compared to boundary region S2.

[0111] <Second Implementation Method>

[0112] Next, the second embodiment will be described.

[0113] Figure 8 This is a cross-sectional view showing the semiconductor device according to this embodiment.

[0114] In the semiconductor device 200 of this embodiment, an n-type barrier layer 215 is also provided in the diode region S1. Furthermore, in this embodiment, each gate electrode 141 is electrically insulated from each internal electrode 122 of the diode region S1 and from each gate electrode 131 and internal electrode 132 of the IGBT region S3.

[0115] Alternatively, the gate electrode 141 can be electrically insulated from the internal electrode 122, and an n-type barrier layer 215 can also be provided in the diode region S1. In this structure, the trade-off between constant loss and recovery loss in the diode region S1 and the boundary region S2 can be improved. Furthermore, in this structure, the destruction of the boundary region S2 during recovery can be suppressed.

[0116] Furthermore, in this embodiment, in diode region S1, the internal electrode 122 adjacent to the n-type barrier layer 215 is electrically insulated relative to the gate electrode 141. Therefore, in diode region S1, the amount of charge carriers can be suppressed to be less than the amount of charge carriers in boundary region S2.

[0117] <First variation of the second embodiment>

[0118] Next, a first variation of the second embodiment will be described.

[0119] Figure 9A This is a cross-sectional view showing a first modified example of the semiconductor device according to the second embodiment.

[0120] Figure 9B This is a top view showing a first modified example of the semiconductor device according to the second embodiment.

[0121] Furthermore, in the following description, only the differences from the second embodiment will be explained in principle. Except for the matters described below, it is the same as the second embodiment. The same applies to other variations and embodiments described below. In addition, in Figure 9B The upper electrode 150 and the upper layer of insulating films 161, 163, and 164 are omitted in the original text.

[0122] In the first and second embodiments, each p in the boundary region S2 is provided + The length L1 of region 116b in the X direction of type is related to the p in diode region S1. + The length L2 in the X direction of region 116b of type 1 is approximately equal. However, it is also possible to... Figure 9A As shown, let each p in the boundary region S2 + The length L21x in the X direction of region 216b of type 2 is greater than that of each p in diode region S1. + The length L22x in the X direction of region 216b of type 2 is [length missing]. Furthermore, as... Figure 9B As shown, in this embodiment, each p in the boundary region S2 is set as follows: + The length L21y in the Y direction of region 216b of type 2 is related to each p in diode region S1. + The length L22y in the Y direction of region 216b of type S2 is approximately equal. Therefore, when viewed from above, that is, along the direction from the upper electrode 150 to the lower electrode 110, each p in the boundary region S2 is approximately equal. + The area ratio of region 216b of type is set in each p in diode region S1. + The area of ​​region 216b is large.

[0123] With this configuration, when the diode region S1 and the boundary region S2 are conducting, holes can easily escape from the p-hole of the boundary region S2. + Region 216b of type n － The base region 114b of the type is injected. Furthermore, with this configuration, in the recovered state of diode region S1 and boundary region S2, holes can easily emerge from the n-type boundary region S2. － The base region of type 114b is directed towards p + Region 216b of type 2 is discharged. Thus, it is possible to suppress the destruction of boundary region S2 during recovery.

[0124] However, let each p in the boundary region + The area ratio of the type region is set in each p in the diode region. +The method for determining the area of ​​a region of type [p] is not limited to the above. For example, it could also be that each p in the boundary region [is...]. + The length of the region in the X direction of the type is related to the p-values ​​in the diode region. + The lengths of the regions of type p in the X direction are approximately equal. Let each p in the boundary region be... + The length of the region in the Y direction of the type is set to be equal to the length of each p in the diode region. + The region of type [type] has a long length in the Y direction. Alternatively, it can be that each p in the boundary region [is longer / longer / longer]. + The length of the region in the X direction of the type is proportional to the length of each p in the diode region. + The region of type X has a long length in the X direction. Let each p in the boundary region be... + The length of the region in the Y direction of the type is set to be equal to the length of each p in the diode region. + The region of this type has a long length in the Y direction.

[0125] <Second variation of the second embodiment>

[0126] Next, a second variation of the second embodiment will be described.

[0127] Figure 10 This is a cross-sectional view showing a second modified example of the semiconductor device according to the second embodiment.

[0128] In the first and second embodiments, the distance L3 in the X direction between two adjacent gate electrodes 141 in the boundary region S2 is approximately equal to the distance L4 in the X direction between two adjacent internal electrodes 122 in the diode region S1. However, it is also possible to... Figure 10 As shown, the distance L23 in the X direction between two adjacent gate electrodes 141 in the boundary region S2 is shorter than the distance L24 in the X direction between two adjacent internal electrodes 122 in the diode region S1.

[0129] This configuration increases the density of the p-type channel ch1 in the boundary region S2. Therefore, when the diode region S1 and the boundary region S2 recover, holes can easily escape from the n-type channel ch1. － The base layer 114 is discharged into the p-type layer 116. This helps to prevent the boundary region S2 from being damaged during recovery.

[0130] <Third Implementation Method>

[0131] Next, the third embodiment will be described.

[0132] Figure 11 This is a cross-sectional view showing the semiconductor device according to this embodiment.

[0133] In the semiconductor device 200 of the second embodiment, an n-type barrier layer 215 is also provided in the diode region S1, and each gate electrode 141 of the boundary region S2 is electrically insulated from each internal electrode 122 of the diode region S1. In contrast, in the semiconductor device 300 of this embodiment, although the n-type barrier layer 215 is also provided in the diode region S1, a gate electrode 321 is disposed in each trench T1 of the diode region S1, electrically connected to the gate electrode 141 of the boundary region S2 and electrically insulated from the gate electrode 131 and the upper electrode 150. Thus, the gate electrode 321 can also be provided in the diode region S1.

[0134] Furthermore, in the semiconductor device 300 of this embodiment, an n-type layer is provided instead of the n-type layer 113. － The base layer 314a is of type 3. No n is set in the boundary region S2. + Type 111 cathode layer and p + Type 112,n collector layer － The base layer 314a of the n-type is disposed on the lower electrode 110 and connected to the lower electrode 110. That is, in n + Type 111 cathode layer and p + Between the current collector layers 112 of the type, there are impurity concentrations higher than n. + Type 111 cathode layer with low n － The base layer 314a is of the n-type. Therefore, in this embodiment, in the semiconductor device 300, an n-type barrier layer 115 is provided adjacent to the gate electrode 141 and the n-type barrier layer 115 is of the n-type. － The region where the base layer 314a of the type is connected to the lower electrode 110 corresponds to the boundary region S2.

[0135] In this way, gate electrodes 321 electrically connected to the n-type barrier layer 215 and each gate electrode 141 of the boundary region S2 can also be provided in the diode region S1. Furthermore, in the n-type region S2... + Type 111 cathode layer and p + The impurity concentration ratio n is sandwiched between the collector layers 112 of the type. + The cathode layer 111 of type n has a low impurity concentration. － The base layer 314a is of this type. In such a structure, carrier concentration in the boundary region S2 can be suppressed. Thus, the destruction of the boundary region S2 during recovery can be suppressed.

[0136] <Fourth Implementation>

[0137] Next, the fourth embodiment will be described.

[0138] Figure 12 This is a cross-sectional view showing the semiconductor device according to this embodiment.

[0139] In the semiconductor device 200 of the second embodiment, an n-type barrier layer 215 is also provided in the diode region S1, and each gate electrode 141 of the boundary region S2 is electrically insulated from each internal electrode 122 of the diode region S1. In contrast, in the semiconductor device 400 of this embodiment, although an n-type barrier layer 215 is also provided in the diode region S1, in some of the trenches T1 of the diode region S1, a gate electrode 321 electrically connected to the gate electrode 141 of the boundary region S2 is disposed, and in the remaining trenches T1 of the diode region S1, an internal electrode 122 electrically insulated from the gate electrode 141 of the boundary region S2 is disposed.

[0140] Specifically, in this embodiment, in the diode region S1, the gate electrode 321 and the internal electrode 122 are alternately arranged in the X direction. In contrast, in the boundary region S2, the gate electrode 141 is arranged throughout the entire trench T3. Therefore, the average number of gate electrodes 141 provided per unit length ΔL in the X direction in the boundary region S2 is greater than the average number of gate electrodes 321 provided per unit length ΔL in the X direction in the diode region S1. The average number of gate electrodes provided per unit length ΔL in the X direction in a certain region is calculated, for example, by dividing the length of that region in the X direction by the total number of gate electrodes in that region. Thus, in this embodiment, the region with a smaller average number of gate electrodes provided per unit length ΔL in the region where an n-type barrier layer 115 adjacent to the gate electrode of the semiconductor device 400 is provided corresponds to the boundary region S2.

[0141] Alternatively, the n-type barrier layer 215 and gate electrode 321 can also be provided in the diode region S1, and the average number of gate electrodes 141 provided per unit length ΔL in the X direction in the boundary region S2 is greater than the average number of gate electrodes 321 provided per unit length ΔL in the X direction in the diode region S1. In this structure, the trade-off between constant loss and recovery loss in the diode region S1 and the boundary region S2 can be improved. Furthermore, in this structure, the destruction of the boundary region S2 during recovery can be suppressed. Additionally, in this structure, the decrease in the amount of charge carriers in the diode region S1 compared to the amount of charge carriers in the boundary region S2 can be suppressed.

[0142] Furthermore, in this embodiment, no internal electrode electrically connected to the upper electrode 150 is provided in the boundary region S2. However, as long as the average number of gate electrodes 141 provided per unit length ΔL in the X direction in the boundary region S2 is greater than the average number of gate electrodes 321 provided per unit length ΔL in the X direction in the diode region S1, an internal electrode electrically connected to the upper electrode 150 may be provided in the boundary region S2.

[0143] <Fifth Implementation>

[0144] Next, the fifth embodiment will be described.

[0145] Figure 13 This is a cross-sectional view showing the semiconductor device according to this embodiment.

[0146] In embodiments 1 to 4, the n-type barrier layer 115 is in contact with the insulating film 164. In contrast, in the semiconductor device 500 of this embodiment, the n-type barrier layer 515 is not in contact with the insulating film 164.

[0147] An n-type barrier layer 515 is disposed in the p-type layer 116, more specifically, in the p-type region 116a. Furthermore, the upper surface 515a, lower surface 515b, and two side surfaces 515c of the n-type barrier layer 515 are covered by the p-type region 116a. In the p-type layer 116, the length ΔT in the X direction of the portion located between the n-type barrier layer 515 and the insulating film 164 is set to a length such that when a positive voltage V22 is applied to the gate electrode 141, the n-type inversion layer formed in the p-type layer 116 is in contact with the n-type barrier layer 515.

[0148] Alternatively, the n-type barrier layer 515 can be disposed within the p-type layer 116, with the sidewalls 515c of the n-type barrier layer 515 covered by the p-type layer 116. This structure improves the trade-off between constant loss and recovery loss in the diode region S1 and the boundary region S2. Furthermore, this structure suppresses the destruction of the boundary region S2 during recovery. Additionally, this structure allows the voltage V21 to be set to 0V instead of a negative voltage. That is, signal sources SG2 and SG4, such as those applying a negative voltage to the gate electrode 141, are not required.

[0149] The above describes multiple embodiments and modifications, but they can be combined with each other. For example, the first modification of the second embodiment regarding p can also be applied to the semiconductor device 100 of the first embodiment, the semiconductor device 300 of the third embodiment, the semiconductor device 400 of the fourth embodiment, and the semiconductor device 500 of the fifth embodiment. +The structure of the area of ​​region 216b of type . Furthermore, for example, the structure of the second variation of the second embodiment regarding the distances L23, L24 between adjacent electrodes can also be applied to the semiconductor device 100 of the first embodiment, the semiconductor device 300 of the third embodiment, the semiconductor device 400 of the fourth embodiment, and the semiconductor device 500 of the fifth embodiment. Furthermore, for example, the structure of the first variation or the second variation of the first embodiment can also be applied to the semiconductor device 200 of the second embodiment, the semiconductor device 400 of the fourth embodiment, and the semiconductor device 500 of the fifth embodiment. Furthermore, for example, the structure of the fifth embodiment can also be applied to the semiconductor device 200 of the second embodiment, the semiconductor device 300 of the third embodiment, and the semiconductor device 400 of the fourth embodiment.

[0150] Furthermore, while the embodiments described above illustrate an example of an n-channel RC-IGBT, the semiconductor device could also be a p-channel RC-IGBT. In this case, the p-type of each layer in the above embodiments is replaced with an n-type, and vice versa. Also, in this case, the positive voltage in the above embodiments is replaced with a negative voltage, and vice versa. That is, as long as a positive voltage relative to the internal electrode is applied to the gate electrode in the boundary region when the diode region is in the on state, a negative voltage relative to the internal electrode is applied to the gate electrode in the boundary region before the diode region recovers, and a positive voltage relative to the internal electrode is applied to the gate electrode in the boundary region during the reverse recovery current flowing through the diode region.

[0151] The implementation methods include the following approaches.

[0152] (Postscript 1)

[0153] A semiconductor device includes a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein...

[0154] have:

[0155] The first electrode is disposed throughout the diode region, the boundary region and the IGBT region.

[0156] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;

[0157] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;

[0158] The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer.

[0159] The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer.

[0160] The fifth semiconductor layer of the second conductivity type is disposed on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region.

[0161] The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region;

[0162] The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region.

[0163] The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction.

[0164] The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the aforementioned first direction, and is electrically insulated relative to the third electrode.

[0165] The fifth electrode is disposed on the aforementioned fifth semiconductor layer;

[0166] The first insulating film is disposed between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer.

[0167] A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and

[0168] The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

[0169] (Postscript 2)

[0170] A semiconductor device includes a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein...

[0171] The first electrode is disposed throughout the diode region, the boundary region and the IGBT region.

[0172] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;

[0173] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;

[0174] The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer.

[0175] The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the diode region, the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer.

[0176] The fifth semiconductor layer of the second conductivity type is disposed on the fourth semiconductor layer in the diode region, the boundary region and the IGBT region.

[0177] The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region;

[0178] The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region.

[0179] The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction.

[0180] The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the aforementioned first direction, and is electrically insulated relative to the second electrode and the third electrode.

[0181] The fifth electrode is disposed on the aforementioned fifth semiconductor layer;

[0182] The first insulating film is disposed between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer.

[0183] A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and

[0184] The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

[0185] (Note 3)

[0186] A semiconductor device includes a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein...

[0187] have:

[0188] The first electrode is disposed throughout the diode region, the boundary region and the IGBT region.

[0189] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;

[0190] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;

[0191] The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer.

[0192] The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer.

[0193] The fifth semiconductor layer of the second conductivity type is disposed on the third semiconductor layer in the diode region and the boundary region, and on the fourth semiconductor layer in the IGBT region;

[0194] The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region;

[0195] The seventh semiconductor layer of the first conductivity type is disposed in the fifth semiconductor layer in the diode region and is covered by the fifth semiconductor layer on the side.

[0196] The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region.

[0197] The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction.

[0198] The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to both the fifth and third semiconductor layers in the first direction, and is electrically insulated relative to the third electrode.

[0199] The fifth electrode is disposed on the aforementioned fifth semiconductor layer;

[0200] The first insulating film is disposed between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer.

[0201] A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and

[0202] The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

[0203] (Note 4)

[0204] The semiconductor device as described in any one of Appendices 1 to 3, wherein,

[0205] It also has:

[0206] The other second electrode, in the diode region, extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the second electrode in the first direction, separated by the fifth semiconductor layer; and

[0207] The other fourth electrode, in the aforementioned boundary region, extends from the upper surface of the aforementioned fifth semiconductor layer toward the aforementioned third semiconductor layer, and is adjacent to the aforementioned fourth electrode in the aforementioned first direction, separated by the aforementioned fifth semiconductor layer;

[0208] The distance between the fourth electrode and the other fourth electrodes in the first direction is shorter than the distance between the second electrode and the other second electrodes in the first direction.

[0209] (Note 5)

[0210] A semiconductor device includes a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein...

[0211] have:

[0212] The first electrode is disposed throughout the diode region, the boundary region and the IGBT region.

[0213] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;

[0214] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;

[0215] The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer.

[0216] The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the diode region, the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer.

[0217] The fifth semiconductor layer of the second conductivity type is disposed on the fourth semiconductor layer in the diode region, the boundary region and the IGBT region.

[0218] The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region;

[0219] The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region.

[0220] The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction.

[0221] A plurality of fourth electrodes extend from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and the boundary region, are adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction, and are electrically insulated relative to the second electrode and the third electrode. The average number of fourth electrodes provided per unit length in the first direction in the boundary region is greater than the average number of fourth electrodes provided per unit length in the first direction in the diode region.

[0222] The fifth electrode is disposed on the aforementioned fifth semiconductor layer;

[0223] The first insulating film is disposed between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer.

[0224] A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and

[0225] The third insulating film is disposed between each of the fourth electrodes and the fifth electrodes, between each of the fourth electrodes and the fifth semiconductor layer, between each of the fourth electrodes and the fourth semiconductor layer, and between each of the fourth electrodes and the third semiconductor layer.

[0226] (Note 6)

[0227] The semiconductor device as described in any one of Appendix 1 to 5,

[0228] In the aforementioned boundary region, a portion of the third semiconductor layer is located on the first electrode and is situated between the first semiconductor layer and the second semiconductor layer in the first direction.

[0229] (Note 7)

[0230] The semiconductor device as described in any one of Appendix 1 to 5,

[0231] The first semiconductor layer and the second semiconductor layer are also disposed in the boundary region, located between the first electrode and the third semiconductor layer in the boundary region.

[0232] (Postscript 8)

[0233] The semiconductor device as described in any one of Appendix 1 to 5,

[0234] The second semiconductor layer is also disposed in the boundary region, located between the first electrode and the third semiconductor layer in the boundary region.

[0235] (Note 9)

[0236] The semiconductor device as described in any one of Appendix 1 to 5,

[0237] The first semiconductor layer is also disposed in the boundary region, and is located between the first electrode and the third semiconductor layer in the boundary region.

[0238] (Postscript 10)

[0239] A semiconductor device includes a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein...

[0240] have:

[0241] The first electrode is disposed throughout the diode region, the boundary region and the IGBT region.

[0242] A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region;

[0243] A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region;

[0244] The third semiconductor layer of the first conductivity type is located on the first semiconductor layer in the diode region, on the first electrode in the boundary region, and on the second semiconductor layer in the IGBT region, and has a lower impurity concentration than the impurity concentration of the first semiconductor layer.

[0245] The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the diode region, the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer.

[0246] The fifth semiconductor layer of the second conductivity type is disposed on the fourth semiconductor layer in the diode region, the boundary region and the IGBT region.

[0247] The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region;

[0248] The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region.

[0249] The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction.

[0250] The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the aforementioned first direction, and is electrically insulated relative to the third electrode.

[0251] The fifth electrode is disposed on the aforementioned fifth semiconductor layer;

[0252] The first insulating film is disposed between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer.

[0253] A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and

[0254] The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

[0255] (Postscript 11)

[0256] The semiconductor device as described in any one of Appendix 1 to 10,

[0257] The aforementioned fifth semiconductor layer has:

[0258] A first semiconductor region is disposed covering the aforementioned diode region, the aforementioned boundary region, and the aforementioned IGBT region; and

[0259] Multiple second semiconductor regions are disposed on the upper layer of the first semiconductor region in the diode region, the boundary region and the IGBT region. The impurity concentration of the multiple second semiconductor regions is higher than that of the first semiconductor region, and they are separated from each other in the first direction.

[0260] When viewed from the fifth electrode toward the first electrode in a second direction, the area of ​​the second semiconductor region in the boundary region is larger than the area of ​​the second semiconductor region in the diode region.

[0261] (Postscript 12)

[0262] The semiconductor device as described in any one of Appendix 1 to 10,

[0263] The length of the first direction of the aforementioned boundary region is shorter than the distance between the lower surface of the first semiconductor layer and the upper surface of the fifth semiconductor layer in the aforementioned diode region.

[0264] (Postscript 13)

[0265] A method for driving a semiconductor device according to any one of Appendices 1 to 9, 11, and 12.

[0266] The first conductivity type mentioned above is n-type, and the second conductivity type mentioned above is p-type.

[0267] When the diode region is in the conducting state, a voltage that is negative relative to the second electrode is applied to the fourth electrode in the boundary region.

[0268] Before the diode region is restored, a positive voltage relative to the second electrode is applied to the fourth electrode.

[0269] During the period when the reverse recovery current flows through the diode region, a voltage that is negative relative to the second electrode is applied to the fourth electrode.

[0270] (Postscript 14)

[0271] A method for driving a semiconductor device according to any one of Appendices 1 to 9, 11, and 12.

[0272] The first conductivity type mentioned above is p-type, and the second conductivity type mentioned above is n-type.

[0273] When the diode region is in the conducting state, a positive voltage relative to the second electrode is applied to the fourth electrode within the boundary region.

[0274] Before the diode region is restored, a negative voltage relative to the second electrode is applied to the fourth electrode.

[0275] During the period when the reverse recovery current flows through the diode region, a voltage that is positive relative to the second electrode is applied to the fourth electrode.

[0276] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein, have: The first electrode is disposed throughout the diode region, the boundary region and the IGBT region. A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer. The fifth semiconductor layer of the second conductivity type is disposed on the third semiconductor layer in the diode region and on the fourth semiconductor layer in the boundary region and the IGBT region. The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region; The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region. The third electrode, in the IGBT region, extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction, and is electrically insulated relative to the second electrode. The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the aforementioned first direction, and is electrically insulated relative to the second electrode and the third electrode. The fifth electrode is disposed on the aforementioned fifth semiconductor layer; The first insulating film is disposed between the second electrode and the fifth semiconductor layer, and between the second electrode and the third semiconductor layer. A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

2. The semiconductor device of claim 1, wherein, It also has: The other second electrode, in the diode region, extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer, and is adjacent to the second electrode in the first direction, separated by the fifth semiconductor layer; as well as The other fourth electrode, in the aforementioned boundary region, extends from the upper surface of the aforementioned fifth semiconductor layer toward the aforementioned third semiconductor layer, and is adjacent to the aforementioned fourth electrode in the aforementioned first direction, separated by the aforementioned fifth semiconductor layer; The distance between the fourth electrode and the other fourth electrodes in the first direction is shorter than the distance between the second electrode and the other second electrodes in the first direction.

3. The semiconductor device as claimed in claim 1, wherein, In the aforementioned boundary region, a portion of the third semiconductor layer is located on the first electrode and is situated between the first semiconductor layer and the second semiconductor layer in the first direction.

4. The semiconductor device of claim 1, wherein, The first semiconductor layer and the second semiconductor layer are also disposed in the boundary region, located between the first electrode and the third semiconductor layer in the boundary region.

5. The semiconductor device of claim 1, wherein, The second semiconductor layer is also disposed in the boundary region, located between the first electrode and the third semiconductor layer in the boundary region.

6. The semiconductor device of claim 1, wherein, The first semiconductor layer is also disposed in the boundary region, and is located between the first electrode and the third semiconductor layer in the boundary region.

7. The semiconductor device of claim 1, wherein, The aforementioned fifth semiconductor layer has: A first semiconductor region is disposed covering the aforementioned diode region, the aforementioned boundary region, and the aforementioned IGBT region; and A plurality of second semiconductor regions are disposed on the upper part of the first semiconductor region in the diode region, the boundary region and the IGBT region. The impurity concentration of the plurality of second semiconductor regions is higher than that of the first semiconductor region, and the plurality of second semiconductor regions are separated from each other in the first direction. When viewed from the fifth electrode toward the first electrode in a second direction, the area of ​​the second semiconductor region in the boundary region is larger than the area of ​​the second semiconductor region in the diode region.

8. The semiconductor device of claim 1, wherein, The length of the first direction of the aforementioned boundary region is shorter than the distance between the lower surface of the first semiconductor layer and the upper surface of the fifth semiconductor layer in the aforementioned diode region.

9. A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein, have: The first electrode is disposed throughout the diode region, the boundary region and the IGBT region. A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the diode region, the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer. The fifth semiconductor layer of the second conductivity type is disposed on the fourth semiconductor layer in the diode region, the boundary region and the IGBT region. The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region; The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region. The third electrode, in the IGBT region, extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction, and is electrically insulated relative to the second electrode. The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the aforementioned first direction, and is electrically insulated relative to the second electrode and the third electrode. The fifth electrode is disposed on the aforementioned fifth semiconductor layer; The first insulating film is disposed between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer. A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

10. A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein, have: The first electrode is disposed throughout the diode region, the boundary region and the IGBT region. A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer. The fifth semiconductor layer of the second conductivity type is disposed on the third semiconductor layer in the diode region and the boundary region, and on the fourth semiconductor layer in the IGBT region; The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region; The seventh semiconductor layer of the first conductivity type is disposed in the fifth semiconductor layer in the diode region and is covered by the fifth semiconductor layer on the side. The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region. The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction. The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to both the fifth and third semiconductor layers in the aforementioned first direction, and is electrically insulated relative to the third electrode. The fifth electrode is disposed on the aforementioned fifth semiconductor layer; The first insulating film is disposed between the second electrode and the fifth semiconductor layer and between the second electrode and the third semiconductor layer. The second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer. as well as The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

11. A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein, have: The first electrode is disposed throughout the diode region, the boundary region and the IGBT region. A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The third semiconductor layer of the first conductivity type is disposed throughout the diode region, the boundary region and the IGBT region. It is located on the first semiconductor layer in the diode region and on the second semiconductor layer in the IGBT region. The impurity concentration is lower than that of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the diode region, the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer. The fifth semiconductor layer of the second conductivity type is disposed on the fourth semiconductor layer in the diode region, the boundary region and the IGBT region. The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region; The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region. The third electrode extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer in the IGBT region and is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction. A plurality of fourth electrodes extend from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and the boundary region, are adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction, and are insulated relative to the second electrode and the third electrode. The average number of the plurality of fourth electrodes provided per unit length in the first direction in the boundary region is greater than the average number of the plurality of fourth electrodes provided per unit length in the first direction in the diode region. The fifth electrode is disposed on the aforementioned fifth semiconductor layer; The first insulating film is disposed between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer. A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and Multiple third insulating films are disposed between each of the fourth and fifth electrodes, between each of the fourth electrodes and the fifth semiconductor layer, between each of the fourth electrodes and the fourth semiconductor layer, and between each of the fourth electrodes and the third semiconductor layer.

12. A semiconductor device comprising a diode region, an IGBT region, and a boundary region located between the diode region and the IGBT region, wherein, have: The first electrode is disposed throughout the diode region, the boundary region and the IGBT region. A first semiconductor layer of a first conductivity type is disposed on the first electrode in the diode region; A second semiconductor layer of a second conductivity type is disposed on the first electrode in the IGBT region; The third semiconductor layer of the first conductivity type is located on the first semiconductor layer in the diode region, on the first electrode in the boundary region, and on the second semiconductor layer in the IGBT region, and has a lower impurity concentration than the impurity concentration of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type is disposed on the third semiconductor layer in the diode region, the boundary region and the IGBT region, and the impurity concentration is higher than the impurity concentration of the upper part of the third semiconductor layer. The fifth semiconductor layer of the second conductivity type is disposed on the fourth semiconductor layer in the diode region, the boundary region and the IGBT region. The sixth semiconductor layer of the first conductivity type is disposed on the upper part of the fifth semiconductor layer in the IGBT region; The second electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the diode region and is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in a first direction from the diode region toward the IGBT region. The third electrode, in the IGBT region, extends from the upper surface of the sixth semiconductor layer toward the third semiconductor layer, is adjacent to the sixth semiconductor layer, the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the first direction, and is electrically insulated relative to the second electrode. The fourth electrode extends from the upper surface of the fifth semiconductor layer toward the third semiconductor layer in the aforementioned boundary region, is adjacent to the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer in the aforementioned first direction, and is electrically insulated relative to the second electrode and the third electrode. The fifth electrode is disposed on the aforementioned fifth semiconductor layer; The first insulating film is disposed between the second electrode and the fifth semiconductor layer, between the second electrode and the fourth semiconductor layer, and between the second electrode and the third semiconductor layer. A second insulating film is disposed between the third electrode and the fifth electrode, between the third electrode and the sixth semiconductor layer, between the third electrode and the fifth semiconductor layer, between the third electrode and the fourth semiconductor layer, and between the third electrode and the third semiconductor layer; and The third insulating film is disposed between the fourth electrode and the fifth electrode, between the fourth electrode and the fifth semiconductor layer, between the fourth electrode and the fourth semiconductor layer, and between the fourth electrode and the third semiconductor layer.

13. A method for driving a semiconductor device, as described in any one of claims 1-9, 11, and 12. The first conductivity type mentioned above is n-type, and the second conductivity type mentioned above is p-type. When the diode region is in the conducting state, a voltage that is negative relative to the second electrode is applied to the fourth electrode in the boundary region. Before the diode region is restored, a positive voltage relative to the second electrode is applied to the fourth electrode. During the period when the reverse recovery current flows through the diode region, a voltage that is negative relative to the second electrode is applied to the fourth electrode.

14. A driving method for a semiconductor device, as described in any one of claims 1-9, 11, and 12. The first conductivity type mentioned above is p-type, and the second conductivity type mentioned above is n-type. When the diode region is in the conducting state, a positive voltage relative to the second electrode is applied to the fourth electrode within the boundary region. Before the diode region is restored, a negative voltage relative to the second electrode is applied to the fourth electrode. During the period when the reverse recovery current flows through the diode region, a voltage that is positive relative to the second electrode is applied to the fourth electrode.

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