Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of suppressing a change in characteristics of a gate electrode and a manufacturing method of the semiconductor device. The semiconductor device has a semiconductor layer, an insulating film provided over the semiconductor layer and formed with an opening, a gate electrode connected to the semiconductor layer via the opening, and a protective film covering the gate electrode. The insulating film has a first surface on the semiconductor layer side and a second surface on the opposite side of the first surface. The gate electrode has a third surface apart from and facing the second surface, and a fourth surface connecting the second surface and the third surface. The gate electrode includes a Ni film constituting the third surface and the fourth surface, has a Ni oxide film covering the Ni film on the third surface and the fourth surface, and the protective film covers the third surface and the fourth surface from above the Ni oxide film.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] As a semiconductor device with a high electron mobility transistor (HEMT), a semiconductor device having a gate electrode has been proposed, which has a base and an eave extending laterally from the base (Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: US Patent No. 8741715

[0006] Patent Document 2: Japanese Patent Application Publication No. 2013-207086

[0007] Patent Document 3: Japanese Patent Application Publication No. 2019-216188

[0008] In conventional semiconductor devices, the characteristics of the gate electrode can sometimes change. Summary of the Invention

[0009] The purpose of this disclosure is to provide a semiconductor device capable of suppressing changes in the characteristics of the gate electrode, and a method for manufacturing the semiconductor device.

[0010] The semiconductor device disclosed herein includes: a semiconductor layer; an insulating film disposed on the semiconductor layer and having an opening formed therein; a gate electrode connected to the semiconductor layer via the opening; and a protective film covering the gate electrode. The insulating film has: a first side on the semiconductor layer side; and a second side opposite to the first side. The gate electrode has: a third side away from the second side and facing the second side; and a fourth side connecting the second side and the third side. The gate electrode includes a Ni film constituting the third side and the fourth side, and a Ni oxide film covering the Ni film is present on the third side and the fourth side. The protective film covers the third side and the fourth side from above the Ni oxide film.

[0011] Invention Effects

[0012] According to this disclosure, changes in the characteristics of the gate electrode can be suppressed. Attached Figure Description

[0013] Figure 1 This is a cross-sectional view showing an outline of the semiconductor device according to an embodiment.

[0014] Figure 2This is a cross-sectional view showing details of the gate electrode and its surroundings in a semiconductor device according to an embodiment.

[0015] Figure 3 This is a cross-sectional view (1) showing a method for manufacturing a semiconductor device according to an embodiment.

[0016] Figure 4 This is a cross-sectional view (2) showing a method for manufacturing a semiconductor device according to an embodiment.

[0017] Figure 5 This is a cross-sectional view (3) showing a method for manufacturing a semiconductor device according to an embodiment.

[0018] Figure 6 This is a cross-sectional view (4) showing a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 7 This is a cross-sectional view (5) showing a method for manufacturing a semiconductor device according to an embodiment.

[0020] Figure 8 This is a cross-sectional view (6) showing a method for manufacturing a semiconductor device according to an embodiment.

[0021] Figure 9 This is a cross-sectional view (7) showing a method for manufacturing a semiconductor device according to an embodiment.

[0022] Figure 10 This is a cross-sectional view (8) showing a method for manufacturing a semiconductor device according to an embodiment.

[0023] Figure 11 This is a cross-sectional view (9) showing a method for manufacturing a semiconductor device according to an embodiment.

[0024] Figure 12 This is a cross-sectional view (10) showing a method for manufacturing a semiconductor device according to an embodiment.

[0025] Figure 13 This is a cross-sectional view (11) showing a method for manufacturing a semiconductor device according to an embodiment.

[0026] Figure 14 This is a cross-sectional view (12) showing a method for manufacturing a semiconductor device according to an embodiment.

[0027] Figure 15 This is a cross-sectional view (13) showing a method for manufacturing a semiconductor device according to an embodiment.

[0028] Figure 16 This is a cross-sectional view (14) showing a method for manufacturing a semiconductor device according to an embodiment.

[0029] Explanation of reference numerals in the attached figures

[0030] 10: Substrate

[0031] 12: Electron Transit Layer

[0032] 14: Electronic Supply Layer

[0033] 16: Hat Layer

[0034] 20: Layered structure

[0035] 22: First insulating film

[0036] 22X: Opening

[0037] 24: Second insulating film

[0038] 24X: Open

[0039] 26: Insulating film

[0040] 26A: First page

[0041] 26B: Second page

[0042] 31, 32: Opening

[0043] 41: Source electrode

[0044] 42: Drain electrode

[0045] 43: Gate electrode

[0046] 43A: Third side

[0047] 43B: Page Four

[0048] 43S: Base

[0049] 43T: Eaves

[0050] 46: Gap

[0051] 51, 52, 53, 54, 55: Electron beam resist

[0052] 51X, 52X, 53X, 54X, 55X: Open

[0053] 61, 62: Metal layer

[0054] 64:Ni film

[0055] 66: Au membrane

[0056] 68: Ni oxide film

[0057] 70: Protective film

[0058] 100: Semiconductor devices. Detailed Implementation

[0059] The following describes the implementation method.

[0060] [Description of embodiments of this disclosure]

[0061] First, embodiments of this disclosure are listed for illustration. In the following description, the same or corresponding elements are labeled with the same reference numerals, and they are not described in the same way repeatedly.

[0062] [1] A semiconductor device according to one aspect of the present disclosure includes: a semiconductor layer; an insulating film disposed on the semiconductor layer and having an opening formed therein; a gate electrode connected to the semiconductor layer via the opening; and a protective film covering the gate electrode, the insulating film having: a first side on the semiconductor layer side; and a second side opposite to the first side, the gate electrode having: a third side away from the second side and facing the second side; and a fourth side connecting the second side and the third side, the gate electrode comprising a Ni film constituting the third side and the fourth side, the third side and the fourth side having a Ni oxide film covering the Ni film, and the protective film covering the third side and the fourth side from the Ni oxide film.

[0063] When the Ni film is exposed on the surface of the gate electrode and is covered by a Si nitride film formed as a protective film by chemical vapor deposition (CVD), Ni diffuses into the protective film, sometimes altering the characteristics of the gate electrode. Furthermore, when the Ni film is covered by an Al oxide film formed as a protective film by atomic layer deposition (ALD), Ni diffuses at the interface between the protective film and the Ni film, sometimes altering the characteristics of the gate electrode. In contrast, in a semiconductor device according to one embodiment of this disclosure, the Ni film is covered by a Ni oxide film on the third and fourth surfaces, and a protective film covers the third and fourth surfaces from above the Ni oxide film. Therefore, Ni diffusion in the Ni film can be suppressed, thereby suppressing changes in the characteristics of the gate electrode.

[0064] [2] In [1], there may also be a gap between the portion of the protective film covering the third surface and the second surface. In this case, it is easier to reduce the parasitic capacitance between the gate electrode and the stacked structure.

[0065] [3] In [1] or [2], the protective film may also comprise an Al oxide film or a Si nitride film. In this case, it is easy to protect the gate electrode from the intrusion of external moisture, etc.

[0066] [4] In [1] to [3], the thickness of the Ni oxide film may also be 3 nm or more. In this case, it is easier to suppress the diffusion of Ni in the Ni film.

[0067] [5] In [1] to [4], the protective film may also cover the insulating film. In this case, the laminated structure can be protected more firmly.

[0068] [6] In [1] to [5], the area of ​​the portion of the Ni film in contact with the insulating film may be less than 0.10 times the area of ​​the portion of the Ni film in contact with the Ni oxide film. In this case, it is easier to suppress the diffusion of Ni at the portion of the Ni film in contact with the insulating film.

[0069] [7] Another aspect of the semiconductor device disclosed herein includes: a semiconductor layer; an insulating film disposed on the semiconductor layer and having an opening formed therein; a gate electrode connected to the semiconductor layer via the opening; and a protective film comprising an Al oxide film or a Si nitride film covering the gate electrode and the insulating film, the insulating film having: a first side on the semiconductor layer side; and a second side opposite to the first side, the gate electrode having: a third side away from the second side and facing the second side; and a fourth side connecting the second side and the third side, the gate electrode comprising: a Ni film constituting the third side and the fourth side; and an Au film formed on the Ni film, the third side and the fourth side having a Ni oxide film covering the Ni film, the protective film covering the third side and the fourth side from the Ni oxide film, and a gap existing between the portion of the protective film covering the third side and the second side.

[0070] [8] Another aspect of the present disclosure describes a method for manufacturing a semiconductor device comprising the following steps: forming an insulating film on a semiconductor layer, the insulating film having a first side on the semiconductor layer and a second side opposite to the first side; forming an opening in the insulating film; forming a metal layer connected to the semiconductor layer via the opening, the metal layer having a third side and a fourth side, the third side being away from and facing the second side, the fourth side connecting the second side and the third side, the metal layer comprising a Ni film constituting the third side and the fourth side; forming a Ni oxide film covering the Ni film on the third side and the fourth side by oxidizing the Ni film, forming a gate electrode from the remaining portion of the metal layer; and forming a protective film covering the third side and the fourth side from the Ni oxide film and covering the gate electrode.

[0071] [Details of the embodiments of this disclosure]

[0072] The embodiments of this disclosure will be described in detail below, but these embodiments are not limited thereto. It should be noted that in this specification and drawings, sometimes repeated descriptions are omitted by labeling constituent elements having substantially the same functional configuration with the same reference numerals.

[0073] This embodiment relates to a semiconductor device comprising a GaN-HEMT, which is mainly composed of nitride semiconductors. Figure 1 This is a cross-sectional view showing an outline of the semiconductor device according to an embodiment. Figure 2 This is a cross-sectional view showing details of the gate electrode and its surroundings in a semiconductor device according to an embodiment. Figure 1 and Figure 2 This represents a cross-section perpendicular to the gate width direction.

[0074] like Figure 1 As shown, the semiconductor device 100 of this embodiment has a substrate 10 and a stacked structure 20 of multiple semiconductor layers formed on the substrate 10. The substrate 10 is, for example, a SiC substrate having a (0001) main surface, and the stacking direction of the stacked structure 20 is, for example, the

[0001] direction. The stacked structure 20 includes an electron transit layer 12, an electron supply layer 14, and a cap layer 16 formed sequentially from the substrate 10 side. The electron transit layer 12 is, for example, an undoped GaN layer with a thickness of about 1000 nm. The electron supply layer 14 is, for example, an n-type AlGaN layer with a thickness of about 20 nm. The cap layer 16 is, for example, an n-type GaN layer with a thickness of about 5 nm. The stacked structure 20 is an example of a semiconductor layer.

[0075] A first insulating film 22 is formed on the laminated structure 20. The first insulating film 22 is, for example, a Si nitride film. An opening 31 for the source electrode and an opening 32 for the drain electrode are formed on the first insulating film 22 and the laminated structure 20. A source electrode 41, which is in ohmic contact with the laminated structure 20, is formed within the opening 31, and a drain electrode 42, which is in ohmic contact with the laminated structure 20, is formed within the opening 32. A second insulating film 24 is formed on the first insulating film 22, the source electrode 41, and the drain electrode 42. The second insulating film 24 is, for example, a Si nitride film. The first insulating film 22 and the second insulating film 24 are contained within an insulating film 26. The insulating film 26 has a first surface 26A on the side of the laminated structure 20 and a second surface 26B opposite to the first surface 26A. The first surface 26A is also the lower surface of the insulating film 26, and the second surface 26B is also the upper surface of the insulating film 26. The first surface 26A can be in contact with the laminated structure 20.

[0076] like Figure 2As shown, an opening 22X is formed in the first insulating film 22 and an opening 24X is formed in the second insulating film 24 between the source electrode 41 and the drain electrode 42. The opening width of the opening 24X, i.e., the dimension in the gate length direction, is larger than the opening width of the opening 22X. For example, the opening width of the opening 24X is about 140 nm, and the opening width of the opening 22X is about 90 nm. The opening 24X penetrates the second insulating film 24, and the opening 22X penetrates the first insulating film 22. The opening 22X is exposed through the opening 24X, and the stacked structure 20 is exposed through the openings 24X and 22X.

[0077] The semiconductor device 100 has a gate electrode 43 connected to the stacked structure 20 via openings 22X and 24X. The gate electrode 43 has a Ni film 64 and an Au film 66 formed on the Ni film 64. For example, the thickness of the Ni film 64 is approximately 50 nm to 100 nm, and the thickness of the Au film 66 is approximately 300 nm to 600 nm. The gate electrode 43, for example, has a T-shaped shape in cross-section. That is, the gate electrode 43 has a base 43S and eaves 43T extending to both sides from the base 43S. Furthermore, the gate electrode 43 has a second surface 26B that is separated from and opposite to the insulating film 26. The third surface 43A is also the lower surface of the eaves 43T. The gate electrode 43 also has a fourth surface 43B that connects the second surface 26B and the third surface 43A. The fourth surface 43B is also the side surface of the base 43S, which is above the second surface 26B and below the third surface 43A. The Ni film 64 forms the third surface 43A and the fourth surface 43B. The gate electrode 43 may have a Pd film between the Ni film 64 and the Au film 66, or it may have a Ta film on top of the Au film 66.

[0078] The semiconductor device 100 has a Ni oxide film 68 covering a Ni film 64 on its third surface 43A and fourth surface 43B. The semiconductor device 100 also has a protective film 70 covering a gate electrode 43. The protective film 70 covers the third surface 43A and fourth surface 43B from above the Ni oxide film 68. The protective film 70 covers not only the gate electrode 43 but may also cover an insulating film 26. The protective film 70 is, for example, an Al oxide film or a Si nitride film. The thickness of the protective film 70 is not particularly limited, but the thickness of the portion covering the third surface 43A is preferably 20 nm or more, more preferably 25 nm or more.

[0079] In this embodiment, the Ni film 64 is covered by a Ni oxide film 68 on the third surface 43A and the fourth surface 43B. Therefore, the diffusion of Ni in the Ni film 64 can be suppressed, thereby suppressing changes in the characteristics of the gate electrode 43.

[0080] A gap 46 can exist between the portion of the protective film 70 covering the third surface 43A and the second surface 26B. The presence of the gap 46 facilitates the reduction of parasitic capacitance between the eaves 43T of the gate electrode 43 and the stacked structure 20. It should be noted that a so-called low-k dielectric constant material can also be used instead of the gap 46. Compared to the case where the gap 46 is present, mechanical strength can be improved. The relative permittivity of the low-k dielectric constant material is preferably 7.0 or less, more preferably 4.0 or less.

[0081] The protective film 70 comprises an Al oxide film or a Si nitride film, thereby easily protecting the gate electrode 43 from external moisture intrusion. When the protective film 70 covers the insulating film 26, the laminated structure 20 can be more firmly protected.

[0082] The Ni oxide film 68 is thicker than the natural Ni oxide film, and the thickness of the Ni oxide film 68 is preferably 3 nm or more, more preferably 5 nm or more. This is to make it easier to suppress the diffusion of Ni in the Ni film 64.

[0083] The area of ​​the portion of Ni film 64 in contact with insulating film 26 is preferably 0.10 times or less, more preferably 0.07 times or less, and even more preferably 0.05 times or less, of the area of ​​the portion of Ni film 64 in contact with Ni oxide film 68. This is to make it easier to suppress the diffusion of Ni at the portion of Ni film 64 in contact with insulating film 26.

[0084] The insulating film 26 may also comprise a Si oxide nitride film in contact with the Ni film 64. For example, the first insulating film 22 and the second insulating film 24 may also comprise a Si nitride film as the main body and a Si oxide nitride film covering the surface of the Si nitride film. The insulating film 26 comprising a Si oxide nitride film in contact with the Ni film 64 facilitates the suppression of Ni diffusion at the interface between the Ni film 64 and the insulating film 26.

[0085] Next, the manufacturing method of the semiconductor device 100 according to the embodiment will be described. Figures 3 to 16 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment. Figures 3-8 express Figure 1 The change in the cross section shown, Figures 9-16 express Figure 2 The changes in the cross-section shown.

[0086] First, such as Figure 3As shown, a multilayer structure 20 comprising multiple nitride semiconductor layers is grown on substrate 10 using metal-organic chemical vapor deposition (MOCVD). Next, a first insulating film 22 is deposited on the upper surface of the multilayer structure 20 using low-pressure (LP) CVD. The first insulating film 22 is, for example, a Si nitride film with a thickness of 40 nm. A nucleation layer can be formed on substrate 10 before the formation of electron transit layer 12, and the electron transit layer 12 is formed on top of the nucleation layer. The nucleation layer is, for example, an AlN layer with a thickness of tens of nm.

[0087] Next, as Figure 4 As shown, an electron beam resist 51 is coated on the first insulating film 22, and an opening 51X is formed in the electron beam resist 51 by electron beam photolithography. The first insulating film 22 is exposed through the opening 51X.

[0088] Next, as Figure 5 As shown, using electron beam resist 51 as a mask, source opening 31 and drain opening 32 are formed on the first insulating film 22 and the stacked structure 20 by reactive ion etching (RIE). For example, a reactive gas containing fluorine (F) is used in the etching of the first insulating film 22, and a reactive gas containing chlorine (Cl) is used in the etching of the stacked structure 20.

[0089] Next, as Figure 6 As shown, a metal layer 61 is formed inside the opening 31 and the opening 32 by vapor deposition. The metal layer 61 is also attached to the upper surface of the electron beam resist 51 and the sidewall of the opening 51X. The metal layer 61 includes, for example, a Ta film, an Al film, and a Mo film formed sequentially from the substrate 10 side.

[0090] Next, as Figure 7 As shown, the electron beam resist 51 is removed. With the removal of the electron beam resist 51, the portion of the metal layer 61 attached to the electron beam resist 51 is also removed. On the other hand, the metal layer 61 remains inside the openings 31 and 32. That is, a stripping process is performed. Next, the metal layer 61 is alloyed by heat treatment. Thus, a source electrode 41 in 20-ohm contact with the stacked structure 20 is formed within the opening 31, and a drain electrode 42 in 20-ohm contact with the stacked structure 20 is formed within the opening 32.

[0091] Next, as Figure 8As shown, a second insulating film 24 is formed on the first insulating film 22, the source electrode 41, and the drain electrode 42 using plasma-enhanced CVD. The second insulating film 24 is, for example, a Si nitride film with a thickness of 20 nm. The first insulating film 22 and the second insulating film 24 are contained within the insulating film 26.

[0092] Next, as Figure 9 As shown, an electron beam resist 52 is coated on the second insulating film 24, the source electrode 41, and the drain electrode 42. For example, polymethyl methacrylate (PMMA) can be used as the electron beam resist 52. ZEP520A-7 manufactured by Zeon Corporation of Japan can also be used. Next, an opening 52X is formed in the electron beam resist 52 by electron beam lithography. The opening width of the opening 52X, i.e., the dimension in the gate length direction, is, for example, about 70 nm. The second insulating film 24 is exposed through the opening 52X.

[0093] Next, as Figure 10 As shown, using electron beam resist 52 as a mask, an opening 24X for the gate is formed on the second insulating film 24 using a reactive ion exchange (RIE) containing fluorine, and an opening 22X for the gate is formed on the first insulating film 22. During the formation of openings 24X and 22X, the second insulating film 24 and the first insulating film 22 are etched under certain conditions. Significant side etching occurs on the second insulating film 24, resulting in an opening width of opening 24X that is larger than that of opening 22X. For example, the opening width of opening 24X is approximately 140 nm, and the opening width of opening 22X is approximately 90 nm. The stacked structure 20 is exposed through openings 24X and 22X.

[0094] Next, as Figure 11As shown, electron beam resist 52 is removed. Next, electron beam resist 53, electron beam resist 54, and electron beam resist 55 are sequentially coated onto the cap layer 16, the first insulating film 22, the second insulating film 24, the source electrode 41, and the drain electrode 42. PMMA is used as electron beam resists 53 and 55, and polymethylglutarimide (PMGI) is used as electron beam resist 54. Electron beam resists 53 and 55 can be processed with finer precision than electron beam resist 54. Next, by electron beam lithography, an opening 55X is formed on electron beam resist 55, an opening 54X is formed on electron beam resist 54, and an opening 53X is formed on electron beam resist 53. For example, the opening width of opening 55X is approximately 500 nm, the opening width of opening 54X is approximately 580 nm, and the opening width of opening 53X is approximately 290 nm. The second insulating film 24, the first insulating film 22, and the cap layer 16 are exposed through openings 55X, 54X, and 53X.

[0095] Next, as Figure 12 As shown, baking is performed to deform the electron beam resist 53 such that the opening width at the lower end of the opening 53X is smaller than the opening width at the upper end of the opening 53X. That is, the sidewall surface of the opening 53X is deformed into a cone shape. Alternatively, the electron beam resist 53 can be self-aligned so that the lower end of the opening 53X aligns with the upper end of the opening 24X.

[0096] Next, as Figure 13 As shown, a metal layer 62 is formed inside openings 55X, 54X, 53X, 24X, and 22X by vapor deposition. During the formation of the metal layer 62, a Ni film 64 is formed, and an Au film 66 is formed on top of the Ni film 64. For example, the thickness of the Ni film 64 is approximately 50 nm to 100 nm, and the thickness of the Au film 66 is approximately 300 nm to 600 nm. A Pd film can be formed between the Ni film 64 and the Au film 66, or a Ta film can be formed on top of the Au film 66. The metal layer 62 is also attached to the upper surface of the electron beam resist 55 and the sidewalls of openings 55X.

[0097] Next, as Figure 14 As shown, electron beam resists 55, 54, and 53 are removed. With the removal of electron beam resists 55, 54, and 53, the portion of the metal layer 62 attached to electron beam resist 55 is also removed. On the other hand, the metal layer 62 remains inside the openings 24X and 22X and on the first insulating film 22 and the second insulating film 24. That is, it is stripped. The remaining metal layer 62, for example, has a T-shaped shape when viewed in cross-section.

[0098] Next, as Figure 15As shown, a Ni oxide film 68 is formed by oxidizing the surface of the Ni film 64 contained in the metal layer 62. This forms a gate electrode 43 having both a Ni film 64 and an Au film 66, and which is in Schottky contact with the stacked structure 20 via an opening 22X. In other words, the gate electrode 43 is formed from the remaining portion of the metal layer 62 that forms the Ni oxide film 68. The gate electrode 43, for example, has a T-shaped form in cross-section. For example, ozone can be used to oxidize the Ni film 64.

[0099] Next, as Figure 16 As shown, a protective film 70 is formed covering the gate electrode 43. The protective film 70 is in contact with the Ni oxide film 68 and the Au film 66, but not with the Ni film 64. The protective film 70 covers the Ni film 64 over the Ni oxide film 68. The protective film 70 is, for example, an Al oxide film or a Si nitride film. The Al oxide film can be formed, for example, by the ALD method. The Si nitride film can be formed, for example, by the plasma CVD method. In the case where the Si nitride film is formed by the plasma CVD method, the Si nitride film may also contain fluorine (F) in order to improve the characteristics of the device.

[0100] Then, wiring and other processes are formed as needed. In this way, a semiconductor device 100 containing GaN-HEMT can be manufactured.

[0101] According to this manufacturing method, it is easy to form a Ni oxide film 68 that inhibits the diffusion of Ni in the Ni film 64.

[0102] Furthermore, when forming an Al oxide film as a protective film 70 by the ALD method, the same apparatus used for the oxidation of the surface of the Ni film 64 can be used for film formation. On the other hand, when forming a Si nitride film as a protective film 70 by the CVD method, the protective film 70 can be formed at a high film formation rate.

[0103] It should be noted that when the insulating film 26 contains a Si nitride film, the surface of the Si nitride film can also be oxidized. That is, the surface of the insulating film 26 can also become a Si oxide nitride film. For example, the surface of the Si nitride film can be oxidized during various heat treatments or the like during the period from the formation of the second insulating film 24 to the formation of the Ni film 64.

[0104] Furthermore, the Ni film 64 only needs to be in contact with the Schottky layer 20, and does not need to be continuous from the part in contact with the layer 20 to the third surface 43A; it can be partially truncated. For example, due to the influence of coverage during vapor deposition, the Ni film 64 may be discontinuous at the corners of the first insulating film 22, the corners of the second insulating film 24, etc.

[0105] The embodiments have been described in detail above, but are not limited to specific embodiments. Various modifications and alterations can be made within the scope of the claims.

Claims

1. A semiconductor device comprising: Semiconductor layer; An insulating film is disposed on the semiconductor layer and has openings formed thereon; The gate electrode is connected to the semiconductor layer via the opening; as well as A protective film covers the gate electrode. The insulating film has the following characteristics: The first surface of the semiconductor layer; and The second surface, opposite to the first surface. The gate electrode has: The third side is separated from the second side and faces the second side; as well as Fourthly, connect the second surface to the third surface. The gate electrode comprises a Ni film constituting the third and fourth surfaces. The third and fourth surfaces have Ni oxide films covering the Ni film. A portion of the gate electrode has a surface made of Au. The protective film covers the third and fourth surfaces from above the Ni oxide film and directly covers the surface composed of Au.

2. The semiconductor device according to claim 1, wherein, There is a gap between the portion of the protective film covering the third side and the second side.

3. The semiconductor device according to claim 1 or 2, wherein, The protective film comprises an Al oxide film or a Si nitride film.

4. The semiconductor device according to claim 1 or 2, wherein, The thickness of the Ni oxide film is 3 nm or more.

5. The semiconductor device according to claim 1 or 2, wherein, The protective film also covers the insulating film.

6. The semiconductor device according to claim 1 or 2, wherein, The area of ​​the portion of the Ni film that contacts the insulating film is less than 0.10 times the area of ​​the portion of the Ni film that contacts the Ni oxide film.

7. A semiconductor device comprising: Semiconductor layer; An insulating film is disposed on the semiconductor layer and has openings formed thereon; The gate electrode is connected to the semiconductor layer via the opening; as well as The protective film comprises an Al oxide film or a Si nitride film covering the gate electrode and the insulating film. The insulating film has the following characteristics: The first surface of the semiconductor layer; and The second surface, opposite to the first surface. The gate electrode has: The third side is separated from the second side and faces the second side; Fourthly, connect the second surface to the third surface; Ni film, constituting the third and fourth surfaces; Au, formed on the Ni film; and A Ni oxide film is formed on the third and fourth surfaces. A portion of the gate electrode has a surface made of Au. The protective film covers the third and fourth surfaces from above the Ni oxide film, and directly covers the surface composed of Au. There is a gap between the portion of the protective film covering the third side and the second side.

8. A method for manufacturing a semiconductor device, comprising the following steps: An insulating film is formed on a semiconductor layer, the insulating film having a first side on the semiconductor layer side and a second side opposite to the first side; An opening is formed in the insulating film; A metal layer is formed, the metal layer being connected to the semiconductor layer via the opening, the metal layer having a third surface and a fourth surface, the third surface being away from and facing the second surface, the fourth surface connecting the second surface and the third surface, the metal layer comprising a Ni film constituting the third surface and the fourth surface; A Ni oxide film covering the Ni film is formed on the third and fourth surfaces by oxidizing the Ni film, and a gate electrode is formed on the remaining portion of the metal layer and includes a surface made of Au. as well as A protective film is formed, which covers the third and fourth surfaces from the Ni oxide film of the gate electrode and directly covers the surface composed of Au.

Images