Semiconductor structure, HEMT structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure, a HEMT structure and methods of forming the same. The present disclosure provides a semiconductor structure including a channel layer; an active layer located above the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode formed above a top surface of the active layer; and a source / drain electrode located above the top surface of the active layer; wherein the active layer includes a first layer and a second layer stacked in sequence from the top surface to a bottom surface of the active layer, the first layer has a higher aluminum (Al) atomic concentration than the second layer. The present disclosure also provides a HEMT structure and related methods.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of the invention patent application filed on June 2, 2017, with application number "201710407585.2" and titled "Semiconductor Structure, HEMT Structure and Method for Forming the Same". Technical Field

[0003] This disclosure relates to a semiconductor structure, a HEMT structure, and a method for forming the same. Background Technology

[0004] High-electron-mobility transistors (HEMTs) are suitable for power applications due to their high current density, high breakdown voltage, and low on-off impedance. An HEMT structure comprises a channel layer and an active layer. A two-dimensional electron gas (2DEG) is generated in the channel layer, which is adjacent to the interface of the active layer. The 2DEG serves as a charge carrier in the HEMT structure. A problem with HEMT structures is that charge falls onto the drain side of the gate, which can cause a phenomenon known as "current collapse" under high-voltage operation. Therefore, there is a need for devices with low turn-on impedance, low current collapse, improved interface trapdensity, and linear drain current degradation. The embodiments disclosed herein at least address these needs. Summary of the Invention

[0005] Some embodiments disclosed herein provide a semiconductor structure comprising a channel layer; an active layer located above the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode formed above a top surface of the active layer; and a source / drain electrode located above the top surface of the active layer; wherein the active layer comprises a first layer and a second layer sequentially stacked from the top surface to the bottom surface of the active layer, the first layer having a higher aluminum (Al) atom concentration than the second layer. Attached Figure Description

[0006] To aid readers in achieving optimal comprehension, it is recommended that you refer to the attached icons and their detailed textual descriptions while reading this disclosure. Please note that, in accordance with industry standard practice, the drawings in this patent specification may not be drawn to scale. In some drawings, dimensions may be intentionally enlarged or reduced to help readers clearly understand the discussion.

[0007] Figures 1 to 8(b) This is a cross-sectional schematic diagram illustrating various stages of manufacturing of a III-V HEMT structure according to some embodiments disclosed herein.

[0008] Figure 9 This disclosure illustrates X-ray energy dispersive X-ray (EDX) analysis of Ga and Al atoms based on some embodiments.

[0009] Figure 10 The graphs illustrate the experimental results conducted by the inventors based on some embodiments of this disclosure, showing the values ​​of the interface trapping density Dit measured on III-V HEMTs fabricated at different depths with or without a high Al diffusion layer.

[0010] Figure 11 The graphs illustrate the experimental results conducted by the inventors based on some embodiments of this disclosure, showing that the linear drain current (Idlin) degenerates into a function of stress time measured on a III-V HEMT with or without a high Al diffusion layer.

[0011] Figure 12 This is a graph illustrating the experimental results conducted by the inventors according to embodiments disclosed herein, showing that the dynamic minimum “on” impedance (Rdson) ratio is a function of the stress voltage measured on a III-V HEMT group with or without a high Al diffusion layer. Detailed Implementation

[0012] This disclosure provides several different implementations or embodiments that can be used to achieve different features of this disclosure. For the sake of simplicity, this disclosure also describes examples of specific components and arrangements. Please note that these specific examples are provided for illustrative purposes only and are not intended to be limiting. For example, in the following description of how a first feature is on or above a second feature, some embodiments may be included in which the first feature and the second feature are in direct contact, while other different embodiments may be included in which there are other features between the first feature and the second feature, such that the first feature and the second feature are not in direct contact. Furthermore, the various examples in this disclosure may use repeated reference numerals and / or textual annotations to simplify and clarify the document; these repeated reference numerals and annotations do not represent a correlation between different embodiments and / or configurations.

[0013] Furthermore, when this disclosure uses spatially related descriptive terms such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one component or feature in the icon and another (or more) components or features. In addition to the angular directions shown in the icon, these spatially related terms are also used to describe the possible angles and directions of the device during use and operation. The angular directions of the device may differ (rotation 90 degrees or other orientations), and these spatially related descriptions used in this disclosure can be interpreted in the same manner.

[0014] While the numerical ranges and parameters claimed in this disclosure are approximate values, the values ​​set forth in particular examples are as precise as possible. However, any numerical value inherently contains some error due to the standard deviation obtained in individual test measurements. Furthermore, in this document, “approximately” generally means within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, “approximately” means within the average standard deviation acceptable to a person skilled in the art. Outside of operational / working examples, unless specifically stated otherwise, all numerical ranges, quantities, values, and proportions disclosed herein, such as amounts of material, time periods, temperatures, operating conditions, proportions of quantities, and the like, should be understood to be modified by the word “approximately.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in this disclosure and the accompanying claims are approximate numbers that may vary as necessary. At a minimum, each numerical parameter should be interpreted according to the reported meaningful number of decimal places and using common rounding techniques. In this document, a range may be expressed as from one endpoint to another, or between two endpoints. Unless otherwise stated, all scopes disclosed herein include endpoints.

[0015] This disclosure relates to a III-V high electron mobility transistor (HEMT) and a method for manufacturing the same. Although this disclosure is described with reference to specific embodiments, the principles of this disclosure as defined in the claims are clearly applicable beyond the specific embodiments described herein. Furthermore, in the description of this disclosure, certain details have been omitted so as not to obscure the inventive aspects of the disclosure. These omitted details are within the knowledge scope of those skilled in the art.

[0016] III-V HEMTs on silicon substrates are power switching transistors used in voltage converter applications. Compared to silicon power transistors, III-V HEMTs exhibit low on-state impedance and low switching losses due to their wide bandgap characteristics. In this disclosure, "group III-V semiconductor" refers to a compound semiconductor comprising at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), aluminum gallium nitride (AlGaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), and the like. Similarly, "III-nitride semiconductor" refers to a compound semiconductor comprising nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, indium nitride (InN), aluminum nitride (AlN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), and the like.

[0017] Figures 1 to 8(b) This is a cross-sectional schematic diagram illustrating the III-V HEMT structure manufactured at different stages according to some embodiments disclosed herein. Figure 1 This is a cross-sectional schematic diagram illustrating a III-V HEMT in the initial manufacturing stage according to an embodiment of this disclosure. A semiconductor substrate 302 suitable as a support substrate for a III-V HEMT is provided. The semiconductor substrate 302 comprises multiple layers. In some embodiments, the semiconductor substrate 302 comprises a bulk silicon on which multiple semiconductor layers are formed. The semiconductor substrate 302 comprises any material suitable as a substrate for manufacturing a III-V semiconductor device. In some embodiments, the semiconductor substrate 302 comprises silicon (Si), silicon carbide (SiC), sapphire, and the like. Alternatively, in some embodiments, the semiconductor substrate 302 comprises a natural substrate of a material suitable for manufacturing a III-V semiconductor device, and, for example, a natural GaN or other III-nitride substrate. Furthermore, although the semiconductor substrate 302 is shown as a substantially single substrate, in other embodiments, the semiconductor substrate 302 is equivalent to a semiconductor on an insulator, such as a silicon on insulator (SOI) or germanium on insulator (GOI) substrate.

[0018] In Figure 2 , a transition structure 304 and a channel layer 312 are sequentially formed above the semiconductor substrate 302. In some embodiments, the transition structure 304 comprises a plurality of layers that mediate the lattice transition from the semiconductor substrate 302 to the channel layer 312. In this way, lattice mismatch between the semiconductor substrate 302 and the channel layer 312 can be reduced.

[0019] In some embodiments, the transition structure 304 includes a nucleation layer above the semiconductor substrate 302. The nucleation layer has a lattice structure and / or thermal expansion coefficient (TEC) suitable for bridging lattice mismatch and / or TEC mismatch between the semiconductor substrate 302 and the overlying layer, such as the GaN layer described in the present disclosure. In some embodiments, the nucleation layer comprises aluminum nitride (AlN). In some embodiments, the nucleation layer has a thickness of 70 to 300 nanometers (nm). In some embodiments, the nucleation layer is omitted.

[0020] In one or more embodiments, the transition structure 304 further comprises a transition layer above the nucleation layer. The transition layer further facilitates gradual changes of the lattice structure and TEC between the nucleation layer (or the semiconductor substrate 302) and the channel layer 312. In some embodiments, the transition layer comprises graded aluminum gallium nitride (Al x Ga (1-x) N, wherein x is the proportion of aluminum content in the aluminum-gallium composition, 0<x<1) layer. In some embodiments, the graded aluminum gallium nitride layer comprises a plurality of layers, each having a decreased proportion x from the bottom layer adjacent to the semiconductor substrate 302 to the channel layer 312. In at least one embodiment, the graded aluminum gallium nitride layer has three layers, wherein the proportion x of the bottom layer ranges from about 0.7 to 0.9, that of the intermediate layer ranges from about 0.4 to 0.6, and that of the top layer ranges from about 0.15 to 0.3. In some embodiments, instead of a plurality of layers with different proportions x, the graded aluminum gallium nitride layer has a continuous gradient of the proportion x. In some embodiments, the transition layer has a thickness of about 500 to 1050 nm. In some embodiments, the transition layer is omitted.

[0021] In some embodiments, the channel layer 312 comprises one or more group III-V compound layers. Examples of group III-V compound layers include, but are not limited to, GaN, AlGaN, InGaN and InAlGaN. In at least one embodiment, the one or more group III-V compound layers are doped. In one or more embodiments, the channel layer 312 comprises interleaved p-doped and n-doped group III-V compound layers. In at least one embodiment, the channel layer 312 comprises a p-doped GaN layer. Examples of p-type dopants in the p-doped GaN layer include, but are not limited to, C, Fe, Mg and Zn. In one embodiment, the thickness of the channel layer 312 is about 100 nm to about 200 nm.

[0022] The channel layer 312 can be formed above the semiconductor substrate 302 using a number of existing growth techniques. In some embodiments, the channel layer 312 can be formed above the transition structure 304 by molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE) or other suitable methods.

[0023] In Figure 3 , an active layer 314 is formed above the channel layer 312. The active layer 314 comprises one or more group III-V compound layers, the composition of which is different from that of the group III-V compound layer of the channel layer 312. In some embodiments, the active layer 314 comprises AlN, Al y Ga (1-y) N (where y is the aluminum content ratio, 0<y<1), or a combination thereof. The active layer 314 is configured to induce a two-dimensional electron gas (2DEG) 318 in the channel layer 312 along the interface between the channel layer 312 and the active layer 314. A heterojunction is formed between the active layer 314 and the channel layer 312, which are made of two different semiconductor materials. There is a band gap discontinuity between the active layer 314 and the channel layer 312. Due to the piezoelectric effect, electrons in the active layer 314 can fall into the channel layer 312, thereby generating a thin layer of high-mobility conducting electrons, that is, 2DEG 318, in the channel layer 312 adjacent to the interface with the active layer 314. The electrons in the 2DEG 318 are charge carriers in the channel layer 312.

[0024] During the manufacturing process, the surface of the active layer 314 can be gradually oxidized, resulting in the formation of (natural) oxides on its exposed surface. These oxides include aluminum oxide (AlO), gallium oxide (GaO), nitrogen oxide (NO), or combinations of Al, Ga, N, and O. In this embodiment, a cleaning step and / or annealing is performed on the surface of the active layer 214 before moving to subsequent stages, such as... Figure 4 As shown. The cleaning step removes contaminants from the surface of the active layer 314. The cleaning step can also remove oxides or reduce the amount of oxides absorbed on the surface of the active layer. In this embodiment, the wet cleaning step is performed by exposing the surface of the active layer 314 to any suitable wet cleaning solution.

[0025] In an exemplary embodiment, a nitrogen-based ambient atmosphere is provided to the surface of the active layer 314 during the annealing process. This annealing reduces the impedance of the active layer 314 by repairing defects caused by the presence of a high density of supplied point defects, such as nitrogen vacancies. N GaN antisites, and their complexes with native defects and acceptor dopants, have relatively low formation energies. These defects are known to have donor behavior in GaN, thus limiting maximum p-type conductivity. High p-type conductivity is even more difficult to achieve in ion-implanted GaN layers because implantation-induced damage generates additional donor defects, compensating for activated holes. The introduced defects have a predominantly deep level within the band gap; therefore, implanted GaN is high-resistivity. This damage must be annealed to achieve electrical activation of the implanted dopant. In some embodiments, annealing is performed in a temperature range of about 350°C to about 800°C.

[0026] In Figure 5(a), a thin AlN film 319 is deposited as a blanket over the cleaned and annealed surface of the active layer 314. The Al concentration of the AlN film 319 is higher than that of the active layer 314. In some embodiments, the ratio of the Al concentration in the AlN film 319 to the Al concentration in the active layer 314 is about 1.1 to 2.5. In some embodiments, atomic layer deposition (ALD) can be used to deposit the thin Al film 319 as a blanket over the active layer 314. However, this is not a limitation of this disclosure. In other embodiments, MBE, chemical vapor deposition (CVD), sputtering, electron beam evaporation, thermal evaporation, or other suitable methods can be used to form the thin Al film 319 over the active layer 314. The thickness of the deposited AlN film 319 is sufficient to provide the required Al concentration for the adjacent active layer 314. In some embodiments, the thickness of the deposited AlN film 319 is about 3 to 20 Al atoms in length.

[0027] In some other embodiments, a thin AlN film 319' is deposited over a portion of the cleaned and annealed surface of the active layer 314, as shown in FIG. 5(b). Specifically, the deposition of the thin AlN film 319' over the active layer 314 may be selective to avoid leaving said portion of the surface of the active layer 314 unused for the gate electrode. The Al concentration in the AlN film 319' is higher than the Al concentration in the active layer 314. In some embodiments, the ratio of the Al concentration in the AlN film 319' to the Al concentration in the active layer 314 is about 1.1 to 2.5. Because the high voltage and high temperature near the gate electrode can accelerate the breakage of the bond between the high-Al-concentration layer and the adjacent active layer 314, partial deposition of the film 319' can provide higher reliability for the manufactured device. The thickness requirement of the thin AlN film 319' may be substantially the same as that of the AlN film 319. In some embodiments, the deposition thickness of the AlN film 319' is about 3 to 21 Al atoms in length. A thin AlN film 319' can be formed above the active layer 314 using MBE, CVD, sputtering, E-beam evaporation, thermal evaporation, or other suitable methods.

[0028] In Figure 6(a), high-temperature annealing is performed on the semiconductor structure of Figure 5(a). During annealing, Al atoms from high-concentration regions (e.g., in the thin AlN film 31) gradually diffuse to and react with the adjacent active layer 314. After annealing, the Al film 319 cooperates with the active layer 314 to form an additional Al-diffusing active layer 321, wherein the Al concentration gradually decreases from the surface / boundary of the additional Al-diffusing active layer 321 toward its interior. In some embodiments, the annealing is completed in a temperature range of about 500°C to about 900°C.

[0029] In some embodiments, additional Al diffusion extends from the additional Al-diffused active layer 321 toward its interior to a depth of less than about 5 nm, forming a highly diffused Al layer (e.g., a high-Al diffusion layer 322), as shown in FIG6(a). Therefore, prior to high-temperature annealing, most of the additional Al-diffused active layer 321 beneath the high-Al diffusion layer 322 still has substantially the same Al concentration as the active layer 314. The interface between the high-Al diffusion layer 322 and the dielectric layer of the gate electrode formed thereon in subsequent steps naturally exhibits a high band barrier. In this manner, the high-Al diffusion layer 322 reduces the chance of electrons falling into lattice mismatch defects at the interface. Therefore, some characteristics related to interface trapping density (Dit), such as linear drain current degradation, current collapse, and dynamic on-state impedance R, can be significantly improved. ON .

[0030] In Figure 6(b), a high-temperature annealing similar to that in Figure 6(a) is performed on the semiconductor structure of Figure 5(b). During annealing, Al atoms from higher concentration regions (e.g., in the thin AlN film 319') gradually diffuse into and react with the adjacent active layer 314. After annealing, the Al film 319' cooperates with the active layer 314 to form an additional Al-diffusing active layer 321', wherein the Al concentration gradually decreases from the surface / boundary of the additional Al-diffusing active layer 321' toward its interior. In some embodiments, the annealing is completed in a temperature range of about 500°C to about 900°C.

[0031] In some embodiments, additional Al diffusion extends from the additional Al-diffused active layer 321' toward its interior to a depth of less than about 5 nm, forming a high-Al diffusion layer 322', as shown in FIG6(b). Therefore, prior to high-temperature annealing, most of the additional Al-diffused active layer 321' outside the high-Al diffusion layer 322' still has substantially the same Al concentration as the active layer 314. The high-Al diffusion layer 322' also improves several properties, such as interface trapping density, Idlin degradation, current collapse, and dynamic on-state impedance R. ON .

[0032] Before discussing the following formation process of the III-V HEMT structure, please refer to Figure 9 . Figure 9This is a graph illustrating energy dispersive X-ray (EDX) analysis of Ga and Al atoms according to some embodiments of this disclosure. In the EDX analysis, the additional Al-diffused active layer 321 is located at a depth of approximately 18 nm, and the region of high Al-diffused layer 322 or high Al-diffused layer 322' is located at a depth of approximately 18 nm to approximately 24 nm. EDX analysis shows that the main peak of Al atoms is located in the high Al-diffused layers 322 / 322'. Before high-temperature annealing, the Al concentration of the flat curve of Al atoms located at a depth deeper than approximately 24 nm is substantially the same as that of the active layer 314. In this embodiment, the total Al atoms of the main peak are approximately 26 atomic%, and the total Al atoms of the flat curve in the additional Al-diffused active layers 321 / 321' are approximately 18 atomic%. In some embodiments, the ratio of the Al concentration of the main peak to the Al concentration of the flat curve is approximately 1.1 to 2.5. Furthermore, at the same depth, the Al concentration of the main peak is lower than the Ga concentration. In some embodiments, the same results can be obtained by X-ray photoelectron spectroscopy (XPS) analysis or any other suitable method.

[0033] Referring to Figure 7(a), the gate structure 362 includes a conductive gate electrode 364 formed over the gate dielectric 320. The conductive gate electrode 364 may include any suitable conductive material, such as doped polysilicon, or a metal, such as titanium (Ti) or aluminum (Al). The gate dielectric 320 may include, for example, alumina (Al2O3), silicon dioxide (SiO2), or silicon nitride (Si3N4). The gate electrode 364 forms a non-ohmic contact on the surface of the high Al diffusion layer 322.

[0034] In a substantially similar manner, as shown in FIG7(b), the gate structure 362 includes forming a conductive gate electrode 364 over the gate dielectric 320. The conductive gate electrode 364 may comprise any suitable conductive material, such as doped polysilicon, or a metal, such as titanium (Ti) or aluminum (Al). The gate electrode 364 forms a non-ohmic contact on the surface of an additional Al-diffused active layer 321'.

[0035] In Figure 8(a), ohmic source contacts 372 and ohmic drain contacts 374 are provided on both sides of the gate electrode 364. The source and drain electrodes 372 and 374 are formed above and in contact with the surface of the high Al diffusion layer 322. In substantially the same manner, as shown in Figure 8(b), ohmic source contacts 372 and ohmic drain contacts 374 are provided on both sides of the gate electrode 364. The source and drain electrodes 372 and 374 are formed above and in contact with the surface of the high Al diffusion layer 322'. In this embodiment, the gate electrode 364 and drain electrode 374 are spaced approximately 20 micrometers apart by a distance L1, and approximately 15 micrometers apart by a distance L2 from the nearest end of the high Al diffusion layer 322' on the side of the gate electrode 364 and drain electrode 374. In some embodiments, the L2 / L1 ratio ranges from about 0 to about 0.8, and the distance L2 may represent the distance between the gate electrode 364 and the drain electrode 374 or the distance between the gate electrode 364 and the source electrode 372.

[0036] Generally, electrons in 2DEG 318 exhibit high carrier mobility. The conductivity in this region is adjusted by applying a voltage to the gate electrode 364. When a reverse voltage is applied, the conduction band near 2DEG 318 rises above the Fermi level, and a portion of 2DEG 318 depletes the carriers, thereby preventing current from flowing from the source electrode 372 to the drain electrode 374.

[0037] Figure 10 This is a graph illustrating the experimental results conducted by the inventors based on some embodiments disclosed herein, showing the values ​​of the interface trapping density Dit measured on III-V HEMTs fabricated at different depths with and without the high Al diffusion layer 322 / 322'. Different depths correspond to different energy levels, denoted as "0.2", "0.3", "0.4", "0.5", "0.6", and "0.7" eV, respectively, treated under the same conditions, differing only in the presence or absence of the high Al diffusion layer 322 / 322'. Smaller energy levels correspond to shallower depths from the surface of the additional Al diffusion active layer 321 / 321'. Compared to III-V HEMTs fabricated with the high Al diffusion layer 322 / 322'... Figure 10 Data points represented by "squares" in the text, III-V HEMTs fabricated without a high Al diffusion layer 322 / 322' ( Figure 10 Data points (represented by "diamonds") have a higher interface capture density at shallower depths (Dit).

[0038] Figure 11This is a graph illustrating the experimental results conducted by the inventors based on some embodiments disclosed herein, showing that the linear drain current (Idlin) degrades as a function of stress time measured on a group of III-V HEMTs fabricated with or without a high Al diffusion layer. It was found that III-V HEMTs fabricated with a high Al diffusion layer 322 / 322' exhibit less Idlin degradation compared to III-V HEMTs fabricated without a high Al diffusion layer 322 / 322' (i.e., square). The difference becomes more significant as stress time increases. Therefore, it can be understood that III-V HEMTs with a high Al diffusion layer 322 / 322' exhibit better performance, at least in terms of reliability.

[0039] Figure 12 This is a graph illustrating the experimental results conducted by the inventors according to embodiments disclosed herein, showing that the dynamic minimum "on" impedance (Rdson) ratio is a function of the stress voltage measured on a group of III-V HEMTs manufactured with or without the high Al diffusion layer 322 / 322'. It was found that III-V HEMTs manufactured with the high Al diffusion layer 322 / 322' have a smaller increase in the Rdson ratio compared to III-V HEMTs manufactured without the high Al diffusion layer 322 / 322' (i.e., square). In other words, the rate of increase in Rdson for HEMTs with the high Al diffusion layer 322 / 322' is less than that for HEMTs without the high Al diffusion layer 322 / 322'. This difference becomes more significant as the stress voltage increases. Therefore, it can be understood that III-V HEMTs with the high Al diffusion layer 322 / 322' exhibit better performance, at least in terms of reliability.

[0040] Some embodiments disclosed herein provide a semiconductor structure. The semiconductor structure includes: a channel layer; an active layer above the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) in the channel layer along an interface between the channel layer and the active layer; a gate electrode above a top surface of the active layer; and source / drain electrodes above the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to the bottom surface of the active layer, and the first layer has a higher aluminum (Al) atom concentration than the second layer.

[0041] The foregoing outlines some features of the embodiments, thus enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described in this application. Those skilled in the art should also understand that this equivalent architecture does not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

[0042] Symbol Explanation

[0043] 302 Semiconductor Substrate

[0044] 304 Transition Structure

[0045] 312 Channel Layer

[0046] 314 Active Layer

[0047] 318 Two-dimensional electron gas

[0048] 319 Thin AlN film

[0049] 319' thin AlN film

[0050] 320 gate dielectric

[0051] 321 Additional Al-diffused active layer

[0052] 321' Additional Al-diffused active layer

[0053] 322 High Al Diffusion Layer

[0054] 322' High Al diffusion layer

[0055] 362 gate structure

[0056] 364 Conductive Gate Electrode

[0057] 372 Ohm Source Contact

[0058] 374 Ohm Drain Contact

Claims

1. A high electron mobility transistor (HEMT) structure, comprising: Channel layer; A first additional Al-diffused active layer is located above the channel layer; The gate electrode is located above the first additional Al-diffused active layer; The source / drain electrodes are located above the first additional Al diffused active layer; as well as A second additional Al diffused active layer is partially located above the first additional Al diffused active layer. The second additional Al diffused active layer is located between the source / drain electrode and the channel layer. The second additional Al diffused active layer has a top surface facing away from the channel layer. The top surface of the second additional Al diffused active layer contacts the source / drain electrode, and the second additional Al diffused active layer is not disposed between the gate electrode and the channel layer. The first additional Al diffusion active layer has a depth of less than 5 nm. Compared with the first additional Al diffusion active layer, the second additional Al diffusion active layer has a higher Al atom concentration, and the Al atom concentration gradually decreases from the top surface of the second additional Al diffusion active layer toward the first additional Al diffusion active layer.

2. The HEMT structure according to claim 1, wherein the first additional Al diffused active layer and the second additional Al diffused active layer comprise aluminum gallium nitride (AlGaN).

3. The HEMT structure of claim 1, further comprising a gate dielectric located between the gate electrode and the first additional Al diffused active layer, the gate dielectric being configured to form a non-ohmic contact with the upper surface of the first additional Al diffused active layer.

4. A method for forming a semiconductor structure, comprising: Provides a channel layer, on which the active layer is formed; Perform surface treatment on the top surface of the active layer; An aluminum nitride (AlN) film is deposited above the top surface of the active layer by atomic layer deposition (ALD). as well as Annealing is performed on the AlN film to diffuse Al atoms from the AlN film into the active layer to form a high Al diffusion layer in the active layer, wherein the high Al diffusion layer has a depth of less than 5 nm and the Al atom concentration of the high Al diffusion layer gradually decreases from the top surface toward the interior of the active layer.

5. The method of claim 4, wherein performing the surface treatment on the top surface of the active layer comprises: Wet washing of the top surface of the active layer; and Annealing is performed on the top surface of the active layer at a first temperature.

6. The method of claim 5, wherein performing the annealing on the AlN film comprises: The AlN film is annealed at a second temperature, which is higher than the first temperature.

7. The method of claim 5, wherein performing the annealing on the top surface of the active layer comprises: A nitrogen-based ambient atmosphere is supplied to the top surface of the active layer.

8. The method of claim 4, wherein depositing the AlN film over the active layer comprises: The AlN film is deposited in a blanket manner over the active layer, with a thickness of 3 to 20 Al atoms.

9. The method according to claim 4, wherein the Al atom concentration in the AlN film is higher than the Al atom concentration in the active layer.

10. The method of claim 9, wherein the ratio of the Al atom concentration in the AlN film to the Al atom concentration in the active layer is 1.1 to 2.

5.

11. The method of claim 4, further comprising: A gate structure is formed above the active layer.

12. A method for forming a semiconductor structure, comprising: Accepts semiconductor substrates; An active layer is formed over the semiconductor substrate; An aluminum nitride (AlN) film is deposited above the top surface of the active layer, wherein the Al atom concentration in the AlN film is higher than the Al atom concentration in the active layer. Annealing is performed on the AlN film to form a high Al diffusion layer in the active layer, wherein the high Al diffusion layer has a depth of less than 5 nm and the Al atom concentration of the high Al diffusion layer gradually decreases from the top surface toward the interior of the active layer; A gate structure is formed above the active layer; as well as A source electrode and a drain electrode are formed on opposite sides of the gate structure, respectively.

13. The method of claim 12, wherein performing the annealing on the AlN film to form the high-Al diffusion layer in the active layer comprises: The AlN film is annealed to allow Al atoms to diffuse from the AlN film into the active layer, thereby forming the high Al diffusion layer in the active layer.

14. The method of claim 13, wherein before and after the annealing of the AlN film to form the high Al diffusion layer in the active layer, the active layer below the high Al diffusion layer has the same Al atom concentration.

15. The method of claim 13, wherein performing the annealing on the AlN film to form the high-Al diffusion layer in the active layer comprises: The AlN film is annealed within a temperature range of 500°C to 900°C to allow Al atoms to diffuse from the AlN film into the active layer.

16. The method of claim 13, wherein forming the gate structure over the active layer comprises: The gate structure is formed above and in contact with the high-Al diffusion layer.

17. The method of claim 13, wherein forming the source electrode and the drain electrode on opposite sides of the gate structure comprises: The source electrode and the drain electrode are formed above the high-Al diffusion layer and are in contact with the high-Al diffusion layer.

18. A method for forming a semiconductor structure, comprising: Accepts semiconductor substrates; A transition structure is formed over the semiconductor substrate; A channel layer is formed above the transition structure; An active layer is formed above the channel layer; An aluminum nitride (AlN) film is deposited above the top surface of the active layer, wherein the Al atom concentration in the AlN film is higher than the Al atom concentration in the active layer. Annealing is performed on the AlN film to form a high Al diffusion layer in the active layer, wherein the high Al diffusion layer has a depth of less than 5 nm and the Al atom concentration of the high Al diffusion layer gradually decreases from the top surface toward the interior of the active layer; A gate structure is formed above the active layer; as well as A source electrode and a drain electrode are formed on opposite sides of the gate structure, respectively.

19. The method of claim 18, wherein forming the transition structure over the semiconductor substrate comprises: A nucleation layer is formed above the semiconductor substrate; and A transition layer is formed above the crystal nucleus layer.

20. The method of claim 18, wherein forming the active layer over the channel layer comprises: The active layer is formed above the channel layer to generate a two-dimensional electron gas (2DEG) in the channel layer along the interface between the channel layer and the active layer.

21. The method of claim 18, wherein depositing the AlN film above the top surface of the active layer comprises: The AlN film is selectively deposited over the active layer to cover a portion of the top surface of the active layer.

22. The method of claim 18, wherein forming the gate structure over the active layer comprises: The gate structure is formed above the top surface of the active layer and is in contact with the top surface; and The formation of the source electrode and the drain electrode includes: The source electrode and the drain electrode are formed above the top surface of the high Al diffusion layer and are in contact with the top surface of the high Al diffusion layer.

23. The method of claim 22, wherein the gate structure is spaced apart from the drain electrode by a distance L1, the gate structure is spaced apart from the nearest end of the high Al diffusion layer by a distance L2, and the ratio of L2 to L1 is 0 to 0.

8.

24. A method for forming a semiconductor structure, comprising: Provides a channel layer, on which the active layer is formed; Annealing is performed on the top surface of the active layer at a first temperature; An aluminum nitride (AlN) film is deposited above the top surface of the active layer; as well as The AlN is annealed at a second temperature to allow Al atoms to diffuse from the AlN film into the active layer, thereby forming a high-Al diffusion layer in the active layer. The second temperature is higher than the first temperature, the high-Al diffusion layer has a depth of less than 5 nm, and the Al atom concentration of the high-Al diffusion layer gradually decreases from the top surface toward the interior of the active layer.

25. The method of claim 24, further comprising: The top surface of the active layer is wet-washed.

26. The method of claim 24, wherein the Al atom concentration in the AlN film is higher than the Al atom concentration in the active layer.

27. The method of claim 26, wherein the ratio of the Al atom concentration in the AlN film to the Al atom concentration in the active layer is 1.1 to 2.

5.

28. The method of claim 24, wherein performing the annealing on the top surface of the active layer comprises: A nitrogen-based ambient atmosphere is supplied to the top surface of the active layer.

29. The method of claim 24, wherein depositing the AlN film above the top surface of the active layer comprises: The AlN film is deposited over the active layer by atomic layer deposition (ALD).

30. The method of claim 24, wherein depositing the AlN film over the active layer comprises: The AlN film is deposited in a blanket manner over the active layer, with a thickness of 3 to 20 Al atoms.

31. A method for forming a semiconductor structure, comprising: Provides a channel layer, on which the active layer is formed; A nitrogen-based ambient atmosphere is supplied to the top surface of the active layer; An aluminum nitride (AlN) film is deposited above the top surface of the active layer; as well as Annealing is performed on the AlN film to form a high Al diffusion layer in the active layer, wherein the high Al diffusion layer has a depth of less than 5 nm and the Al atom concentration of the high Al diffusion layer gradually decreases from the top surface toward the interior of the active layer.

32. The method of claim 31, further comprising: The top surface of the active layer is wet-washed.

33. The method of claim 31, wherein the nitrogen-based ambient atmosphere is supplied to the top surface of the active layer at a first temperature. The AlN film is annealed at a second temperature, which is higher than the first temperature.

34. The method of claim 31, wherein performing the annealing on the AlN film comprises: The AlN film is subjected to the annealing process to allow Al atoms to diffuse from the AlN film into the active layer, wherein the Al atom concentration in the AlN film is higher than the Al atom concentration in the active layer.

35. The method of claim 34, wherein the ratio of the Al atom concentration in the AlN film to the Al atom concentration in the active layer is 1.1 to 2.

5.

36. The method of claim 31, wherein depositing the AlN film over the active layer comprises: The AlN film is deposited over the active layer by atomic layer deposition (ALD).

37. The method of claim 31, wherein depositing the AlN film over the active layer comprises: The AlN film is deposited in a blanket manner over the active layer, with a thickness of 3 to 20 Al atoms.

38. A method for forming a semiconductor structure, comprising: Provides a channel layer, on which the active layer is formed; Perform surface treatment on the top surface of the active layer; An aluminum nitride (AlN) film is deposited above the top surface of the active layer; as well as Annealing is performed on the AlN film to allow Al atoms to diffuse from the AlN film into the active layer, thereby forming a high-Al diffusion layer in the active layer, wherein the high-Al diffusion layer has a depth of less than 5 nm, the Al atom concentration in the AlN film is higher than the Al atom concentration in the active layer, and the Al atom concentration of the high-Al diffusion layer gradually decreases from the top surface toward the interior of the active layer.

39. The method of claim 38, further comprising: A gate structure is formed above the active layer.

40. The method of claim 39, further comprising: A source electrode and a drain electrode are formed on opposite sides of the gate structure, respectively.

41. The method of claim 39, wherein forming the gate structure over the active layer comprises: The gate structure is formed above and in contact with the high-Al diffusion layer.

42. The method of claim 38, wherein depositing the AlN film above the top surface of the active layer comprises: The AlN film is deposited over the active layer by atomic layer deposition (ALD).

43. The method of claim 38, wherein depositing the AlN film over the active layer comprises: The AlN film is deposited in a blanket manner over the active layer, with a thickness of 3 to 20 Al atoms.

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