Magnetic storage device and method of manufacturing a magnetic storage device

Abstract

The embodiments provide a magnetic storage device capable of suppressing the degradation of magnetoresistive elements and arranging the magnetoresistive elements in a high aspect ratio, and a method for manufacturing the magnetic storage device. One embodiment of the magnetic storage device includes a first conductor and a second conductor extending along a first direction, a third conductor and a fourth conductor extending above the first conductor and the second conductor along a second direction, and a first laminate, a second laminate, and a third laminate respectively disposed between the first conductor and the third conductor, between the first conductor and the fourth conductor, and between the second conductor and the third conductor. The cross-sectional shape of each of the first, second, and third laminates is circular. The height from the upper surface of the first part between the first and third laminates to the first surface and the height from the upper surface of the second part between the second and third laminates to the first surface are 90% to 110% of the first height. The first height is the average height of the upper surface of the first part and the upper surface of the second part.

Description

[0001] This application enjoys priority to Japanese Patent Application No. 2021-042396 (filed March 16, 2021) and U.S. Patent Application No. 17 / 472414 (filed September 10, 2021). This application incorporates the entire contents of the basic applications by reference. Technical Field

[0002] The embodiments relate to a magnetic storage device and a method for manufacturing a magnetic storage device. Background Technology

[0003] It is known that magnetic storage devices (MRAM: Magnetoresistive Random Access Memory) use magnetoresistive elements as storage elements. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a magnetic storage device and a method for manufacturing a magnetic storage device that can suppress the degradation of magnetoresistive elements and arrange the magnetoresistive elements in a high aspect ratio.

[0005] The magnetic storage device according to the embodiment includes: a first conductor and a second conductor extending along a first direction and arranged relative to each other along a second direction; a third conductor and a fourth conductor extending above the first conductor and the second conductor and arranged relative to each other along the second direction; a first laminate disposed between the first conductor and the third conductor, including a first magnetoresistive element; a second laminate disposed between the first conductor and the fourth conductor, including a second magnetoresistive element; a third laminate disposed between the second conductor and the third conductor, including a third magnetoresistive element; and an insulator disposed below the first laminate, the second laminate, and the third laminate between the first conductor and the second conductor.

[0006] Viewed from a third direction intersecting the first and second directions, the cross-sectional shape of the first laminate is circular; viewed from the third direction, the cross-sectional shape of the second laminate is circular; viewed from the third direction, the cross-sectional shape of the third laminate is circular. The upper surfaces of the first, second, and third laminates are located within a first plane encompassing the first and second directions. The height from the upper surface of the first portion between the first and third laminates in the insulator to the first plane and the height from the upper surface of the second portion between the second and third laminates in the insulator to the first plane are both within a range of 90% to 110% of a first height. The first height is the average height of the upper surface of the first portion and the upper surface of the second portion. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the structure of a magnetic storage device for implementing an embodiment.

[0008] Figure 2 This is a circuit diagram illustrating the structure of the storage cell array of the magnetic storage device according to the embodiments.

[0009] Figure 3 This is a top view illustrating the structure of the storage cell array of the magnetic storage device used to explain the implementation method.

[0010] Figure 4 This is a cross-sectional view illustrating the structure of the storage cell array of the magnetic storage device used to explain the implementation method.

[0011] Figure 5 This is a cross-sectional view illustrating the structure of the storage cell array of the magnetic storage device used to explain the implementation method.

[0012] Figure 6 This is a cross-sectional view illustrating the structure of the storage cell array of the magnetic storage device used to explain the implementation method.

[0013] Figure 7 This is a cross-sectional view illustrating the structure of the magnetoresistive element of the magnetic storage device in the embodiment.

[0014] Figure 8 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0015] Figure 9 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0016] Figure 10This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0017] Figure 11 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0018] Figure 12 This is a top view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0019] Figure 13 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0020] Figure 14 This is a schematic diagram illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0021] Figure 15 This is a diagram showing the intensity of the ion beam emitted during the manufacturing method of the memory cell array in the magnetic storage device used to illustrate the embodiments.

[0022] Figure 16 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0023] Figure 17 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0024] Figure 18 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0025] Figure 19 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0026] Figure 20 This is a cross-sectional view illustrating a method for manufacturing a storage cell array in a magnetic storage device according to an embodiment.

[0027] Figure 21 This is a cross-sectional view used to illustrate the structure of the storage cell array of a modified magnetic storage device.

[0028] Figure 22 This is a cross-sectional view used to illustrate the structure of the storage cell array of a modified magnetic storage device.

[0029] Figure 23 This is a cross-sectional view used to illustrate the structure of the storage cell array of a modified magnetic storage device.

[0030] Explanation of reference numerals in the attached figures

[0031] 1…Magnetic storage device, 10…Storage cell array, 11…Row selection circuit, 12…Column selection circuit, 13…Decoding circuit, 14…Write circuit, 15…Read circuit, 16…Voltage generation circuit, 17…Input / output circuit, 18…Control circuit, 20…Semiconductor substrate, 21, 24…Conductors, 22, 23…Components, 31, 32, 34, 36…Nonmagnetic materials, 33, 35, 37…Ferromagnetic materials, 41, 45, 46…Insulators, 42…Magnetic reluctance effect element layer, 43…Selection layer, 44, 44A…Mask. Detailed Implementation

[0032] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, components having the same function and structure are labeled with common reference numerals. Additionally, when multiple components sharing common reference numerals are distinguished, superscripts are added to these common reference numerals for differentiation. Furthermore, when it is not particularly necessary to distinguish multiple components, only common reference numerals are used for these multiple components, without superscripts. Here, superscripts are not limited to subscript characters or superscript characters, but include, for example, lowercase letters added to the end of the reference numerals and indices indicating arrangement.

[0033] 1. Implementation Method

[0034] The magnetic storage device of the embodiment will be described. The magnetic storage device of the embodiment includes, for example, a magnetic storage device using a vertically magnetized element that has a magnetoresistance effect through a magnetic tunnel junction (MTJ) as the resistance-changing element. Hereinafter, the element having the aforementioned magnetoresistance effect element will be referred to as a magnetoresistance effect element (MTJ) for description.

[0035] 1.1 Structure

[0036] First, the structure of the magnetic storage device according to the embodiment will be described.

[0037] 1.1.1 Structure of Magnetic Storage Devices

[0038] Figure 1 This is a block diagram illustrating the structure of a magnetic storage device according to an embodiment. Figure 1 As shown, the magnetic storage device 1 includes a storage cell array 10, a row selection circuit 11, a column selection circuit 12, a decoding circuit 13, a writing circuit 14, a reading circuit 15, a voltage generation circuit 16, an input / output circuit 17, and a control circuit 18.

[0039] The storage cell array 10 has multiple storage cells MC, each associated with a group of rows and columns. Specifically, storage cells MC in the same row are connected to the same word line WL, and storage cells MC in the same column are connected to the same bit line BL.

[0040] Row selection circuit 11 is connected to memory cell array 10 via word line WL. The row selection circuit 11 is supplied with the decoding result (row address) of address ADD from decoding circuit 13. Row selection circuit 11 sets the word line WL corresponding to the row based on the decoding result of address ADD to a selected state. Hereinafter, the word line WL set to the selected state is referred to as the selected word line WL. Furthermore, word lines WL other than the selected word line WL are referred to as non-selected word lines WL.

[0041] Column selection circuit 12 is connected to memory cell array 10 via bit line BL. The column selection circuit 12 is supplied with the decoding result (column address) of address ADD from decoding circuit 13. Column selection circuit 12 sets the bit line BL corresponding to the column of the decoding result based on address ADD to a selected state. Hereinafter, the bit line BL set to the selected state is referred to as the selected bit line BL. Furthermore, the bit lines BL other than the selected bit line BL are referred to as non-selected bit lines BL.

[0042] Decoding circuit 13 decodes the address ADD from input / output circuit 17. Decoding circuit 13 supplies the decoding result of address ADD to row selection circuit 11 and column selection circuit 12. Address ADD includes the selected column address and row address.

[0043] The write circuit 14 writes data to the storage unit MC. The write circuit 14 includes, for example, a write driver (not shown).

[0044] The readout circuit 15 reads data from the storage cell MC. The readout circuit 15 includes, for example, a readout amplifier (not shown).

[0045] The voltage generation circuit 16 uses a power supply voltage (not shown) supplied from an external source (external source) of the magnetic storage device 1 to generate voltages for various operations of the storage cell array 10. For example, the voltage generation circuit 16 generates various voltages required during a write operation and outputs them to the write circuit 14. Additionally, for example, the voltage generation circuit 16 generates various voltages required during a read operation and outputs them to the read circuit 15.

[0046] Input / output circuit 17 transmits the address ADD from outside the magnetic storage device 1 to the decoding circuit 13. Input / output circuit 17 transmits the command CMD from outside the magnetic storage device 1 to the control circuit 18. Input / output circuit 17 transmits and receives various control signals CNT between outside the magnetic storage device 1 and the control circuit 18. Input / output circuit 17 transmits data DAT from outside the magnetic storage device 1 to the write circuit 14, and outputs the data DAT transmitted from the read circuit 15 to outside the magnetic storage device 1.

[0047] The control circuit 18 controls the operation of the row selection circuit 11, column selection circuit 12, decoding circuit 13, writing circuit 14, reading circuit 15, voltage generation circuit 16 and input / output circuit 17 in the magnetic storage device 1 based on the control signal CNT and the command CMD.

[0048] 1.1.2 Structure of Storage Cell Array

[0049] Next, use Figure 2 The structure of the storage cell array of the magnetic storage device according to the embodiment will be described. Figure 2 This is a circuit diagram illustrating the structure of a memory cell array in a magnetic storage device according to an embodiment. Figure 2 In the text, the character line WL is indicated by a subscript including the index "<>".

[0050] like Figure 2 As shown, the memory cells MC are arranged in a matrix within the memory cell array 10, and are connected to multiple bit lines BL (BL... <0> BL <1> BL <n>One or more word lines WL (WL) <0> WL <1> ..., WL <m>One of the group associations in ) (M and N are natural numbers greater than 2). That is, the storage unit MC<i,j> (0≤i≤M,0≤j≤N) Connected to word line WL With bit line BL <j>between.

[0051] Storage unit MC<i,j> Including series-connected switching elements SEL<i,j> and magnetoresistive element MTJ<i,j> .

[0052] The switching element SEL functions as a switch to control the supply of current to the corresponding magnetoresistive element MTJ during data writing and reading. More specifically, for example, when the voltage applied to the memory cell MC is lower than the threshold voltage Vth, the switching element SEL, acting as an insulator with high resistance, cuts off the current (becomes in the OFF state); when the voltage is higher than the threshold voltage Vth, it acts as a conductor with low resistance, allowing current to flow (becomes in the ON state). That is, the switching element SEL has the following function: regardless of the direction of the flowing current, it can switch between allowing current to flow or cutting off the current based on the magnitude of the voltage applied to the memory cell MC.

[0053] The switching element SEL can also be a two-terminal switching element, for example. When the voltage applied between the two terminals is below a threshold, the switching element is in a "high resistance" state, for example, a non-conducting state. When the voltage applied between the two terminals is above the threshold, the switching element becomes a "low resistance" state, for example, a conducting state. The switching element can also have this function regardless of the polarity of the voltage.

[0054] The magnetoresistive element (MTJ) can switch its resistance state between low and high resistance states by the current controlled by the switching element (SEL). The MTJ can write data through changes in its resistance state, functioning as a storage element that can non-volatilely retain and read the written data.

[0055] Next, use Figure 3 The shape of the memory cell MC in the memory cell array 10 and the configuration of the memory cell MC relative to the bit line BL and word line WL are described. Figure 3 This shows an example of a top view illustrating the structure of a memory cell array in a magnetic storage device used to explain an embodiment. Figure 3 The image shows a memory cell array 10 with three word lines WL. <m-1>、WL <m>and WL<m+1> With 3 bit lines BL <n-1>、BL <n>and BL<n+1> Multiple storage units MC (1≤m≤M-1, 1≤n≤N-1) are defined between these units. Furthermore, for ease of explanation, in... Figure 3 The interlayer insulating film is omitted from the diagram.

[0056] like Figure 3 As shown, the memory cell array 10 is disposed above the semiconductor substrate 20. In the following description, the plane parallel to the surface of the semiconductor substrate 20 is designated as the XY plane, and the axis perpendicular to the XY plane is designated as the Z-axis. The direction approaching the semiconductor substrate 20 along the Z-axis is designated as "downward", and the direction moving away from the semiconductor substrate 20 along the Z-axis is designated as "upward". In the XY plane, one of the two mutually orthogonal axes is designated as the X-axis and the Y-axis.

[0057] Multiple memory cells (MCs) are positioned between the word line (WL) and the bit line (BL). Figure 3 The example shows a case where the word line WL is placed below the memory cell MC and the bit line BL is placed above the memory cell MC, but it is not limited to this case. The vertical relationship between the word line WL and the bit line BL can also be reversed.

[0058] Multiple memory cells MC each have a circular shape along the XY cross section (the outer diameter of the memory cell MC is approximately the same regardless of the direction within the XY cross section).

[0059] Multiple word lines (WL) extend along the X-axis and are arranged along the Y-axis. Multiple bit lines (BL) extend along the Y-axis and are arranged along the X-axis. The distance between two word lines (WL) and the distance between two bit lines (BL) can, for example, be set to be substantially equal. A memory cell (MC) is provided at the intersection of one bit line (BL) and one word line (WL). That is, two memory cells (MC) that are grounded adjacent to the same bit line (BL) or the same word line (WL) are (e.g., memory cell MC).<m,n> and MC<m,n-1> Or storage unit MC<m,n> and MC<m-1,n> The length d1 of the distance between two storage cells MC arranged diagonally (e.g., storage cell MC) is greater than that between two storage cells MC arranged diagonally.<m+1,n> and MC<m,n+1> The length d2 of the distance between them is shorter.

[0060] Next, use Figure 4 , Figure 5 and Figure 6 The cross-sectional structure of the memory cell array 10 will be described. Figure 4 , Figure 5 and Figure 6 An example of a cross-sectional view showing the structure of a storage cell array for illustrating an embodiment of a magnetic storage device is shown. Figure 4 , Figure 5 and Figure 6 They are along Figure 3 The cross-sectional views of lines IV-IV, VV, and VI-VI.

[0061] like Figure 4 , Figure 5 and Figure 6 As shown, the memory cell array 10 is disposed above the semiconductor substrate 20.

[0062] For example, a plurality of conductors 21 are disposed on the upper surface of the semiconductor substrate 20. Each of the plurality of conductors 21 extends along the X-axis and is arranged along the Y-axis. Each of the plurality of conductors 21 is conductive and functions as a word line WL. An insulator 41 is disposed between adjacent conductors 21. Thus, the plurality of conductors 21 are insulated from each other. Furthermore, in Figure 4 , Figure 5 and Figure 6 The description illustrates the case where multiple conductors 21 are disposed on the semiconductor substrate 20, but is not limited thereto. For example, the multiple conductors 21 may also be disposed away from the semiconductor substrate 20 without being grounded.

[0063] Multiple elements 22, each functioning as a magnetoresistive effect element (MTJ), are disposed on the upper surface of a single conductor 21. Each element 22 has a height L1 along the Z-axis and a conical shape with a cross-sectional area decreasing from bottom to top along the XY plane. The multiple elements 22 disposed on the upper surface of the single conductor 21 are arranged, for example, along the X-axis. That is, multiple elements 22 arranged along the X-axis are connected together on the upper surface of the single conductor 21. Further details regarding the structure of the elements 22 will be described later.

[0064] Along in insulator 41 Figure 4 The upper surface of portion 41A between two adjacent elements 22 in the cross-section shown is located at a height L2a below the lower surface of element 22. The height of the upper surface of portion 41A remains almost unchanged regardless of the distance from element 22.

[0065] Additionally, along the insulator 41 Figure 5 The upper surface of portion 41B between two adjacent elements 22 in the cross-section shown is located at a height L2b below the lower surface of element 22. The height of the upper surface of portion 41B is the same as that of the upper surface of portion 41A, and remains almost unchanged regardless of the distance from element 22.

[0066] Additionally, along the conductor 21 Figure 6 The upper surface of portion 21A between two adjacent elements 22 in the cross-section shown is located at a height L2c below the lower surface of element 22. The height of the upper surface of portion 21A is the same as that of the upper surfaces of portions 41A and 41B, and remains almost unchanged regardless of the distance from element 22.

[0067] A component 23, functioning as a switching element SEL, is disposed on the upper surface of each of the plurality of components 22. Like components 22, component 23 has a tapered shape in which the cross-sectional area decreases from bottom to top along the XY plane. The upper surface of each of the plurality of components 23 is connected to any one of the plurality of conductors 24.

[0068] Multiple conductors 24 each extend along the Y-axis and are arranged along the X-axis. Each conductor 24 is conductive and functions as a bit line BL. A single conductor 24 connects to multiple elements 23 arranged along the Y-axis. Furthermore, in... Figure 4 , Figure 5 and Figure 6 The description illustrates the case where multiple elements 23 are each disposed on element 22 and conductor 24, but is not limited thereto. For example, each of the multiple elements 23 may also be connected to element 22 and conductor 24 via conductive contact plugs (not shown).

[0069] In the structure of the memory cell array 10 described above, heights L2a, L2b, and L2c can be considered to be at the same level. That is, the upper surface of portion 41A of the insulator 41, the upper surface of portion 41B, and portion 21A of the conductor 21 can be considered to be at the same height. Specifically, for example, the ratio of height (L1+L2a) to a predetermined reference height Lref is 0.9 or more and 1.1 or less (0.9≤(L1+L2a) / Lref≤1.1). Similarly, the ratio of height (L1+L2b) to the aforementioned reference height Lref is 0.9 or more and 1.1 or less (0.9≤(L1+L2b) / Lref≤1.1). Furthermore, the ratio of height (L1+L2c) to the aforementioned reference height Lref is 0.9 or more and 1.1 or less (0.9≤(L1+L2c) / Lref≤1.1). The reference height Lref can be, for example, the average height (L1+L2a), (L1+L2b) and (L1+L2c) / 3. However, it is not limited to this. The reference height Lref can also be, for example, the average height between the upper surface of each of four or more portions selected from portions 41A, 41B and 21A and the upper surface of element 22.

[0070] Furthermore, in the following description, the ratio of the height of element 22 to the distance between two elements 22 arranged along the X-axis or Y-axis is also called the aspect ratio AR. Figures 3-6 In the example, where the distance between two elements arranged along the X-axis or Y-axis is considered as the length d1, the aspect ratio AR of the memory cell array 10 is defined, for example, by AR = L1 / d1. The aspect ratio AR is preferably set to 1 or more, more preferably to about 1.5 or more. Furthermore, the length d1 is preferably set to, for example, 50 nanometers (nm) or less.

[0071] 1.1.3 Magnetoresistive effect element

[0072] Next, use Figure 7 The structure of the magnetoresistive effect element of the magnetic device in the embodiment will be described. Figure 7 This is a cross-sectional view illustrating the structure of the magnetoresistive effect element of the magnetic device according to an embodiment. Figure 7 In (A), an example of a cross-section is shown when the tunnel barrier layer TB within the magnetoresistive element MTJ is cut along the XY plane. Figure 7 In (B), for example, it is shown that... Figure 4 , Figure 5 and Figure 6 An example of a cross-section of the magnetoresistive element MTJ when cut along a plane perpendicular to the Z-axis (e.g., the XZ plane).

[0073] First, refer to Figure 7 (A) is used to explain the cross-sectional shape of the magnetoresistive element MTJ along the XY plane.

[0074] like Figure 7 As shown in (A), the magnetoresistive element MTJ, when viewed from above, is, for example, configured as a circle with an outer diameter of length d3 (the outer diameter of the magnetoresistive element MTJ is approximately the same regardless of its orientation in the XY plane). Furthermore, in Figure 7 In (A), as an example, the shape of the cross-section along the XY plane in the tunnel barrier layer TB is described, but regarding the shape of other layers within the magnetoresistive element MTJ, its general overview, apart from the difference in size caused by the conical shape along the Z-axis, is similar to... Figure 7 The situation in (A) is the same.

[0075] The length d3 is preferably set to, for example, 20 nanometers (nm) or less, and the requirement for this length d3 (e.g., d3 ≤ 20 nanometers) and the requirement for the length d1 mentioned above (e.g., d1 ≤ 50 nanometers) are preferably satisfied simultaneously.

[0076] Next, refer to Figure 7 (B) describes the cross-sectional shape of the magnetoresistive element MTJ along the Z-axis.

[0077] Magnetoresistive element (MTJ) includes, for example, a non-magnetic material 31 that functions as a top layer (TOP), a non-magnetic material 32 that functions as a capping layer (CAP), a ferromagnetic material 33 that functions as a storage layer (SL), a non-magnetic material 34 that functions as a tunnel barrier layer (TB), a ferromagnetic material 35 that functions as a reference layer (RL), a non-magnetic material 36 that functions as a spacer layer (SP), a ferromagnetic material 37 that functions as a shift cancelling layer (SCL), and a non-magnetic material 38 that functions as an under layer (UL).

[0078] In a magnetoresistive element (MTJ), for example, multiple films are stacked in the following order from the word line WL side to the bit line BL side (in the Z-axis direction): non-magnetic material 38, ferromagnetic material 37, non-magnetic material 36, ferromagnetic material 35, non-magnetic material 34, ferromagnetic material 33, non-magnetic material 32, and non-magnetic material 31. The magnetoresistive element (MTJ) functions, for example, as a vertically magnetized type MTJ where the magnetization direction of the magnetic materials constituting the MTJ is perpendicular to the film surface. Furthermore, the magnetoresistive element (MTJ) may also include further layers (not shown) between different pairs of the aforementioned layers 31 to 38.

[0079] The non-magnetic body 31 is a non-magnetic conductor. The non-magnetic body 31 functions as a top electrode, improving the electrical connection between the upper end of the magnetoresistive element MTJ and the bit line BL or word line WL. The non-magnetic body 31 may contain, for example, at least one element or compound selected from tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and titanium nitride (TiN).

[0080] The nonmagnetic body 32 is a layer of nonmagnetic material. The nonmagnetic body 32 has the function of suppressing the rise of the damping constant of the ferromagnetic body 33, thereby reducing the write current. The nonmagnetic body 32 may contain oxygen and magnesium or be substantially formed of magnesium oxide (MgO), or contain nitrogen and magnesium or be substantially formed of magnesium nitride (MgN), or contain nitrogen and zirconium or be substantially formed of zirconium nitride (ZrN), or contain nitrogen and niobium or be substantially formed of niobium nitride (NbN), or contain nitrogen and silicon or be substantially formed of silicon nitride (SiN), or contain nitrogen and aluminum or be substantially formed of aluminum nitride (AlN), or contain nitrogen and hafnium or be substantially formed of hafnium nitride. The nonmagnetic body 32 may be formed from (HfN), or contain nitrogen and tantalum or be substantially formed from tantalum nitride (TaN), or contain nitrogen and tungsten or be substantially formed from tungsten nitride (WN), or contain nitrogen and chromium or be substantially formed from chromium nitride (CrN), or contain nitrogen and molybdenum or be substantially formed from molybdenum nitride (MoN), or contain nitrogen and titanium or be substantially formed from titanium nitride (TiN), or contain nitrogen and vanadium or contain at least one composition, nitride, or oxide substantially selected from vanadium nitride (VN). Additionally, the nonmagnetic body 32 may also be a mixture of these compositions, nitrides, or oxides. That is, the nonmagnetic body 32 is not limited to a binary compound formed from two elements, and may contain a ternary compound formed from three elements, for example, containing nitrogen, titanium, and aluminum, or substantially containing aluminum titanium nitride (AlTiN), etc.

[0081] The ferromagnetic material 33 is ferromagnetic. The easy magnetization axis of the ferromagnetic material 33 is perpendicular to the film surface. Therefore, the ferromagnetic material 33 has a magnetization direction along the Z-axis toward either the bit line BL side or the word line WL side. The ferromagnetic material 33 comprises at least one of iron (Fe), cobalt (Co), and nickel (Ni), and also comprises boron (B). More specifically, for example, the ferromagnetic material 33 can be substantially formed of iron cobalt boron (FeCoB) and have a body-centered cubic lattice structure. Alternatively, it can be substantially formed of iron boride (FeB) and have a body-centered cubic lattice structure.

[0082] The nonmagnetic body 34 is a nonmagnetic insulator. The nonmagnetic body 34 may contain, for example, oxygen and magnesium, or be substantially formed of magnesium oxide (MgO), and may also contain boron (B). The nonmagnetic body 34 has a NaCl crystal structure with the film orientation of the (001) plane. During the crystallization process of the ferromagnetic body 33, the nonmagnetic body 34 functions as a seed material for the growth of a crystalline film from the interface with the ferromagnetic body 33. The nonmagnetic body 34 is disposed between the ferromagnetic body 33 and the ferromagnetic body 35, forming a magnetic tunnel junction together with these two ferromagnetic bodies.

[0083] The ferromagnetic material 35 is ferromagnetic. The easy magnetization axis of the ferromagnetic material 35 is perpendicular to the film surface. Therefore, the ferromagnetic material 35 has a magnetization direction along the Z-axis toward either the bit line BL side or the word line WL side. The ferromagnetic material 35 may, for example, contain at least one of iron (Fe), cobalt (Co), and nickel (Ni). Additionally, the ferromagnetic material 35 may also contain boron (B). More specifically, for example, the ferromagnetic material 35 may contain iron cobalt boron (FeCoB) or iron boride (FeB) and have a body-centered cubic lattice structure. The magnetization direction of the ferromagnetic material 35 is fixed. Figure 7 In the example, the direction is along the Z-axis toward the bit line BL side. Furthermore, "the magnetization direction is fixed" means that the magnetization direction does not change due to a current of a magnitude that can reverse the magnetization direction of the ferromagnetic body 33.

[0084] In addition, although Figure 7 The illustration is omitted, but the ferromagnetic body 35 can also be a stack of multiple layers. Specifically, for example, the stack constituting the ferromagnetic body 35 can also be a structure having the aforementioned layer containing iron cobalt boron (FeCoB) or iron boride (FeB) as an interface layer with the nonmagnetic body 34, and further ferromagnetic bodies stacked between the interface layer and the nonmagnetic body 36 via a nonmagnetic conductor. The nonmagnetic conductor in the stack constituting the ferromagnetic body 35 can, for example, contain at least one metal selected from tantalum (Ta), hafnium (Hf), tungsten (W), zirconium (Zr), molybdenum (Mo), niobium (Nb), and titanium (Ti). The further ferromagnetic body in the stack constituting the ferromagnetic body 35 can, for example, contain at least one multilayer film selected from a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), a multilayer film of cobalt (Co) and nickel (Ni) (Co / Ni multilayer film), and a multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

[0085] The nonmagnetic body 36 is a nonmagnetic conductor. The nonmagnetic body 36 contains, for example, at least one element selected from ruthenium (Ru), osmium (Os), iridium (Ir), vanadium (V), and chromium (Cr).

[0086] Ferromagnetic material 37 is ferromagnetic. The easy magnetization axis of ferromagnetic material 37 is perpendicular to the film surface. Ferromagnetic material 37 has a magnetization direction along the Z-axis toward either the bit line BL side or the word line WL side. The magnetization direction of ferromagnetic material 37 is fixed in the same way as that of ferromagnetic material 35. Figure 7 In the example, the direction is towards the WL side of the character line. Ferromagnetic body 37, for example, comprises at least one alloy selected from cobalt-platinum (CoPt), cobalt-nickel (CoNi), and cobalt-palladium (CoPd). Like ferromagnetic body 35, ferromagnetic body 37 can also be a laminate composed of multiple layers. In this case, ferromagnetic body 37 can, for example, comprise at least one multilayer film selected from a multilayer film of cobalt (Co) and platinum (Pt) (Co / Pt multilayer film), a multilayer film of cobalt (Co) and nickel (Ni) (Co / Ni multilayer film), and a multilayer film of cobalt (Co) and palladium (Pd) (Co / Pd multilayer film).

[0087] Ferromagnetic materials 35 and 37 are antiferromagnetically coupled through a nonmagnetic material 36. That is, ferromagnetic materials 35 and 37 are coupled with mutually antiparallel magnetization directions. Figure 7 In the example, the magnetization directions of ferromagnetic materials 35 and 37 are opposite. This coupled structure of ferromagnetic material 35, non-magnetic material 36, and ferromagnetic material 37 is called a SAF (Synthetic Anti-Ferromagnetic) structure. Thus, ferromagnetic material 37 can counteract the influence of the leakage magnetic field of ferromagnetic material 35 on the magnetization direction of ferromagnetic material 33. Therefore, the asymmetry in the reversal ease of magnetization of ferromagnetic material 33 caused by the leakage magnetic field of ferromagnetic material 35 can be suppressed (i.e., the reversal ease of magnetization of ferromagnetic material 33 differs depending on whether the magnetization direction is reversed from one direction to the other and from the other direction to one direction).

[0088] The non-magnetic body 38 is a non-magnetic conductor. The non-magnetic body 38 functions as an electrode to improve the electrical connection with the bit line BL and the word line WL. Furthermore, the non-magnetic body 38 may contain, for example, a high-melting-point metal. The high-melting-point metal may be, for example, a material with a melting point higher than iron (Fe) and cobalt (Co). The high-melting-point metal may contain, for example, at least one element selected from zirconium (Zr), hafnium (Hf), tungsten (W), chromium (Cr), molybdenum (Mo), niobium (Nb), titanium (Ti), tantalum (Ta), vanadium (V), ruthenium (Ru), and platinum (Pt).

[0089] In this implementation, a spin injection writing method is employed: a write current flows through a magnetoresistive element (MTJ), and the spin torque generated by this write current acts on the storage layer SL and the reference layer RL, controlling the magnetization direction of the storage layer SL and the reference layer RL. The magnetoresistive element MTJ can operate in either a low-resistance state or a high-resistance state depending on whether the magnetization directions of the storage layer SL and the reference layer RL are parallel or antiparallel.

[0090] If in Figure 7 If a write current Ic0 of a certain magnitude flows into the magnetoresistive element MTJ in the direction of arrow A1 (from the storage layer SL towards the reference layer RL), then the relative magnetization directions of the storage layer SL and the reference layer RL become parallel. In this parallel state, the resistance value of the magnetoresistive element MTJ becomes lower, and the magnetoresistive element MTJ is set to a low-resistance state. The low-resistance state is called the "P (Parallel) state," which is, for example, defined as the state of data "0".

[0091] Additionally, if in Figure 7 If a write current Ic1, larger than the write current Ic0, flows into the magnetoresistive element MTJ in the direction of arrow A2 (from the reference layer RL towards the storage layer SL, along the Z direction and opposite to arrow A1), then the relative magnetization directions of the storage layer SL and the reference layer RL become antiparallel. In this antiparallel state, the resistance of the magnetoresistive element MTJ becomes high, and the magnetoresistive element MTJ is set to a high-resistance state. This high-resistance state is called the "AP (Anti-Parallel) state," and is, for example, defined as the state of data "1".

[0092] Furthermore, the following explanation follows the method of defining the data as described above, but the method of defining data "1" and data "0" is not limited to the examples above. For example, the P state can also be defined as data "1" and the AP state as data "0".

[0093] 1.2 Manufacturing Method of Memory Cell Array

[0094] Next, the manufacturing method of the memory cell array of the magnetic storage device according to the embodiment will be described. In the following description, details regarding the stacked structure constituting the magnetoresistive element MTJ and the switching element SEL will be omitted.

[0095] Figures 8-11 , Figure 13 and Figures 16-20 This is a cross-sectional view illustrating a method for manufacturing a storage cell array of a magnetic storage device according to an embodiment. Figure 8 , Figure 11 , Figure 13 , Figure 16 , Figure 19 and Figure 20 Showing with Figure 4 The corresponding cross section. Figure 9 and Figure 17 Show respectively with Figure 8 and Figure 16 The state of the same process. Figure 9 and Figure 17 Showing with Figure 5 The corresponding cross section. Figure 10 Showing with Figure 8 and Figure 9 The state in the same process, Figure 18 Showing with Figure 16 and Figure 17 The state of the same process. Figure 10 and Figure 18 Showing with Figure 6 The corresponding cross-section. Additionally... Figure 12 This is a top view of the storage cell array 10 viewed from above. Figure 12 Showing with Figure 11 The state of the same process. Figure 14 and Figure 15 Showing with Figure 13 The state during the same process. Additionally... Figure 14 The process of forming a magnetoresistive element (MTJ) and a switching element (SEL) using ion beam etching is schematically illustrated. Additionally, Figure 15 This is a diagram illustrating the intensity of the ion beam emitted during etching using an ion beam.

[0096] like Figures 8-10 As shown, a plurality of conductors 21 are disposed on the upper surface of the semiconductor substrate 20, which serves as the wafer WF. Specifically, firstly, after a conductor layer is disposed on the upper surface of the semiconductor substrate 20, a mask with partial openings except for the area corresponding to the word line WL is formed by photolithography or the like. Then, the conductor layer is cut off by anisotropic etching of the formed mask to form a plurality of conductors 21, and holes reaching the semiconductor substrate 20 are formed. The anisotropic etching in this process is, for example, RIE (Reactive Ion Etching). Afterward, an insulator 41 is disposed within the formed holes.

[0097] Next, as Figure 11 and Figure 12 As shown, a magnetoresistive effect element layer 42, a selection layer 43, and a mask 44 are sequentially formed on the upper surfaces of the conductor 21 and the insulator 41.

[0098] Specifically, firstly, a magnetoresistive effect element layer 42 is disposed on the upper surface of the conductor 21 and the insulator 41. The magnetoresistive effect element layer 42 is... Figure 7 The magnetoresistive element MTJ, as described above, consists of layers that are stacked in a planar stack according to their stacking order.

[0099] Next, a selection layer 43 is provided on the upper surface of the magnetoresistive effect element layer 42. The selection layer 43 is a laminate of at least one layer structure that functions as a switching element SEL, which is formed into a flat plate according to its stacking order.

[0100] Next, a mask 44, partially open except for the regions corresponding to the magnetoresistive element MTJ and switching element SEL in the magnetoresistive element layer 42 and the select layer 43, is formed on the upper surface of the select layer 43 by photolithography or the like. The mask 44, for example, comprises titanium nitride (TiN) and protects the portions functioning as the magnetoresistive element MTJ and switching element SEL during the ion beam etching described later. The mask 44 is provided, for example, on the upper surface of the select layer 43 as a plurality of cylindrical structures arranged in a matrix, each of which protects a region corresponding to one memory cell MC. The diameter of the cylinder is, for example, larger than... Figure 7 The length d3 of the tunnel barrier layer TB shown is large.

[0101] Next, as Figure 13 and Figure 14 As shown, the magnetoresistive effect element layer 42 and the selection layer 43 are etched by ion beam etching. As a result, the portions of the magnetoresistive effect element layer 42 and the selection layer 43 that are not protected by the mask 44 are removed, exposing the conductor 21 and the insulator 41 located below these portions.

[0102] During ion beam etching, the process was completed. Figure 12 The wafer WF, processed up to this point, is mounted on a stage (not shown) within an ion beam generation apparatus. This stage supports the wafer WF in a manner that allows it to rotate about the Z-axis. Then, as... Figure 13 As shown, the ion beam generating apparatus emits an ion beam at a predetermined incident angle α onto the wafer WF on the stage ST. Here, the incident angle α is defined as the angle between the surface of the wafer WF and the ion beam. The incident angle α is an angle greater than 0 degrees and less than 90 degrees (0 degrees < α < 90 degrees). The stage rotates the wafer WF about the Z-axis at a predetermined angular velocity. Figure 14 As shown, the azimuth angle θ changes as axis A rotates about the Z-axis according to the rotation of the wafer WF. Here, the azimuth angle θ is defined as the angle between a predetermined axis A (e.g., the X-axis or Y-axis) within the surface of the wafer WF and the projection of the ion beam onto the surface of the wafer WF. Figure 14 In this context, a predetermined axis A is defined within the wafer WF surface, and the mask 44 is arranged in the direction of the shortest distance (i.e., the direction in which each of the multiple conductors 21 extends or the direction in which the multiple conductors 21 are arranged).

[0103] During ion beam etching, such as Figure 15 As shown, the ion beam generating device continuously varies the intensity of the emitted ion beam according to the azimuth angle θ. Figure 15 The example shown illustrates the intensity of the emitted ion beam as the azimuth angle θ varies from 0 degrees to 360 degrees. The ion beam generating apparatus, for example, makes the emitted ion beam intensity maximum when the azimuth angle θ is 0 degrees, and periodically varies this intensity (e.g., minimum intensity, maximum intensity, minimum intensity, maximum intensity, ...) whenever the azimuth angle θ changes by 45 degrees. That is, the emitted ion beam intensity is maximum when the azimuth angle θ is 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Conversely, the emitted ion beam intensity is minimum when the azimuth angle θ is 45 degrees, 135 degrees, 225 degrees, and 315 degrees. In other words, the ion beam generating apparatus, for example, continuously varies the emitted ion beam intensity at a frequency four times the rotation frequency of the wafer WF.

[0104] Through the ion beam etching described above, the final mask 44 and the portions not protected by the mask 44 (the predetermined portions to be removed in the selection layer 43 and the magnetoresistive effect element layer 42) are etched. According to the ion beam etching described above, the etching rate within the etched area is the same regardless of the etched area itself.

[0105] As a supplement, the ion beam generating device emits the ion beam at an incident angle α of less than 90 degrees (e.g., around 45 degrees). Therefore, the area of ​​the ion beam shielded by the mask 44 varies depending on the azimuth angle θ. That is, even if the intensity of the emitted ion beam is constant, the etching rate of a certain etchable area varies depending on the azimuth angle θ due to the shielding effect.

[0106] In this embodiment, as referenced Figure 15 As explained, the ion beam generating apparatus is controlled in such a way that the intensity of the emitted ion beam continuously varies with the azimuth angle θ. For example, at an azimuth angle θ where the effect of shielding is greater, the ion beam generating apparatus is controlled to increase the intensity of the emitted ion beam, thus suppressing a decrease in the etching rate. Conversely, at an azimuth angle θ where the effect of shielding is less, the ion beam generating apparatus is controlled to decrease the intensity of the emitted ion beam, thus suppressing an increase in the etching rate. Therefore, the ion beam generating apparatus can counteract the effect of shielding, resulting in a uniform etching depth in the etchable area.

[0107] In addition, Figure 15 In, it is shown that in such Figure 3 The example shown illustrates an ion beam generating apparatus in which multiple memory cells (MCs) are arranged at the intersections of a square grid, and the intensity of the emitted ion beam varies at a frequency four times the rotation frequency of the wafer (WF). However, this is not a limitation. The ion beam generating apparatus can vary the intensity of the emitted ion beam at a frequency equal to the etching rate within the etched area. The effect of shielding, depending on the azimuth angle θ, varies, for example, depending on the arrangement of the multiple memory cells (MCs). Therefore, the ion beam generating apparatus can also vary the intensity of the emitted ion beam at a frequency other than four times the rotation frequency of the wafer (WF), depending on the arrangement of the multiple memory cells (MCs).

[0108] Furthermore, during ion beam emission, the stage rotates the wafer WF an arbitrary number of times until the magnetoresistive effect element layer 42 is cut into multiple elements 22, based on the angular velocity of the wafer WF's rotation and the intensity of the ion beam.

[0109] Through the ion beam etching described above, multiple stacks, each including elements 22 and 23, are formed from the magnetoresistive effect element layer 42 and the selection layer 43.

[0110] Furthermore, in order to reliably truncate the magnetoresistive effect element layer 42 into multiple elements 22, a portion of the conductor 21 and insulator 41 beneath the magnetoresistive effect element layer 42 is etched by the aforementioned ion beam etching. For example... Figure 16 As shown, during the period when mask 44 is etched to a height L3 to become mask 44A, the total etch height of portion 41A of the selection layer 43, the magnetoresistive effect element layer 42, and the insulator 41 is (L1+L2a). Figure 17 As shown, during the period when mask 44 is etched to a height L3 to become mask 44A, the total etch height of the selection layer 43, the magnetoresistive effect element layer 42, and the portion 41B of the insulator 41 is (L1+L2b). Figure 18 As shown, during the period when the mask 44 is etched to a height L3 to become the mask 44A, the selection layer 43, the magnetoresistive effect element layer 42 and the portion 21A of the conductor 21 are etched to a total height (L1+L2c).

[0111] According to the ion beam etching described above, the heights (L1+L2a), (L1+L2b), and (L1+L2c) can be made to be of the same degree. Specifically, the ratio of the height (L1+L2a) to the reference height Lref can be made to be 0.9 or more and 1.1 or less (0.9 ≤ (L1+L2a) / Lref ≤ 1.1). Furthermore, the ratio of the height (L1+L2b) to the reference height Lref can be made to be 0.9 or more and 1.1 or less (0.9 ≤ (L1+L2b) / Lref ≤ 1.1). Additionally, the ratio of the height (L1+L2c) to the reference height Lref can be made to be 0.9 or more and 1.1 or less (0.9 ≤ (L1+L2c) / Lref ≤ 1.1).

[0112] Furthermore, although not illustrated, by ion beam etching in which the intensity of the aforementioned ion beam is continuously varied according to the azimuth angle θ, the mask 44A and the elements 22 and 23 below the mask 44A become approximately circular when viewed from above (being etched approximately isotropically in the XY plane).

[0113] Next, as Figure 19 As shown, after the mask 44A is removed, the space etched by the magnetoresistive effect element layer 42 and the selection layer 43 by the ion beam is buried by the insulator 45.

[0114] Next, as Figure 20 As shown, a plurality of conductors 24 arranged along the X-axis are provided on the upper surfaces of the component 23 and the insulator 45. Specifically, firstly, after a conductive layer is provided on the upper surfaces of the component 23 and the insulator 45, a mask with partial openings except for the area corresponding to the bit line BL is formed by photolithography or the like. Then, a plurality of conductors 21 are formed by anisotropic etching of the formed mask to cut through the conductive layer, and holes reaching the insulator 45 are formed. The anisotropic etching in this process is, for example, RIE. Afterward, an insulator (not shown) is provided in the formed holes.

[0115] Through the above process, the structure equivalent to the memory cell array 10 is formed on the wafer WF. Finally, the wafer WF is diced into chip units to form the magnetic storage device 1.

[0116] 1.3. Effects of this implementation method

[0117] According to the embodiment, during the ion beam etching process, the ion beam generating apparatus rotates the wafer WF around the Z-axis. As a result, the azimuth angle θ between the wafer WF and the ion beam changes continuously. That is, the ion beam generating apparatus isotropically emits the ion beam at the wafer WF regardless of the azimuth angle θ. Therefore, unlike cases where the azimuth angle θ when the ion beam is emitted at the wafer WF changes discretely, the cross-sectional shape of the magnetoresistive element MTJ is formed as a circle. Thus, for example, compared to a magnetoresistive element MTJ with a rectangular XY cross-section, the shape of the XY cross-section is more symmetrical about the central axis. Therefore, it is possible to suppress the generation of electric field concentration at specific locations in the XY cross-section (e.g., near the corners of the rectangle), thereby suppressing the degradation of the magnetoresistive element MTJ.

[0118] Furthermore, during the ion beam etching process, the ion beam generating device continuously varies the intensity of the emitted ion beam according to the azimuth angle θ. As mentioned above, the effect of shielding varies depending on the azimuth angle θ. Figure 3 In the layout shown, where multiple memory cells MC are arranged at the intersections of a square grid, the shading effect increases when the azimuth angle θ is 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Conversely, the shading effect decreases when the azimuth angle θ is 45 degrees, 135 degrees, 225 degrees, and 315 degrees. The ion beam generating apparatus continuously varies the intensity of the emitted ion beam at a frequency four times the frequency of the wafer rotation. Therefore, during ion beam etching, the shading effect caused by the geometric relationship between the etch target area of ​​the magnetoresistive element layer 42 and the mask 44 can be mitigated. Consequently, during the ion beam etching process, the etching depth of the conductor 21 and the insulator 41 can be made uniform regardless of their location within the etch target area.

[0119] In addition, the etching rate varies depending on the positional relationship between the arrangement of the masks 44 and the incident direction of the ion beam (i.e., the azimuth angle θ). Specifically, when the ion beam exits from the direction along the X-axis, the etching rate decreases in the region between two masks 44 arranged along the X-axis in a matrix configuration of the multiple masks 44 in the etchable area compared to the regions between two masks 44 arranged diagonally and between two masks 44 arranged along the Y-axis. Similarly, when the ion beam exits from the direction along the Y-axis, the etching rate decreases in the region between two masks 44 arranged along the Y-axis in a matrix configuration of the etchable area compared to the regions between two masks 44 arranged diagonally and between two masks 44 arranged along the X-axis. On the other hand, when the projection of the ion beam onto the wafer WF intersects both the X-axis and the Y-axis, the etching rate in the etchable area between two masks 44 arranged along either the X-axis or the Y-axis is increased compared to the two examples described above. Therefore, during ion beam etching, when the wafer WF is rotated and the intensity of the emitted ion beam is constant regardless of the azimuth angle θ, the etching rate between two masks 44 arranged along the X and Y axes will decrease due to the masking effect compared to the region between two masks 44 arranged diagonally.

[0120] According to the embodiment, the intensity of the ion beam emitted relative to the wafer WF is set to have the maximum intensity at an azimuth angle θ (=0 degrees, 90 degrees, 180 degrees, and 270 degrees) in the region between two masks 44 arranged along the X-axis or Y-axis, where the etching rate decreases. This suppresses the decrease in etching rate in the etchable region between the two masks 44 arranged along the X-axis and Y-axis. Therefore, compared to the case where the intensity of the ion beam is independent of the azimuth angle θ, the non-uniformity of the etching rate in the etchable region can be smoothed. Thus, even in a dense configuration with an aspect ratio AR of magnetoresistive element MTJ exceeding 1 to 1.5, it is possible to manufacture a memory cell array 10 with a length d1 of 50 nanometers (nm) or less and a length d3 of 20 nanometers (nm) or less.

[0121] 2. Variations, etc.

[0122] Furthermore, various modifications can be applied beyond the embodiments described above.

[0123] In the above embodiments, the case where the magnetoresistive element layer 42 is formed below the selection layer 43 has been described, but it is not limited to this. For example, the magnetoresistive element layer may also be formed above the selection layer. In this case, both the selection layer and the magnetoresistive element layer may be etched by ion beam etching, or only the magnetoresistive element layer may be etched by ion beam etching.

[0124] Figure 21 , Figure 22 and Figure 23 An example of a cross-sectional view showing the structure of a storage cell array for illustrating a modified magnetic storage device is shown. Figure 20 , Figure 22 and Figure 23 Corresponding to the implementation methods Figure 4 , Figure 5 and Figure 6 The image shows a memory cell array 10A with the magnetoresistive element layer 42 disposed above the selection layer 43.

[0125] like Figure 21 , Figure 22 and Figure 23 As shown, the memory cell array 10A is disposed above the semiconductor substrate 20.

[0126] For example, a plurality of conductors 21 are disposed on the upper surface of the semiconductor substrate 20. Each of the plurality of conductors 21 has conductivity and functions as word lines WL.

[0127] Multiple elements 23, each functioning as a switching element (SEL), are disposed on the upper surface of a conductor 21. Each element 23 has a conical shape, with its cross-sectional area decreasing from bottom to top along the XY plane. The multiple elements 23 disposed on the upper surface of the conductor 21 are arranged, for example, along the X-axis. That is, multiple elements 23 arranged along the X-axis are connected together on the upper surface of the conductor 21. An insulator 46 is disposed between adjacent elements 23. Thus, the multiple elements 23 are each insulated from each other.

[0128] Insulator 46 along Figure 21 The upper surface of portion 46A between two adjacent elements 22 in the cross-section shown is located at a height L2a' below the lower surface of element 22. The height of the upper surface of portion 46A remains almost unchanged regardless of the distance from element 22.

[0129] Additionally, along the insulator 46 Figure 22 The upper surface of portion 46B between two adjacent elements 23 in the cross-section shown is located at a height L2b' below the lower surface of element 23. The height of the upper surface of portion 46B is the same as that of the upper surface of portion 46A, and hardly changes regardless of the distance from element 23.

[0130] Additionally, along the insulator 46 Figure 23 The upper surface of portion 46C, between two adjacent elements 23 in the cross-section shown, is located at a height L2c' below the lower surface of element 23. The height of the upper surface of portion 46C is the same as that of the upper surfaces of portions 46A and 46B, and remains almost unchanged regardless of the distance from element 23.

[0131] Element 22, which functions as a magnetoresistive element MTJ, is disposed on the upper surface of each of the plurality of elements 23. Element 22 has a height L1 along the Z-axis and, like element 23, has a tapered shape in which the cross-sectional area along the XY plane decreases from bottom to top. The upper surface of each of the plurality of elements 22 is connected to any one of the plurality of conductors 24.

[0132] Multiple conductors 24 are conductive and function as bit lines BL. A single conductor 24 is used to connect multiple elements 22 arranged along the Y-axis.

[0133] In the structure of the memory cell array 10A described above, heights L2a', L2b', and L2c' can be considered to be at the same level. That is, the upper surfaces of portions 46A, 46B, and 46C of the insulator 46 can be considered to be at the same height. Specifically, for example, the ratio of height (L1+L2a') to a predetermined reference height Lref' is 0.9 or more and 1.1 or less (0.9 ≤ (L1+L2a') / Lref' ≤ 1.1). Similarly, the ratio of height (L1+L2b') to the aforementioned reference height Lref' is 0.9 or more and 1.1 or less (0.9 ≤ (L1+L2b') / Lref' ≤ 1.1). Furthermore, the ratio of height (L1+L2c') to the aforementioned reference height Lref' is 0.9 or more and 1.1 or less (0.9 ≤ (L1+L2c') / Lref' ≤ 1.1). The reference height Lref' can be, for example, the average height (L1+L2a'), (L1+L2b'), and (L1+L2c') / 3. However, it is not limited to this. The reference height Lref' can be the average height between the upper surface of each of four or more portions selected from portions 46A, 46B, and 46C and the upper surface of element 22.

[0134] By configuring it as described above, the distance between the mask 44 and the element 22 can be shortened. Therefore, the effect of masking can be reduced during ion beam etching.

[0135] Furthermore, in the above embodiment, the case where the magnetoresistive effect element layer 42 and the selective layer 43 are simultaneously etched by an ion beam has been described, but it is not limited to this. For example, the selective layer 43 may be etched first by RIE or the like, and then only the magnetoresistive effect element layer 42 may be etched by an ion beam.

[0136] Furthermore, in the above embodiment, a top-free type magnetoresistive element MTJ with the storage layer SL disposed above the reference layer RL was described, but it is not limited thereto. For example, the magnetoresistive element MTJ may also be a bottom-free type with the storage layer SL disposed below the reference layer RL.

[0137] Furthermore, while the above-described embodiment describes a memory cell array 10 where all memory cells MC are disposed within the same layer, it is not limited to this. For example, the memory cell array 10 may also have a word line WLd disposed below the bit line BL and a word line WLu disposed above the bit line BL, and may have multiple memory cells MCd disposed between the word line WLd and the bit line BL, and multiple memory cells MCu disposed between the word line WLu and the bit line BL. That is, the number of stacked memory cells MC along the Z-axis is not limited to two, and can be designed with any number of stacked layers.

[0138] While some embodiments of the invention have been described, these embodiments are given by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.< / n> < / m> < / j> < / m> < / n>

Claims

1. A magnetic storage device comprising: The first conductor and the second conductor extend along the first direction and are arranged at intervals with each other along the second direction that intersects the first direction; The third and fourth conductors extend along the second direction above the first and second conductors and are arranged at intervals with each other along the first direction; The first stack is disposed between the first conductor and the third conductor, and includes a first magnetoresistive effect element; The second stack is disposed between the first conductor and the fourth conductor, and includes a second magnetoresistive effect element; The third stack, disposed between the second conductor and the third conductor, includes a third magnetoresistive element; and An insulator is disposed below the first conductor and the second conductor in a third direction intersecting the first and second directions, below the first laminate, the second laminate, and the third laminate. Viewed from the third direction, the cross-sectional shape of the first layer is circular. Viewed from the third direction, the cross-sectional shape of the second layer is circular. Viewed from the third direction, the cross-sectional shape of the third layer is circular. The upper surfaces of the first laminate, the second laminate, and the third laminate are located within a first plane that includes the first direction and the second direction. The insulator includes a first portion between the first laminate and the third laminate, and a second portion between the second laminate and the third laminate. The first conductor includes a third portion between the first laminate and the second laminate. The first height from the upper surface of the first part to the first face, the second height from the upper surface of the second part to the first face, and the third height from the upper surface of the third part to the first face are of the same degree. In the third direction, the height of the upper surface of the first stacked portion of the first conductor, which is stacked with the first stacked body, is higher than the height of the upper surface of the third portion. In the third direction, the height of the upper surface of the second stacked portion of the first conductor, which is stacked with the second stacked body, is higher than the height of the upper surface of the third portion.

2. The magnetic storage device according to claim 1, The distance between the first layer and the second layer is less than 50 nanometers.

3. The magnetic storage device according to claim 2, The first magnetoresistive element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer between the first ferromagnetic layer and the second ferromagnetic layer. The outer diameter of the circular shape in the non-magnetic layer is less than 20 nanometers.

4. The magnetic storage device according to claim 3, The non-magnetic layer contains magnesium (Mg) and oxygen (O).

5. The magnetic storage device according to claim 4, The first ferromagnetic layer and the second ferromagnetic layer contain at least one element selected from iron (Fe), cobalt (Co), and nickel (Ni).

6. The magnetic storage device according to claim 5, The first ferromagnetic layer and the first current flowing from the first ferromagnetic layer to the second ferromagnetic layer correspondingly constitute the first resistance value. The first ferromagnetic layer and the second current flowing from the second ferromagnetic layer to the first ferromagnetic layer correspond to the second resistance value.

7. The magnetic storage device according to claim 6, The first resistance value is smaller than the second resistance value.

8. The magnetic storage device according to claim 1, The first stack also includes a switching element connected in series with the first magnetoresistive effect element.

9. A method for manufacturing a magnetic storage device, comprising: The step of forming a laminate including a first layer and a second layer on the upper surface of the first layer on top of a substrate; and The step of etching the laminate after forming multiple masks, each with a cylindrical shape, on the upper surface of the laminate. The first layer includes a first conductive film and a second conductive film, each extending along a first direction and arranged together along a second direction, and an insulating film between the first conductive film and the second conductive film. The second layer includes a magnetoresistive element layer. The etching step includes: The step of etching the magnetoresistive effect element layer using an ion beam emitted from a predetermined fourth direction; and The steps include rotating the substrate at a first frequency and continuously varying the intensity of the emitted ion beam at a second frequency during the emission of the ion beam.

10. The manufacturing method according to claim 9, The second frequency is determined based on the first frequency and the configuration of the plurality of masks.

11. The manufacturing method according to claim 9, The second frequency is determined to be a frequency higher than or equal to the first frequency.

12. The manufacturing method according to claim 9, The etching depth of the ion beam on the laminate is independent of the distance from the plurality of masks along the surface of the substrate.

13. The manufacturing method according to claim 9, The etching step using the ion beam continues until the magnetoresistive effect element layer is separated into multiple magnetoresistive effect elements corresponding to the multiple masks.

14. The manufacturing method according to claim 13, Each of the plurality of magnetoresistive effect elements includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer between the first ferromagnetic layer and the second ferromagnetic layer.

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