frequency converter

Abstract

A frequency converter having: - a DC voltage intermediate circuit, wherein the DC voltage intermediate circuit has a first connection pole at which a positive intermediate circuit potential exists when the frequency converter is in operation, and the DC voltage intermediate circuit has a second connection pole at which a negative intermediate circuit potential exists when the frequency converter is in operation; - an inverter, wherein the inverter has a first connection pole at which a positive inverter potential exists when the frequency converter is in operation, and the inverter has a second connection pole at which a negative inverter potential exists when the frequency converter is in operation; - a shunt resistor (7) which is connected between the first connection pole of the DC voltage intermediate circuit and the first connection pole of the inverter; - a differential amplifier (8) which is designed to generate a test voltage (UP) from a potential difference which falls across the shunt resistor (7); and - an evaluation unit (9) which is designed to identify a ground fault on the basis of the test voltage (UP).

Description

Technical Field

[0001] This invention relates to a frequency converter. Summary of the Invention

[0002] The objective of this invention is to provide a frequency converter that enables reliable and cost-effective ground fault identification.

[0003] This frequency converter typically has a DC voltage intermediate circuit, wherein the DC voltage intermediate circuit has a first connection terminal, at which a positive intermediate circuit potential exists or is applied during the operation of the frequency converter, and the DC voltage intermediate circuit has a second connection terminal, at which a negative intermediate circuit potential exists or is applied during the operation of the frequency converter. Relevant professional literature should also be consulted in this regard.

[0004] The inverter also has a conventional inverter, wherein the inverter has a first connection terminal at which a positive inverter potential exists when the inverter is running, and the inverter has a second connection terminal at which a negative inverter potential exists when the inverter is running.

[0005] The inverter also has a shunt resistor connected between the first connection terminal of the DC voltage intermediate circuit and the first connection terminal of the inverter.

[0006] The positive intermediate circuit potential corresponds to the positive inverter potential minus the voltage dropped across the shunt resistor. The negative intermediate circuit potential corresponds to the negative inverter potential, provided that there are no components with voltage drops across them in the current path between the negative intermediate circuit potential and the negative inverter potential.

[0007] The inverter also features a differential amplifier designed to generate a test voltage from the potential difference falling across the shunt resistor.

[0008] The inverter also features an evaluation unit designed to identify ground faults based on the test voltage. For example, the evaluation unit can identify a ground fault once the test voltage exceeds or falls below a specified level, and / or once the test voltage exhibits a pulse shape change, etc.

[0009] In one embodiment, the differential amplifier is designed to generate the test voltage with the negative intermediate circuit potential as a reference potential. This test voltage can, for example, have a level between 0 V and 3.3 V or 5 V.

[0010] In one embodiment, the parameters of the shunt resistor are determined such that, in the event of a ground fault, the potential difference at the shunt resistor is in the range of 50 mV to 500 mV. For example, the resistance value of the shunt resistor can be in the range of 1 mOhm to 20 mOhm.

[0011] In one embodiment, the evaluation unit has a digital input terminal on which the test voltage is applied, wherein the differential amplifier is designed to generate the test voltage at a level corresponding to a first logic level of the digital input terminal, such as logic level zero, in the absence of a ground fault, and wherein the differential amplifier is designed to generate the test voltage at a level corresponding to a second logic level of the digital input terminal, such as logic level one, in the presence of a ground fault.

[0012] According to one embodiment, the differential amplifier has: a first transistor, particularly a bipolar transistor or a diode; and a second transistor, particularly a bipolar transistor, wherein the first transistor or diode biases the second transistor with respect to the switching behavior of the second transistor, such that in the event of a ground fault, the second transistor will change its switching state even if the potential difference at the shunt resistor is less than 500 mV.

[0013] In one embodiment, the second transistor is wired such that the alternating voltage gain of the second transistor is at least 10 to 20 times its DC voltage gain.

[0014] According to one embodiment, the first transistor and the second transistor are bipolar transistors, particularly pnp bipolar transistors, and the differential amplifier has: a first resistor and a first capacitor connected in series between a first terminal of a shunt resistor and the emitter terminal of the second transistor; a second resistor connected between the first terminal of the shunt resistor and the emitter terminal of the second transistor; a third resistor and a fourth resistor connected in series between the collector terminal of the second transistor and a negative intermediate circuit potential; a second capacitor connected in parallel with the third resistor; and a fifth resistor connected in parallel with the base-collector path of the second transistor.

[0015] In one embodiment, the base connection terminal of the first transistor and the base connection terminal of the second transistor are electrically connected to each other, the emitter connection terminal and the collector connection terminal of the first transistor are electrically connected to each other, and a sixth resistor is connected in series between the second connection terminal of the shunt resistor and the emitter connection terminal of the first transistor.

[0016] If a diode is used instead of the first transistor for temperature compensation, the cathode of the diode and the base of the second transistor are electrically connected to each other, and a sixth resistor is connected in series between the second terminal of the shunt resistor and the anode of the diode.

[0017] In one embodiment, the frequency converter has a test voltage generation circuit designed to generate the test voltage from a voltage dropped across a fourth resistor. Attached Figure Description

[0018] The present invention will then be described in detail with reference to the accompanying drawings. In this case:

[0019] Figure 1 A schematic circuit diagram of a frequency converter according to the present invention is shown; and

[0020] Figure 2 It shows in Figure 1 The diagram shows a detailed circuit diagram of the inverter's differential amplifier, test voltage generation circuit, and evaluation unit. Detailed Implementation

[0021] Figure 1 A frequency converter 100 is shown, which typically has a DC voltage intermediate circuit 1 with an intermediate circuit capacitor 30. The DC voltage intermediate circuit 1 has a first connection 2 at which a positive intermediate circuit potential ZK+ exists during operation of the frequency converter 100, and a second connection 3 at which a negative intermediate circuit potential ZK- exists during operation of the frequency converter 100. The potential difference, or intermediate circuit voltage, between the positive intermediate circuit potential ZK+ and the negative intermediate circuit potential ZK- can be, for example, in the range of 800 V.

[0022] The inverter 100 also features a conventional inverter 4, which has: three half-bridges with their respective semiconductor switches T1 to T6, such as in the form of IGBTs; and three shunt resistors RU, RV, and RW for current measurement. These half-bridges typically generate phase voltages U, V, and W for a three-phase motor.

[0023] Inverter 4 has: a first connection 5, at which a positive inverter potential WR+ exists when inverter 100 is running; and a second connection 6, at which a negative inverter potential WR- exists when inverter 100 is running. In the case shown, potentials ZK- and WR- are the same.

[0024] The inverter 100 also has a shunt resistor 7 with a resistance of 10 mOhm, which is connected between the first connection 2 of the DC voltage intermediate circuit 1 and the first connection 5 of the inverter 4.

[0025] The inverter 100 also has a differential amplifier 8, which is designed to generate a test voltage UP from the potential difference US falling on the shunt resistor 7. In the event of a ground fault, the test voltage has, for example, a pulse-shaped change process.

[0026] The inverter 100 also has an evaluation unit 9, which is designed to identify ground faults based on the test voltage UP or its change over time.

[0027] Differential amplifier 8 is designed to generate the test voltage UP with the negative intermediate circuit potential ZK- as a reference potential, where the negative intermediate circuit potential is... Figure 2 It is referred to as GND in China.

[0028] The parameters of the shunt resistor 7 are determined such that, in the event of a ground fault, the potential difference US at the shunt resistor 7 is in the range of 50 mV to 500 mV.

[0029] refer to Figure 2 Evaluation unit 9 has a digital input terminal 10, which is loaded with the test voltage UP. In the absence of a ground fault, differential amplifier 8 generates the test voltage UP at a level corresponding to a first logic level of digital input terminal 10; while in the presence of a ground fault, differential amplifier generates the test voltage UP at a level corresponding to a second logic level of digital input terminal 10.

[0030] refer to Figure 2 The differential amplifier 8 has a first PNP bipolar transistor 11 and a second PNP bipolar transistor 12, wherein the first transistor 11 biases the second transistor 12 such that, in the event of a ground fault, even if the potential difference US at the shunt resistor 7 is less than 500 mV, the second transistor 12 will change its switching state.

[0031] The second transistor 12 is wired such that the alternating voltage gain of the second transistor is at least 100 times its DC voltage gain.

[0032] The differential amplifier 8 has a first resistor 13 and a first capacitor 14, which are connected in series between the first connection terminal 22 of the shunt resistor 7 and the emitter connection terminal of the second transistor 12.

[0033] The differential amplifier 8 also has a second resistor 15, which is connected between the first connection terminal 22 of the shunt resistor 7 and the emitter connection terminal of the second transistor 12.

[0034] The differential amplifier 8 also has a third resistor 16 and a fourth resistor 18, which are connected in series between the collector terminal of the second transistor 12 and the negative intermediate circuit potential ZK- or GND.

[0035] The differential amplifier 8 also has a second capacitor 17, which is connected in parallel with a third resistor 16.

[0036] The differential amplifier 8 also has a fifth resistor 19, which is connected in parallel with the base-collector path of the second transistor 12.

[0037] The base connection terminal of the first transistor 11 and the base connection terminal of the second transistor 12 are electrically connected to each other.

[0038] The emitter and collector terminals of the first transistor 11 are electrically connected to each other.

[0039] The differential amplifier 8 also has a sixth resistor 20, which is connected in series between the second connection terminal 23 of the shunt resistor 7 and the emitter connection terminal of the first transistor 11.

[0040] The test voltage generation circuit 21 is designed to generate the test voltage UP from the voltage dropped across the fourth resistor 18. For this purpose, the test voltage generation circuit 21 has capacitor 24, resistors 25, 26, and 27 with the wiring shown, and transistor 28.

[0041] Capacitor 29 is connected in parallel with shunt resistor 7.

[0042] By means of the present invention, ground faults of motor output in the presence of frequency converters can be prevented by measuring the intermediate circuit current in the ZK+ branch with shunt resistor 7, including short circuit protection of brake chopper output.

[0043] Since only the motor phase current is recorded to the ZK- potential when measuring the emitter shunt current using shunt resistors RU, RV, and RW, ground faults in the motor phase during operation can only be conditionally identified. If a ground fault occurs during the conduction phase of the upper IGBTs T1, T3, and T5, the power section will be damaged. Therefore, according to the present invention, a sensing device is provided for reliable ground fault identification in the ZK+ current path.

[0044] However, since the evaluation unit 9 is at the ZK- or GND potential, a voltage US must be generated relative to ZK- or GND and dropped across the shunt resistor 7 for evaluation.

[0045] The high current flowing in the ZK+ path due to a ground fault is converted into a voltage US by means of a shunt resistor 7. Because the ohmic value of the shunt resistor 7 must be chosen as small as possible for low power loss, only a small voltage drop of about 100 to 200 mV is obtained across the shunt resistor 7 in the event of a ground fault. This voltage drop is insufficient to directly control an optocoupler or a bipolar transistor.

[0046] For this reason, transistor 11 is used to bias the base voltage of transistor 12. Since the resistance of resistor 20 is chosen to be much lower than that of resistor 15, the quiescent current mainly flows through transistor 12. Therefore, a high voltage, for example, about 200 V, drops across resistor 19.

[0047] If a ground fault occurs, transistor 11 will immediately turn off, and then transistor 12 will turn on high. Due to capacitor 17, the voltage pulse generated is transferred to the lower voltage potential ZK- or GND, and transistor 28 will then report a short-circuit signal to evaluation unit 9.

[0048] In theory, the resulting voltage pulse could be transferred even without capacitor 17, but this would require the use of transistors (pnp or P-channel MOS-FET) with high cutoff voltage and high safety distance.

[0049] According to the present invention, the resistance value of the resistor used is selected such that a maximum of 210V drops across transistor 12 when the intermediate circuit voltage is 800V, and correspondingly, 590V to 800V drops across capacitor 17. Therefore, capacitor 17 plays a decisive role in insulation distance and signal transmission. However, since this capacitor only needs to have a capacitance of, for example, 470 pF, it is very inexpensive and small in size. Small, inexpensive transistors can be used as transistor 12.

[0050] According to the present invention, current isolation between the shunt resistor 7 and the evaluation unit 9 is not required. Furthermore, a differential amplifier with power supply at the ZK+ potential is not required. Moreover, the differential amplifier 8 can be implemented using inexpensive standard components, eliminating the need for dedicated ICs or sensors.

Claims

1. A frequency converter (100) having: - A DC voltage intermediate circuit (1), wherein the DC voltage intermediate circuit (1) has a first connection pole (2), and a positive intermediate circuit potential (ZK+) exists at the first connection pole when the inverter (100) is running, and the DC voltage intermediate circuit has a second connection pole (3), and a negative intermediate circuit potential (ZK-) exists at the second connection pole when the inverter (100) is running. - Inverter (4), wherein the inverter (4) has a first connection pole (5) where a positive inverter potential (WR+) exists at the first connection pole when the inverter (100) is running, and the inverter has a second connection pole (6) where a negative inverter potential (WR-) exists at the second connection pole when the inverter (100) is running. - Shunt resistor (7), which is connected between the first connection terminal (2) of the DC voltage intermediate circuit (1) and the first connection terminal (5) of the inverter (4); - Differential amplifier (8), which is designed to generate a test voltage (UP) from the potential difference (US) falling across the shunt resistor (7); and - Evaluation unit (9), which is designed to identify ground faults based on the test voltage (UP). in, The differential amplifier (8) has: - First transistor (11) or diode; and - Second transistor (12) - Wherein the first transistor (11) or the diode biases the second transistor (12) such that, in the event of a ground fault, the second transistor (12) will change its switching state even if the potential difference (US) at the shunt resistor (7) is less than 500 mV.

2. The frequency converter (100) according to claim 1, characterized in that, - The differential amplifier (8) is designed to generate the test voltage (UP) with the negative intermediate circuit potential (ZK-) as the reference potential.

3. The frequency converter (100) according to claim 1 or 2, characterized in that, - The parameters of the shunt resistor (7) are determined such that, in the event of a ground fault, the potential difference (US) at the shunt resistor (7) is in the range of 50 mV to 500 mV.

4. The frequency converter (100) according to claim 1 or 2, characterized in that, - The evaluation unit (9) has a digital input terminal (10) on which the test voltage (UP) is applied. - The differential amplifier (8) is designed to generate the test voltage (UP) at a level corresponding to the first logic level of the digital input (10) in the absence of a ground fault, and - The differential amplifier (8) is designed to generate the test voltage (UP) at a level corresponding to the second logic level of the digital input (10) in the event of a ground fault.

5. The frequency converter (100) according to claim 1 or 2, characterized in that, - The second transistor (12) is wired such that the alternating voltage gain of the second transistor is at least 100 times its DC voltage gain.

6. The frequency converter (100) according to claim 1 or 2, characterized in that, - The first transistor (11) and the second transistor (12) are both bipolar transistors, and - The differential amplifier (8) has: - A first resistor (13) and a first capacitor (14), the first resistor and the first capacitor being connected in series between the first connection terminal (22) of the shunt resistor (7) and the emitter connection terminal of the second transistor (12); - A second resistor (15) is connected between the first connection terminal (22) of the shunt resistor (7) and the emitter connection terminal of the second transistor (12); - A third resistor (16) and a fourth resistor (18), the third resistor and the fourth resistor being connected in series between the collector terminal of the second transistor (12) and the negative intermediate circuit potential (ZK-); - A second capacitor (17), which is connected in parallel with the third resistor (16); as well as - A fifth resistor (19) is connected in parallel with the base-collector path of the second transistor (12).

7. The frequency converter (100) according to claim 1 or 2, characterized in that, - The base connection terminal of the first transistor (11) and the base connection terminal of the second transistor (12) are electrically connected to each other. - The emitter and collector terminals of the first transistor (11) are electrically connected to each other, and - The sixth resistor (20) is connected in series between the second connection terminal (23) of the shunt resistor (7) and the emitter connection terminal of the first transistor (11).

8. The frequency converter (100) according to claim 6, characterized in that... - Test voltage generation circuit (21), which is designed to generate the test voltage (UP) from the voltage dropped across the fourth resistor (18).

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