Power amplifier circuit, high frequency circuit, and communication device

Abstract

A power amplifier circuit is implemented to operate at a higher speed. A power amplifier circuit (1) includes a multi-stage amplifier section (10), an ET terminal (101), and an APT terminal (102). The multi-stage amplifier section (10) includes a final-stage amplifier section (11). The final-stage amplifier section (11) has a first amplifier element (111) and a second amplifier element (112) connected in parallel with each other. The first amplifier element (111) is connected to the ET terminal (101). The second amplifier element (112) is connected to the APT terminal (102).

Description

Technical Field

[0001] This invention generally relates to a power amplifier circuit, a high-frequency circuit, and a communication device; more specifically, it relates to a power amplifier circuit, a high-frequency circuit, and a communication device having a multi-stage amplification section. Background Technology

[0002] Previously, a power management system having multiple power amplifier circuits, a first tracking circuit, and a second tracking circuit was known (see, for example, Patent Document 1).

[0003] The first tracking circuit generates a first ET modulation voltage corresponding to the first ET modulation signal or a first APT modulation voltage corresponding to the first APT modulation signal. The second tracking circuit generates a second ET modulation voltage corresponding to the second ET modulation signal or a first APT modulation voltage corresponding to the second APT modulation signal.

[0004] In the power management system described in Patent Document 1, a first tracking circuit or a second tracking circuit applies a bias voltage to one or more selected power amplifier circuits among a plurality of power amplifier circuits.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: U.S. Patent Application Publication No. 2018 / 0309409 Summary of the Invention

[0008] The problem the invention aims to solve

[0009] Furthermore, in the field of power amplifier circuit technology, there is a desire for higher speed operation of power amplifier circuits.

[0010] The purpose of this invention is to provide a power amplifier circuit, a high-frequency circuit, and a communication device that can achieve higher speed operation.

[0011] Solution for solving the problem

[0012] One embodiment of the present invention relates to a power amplifier circuit comprising a multi-stage amplification section, an ET terminal, and an APT terminal. The multi-stage amplification section includes a final stage amplification section. The final stage amplification section has a first amplifying element and a second amplifying element connected in parallel with each other. The first amplifying element is connected to the ET terminal. The second amplifying element is connected to the APT terminal.

[0013] One aspect of the present invention relates to a high-frequency circuit comprising the aforementioned power amplifier circuit, a first power supply circuit, and a second power supply circuit. The first power supply circuit is connected to the ET terminal and generates a first power supply voltage, which varies in response to the amplitude of the high-frequency signal input to the first amplifying element. The second power supply circuit is connected to the APT terminal and generates a second power supply voltage, which varies in response to the amplitude of the high-frequency signal input to the second amplifying element and at a frequency lower than that of the first power supply voltage.

[0014] One aspect of the present invention relates to a communication device comprising the aforementioned high-frequency circuit and signal processing circuit. The signal processing circuit processes the high-frequency signal and outputs it to the high-frequency circuit. The power amplification circuit of the high-frequency circuit amplifies the high-frequency signal input from the signal processing circuit.

[0015] The effects of the invention

[0016] The power amplifier circuit, high-frequency circuit, and communication device according to the above-described manner of the present invention can achieve higher speed operation of the power amplifier circuit. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the power amplifier circuit and high-frequency circuit involved in Implementation Method 1.

[0018] Figure 2 This is a block diagram of the communication device according to Embodiment 1.

[0019] Figure 3 A is a graph relating to the power amplifier circuit involved in the comparative example, showing the change of the first power supply voltage applied from the first power supply circuit to the first amplifying element. Figure 3 B is a graph related to the power amplifier circuit above, showing the change of the second power supply voltage applied from the second power supply circuit to the first amplifying element.

[0020] Figure 4 It is a graph relating to the power amplifier circuit of Embodiment 1, showing the change of the first power supply voltage applied from the first power supply circuit to the first amplifying element.

[0021] Figure 5 This is a graph showing the ACLR characteristics of the power amplifier circuit described above.

[0022] Figure 6 This is a schematic diagram of the power amplifier circuit and high-frequency circuit involved in variation 1 of implementation method 1.

[0023] Figure 7This is a schematic diagram of the power amplifier circuit and high-frequency circuit involved in Implementation Method 2.

[0024] Figure 8 This is a characteristic diagram related to the power conversion circuit mentioned above, showing the relationship between output power and amplification efficiency.

[0025] Figure 9 This is a schematic diagram of the power amplifier circuit and high-frequency circuit involved in Implementation Method 3.

[0026] Figure 10 This is a schematic diagram of the power amplifier circuit and high-frequency circuit involved in Implementation Method 4. Detailed Implementation

[0027] The figures referenced in embodiments 1 to 4 below are schematic diagrams, and the size and thickness ratios of the structural elements in the figures may not reflect the actual size ratios. Furthermore, in Figure 1 , Figure 6 , Figure 7 , Figure 9 as well as Figure 10 The diagram of filter circuit 4 in high-frequency circuits 7, 7a, 7b, 7c, and 7d is omitted. Figure 2 The diagrams of the first power supply circuit 2 and the second power supply circuit 3 in the high-frequency circuit 7 are omitted.

[0028] (Implementation Method 1)

[0029] Below, refer to Figures 1-6 To illustrate the power amplifier circuit, high-frequency circuit, and communication device involved in Embodiment 1.

[0030] (1) Structure of power amplifier circuit

[0031] First, the structure of the power amplifier circuit 1 according to Embodiment 1 will be described with reference to the accompanying drawings.

[0032] like Figure 1 As shown, the power amplifier circuit 1 according to Embodiment 1 includes multiple (two in the example) amplification sections 10, an ET terminal 101, and an APT terminal 102. Furthermore, in Embodiment 1, the power amplifier circuit 1 also includes a demultiplexer 13, a combining circuit 14, and an output matching circuit 15.

[0033] The multiple amplification sections 10 include a final stage amplification section 11 disposed on the output side (antenna terminal 72 side) of the power amplifier circuit 1 relative to the demultiplexer 13, and a drive stage amplification section 12 disposed on the input side (signal input terminal 71 side) of the power amplifier circuit 1 relative to the demultiplexer 13. In Embodiment 1, the power amplifier circuit 1 has two stages of amplification.

[0034] The final stage amplification section 11 includes a first amplifying element 111 and a second amplifying element 112. Additionally, in Embodiment 1, the final stage amplification section 11 also includes multiple (two in the example) capacitors 113 and 114. In Embodiment 1, the first amplifying element 111 and the second amplifying element 112 constitute a differential amplifier circuit 20. The driver stage amplification section 12 includes an amplifying element 121 and a capacitor 122.

[0035] The first amplifying element 111 is connected to the ET terminal 101. The ET terminal 101 is connected to the first power supply circuit 2, described later. The first power supply circuit 2 generates a first power supply voltage V1, which changes in response to the amplitude of the high-frequency signal input to the first amplifying element 111. The second amplifying element 112 is connected to the APT terminal 102. The APT terminal 102 is connected to the second power supply circuit 3, described later. The second power supply circuit 3 generates a second power supply voltage V2, which changes in response to the amplitude of the high-frequency signal input to the second amplifying element 112, and changes at a frequency lower than that of the first power supply voltage V1.

[0036] In this specification, etc., "connection" refers to the electrical connection of two connected objects. Furthermore, in this specification, "electrical connection" includes both the case of a direct electrical connection between two connected objects and the case of an indirect connection between two connected objects.

[0037] Demultiplexer 13 is disposed between the amplification section 12 of the drive stage and the amplification section 11 of the final stage. Demultiplexer 13 includes transformer 130. Transformer 130 has a primary winding 131 and a secondary winding 132. Synthesizer 14 is disposed between the amplification section 11 of the final stage and the output matching circuit 15. Synthesizer 14 includes transformer 140. Transformer 140 has a primary winding 141 and a secondary winding 142.

[0038] The output matching circuit 15 is disposed between the synthesis circuit 14 and the output side circuit (e.g., the filter circuit 4) of the output matching circuit 15.

[0039] like Figure 1 As shown, the power amplifier circuit 1 is used, for example, in the high-frequency circuit 7. In addition to the power amplifier circuit 1 described above, the high-frequency circuit 7 also includes a first power supply circuit 2, a second power supply circuit 3, and a filter circuit 4 (see reference). Figure 2 ), signal input terminal 71 and antenna terminal 72.

[0040] And, as Figure 2As shown, the high-frequency circuit 7 is used, for example, in a communication device 8. The communication device 8 is, for example, a portable telephone such as a smartphone. However, the communication device 8 is not limited to a portable telephone; it could also be, for example, a wearable terminal such as a smartwatch. The high-frequency circuit 7 is, for example, a circuit capable of supporting 4G (fourth-generation mobile communication) standards, 5G (fifth-generation mobile communication) standards, etc. The 4G standard is, for example, the 3GPP (Third Generation Partnership Project) LTE (Long Term Evolution) standard. The 5G standard is, for example, 5G NR (New Radio). The high-frequency circuit 7 can also be a circuit capable of supporting carrier aggregation and dual connectivity.

[0041] (2) Structural elements of power amplifier circuit

[0042] Next, refer to Figure 1 The structural elements of the power amplifier circuit 1 involved in Embodiment 1 will be explained.

[0043] (2.1) Amplification section of the final stage

[0044] like Figure 1 As shown, the final stage amplification section 11 has a first amplification element 111 and a second amplification element 112. Furthermore, in Embodiment 1, the final stage amplification section 11 also has a plurality of capacitors 113 and 114 (two in the example shown). In Embodiment 1, capacitor 113 corresponds to the first amplification element 111, and capacitor 114 corresponds to the second amplification element 112.

[0045] The first amplifying element 111 and the second amplifying element 112 are, for example, npn-type bipolar transistors. More specifically, the first amplifying element 111 and the second amplifying element 112 are HBTs (Heterojunction Bipolar Transistors). The first amplifying element 111 and the second amplifying element 112 are multifinite-finger transistors formed by connecting multiple unit transistors (also called "fingers") in parallel. A unit transistor refers to the minimum structure that constitutes a transistor. The first amplifying element 111 and the second amplifying element 112 respectively supply power to the RF signal processing circuit 51 (see reference 51) from the signal processing circuit 5 described later. Figure 2 The high-frequency signal is amplified. In embodiment 1, the first amplifying element 111 and the second amplifying element 112 are connected in parallel to each other to form a differential amplifier circuit 20.

[0046] In Embodiment 1, the size of the first amplifying element 111 is the same as the size of the second amplifying element 112. When the first amplifying element 111 and the second amplifying element 112 are both polyacrylonitrile (PATs) as in Embodiment 1, a larger size results in a greater number of PATs, and a smaller size results in a smaller number of PATs. Therefore, in Embodiment 1, since the size of the first amplifying element 111 is the same as the size of the second amplifying element 112, the number of PATs constituting the first amplifying element 111 is the same as the number of PATs constituting the second amplifying element 112.

[0047] The first amplifying element 111 has a first base terminal, a first collector terminal, and a first emitter terminal. The first amplifying element 111 amplifies the high-frequency signal input to the first base terminal and outputs it from the first collector terminal. The first emitter terminal is electrically connected to ground. In other words, the first emitter terminal is directly or indirectly connected to ground. That is, the first emitter terminal is grounded (emitter grounded). The first collector terminal is electrically connected to the first power supply circuit 2 (described later) via the ET terminal 101, thereby applying (providing) a first power supply voltage V1. Additionally, the first collector terminal is electrically connected to the first end of the primary winding 141 of the transformer 140 of the combining circuit 14 via a capacitor 113. Furthermore, the first base terminal is electrically connected to the first end of the secondary winding 132 of the transformer 130 of the demultiplexer 13.

[0048] The second amplifying element 112 has a second base terminal, a second collector terminal, and a second emitter terminal. The second amplifying element 112 amplifies the high-frequency signal input to the second base terminal and outputs it from the second collector terminal. The second emitter terminal is electrically connected to ground. In other words, the second emitter terminal is directly or indirectly connected to ground. That is, the second emitter terminal is grounded (emitter grounded). The second collector terminal is electrically connected to the second power supply circuit 3 (described later) via the APT terminal 102, thereby applying (providing) the second power supply voltage V2. Additionally, the second collector terminal is electrically connected to the second terminal of the primary winding 141 of the transformer 140 via the capacitor 114. Furthermore, the second base terminal is electrically connected to the second terminal of the secondary winding 132 of the transformer 130.

[0049] That is, in the power amplifier circuit 1 according to Embodiment 1, the first base terminal of the first amplifying element 111 and the second base terminal of the second amplifying element 112 are electrically connected to each other via the secondary winding 132 of the transformer 130. In addition, the first collector terminal of the first amplifying element 111 and the second collector terminal of the second amplifying element 112 are electrically connected to each other via capacitors 113 and 114 and the primary winding 141 of the transformer 140.

[0050] Capacitor 113 is a DC blocking capacitor that blocks the DC component output from the first amplifying element 111. Additionally, capacitor 114 is a DC blocking capacitor that blocks the DC component output from the second amplifying element 112.

[0051] Here, the first base terminal of the first amplifying element 111 and the second base terminal of the second amplifying element 112 correspond to the base of the HBT. Similarly, the first collector terminal of the first amplifying element 111 and the second collector terminal of the second amplifying element 112 correspond to the collector of the HBT. Furthermore, the first emitter terminal of the first amplifying element 111 and the second emitter terminal of the second amplifying element 112 correspond to the emitter of the HBT. The same applies to amplifying element 121, which will be described later.

[0052] (2.2) Amplification section of the driver stage

[0053] like Figure 1 As shown, the amplification section 12 of the drive stage has an amplification element 121 and a capacitor 122.

[0054] Amplifying element 121, like the first amplifying element 111 and the second amplifying element 112, is, for example, an npn-type bipolar transistor. More specifically, amplifying element 121 is an HBT. Like the first amplifying element 111 and the second amplifying element 112, amplifying element 121 is a polyphasic transistor formed by connecting multiple unit transistors in parallel. Amplifying element 121 supplies power to the RF signal processing circuit 51 (see reference 51) from the signal processing circuit 5 described later. Figure 2 The high-frequency signal is amplified.

[0055] Amplifying element 121 has a base terminal, a collector terminal, and an emitter terminal. Amplifying element 121 amplifies the high-frequency signal input to the base terminal and outputs it from the collector terminal. The emitter terminal is electrically connected to ground. In other words, the emitter terminal is directly or indirectly connected to ground. That is, the emitter terminal is grounded (emitter grounded). The collector terminal is electrically connected to the second power supply circuit 3 (described later) via the APT terminal 102, thereby applying (providing) a third power supply voltage V3. Additionally, the collector terminal is electrically connected to the first end of the primary winding 131 of transformer 130. Furthermore, the base terminal is electrically connected to the signal input terminal 71 via capacitor 122.

[0056] Capacitor 122 is a DC blocking capacitor that blocks the DC component input to amplifying element 121.

[0057] (2.3) Demultiplexer

[0058] The splitter 13 is a circuit used to electrically insulate the amplification section 12 of the driver stage from the amplification section 11 of the final stage. For example... Figure 1As shown, the demultiplexer 13 includes a transformer 130. (As...) Figure 1 As shown, transformer 130 has a primary winding 131 and a secondary winding 132.

[0059] The first end of the primary winding 131 is electrically connected to the collector terminal of the amplifying element 121. The second end of the primary winding 131 is electrically connected to ground. Furthermore, a capacitor 133 is electrically connected between the first and second ends of the primary winding 131.

[0060] The first end of the secondary winding 132 is electrically connected to the first base terminal of the first amplifying element 111. The second end of the secondary winding 132 is electrically connected to the second base terminal of the second amplifying element 112. The turns ratio of the primary winding 131 to the secondary winding 132 is, for example, one to one.

[0061] (2.4) Synthesis Circuit

[0062] The synthesizing circuit 14 is used to electrically insulate the final stage amplification section 11 from the output matching circuit 15. For example... Figure 1 As shown, the synthesis circuit 14 includes a transformer 140. (As indicated...) Figure 1 As shown, transformer 140 has a primary winding 141 and a secondary winding 142.

[0063] The first end of the primary winding 141 is electrically connected to the first collector terminal of the first amplifying element 111 via a capacitor 113. The second end of the primary winding 141 is electrically connected to the second collector terminal of the second amplifying element 112 via a capacitor 114.

[0064] The first end of the secondary winding 142 is electrically connected to the first input terminal of the output matching circuit 15 (the connection point between inductor 151 and capacitor 153). Additionally, the second end of the secondary winding 142 is electrically connected to the second input terminal of the output matching circuit 15 (the end of inductor 152 opposite to capacitor 153) and is also connected to ground. The turns ratio of the primary winding 141 to the secondary winding 142 is, for example, one to one.

[0065] (2.5) Output Matching Circuit

[0066] like Figure 1 As shown, the output matching circuit 15 is disposed on the secondary side of the combining circuit 14. The output matching circuit 15 is a circuit used to match the impedance between the circuit on the input side of the output matching circuit 15 (the final stage amplification section 11 and the combining circuit 14) and the circuit on the output side of the output matching circuit 15 (e.g., the filter circuit 4). The output matching circuit 15 includes two inductors 151 and 152 and two capacitors 153 and 154.

[0067] The first terminal of inductor 151 is electrically connected to the first terminal of the secondary winding 142 of transformer 140, and the second terminal of inductor 151 is connected to the filter circuit 4 (see reference). Figure 2 The input terminal of the capacitor 151 is electrically connected. Inductor 152 is connected in series with capacitor 153, and together with capacitor 153, is electrically connected between the two ends of the secondary winding 142 of transformer 140. Additionally, the end of capacitor 153 opposite to inductor 152 is electrically connected to the connection point between the secondary winding 142 of transformer 140 and inductor 151. Capacitor 154 is electrically connected between the two ends of the secondary winding 142 of transformer 140 via inductor 151.

[0068] (3) Structural elements of high-frequency circuits

[0069] Next, refer to Figure 1 and Figure 2 To illustrate the structural elements of the high-frequency circuit 7 involved in Implementation Method 1.

[0070] like Figure 1 As shown, the high-frequency circuit 7 according to Embodiment 1 includes a power amplifier circuit 1, a first power supply circuit 2, and a second power supply circuit 3. Furthermore, in Embodiment 1, as... Figure 2 As shown, the high-frequency circuit 7 also includes a filter circuit 4, a signal input terminal 71, and an antenna terminal 72.

[0071] (3.1)Terminal

[0072] like Figure 2 As shown, signal input terminal 71 is electrically connected to the RF signal processing circuit 51 of the signal processing circuit 5 described later. Signal input terminal 71 is a terminal used to input high-frequency signals (transmit signals) from the RF signal processing circuit 51 to the high-frequency circuit 7.

[0073] like Figure 2 As shown, antenna terminal 72 is electrically connected to antenna 6, which will be described later. In Embodiment 1, antenna terminal 72 is a terminal used to output high-frequency signals from high-frequency circuit 7 to antenna 6.

[0074] (3.2) First power supply circuit

[0075] The first power supply circuit 2 is, for example, an ET (Envelope Tracking) modulator. The first power supply circuit 2 includes, for example, a DC-DC converter. As described above, the first power supply circuit 2 applies (provides) a first power supply voltage V1 to the first amplifying element 111 (the first collector terminal). The first power supply circuit 2 detects signals from the baseband signal processing circuit 52 (see below). Figure 2The first power supply circuit 2 detects the envelope of the output signal. Specifically, the first power supply circuit 2 detects the waveform (envelope signal) of the amplitude modulation of the carrier signal that constitutes the transmitted signal.

[0076] The first power supply circuit 2 uses the waveform of the envelope signal and a preset amplification rate to generate a first power supply voltage V1. The first power supply voltage V1 varies accordingly with the envelope. The period of the first power supply voltage V1 is the same as the period of the envelope signal. The amplitude variation of the first power supply voltage V1 is the same as the amplitude variation of the envelope signal. That is, the amplitude characteristics (period and amplitude variation) of the envelope signal and the first power supply voltage V1 are the same. The first power supply circuit 2 outputs the generated first power supply voltage V1 to the first amplification element 111.

[0077] Figure 3 A is a graph representing an example of the first power supply voltage V1 output from the first power supply circuit 2. For example... Figure 3 As shown by the solid line a1 in diagram A, the first power supply voltage V1 changes accordingly with the amplitude of the high-frequency signal. Therefore, the first amplifying element 111 can operate in a near-saturation state. Furthermore, Figure 3 The “w1” in A indicates the waveform of the high-frequency signal. That is, the signal input from the first power supply circuit 2 to the ET terminal 101 is a signal that changes in a manner that follows the envelope of the high-frequency signal input to the first amplification element 111.

[0078] Furthermore, in the high-frequency circuit 7 according to Embodiment 1, the first power supply circuit 2 is configured to acquire voltage information from the second power supply circuit 3. The voltage information is information related to the second power supply voltage V2 output from the second power supply circuit 3, and is information related to the amplitude change of the second power supply voltage V2. That is, the first power supply circuit 2 holds information about each period T1, T2, T3 (refer to...). Figure 3 The amplitude of the second power supply voltage V2 of B).

[0079] (3.3) Second power supply circuit

[0080] The second power supply circuit 3 is, for example, a circuit that generates the second power supply voltage V2 and the third power supply voltage V3 according to the APT (Average Power Tracking) method. The second power supply circuit 3 includes, for example, a DC-DC converter. The second power supply circuit 3 calculates the average power amplitude of the high-frequency signal according to a predetermined period (the periods T1, T2, and T3 described below), and adjusts the voltage level supplied to the second amplification element 112 and the amplification element 121 according to the calculated average power amplitude.

[0081] In Embodiment 1, the frequency of the second power supply voltage V2 is the same as the frequency of the third power supply voltage V3. In this specification, "same frequency" includes not only the case where the two frequencies are completely identical, but also the case where the frequency of one frequency converges within a certain range (e.g., ±5%) relative to the frequency of the other. Furthermore, in Embodiment 1, it is assumed that the amplitude of the second power supply voltage V2 is the same as the amplitude of the third power supply voltage V3; however, the amplitudes of the second power supply voltage V2 and the third power supply voltage V3 may also be different.

[0082] Figure 3 B is a diagram representing an example of the second power supply voltage V2 and the third power supply voltage V3 output from the second power supply circuit 3. Figure 3 In example B, the second power supply circuit 3, as shown by solid line b1, calculates the average power amplitude of the high-frequency signal in three consecutive periods T1, T2, and T3. Based on the calculated average power amplitude, it adjusts the voltage supply levels (amplitudes) of the second power supply voltage V2 and the third power supply voltage V3 according to the three periods T1, T2, and T3. That is, the signal input from the second power supply circuit 3 to the APT terminal 102 is a signal that changes accordingly with the average amplitude of the high-frequency signal detected according to the specified periods T1, T2, and T3.

[0083] (3.4) Filtering circuit

[0084] Filtering circuit 4 is a filter whose passband is the transmit band of a specific communication frequency band (e.g., Band 3). Filtering circuit 4 is, for example, a monolithic elastic wave filter, in which each resonator in the multiple series-arm resonators and multiple parallel-arm resonators is an elastic wave resonator. The elastic wave filter is, for example, a surface acoustic wave (SAW) filter utilizing surface acoustic waves. In the SAW filter, each resonator in the multiple series-arm resonators and multiple parallel-arm resonators is, for example, a SAW (Surface Acoustic Wave) resonator.

[0085] (4) Structural elements of communication devices

[0086] Next, refer to Figure 2 The structural elements of the communication device 8 involved in Embodiment 1 will be explained.

[0087] like Figure 2 As shown, the communication device 8 according to Embodiment 1, in addition to the high-frequency circuit 7 described above, also includes a signal processing circuit 5 and an antenna 6.

[0088] (4.1) Signal processing circuit

[0089] like Figure 2As shown, the signal processing circuit 5 includes an RF signal processing circuit 51 and a baseband signal processing circuit 52. In Embodiment 1, the signal processing circuit 5 processes the high-frequency signal (transmit signal) sent to the high-frequency circuit 7.

[0090] (4.1.1) RF signal processing circuit

[0091] The RF signal processing circuit 51 is electrically connected to the signal input terminal 71 of the high-frequency circuit 7. The RF signal processing circuit 51, for example, is an RFIC (Radio Frequency Integrated Circuit) that processes the high-frequency signal (transmit signal) from the baseband signal processing circuit 52. The RF signal processing circuit 51 performs up-conversion and other signal processing on the high-frequency signal output from the baseband signal processing circuit 52, and outputs the processed high-frequency signal to the high-frequency circuit 7.

[0092] (4.1.2) Baseband signal processing circuit

[0093] The baseband signal processing circuit 52 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 52 generates I-phase and Q-phase signals based on the baseband signal. The baseband signal can be, for example, an externally input audio signal or image signal. The baseband signal processing circuit 52 performs IQ modulation processing by combining the I-phase and Q-phase signals, and then outputs a transmit signal. At this time, the transmit signal is generated as a modulated signal (IQ signal) obtained by amplitude modulation of a carrier signal of a specified frequency with a period longer than the period of the carrier signal.

[0094] (4.2) Antenna

[0095] Antenna 6 is electrically connected to antenna terminal 72 of high-frequency circuit 7. Antenna 6 has the function of transmitting by radiating the transmission signal (high-frequency signal) output from high-frequency circuit 7 using radio waves.

[0096] (5) Operation of the power amplifier circuit

[0097] Next, refer to Figure 3 A, Figure 3 B and Figure 4 The operation of the power amplifier circuit 1 involved in Embodiment 1 will be explained.

[0098] The power amplifier circuit 1 involved in Embodiment 1, for example, amplifies the high-frequency signal (transmit signal) output from the signal processing circuit 5, and outputs the amplified high-frequency signal to the subsequent filter circuit 4 (see reference). Figure 2That is, the power amplifier circuit 1 according to embodiment 1 amplifies the high-frequency signal input from the signal input terminal 71 and outputs the amplified high-frequency signal to the filter circuit 4.

[0099] Here, consider the following scenario: the final stage amplification section 11 only has a first amplification element 111, and a first power supply voltage V1 is applied to the first amplification element 111 from the first power supply circuit 2. In this case, as... Figure 3 As shown in Figure A, the amplitude of the first power supply voltage V1 changes accordingly with the change in the amplitude of the high-frequency signal, thus minimizing the power loss of the first amplifying element 111. However, in this case, the amplitude of the first power supply voltage V1 varies greatly, resulting in a decrease in the responsiveness of the first amplifying element 111.

[0100] Furthermore, consider the following scenario: the final stage amplification section 11 only has the first amplification element 111, and the second power supply voltage V2 is applied to the first amplification element 111 from the second power supply circuit 3. In this case, as... Figure 3 As shown in B, the voltage supply level (amplitude) of the second power supply voltage V2 is changed accordingly to the average power amplitude of the high-frequency signal calculated over a specified period (periods T1, T2, T3), thereby suppressing the decrease in the responsiveness of the first amplifying element 111. However, in this case, the difference between the amplitude of the high-frequency signal and the amplitude of the second power supply voltage V2 is large, resulting in a problem of increased power loss of the first amplifying element 111.

[0101] In the power amplifier circuit 1 according to Embodiment 1, a first power supply voltage V1 is applied (provided) to the first amplifying element 111 to minimize the power consumption loss of the first amplifying element 111 and to suppress the decrease in the responsiveness of the first amplifying element 111. Furthermore, in the power amplifier circuit 1 according to Embodiment 1, the first power supply circuit 2 controls the amplitude variation of the second power supply voltage V2, which is the output voltage of the second power supply circuit 3, and uses this second power supply voltage V2 as a reference to change the first power supply voltage V1.

[0102] Figure 4 This is a graph showing the change of the first power supply voltage V1 applied to the first amplifying element 111 (first collector terminal) of the power amplifier circuit 1 according to Embodiment 1. Figure 4 In the diagram, solid line a2 represents the first power supply voltage V1, and dashed line b2 represents the second power supply voltage V2. Additionally, Figure 4 The “w1” in the figure shows the waveform of the high-frequency signal input from the RF signal processing circuit 51.

[0103] As described above, the first power supply circuit 2 controls the change in the amplitude of the second bias voltage V2 output from the second power supply circuit 3. Here, in Embodiment 1, as described above, the size of the first amplifying element 111 is the same as the size of the second amplifying element 112. Therefore, a first power supply voltage V1 is applied to the first amplifying element 111, which generates half of the combined power in the final amplification section 11, and a second power supply voltage V2 is applied to the second amplifying element 112, which generates the remaining half. Therefore, as... Figure 4 As shown, the first power supply circuit 2 varies the first power supply voltage V1 by a amount relative to the second power supply voltage V2, using the second power supply voltage V2 as a reference. This reduces the amplitude variation of the first power supply voltage V1 by approximately half. Consequently, the decrease in the responsiveness of the first amplifying element 111 can be suppressed, enabling higher-speed operation of the power amplifier circuit 1. Furthermore, compared to applying the second power supply voltage V2 to the first amplifying element 111, the power consumption loss of the first amplifying element 111 is also reduced.

[0104] (6) Characteristics of power amplifier circuits

[0105] Next, refer to Figure 5 The characteristics of the power amplifier circuit 1 involved in Embodiment 1 will be explained.

[0106] Figure 5 This is a graph showing the ACLR (Adjacent Channel Leakage Ratio) characteristics of the power amplifier circuit 1 according to Embodiment 1. Figure 5 The ACLR characteristics of the power amplifier circuit involved in the comparative example are also shown in the diagram. Figure 5 In the diagram, solid line c1 shows the ACLR characteristics of the power amplifier circuit 1 according to Embodiment 1, and dashed line c2 shows the ACLR characteristics of the power amplifier circuit according to the comparative example. Furthermore, Figure 5 The “UTRA1” in the figure indicates the leakage power ratio at 5MHz offset. Here, in Figure 5 In this case, the bandwidth of the high-frequency signal (transmitted signal) is, for example, 60MHz.

[0107] In the power amplifier circuit 1 according to Embodiment 1, a first power supply voltage V1 is applied to the first amplifying element 111 and a second power supply voltage V2 is applied to the second amplifying element 112. The leakage power ratio UTRA1 changes as shown by the solid line c1. Specifically, in the power amplifier circuit 1 according to Embodiment 1, UTRA1 becomes less than -45dBc in the range where the output power is below 23dBm, and becomes greater than -45dBc in the range where the output power is greater than 23dBm.

[0108] On the other hand, in the power amplifier circuit of the comparative example, when a first power supply voltage V1 is applied to the first amplifying element 111, the leakage power ratio UTRA1 changes as shown by the dashed line c2. Specifically, in the power amplifier circuit of the comparative example, UTRA1 is about -45dBc in the range where the output power is below 15dBm, and UTRA1 becomes greater than -45dBc in the range where the output power is greater than 15dBm.

[0109] That is, compared to the power amplifier circuit involved in the comparative example, the power amplifier circuit 1 according to Embodiment 1 can expand the range of output power of UTRA1 to -45dBc or less. In other words, the power amplifier circuit 1 according to Embodiment 1 can suppress UTRA1 to -45dBc or less for a wide range of output power.

[0110] (7) Effect

[0111] As explained above, in the power amplifier circuit 1 according to Embodiment 1, the first amplifying element 111 is connected to the ET terminal 101, and the second amplifying element 112 is connected to the APT terminal 102. Furthermore, in the power amplifier circuit 1 according to Embodiment 1, the first amplifying element 111 and the second amplifying element 112 are connected in parallel. Therefore, the combined power output from the final amplification section 11 can be shared by both the first amplifying element 111 and the second amplifying element 112, thereby reducing the amplitude of the voltage applied to the first amplifying element 111 (the first power supply voltage V1). As a result, the decrease in the responsiveness of the first amplifying element 111 can be suppressed, enabling the power amplifier circuit 1 to operate at a higher speed.

[0112] Furthermore, in the power amplifier circuit 1 according to Embodiment 1, a transformer 140 is provided between the final stage amplification section 11 and the filter circuit 4. As a result, the bandwidth of the high-frequency signal can be widened.

[0113] (8) Variations

[0114] Embodiment 1 is merely one of the various embodiments of the present invention. Various modifications can be made to Embodiment 1 as long as the objective of the present invention is achieved, depending on the design, etc. Hereinafter, variations of Embodiment 1 will be described.

[0115] (8.1) Variation Example 1

[0116] In Embodiment 1, a combining circuit 14 is provided between the final stage amplification section 11 and the antenna terminal 72; however, the combining circuit 14 may be omitted. Additionally, in Embodiment 1, a demultiplexer 13 is provided between the drive stage amplification section 12 and the final stage amplification section 11; however, the demultiplexer 13 may also be omitted. Referring now... Figure 6The power amplifier circuit 1a and high-frequency circuit 7a involved in Modification Example 1 will be explained here. In addition, the first power supply circuit 2 and the second power supply circuit 3 are the same as the first power supply circuit 2 and the second power supply circuit 3 of the high-frequency circuit 7 involved in Embodiment 1, and the description is omitted here.

[0117] like Figure 6 As shown, the high-frequency circuit 7a involved in Modification 1 includes a power amplifier circuit 1a, a first power supply circuit 2, and a second power supply circuit 3. Furthermore, in Modification 1, the high-frequency circuit 7a also includes a signal input terminal 71, an antenna terminal 72, and a filter circuit (not shown).

[0118] (8.1.1) Structural elements of a power amplifier circuit

[0119] Next, refer to Figure 6 To illustrate the structural elements of the power amplifier circuit 1a involved in Modified Example 1.

[0120] like Figure 6 As shown, the power amplifier circuit 1a according to Modification 1 includes a multi-stage (two-stage in the example) amplification section 10a, an ET terminal 101, and an APT terminal 102. The multi-stage amplification section 10a includes a final stage amplification section 11a and a driver stage amplification section 12a. In addition, in Modification 1, the power amplifier circuit 1a also includes multiple (three in the example) matching circuits 161, 162, and 163.

[0121] (8.1.1.1) Amplification section of the final stage

[0122] like Figure 6 As shown, the final stage amplification section 11a has a first amplification element 111 and a second amplification element 112. In addition, in Modified Example 1, the final stage amplification section 11a also has a plurality of capacitors 113 and 114 (two in the example) and a plurality of matching circuits 115 and 116 (two in the example).

[0123] Matching circuit 115 is a circuit used to match the impedance between the final stage amplification section 11a and the subsequent stage filter circuit (not shown). Matching circuit 115 is disposed between the first amplification element 111 and the capacitor 113.

[0124] Matching circuit 116, like matching circuit 115, is a circuit used to match the impedance between the final stage amplification section 11a and the subsequent stage filter circuit (not shown). Matching circuit 116 is disposed between the second amplification element 112 and the capacitor 114.

[0125] Each matching circuit 115, 116 includes, for example, multiple inductors (not shown) and multiple capacitors (not shown). Furthermore, each matching circuit 115, 116 is not limited to a structure including multiple inductors and multiple capacitors; for example, it may also be a structure including only multiple inductors, or a structure including only multiple capacitors. Alternatively, each matching circuit 115, 116 may also be a structure including only one inductor, or a structure including only one capacitor.

[0126] In the power amplifier circuit 1a according to Modification 1, similarly to the power amplifier circuit 1 according to Embodiment 1, the first amplifying element 111 and the second amplifying element 112 are connected in parallel to each other to form a differential amplifier circuit 20a. The first amplifying element 111 is supplied with a first power supply voltage V1 from the first power supply circuit 2 via the ET terminal 101, and the second amplifying element 112 is supplied with a second power supply voltage V2 from the second power supply circuit 3 via the APT terminal 102.

[0127] (8.1.1.2) Amplification section of the driver stage

[0128] like Figure 6 As shown, the amplification section 12a of the drive stage includes an amplification element 121, a capacitor 122, and a matching circuit 123.

[0129] Matching circuit 123 is a circuit used to match the impedance between the RF signal processing circuit (not shown) of the preamplifier stage and the amplification section 12a of the driver stage. Matching circuit 123 is disposed between amplifying element 121 and capacitor 122.

[0130] Matching circuit 123 may include, for example, multiple inductors (not shown) and multiple capacitors (not shown). Furthermore, matching circuit 123 is not limited to a structure including multiple inductors and multiple capacitors; for example, it may also be a structure including only multiple inductors or only multiple capacitors. Alternatively, matching circuit 123 may also be a structure including only one inductor or only one capacitor.

[0131] (8.1.1.3) Matching Circuit

[0132] Matching circuit 161 is a circuit used to match the impedance between the amplification section 12a of the driving stage and the amplification section 11a of the final stage. Matching circuit 161 is disposed between the amplification element 121 of the amplification section 12a of the driving stage and the first amplification element 111 of the amplification section 11a of the final stage.

[0133] Matching circuit 162, like matching circuit 161, is a circuit used to match the impedance between the amplification section 12a of the driving stage and the amplification section 11a of the final stage. Matching circuit 162 is disposed between the amplification element 121 of the amplification section 12a of the driving stage and the second amplification element 112 of the amplification section 11a of the final stage.

[0134] Matching circuit 163 is a circuit used to match the impedance between the final stage amplifier section 11a and the subsequent filter circuit (not shown). Matching circuit 163 is disposed between capacitors 113 and 114 of the final stage amplifier section 11a and the input terminal of the filter circuit.

[0135] Each matching circuit 161, 162, and 163 includes, for example, multiple inductors (not shown) and multiple capacitors (not shown). Furthermore, each matching circuit 161, 162, and 163 is not limited to a structure including multiple inductors and multiple capacitors; for example, it may also be a structure including only multiple inductors, or a structure including only multiple capacitors. Alternatively, each matching circuit 161, 162, and 163 may also be a structure including only one inductor, or a structure including only one capacitor.

[0136] In the power amplifier circuit 1a according to Modification 1, similarly to the power amplifier circuit 1 according to Embodiment 1, the first amplifying element 111 is connected to the ET terminal 101, and the second amplifying element 112 is connected to the APT terminal 102. Furthermore, in the power amplifier circuit 1a according to Modification 1, the first amplifying element 111 and the second amplifying element 112 are connected in parallel. Therefore, the combined power output from the final amplification section 11a can be shared by both the first amplifying element 111 and the second amplifying element 112, thereby reducing the amplitude of the voltage applied to the first amplifying element 111 (the first power supply voltage V1). As a result, the decrease in the responsiveness of the first amplifying element 111 can be suppressed, enabling the power amplifier circuit 1 to operate at a higher speed.

[0137] (8.2) Other variations

[0138] Below are other variations.

[0139] In Embodiment 1 and Modification 1, the number of amplification stages is 2, but it can also be 3 or more. For example, an additional amplification stage can be provided between the amplification stages 12, 12a of the driving stage and the amplification stages 11, 11a of the final stage.

[0140] Furthermore, in Embodiment 1 and Modification 1, the first amplifying element 111, the second amplifying element 112, and the amplifying element 121 each comprise an npn-type bipolar transistor, but for example, they may also comprise a pnp-type bipolar transistor. Alternatively, the first amplifying element 111, the second amplifying element 112, and the amplifying element 121 may each comprise a field-effect transistor such as a MOSFET (Metal Oxide Field-Effect Transistor). In this case, the dimensions of each of the first amplifying element 111, the second amplifying element 112, and the amplifying element 121 are determined by the gate width of the MOSFET constituting each amplifying element. For example, if the dimensions of the first amplifying element 111 and the second amplifying element 112 are the same, the gate width of the MOSFET constituting the first amplifying element 111 is the same as the gate width of the MOSFET constituting the second amplifying element 112.

[0141] In addition, in Embodiment 1 and Modification 1, the filter circuit 4 is an elastic wave filter that utilizes surface acoustic waves, but it is not limited to this. For example, it can also be an elastic wave filter that utilizes elastic interface waves, plate waves, etc.

[0142] In addition, in elastic wave filters, the resonators in multiple series arm resonators and multiple parallel arm resonators are not limited to SAW resonators, but can also be BAW (Bulk Acoustic Wave) resonators, for example.

[0143] Furthermore, in Embodiment 1 and Modification 1, the high-frequency circuits 7 and 7a only include a transmitting circuit comprising power amplifier circuits 1 and 1a and a filter circuit 4. However, they may also include a receiving circuit comprising a low-noise amplifier that amplifies the received signal input from antenna terminal 72 and a filter circuit connected to the low-noise amplifier. Moreover, the filter circuit 4 is not limited to a transmitting filter; it may also be a duplexer.

[0144] In Embodiment 1 and Modification 1, the first power supply circuit 2 obtains voltage information from the second power supply circuit 3, but is not limited thereto. For example, the first power supply circuit 2 may also calculate the average power amplitude of the high-frequency signal over a predetermined period, and calculate the amplitude of the second power supply voltage V2 based on the calculated average power amplitude.

[0145] In Embodiment 1 and Modification 1, the size of the first amplifying element 111 is the same as the size of the second amplifying element 112, but this is not a limitation. For example, the size of the first amplifying element 111 may be larger than the size of the second amplifying element 112, or the size of the first amplifying element 111 may be smaller than the size of the second amplifying element 112. When the size of the first amplifying element 111 is larger than the size of the second amplifying element 112, power consumption can be reduced. Furthermore, when the size of the first amplifying element 111 is smaller than the size of the second amplifying element 112, the responsiveness is improved (faster).

[0146] (Implementation Method 2)

[0147] Reference Figure 7 and Figure 8 The power amplifier circuit 1b and the high-frequency circuit 7b involved in Embodiment 2 will be described below. Regarding the power conversion circuit 1b and the high-frequency circuit 7b involved in Embodiment 2, the same structural elements as the power conversion circuit 1 and the high-frequency circuit 7 involved in Embodiment 1 will be marked with the same reference numerals and the description will be omitted.

[0148] (1) Structure of power amplifier circuit and high frequency circuit

[0149] like Figure 7 As shown, the high-frequency circuit 7b according to Embodiment 2 includes a power amplifier circuit 1b, a first power supply circuit 2, a second power supply circuit 3, and a filter circuit 4 (see reference). Figure 2 Furthermore, the first power supply circuit 2, the second power supply circuit 3, and the filter circuit 4 are the same as the first power supply circuit 2, the second power supply circuit 3, and the filter circuit 4 of the high-frequency circuit 7 involved in Embodiment 1 described above, and their descriptions are omitted here.

[0150] like Figure 7 As shown, the power amplifier circuit 1b according to Embodiment 2 includes an amplification section 12 of the driving stage, an amplification section 11b of the final stage, a demultiplexer 13, and a combining circuit 14.

[0151] The amplification section 12 of the drive stage includes an amplifying element 121 and a capacitor 122. The amplifying element 121 is, for example, an npn-type bipolar transistor. The amplifying element 121 supplies power to the RF signal processing circuit 51 (see reference 5). Figure 2 The high-frequency signal is amplified.

[0152] Amplifying element 121 has a base terminal, a collector terminal, and an emitter terminal. Amplifying element 121 amplifies the high-frequency signal input to the base terminal and outputs it from the collector terminal. The emitter terminal is connected to ground. In other words, the emitter terminal is directly or indirectly connected to ground. That is, the emitter terminal is grounded (emitter grounded). The collector terminal is electrically connected to the first end of the primary winding 131 of the transformer 130 of the demultiplexer 13. The second end of the primary winding 131 of the transformer 130 is connected to the second power supply circuit 3 via the APT terminal 102. Furthermore, the base terminal is electrically connected to the signal input terminal 71 via capacitor 122. Capacitor 122 is a DC blocking capacitor that blocks the DC component input to amplifying element 121.

[0153] The final stage amplification section 11b has a first amplifying element 111 and a second amplifying element 112. Additionally, the final stage amplification section 11b also has multiple (e.g., five) capacitors 113, 114, 118, 119, and 120. Furthermore, the final stage amplification section 11b also has a phase adjustment circuit 117. The first amplifying element 111 and the second amplifying element 112 are, for example, npn-type bipolar transistors. The first amplifying element 111 is, for example, a Class C amplifier. The second amplifying element 112 is, for example, a Class AB amplifier.

[0154] The first amplifying element (Peaking Amplifier / Aux Amplifier) ​​111 has a first base terminal, a first collector terminal, and a first emitter terminal. The first amplifying element 111 amplifies a first signal (high-frequency signal) input to the first base terminal to output a first amplified signal from the first collector terminal. The first emitter terminal is connected to ground. In other words, the first emitter terminal is directly or indirectly connected to ground. That is, the first emitter terminal is grounded (emitter grounded). The first collector terminal is connected to the first power supply circuit 2 via the ET terminal 101, thereby applying (providing) a first power supply voltage V1. Additionally, the first collector terminal is connected to the first end of the primary winding 141 of the transformer 140 of the combining circuit 14 via capacitor 113 and phase adjustment circuit 117. Furthermore, the first base terminal is connected to the first end of the secondary winding 132 of the transformer 130 of the demultiplexer 13 via capacitor 118. Capacitor 113 is a DC blocking capacitor that blocks the DC component output from the first amplifying element 111. Capacitor 118 is a DC blocking capacitor that blocks the DC component input to the first amplifying element 111.

[0155] The second amplifying element (Main Amplifier / Carrier Amplifier) ​​112 has a second base terminal, a second collector terminal, and a second emitter terminal. The second amplifying element 112 amplifies the second signal (high-frequency signal) input to the second base terminal to output a second amplified signal from the second collector terminal. The second emitter terminal is connected to ground. In other words, the second emitter terminal is directly or indirectly connected to ground. That is, the second emitter terminal is grounded (emitter grounded). The second collector terminal is connected to the second power supply circuit 3 via the APT terminal 102, thereby applying (providing) a second power supply voltage V2. Additionally, the second collector terminal is connected to the second end of the primary winding 141 of the transformer 140 via capacitor 114. Furthermore, the second base terminal is connected to the second end of the secondary winding 132 of the transformer 130 via capacitor 119. Capacitor 114 is a DC blocking capacitor that blocks the DC component output from the second amplifying element 112. Capacitor 119 is a DC blocking capacitor that blocks the DC component input to the second amplifying element 112.

[0156] In the power amplifier circuit 1b according to embodiment 2, such as Figure 7 As shown, the first signal path R1 through which the first amplified signal passes and the second signal path R2 through which the second amplified signal passes are connected to each other via the primary winding 141 of the transformer 140 of the combining circuit 14. Furthermore, in the power amplifier circuit 1b according to Embodiment 2, a phase adjustment circuit 117 is provided in the first signal path R1. Therefore, in the power amplifier circuit 1b according to Embodiment 2, the first signal path R1 is a specific signal path.

[0157] like Figure 7 As shown, the demultiplexer 13 includes a transformer 130. The transformer 130 has a primary winding 131 and a secondary winding 132. The first end of the primary winding 131 is connected to the collector terminal of the amplifying element 121 as described above. The second end of the primary winding 131 is connected to the second power supply circuit 3 via the APT terminal 102 as described above. The first end of the secondary winding 132 is connected to the first base terminal of the first amplifying element 111 via a capacitor 118 as described above. The second end of the secondary winding 132 is connected to the second base terminal of the second amplifying element 112 via a capacitor 119 as described above. A capacitor 120 is connected between the two ends of the secondary winding 132. The demultiplexer 13 divides the high-frequency input signal input via the amplification section 12 of the drive stage into a first signal and a second signal. The first signal and the second signal are signals with different phases. As described above, the first signal is input to the first amplifying element 111, and the second signal is input to the second amplifying element 112.

[0158] like Figure 7 As shown, the combining circuit 14 includes a transformer 140. The transformer 140 has a primary winding 141 and a secondary winding 142. The first end of the primary winding 141 is connected to the first collector terminal of the first amplifying element 111 via a capacitor 113 and a phase adjustment circuit 117, as described above. The second end of the primary winding 141 is connected to the second collector terminal of the second amplifying element 112 via a capacitor 114, as described above. The first end of the secondary winding 142 is connected to ground. Furthermore, the second end of the secondary winding 142 is connected to the antenna terminal 72 via a capacitor 134. The capacitor 134 is a DC blocking capacitor that blocks the DC component input to the antenna terminal 72. The combining circuit 14 combines the first amplified signal output from the first amplifying element 111 with the second amplified signal output from the second amplifying element 112. This further amplifies the signal input to the antenna terminal 72.

[0159] Phase adjustment circuit 117 includes, for example, a λ / 4 line. Phase adjustment circuit 117 adjusts the phase of the first amplified signal passing through the first signal path R1. More specifically, phase adjustment circuit 117 lags the phase of the first amplified signal by 90°. Here, "λ" is the wavelength of the high-frequency signals (first amplified signal and second amplified signal) output from the first amplifying element 111 and the second amplifying element 112.

[0160] (2) Operation of power amplifier circuit

[0161] Next, the operation of the power amplifier circuit 1b according to Embodiment 2 will be explained.

[0162] (2.1) First action

[0163] During the first operation of the power amplifier circuit 1b, both the first amplifying element 111 and the second amplifying element 112 operate. At this time, the power level of the first signal input to the first amplifying element 111 is above the reference power level. For example, when the output power of the first amplifying element 111 is the same as the output power of the second amplifying element 112, the "reference power level" is defined as approximately twice the power input to the second amplifying element 112. Furthermore, for example, when the input power input to the first amplifying element 111 and the second amplifying element 112 gradually increases, the "reference power level" is defined as the power from the saturation of the second amplifying element 112 until the first amplifying element 111 begins to output. That is, when the power level of the first signal input to the first amplifying element 111 becomes above the reference power level, the first amplifying element 111 amplifies the first signal to output a first amplified signal. On the other hand, regardless of the power level of the second signal input to the second amplifying element 112, the second amplifying element 112 amplifies the second signal to output a second amplified signal.

[0164] Here, the impedance of the first amplifying element 111 is assumed to be Z1, and the impedance of the second amplifying element 112 is assumed to be Z2. Furthermore, the output voltage of each of the first amplifying element 111 and the second amplifying element 112 is assumed to be V0, and the voltage across the primary winding 141 of the transformer 140 (hereinafter referred to as the "primary voltage") is assumed to be V. 11 Let the voltage across the secondary winding 142 of transformer 140 (hereinafter referred to as "secondary voltage") be V. 21 Furthermore, the current flowing through the primary winding 141 (hereinafter referred to as the "primary current") is assumed to be i. 11 Let the current flowing through the secondary winding 142 (hereinafter referred to as "secondary current") be i. 21 In addition, the turns ratio of the primary winding 141 to the secondary winding 142 is assumed to be 1:m.

[0165] Here, the phase of the first amplified signal (voltage signal) output from the first amplifying element 111 is opposite to the phase of the second amplified signal (voltage signal) output from the second amplifying element 112. Therefore, the primary voltage V applied to the primary winding 141 is... 11 As shown in equation (1).

[0166] [Formula 1]

[0167] V 11 =2×V0…(1)

[0168] Therefore, the secondary voltage V applied to the secondary winding 142 21 As shown in equation (2).

[0169] [Formula 2]

[0170] V 21 =m×V 11 =2×m×V0…(2)

[0171] In addition, the secondary current i flowing through the secondary winding 142 21 As shown in equation (3).

[0172] [Formula 3]

[0173]

[0174] Here, when the resistance value of the load connected to the secondary winding 142 is set to RL, the resistance value RL is as shown in equation (4).

[0175] [Formula 4]

[0176]

[0177] Therefore, during the first operation, the impedance Z1 of the first amplifying element 111 and the impedance Z2 of the second amplifying element 112 are respectively as shown in equation (5).

[0178] [Formula 5]

[0179]

[0180] During the first operation, the impedance Z1 of the first amplifying element 111 and the impedance Z2 of the second amplifying element 112 are both low, for example, 5Ω to 10Ω.

[0181] (2.2) Second action

[0182] During the second operation of the power amplifier circuit 1b, the input power to the first amplifying element 111 decreases, and the output power of the first amplifying element 111 approaches zero. In the power amplifier circuit 1b according to Embodiment 2, a λ / 4 line (phase adjustment circuit 117) is provided on the first signal path R1 connected to the first amplifying element 111, thus the first end of the primary winding 141 of the transformer 140 becomes short-circuited. At this time, since the impedance Z1 of the first amplifying element 111 is always large, the first amplifying element 111 becomes disconnected from the first signal path R1.

[0183] At this time, the primary voltage V applied to the primary winding 141 11 As shown in equation (6).

[0184] [Formula 6]

[0185] V 11 =V0…(6)

[0186] Therefore, the secondary voltage V applied to the secondary winding 14221 As shown in equation (7).

[0187] [Formula 7]

[0188] V 21 =m×V 11 =m×V0…(7)

[0189] Regarding the secondary current i 21 As in the first operation, the resistance value R of the load connected to the secondary winding 142 is the same. L As shown in equation (8).

[0190] "Formula 8"

[0191]

[0192] Therefore, during the second operation, the impedance Z2 of the second amplifying element 112 is as shown in equation (9).

[0193] [Formula 9]

[0194]

[0195] In summary, according to equations (5) and (9), the impedance Z2 of the second amplifying element 112 during the second operation becomes twice the impedance Z2 of the second amplifying element 112 during the first operation. Therefore, compared to the first operation, the amplification efficiency of the power amplifier circuit 1b can be improved during the second operation. That is, according to the power amplifier circuit 1b of Embodiment 2, the decrease in amplification efficiency can be suppressed.

[0196] Figure 8 This is a characteristic graph showing the relationship between the output power and amplification efficiency of a power amplifier circuit. Figure 8 The solid line d1 in the figure illustrates the characteristics of the power amplifier circuit 1b according to Embodiment 2. Furthermore, Figure 8 The dashed line d2 in the diagram illustrates the characteristics of the Dougherty amplifier circuit involved in the comparative example. Additionally, Figure 8 The dotted line d3 in the diagram illustrates the characteristics when both the first amplifying element 111 and the second amplifying element 112 are operated using the first power supply circuit 2.

[0197] like Figure 8As shown, compared to the case where both the first amplifying element 111 and the second amplifying element 112 are operated using the first power supply circuit 2, the power amplifier circuit 1b according to Embodiment 2 can improve amplification efficiency throughout the entire output power range (the range from 0 dBm to 33 dBm). Furthermore, compared to the Dougherty amplifier circuit according to the comparative example, the power amplifier circuit 1b according to Embodiment 2 can improve amplification efficiency in the region where the output power is 28 dBm or higher. On the other hand, compared to the Dougherty amplifier circuit according to the comparative example, the power amplifier circuit 1b according to Embodiment 2 exhibits a slightly lower amplification efficiency in the region where the output power is less than 28 dBm.

[0198] In the power amplifier circuit 1b according to Embodiment 2, the phase adjustment circuit 117 is provided in the first signal path R1, but is not limited thereto. The phase adjustment circuit 117 may also be provided in the second signal path R2, for example. That is, the second signal path R2 may be a specific signal path.

[0199] (Implementation Method 3)

[0200] Reference Figure 9 The power amplifier circuit 1c and the high-frequency circuit 7c involved in Embodiment 3 will be described below. Regarding the power conversion circuit 1c and the high-frequency circuit 7c involved in Embodiment 3, the same structural elements as the power conversion circuit 1 and the high-frequency circuit 7 involved in Embodiment 1 will be marked with the same reference numerals and the description will be omitted.

[0201] (1) Structure of power amplifier circuit and high frequency circuit

[0202] like Figure 9 As shown, the high-frequency circuit 7c according to Embodiment 3 includes a power amplifier circuit 1c, a first power supply circuit 2, a second power supply circuit 3, and a filter circuit 4 (see reference). Figure 2 Furthermore, the first power supply circuit 2, the second power supply circuit 3, and the filter circuit 4 are the same as the first power supply circuit 2, the second power supply circuit 3, and the filter circuit 4 of the high-frequency circuit 7 involved in Embodiment 1 described above, and their descriptions are omitted here.

[0203] like Figure 9As shown, the power amplifier circuit 1c according to Embodiment 3 includes an amplification section 12c of the driving stage, an amplification section 11c of the final stage, multiple (e.g., two) demultiplexers 13A and 13B, and multiple (e.g., two) combining circuits 14A and 14B. Furthermore, the power amplifier circuit 1c according to Embodiment 3 also includes a demultiplexer 17. In the following description, when the multiple demultiplexers 13A and 13B are described separately, they may sometimes be referred to as the first demultiplexer 13A and the second demultiplexer 13B, respectively. Similarly, in the following description, when the multiple combining circuits 14A and 14B are described separately, they may sometimes be referred to as the first combining circuit 14A and the second combining circuit 14B, respectively.

[0204] The amplification section 12c of the driver stage has multiple (e.g., two) amplifying elements 121, 124 and multiple (e.g., two) capacitors 122, 125. The multiple amplifying elements 121, 124 are, for example, npn-type bipolar transistors. The multiple amplifying elements 121, 124 respectively supply power to the RF signal processing circuit 51 (refer to...) from the signal processing circuit 5. Figure 2 The high-frequency signal is amplified.

[0205] Multiple amplifying elements 121 and 124 each have a base terminal, a collector terminal, and a emitter terminal. The high-frequency signal input to the base terminal is amplified by each amplifying element 121 and 124 and output from the collector terminal. The emitter terminals of each amplifying element 121 and 124 are connected to ground. In other words, the emitter terminals of each amplifying element 121 and 124 are directly or indirectly connected to ground. That is, the emitter terminals of each amplifying element 121 and 124 are grounded (emitter grounded). The collector terminal of amplifying element 121 is connected to the first end of the primary winding 131 of the transformer 130 of the second demultiplexer 13B. The second end of the primary winding 131 of the transformer 130 of the second demultiplexer 13B is connected to the second power supply circuit 3 via the APT terminal 102. Additionally, the base terminal of amplifying element 121 is connected to the signal input terminal 71 via capacitor 122 and the primary winding 1711 of the transformer 171 of the demultiplexer 17. The collector terminal of amplifying element 124 is connected to the first end of the primary winding 131 of the transformer 130 of the first demultiplexer 13A. The second end of the primary winding 131 of the transformer 130 of the first demultiplexer 13A is connected to the second power supply circuit 3 via the APT terminal 102. Additionally, the base terminal of amplifying element 124 is connected to the signal input terminal 71 via capacitor 125 and capacitor 172 of the demultiplexer 17. Capacitor 122 is a DC blocking capacitor that blocks the DC component input to amplifying element 121. Capacitor 125 is a DC blocking capacitor that blocks the DC component input to amplifying element 124.

[0206] The final stage amplification section 11c has a first amplifying element 111 and a second amplifying element 112. Additionally, the final stage amplification section 11c also has a third amplifying element 164 and a fourth amplifying element 165. Furthermore, the final stage amplification section 11c also has multiple (e.g., eight) capacitors 135, 136, 137, 138, 143, 144, 145, and 146. Additionally, the final stage amplification section 11c also has multiple (e.g., two) phase adjustment circuits 117A and 117B. The first amplifying element 111, the second amplifying element 112, the third amplifying element 164, and the fourth amplifying element 165 are, for example, npn-type bipolar transistors. Furthermore, the first amplifying element 111 and the third amplifying element 164 are, for example, Class C amplifiers. The second amplifying element 112 and the fourth amplifying element 165 are, for example, Class AB amplifiers. In the following description, while the multiple phase adjustment circuits 117A and 117B are described separately, the multiple phase adjustment circuits 117A and 117B are sometimes referred to as the first phase adjustment circuit 117A and the second phase adjustment circuit 117B, respectively.

[0207] The first amplifying element 111 has a first base terminal, a first collector terminal, and a first emitter terminal. The first amplifying element 111 amplifies a first signal (high-frequency signal) input to the first base terminal to output a first amplified signal from the first collector terminal. The first emitter terminal is connected to ground. In other words, the first emitter terminal is directly or indirectly connected to ground. That is, the first emitter terminal is grounded (emitter grounded). The first collector terminal is connected to the first end of the primary winding 141 of the transformer 140 of the first combining circuit 14A via the first phase adjustment circuit 117A. Furthermore, the first base terminal is connected to the first end of the secondary winding 132 of the transformer 130 of the first demultiplexer 13A via capacitor 136. Capacitor 136 is a DC blocking capacitor that blocks the DC component input to the first amplifying element 111.

[0208] The second amplifying element 112 has a second base terminal, a second collector terminal, and a second emitter terminal. The second amplifying element 112 amplifies the second signal (high-frequency signal) input to the second base terminal to output a second amplified signal from the second collector terminal. The second emitter terminal is connected to ground. In other words, the second emitter terminal is directly or indirectly connected to ground. That is, the second emitter terminal is grounded (emitter grounded). The second collector terminal is connected to the first end of the primary winding 141 of the transformer 140 of the second synthesis circuit 14B. Furthermore, the second base terminal is connected to the first end of the secondary winding 132 of the transformer 130 of the second demultiplexer 13B via a capacitor 144. The capacitor 144 is a DC blocking capacitor that blocks the DC component input to the second amplifying element 112.

[0209] The third amplifying element 164 has a third base terminal, a third collector terminal, and a third emitter terminal. The third amplifying element 164 amplifies the third signal (high-frequency signal) input to the third base terminal to output a third amplified signal from the third collector terminal. The third emitter terminal is connected to ground. In other words, the third emitter terminal is directly or indirectly connected to ground. That is, the third emitter terminal is grounded (emitter grounded). The third collector terminal is connected to the second end of the primary winding 141 of the transformer 140 of the first synthesizer circuit 14A via the second phase adjustment circuit 117B. Furthermore, the third base terminal is connected to the second end of the secondary winding 132 of the transformer 130 of the first splitter 13A via capacitor 137. Capacitor 137 is a DC blocking capacitor that blocks the DC component input to the third amplifying element 164. In the power amplifier circuit 1c according to Embodiment 3, the third amplifying element 164 is connected in parallel with the first amplifying element 111. Furthermore, a capacitor 135 is connected between the first collector terminal of the first amplifying element 111 and the third collector terminal of the third amplifying element 164.

[0210] The fourth amplifying element 165 has a fourth base terminal, a fourth collector terminal, and a fourth emitter terminal. The fourth amplifying element 165 amplifies the fourth signal (high-frequency signal) input to the fourth base terminal to output a fourth amplified signal from the fourth collector terminal. The fourth emitter terminal is connected to ground. In other words, the fourth emitter terminal is directly or indirectly connected to ground. That is, the fourth emitter terminal is grounded (emitter grounded). The fourth collector terminal is connected to the second end of the primary winding 141 of the transformer 140 of the second synthesizer circuit 14B. Furthermore, the fourth base terminal is connected to the second end of the secondary winding 132 of the transformer 130 of the second splitter 13B via a capacitor 145. The capacitor 145 is a DC blocking capacitor that blocks the DC component input to the fourth amplifying element 165. In the power amplifier circuit 1c according to Embodiment 3, the fourth amplifying element 165 is connected in parallel with the second amplifying element 112. Furthermore, a capacitor 143 is connected between the second collector terminal of the second amplifying element 112 and the fourth collector terminal of the fourth amplifying element 165.

[0211] In the power amplifier circuit 1c according to embodiment 3, such as Figure 9 As shown, the first signal path R1 through which the first amplified signal passes and the third signal path R3 through which the third amplified signal passes are connected to each other via the primary winding 141 of the transformer 140 of the first combining circuit 14A. Furthermore, in the power amplifier circuit 1c according to Embodiment 3, as... Figure 9 As shown, the second signal path R2 through which the second amplified signal passes and the fourth signal path R4 through which the fourth amplified signal passes are connected to each other via the primary winding 141 of the transformer 140 of the second combining circuit 14B. Furthermore, in the power amplifier circuit 1c according to Embodiment 3, the first phase adjustment circuit 117A is provided in the first signal path R1. Additionally, in the power amplifier circuit 1c according to Embodiment 3, the second phase adjustment circuit 117B is provided in the third signal path R3. Therefore, in the power amplifier circuit 1c according to Embodiment 3, the first signal path R1 is a first specific signal path, and the third signal path R3 is a second specific signal path.

[0212] In the power amplifier circuit 1c according to Embodiment 3, the two amplifying elements 121 and 124 constituting the amplification section 12c of the drive stage are connected in parallel. Therefore, the first amplifying element 111 and the second amplifying element 112, which are connected to the two amplifying elements 124 and 121 via the first splitter 13A and the second splitter 13B respectively, are also connected in parallel. Similarly, the third amplifying element 164 and the fourth amplifying element 165, which are connected to the two amplifying elements 124 and 121 via the first splitter 13A and the second splitter 13B respectively, are also connected in parallel.

[0213] like Figure 9 As shown, the first demultiplexer 13A includes a transformer 130. The transformer 130 has a primary winding 131 and a secondary winding 132. The first end of the primary winding 131 is connected to the collector terminal of the amplifying element 124 as described above. The second end of the primary winding 131 is connected to the second power supply circuit 3 via the APT terminal 102 as described above. The first end of the secondary winding 132 is connected to the third base terminal of the third amplifying element 164 via the capacitor 137 as described above. The second end of the secondary winding 132 is connected to the first base terminal of the first amplifying element 111 via the capacitor 136 as described above. Furthermore, a capacitor 138 is connected between the two ends of the secondary winding 132. The first demultiplexer 13A divides the high-frequency first input signal input via the amplifying element 124 of the amplification section 12c of the drive stage into a first signal and a third signal. The first signal and the third signal are signals with different phases. As described above, the first signal is input to the first amplifying element 111, and the third signal is input to the third amplifying element 164.

[0214] like Figure 9 As shown, the second demultiplexer 13B includes a transformer 130. The transformer 130 has a primary winding 131 and a secondary winding 132. The first end of the primary winding 131 is connected to the collector terminal of the amplifying element 121 as described above. The second end of the primary winding 131 is connected to the second power supply circuit 3 via the APT terminal 102 as described above. The first end of the secondary winding 132 is connected to the fourth base terminal of the fourth amplifying element 165 via a capacitor 145 as described above. The second end of the secondary winding 132 is connected to the second base terminal of the second amplifying element 112 via a capacitor 144 as described above. Furthermore, a capacitor 146 is connected between the two ends of the secondary winding 132. The second demultiplexer 13B distributes the high-frequency second input signal input via the amplifying element 121 of the amplifying section 12c of the drive stage into a second signal and a fourth signal. The second signal and the fourth signal are signals with different phases. As described above, the second signal is input to the second amplifying element 112, and the fourth signal is input to the fourth amplifying element 165.

[0215] like Figure 9As shown, the first combining circuit 14A includes a transformer 140. The transformer 140 has a primary winding 141 and a secondary winding 142. The first end of the primary winding 141 (the end on the third signal path R3 side) is connected to the third collector terminal of the third amplifying element 164 via the second phase adjustment circuit 117B, as described above. The second end of the primary winding 141 (the end on the first signal path R1 side) is connected to the first collector terminal of the first amplifying element 111 via the first phase adjustment circuit 117A, as described above. The first end of the secondary winding 142 is connected to ground. Furthermore, the second end of the secondary winding 142 is connected to the first end of the primary winding 141 of the transformer 140 in the second combining circuit 14B. Additionally, the midpoint M1 of the primary winding 141 is connected to the first power supply circuit 2 via the ET terminal 101. The first combining circuit 14A combines the first amplified signal output from the first amplifying element 111 with the third amplified signal output from the third amplifying element 164. This further amplifies the signal output toward the antenna terminal 72.

[0216] like Figure 9 As shown, the second combining circuit 14B includes a transformer 140. The transformer 140 has a primary winding 141 and a secondary winding 142. The first end of the primary winding 141 (the end on the fourth signal path R4 side) is connected to the fourth collector terminal of the fourth amplifying element 165 as described above. The second end of the primary winding 141 (the end on the second signal path R2 side) is connected to the second collector terminal of the second amplifying element 112 as described above. The first end of the secondary winding 142 is connected to the second end of the secondary winding 142 of the transformer 140 of the first combining circuit 14A as described above. Furthermore, the second end of the secondary winding 142 is connected to the antenna terminal 72 via a capacitor 134. The capacitor 134 is a DC blocking capacitor that blocks the DC component input to the antenna terminal 72. Additionally, the midpoint M2 of the primary winding 141 is connected to the second power supply circuit 3 via the APT terminal 102. The second combining circuit 14B combines the second amplified signal output from the second amplifying element 112 with the fourth amplifying signal output from the fourth amplifying element 165. This further amplifies the signal output toward the antenna terminal 72.

[0217] The first phase adjustment circuit 117A includes, for example, a λ / 4 line. The first phase adjustment circuit 117A adjusts the phase of the first amplified signal passing through the first signal path R1. More specifically, the first phase adjustment circuit 117A causes the phase of the first amplified signal to lag by 90°.

[0218] The second phase adjustment circuit 117B includes, for example, a λ / 4 line. The second phase adjustment circuit 117B adjusts the phase of the third amplified signal passing through the third signal path R3. More specifically, the second phase adjustment circuit 117B causes the phase of the third amplified signal to lag by 90°.

[0219] The demultiplexer 17 includes a transformer 171, multiple (e.g., two) capacitors 172 and 173, and a resistor 174. The transformer 171 has a primary winding 1711 and a secondary winding 1712. A first end of the primary winding 1711 is connected to a signal input terminal 71. A second end of the primary winding 1711 is connected to the base terminal of an amplifying element 121 via a capacitor 122. A first end of the secondary winding 1712 is connected to the junction of capacitors 125 and 172. A second end of the secondary winding 1712 is connected to the junction of capacitor 173 and resistor 174. Furthermore, capacitor 173 and resistor 174 are connected in series between the junction of the primary winding 1711 and capacitor 122 and ground. The demultiplexer 17 divides the signal input via the signal input terminal 71 into two signals with different phases and inputs them to the amplification section 12c of the drive stage.

[0220] (2) Operation of power amplifier circuit

[0221] Next, the operation of the power amplifier circuit 1c according to Embodiment 3 will be explained.

[0222] (2.1) First action

[0223] During the first operation of the power amplifier circuit 1c, the first amplifying element 111, the second amplifying element 112, the third amplifying element 164, and the fourth amplifying element 165 all operate. At this time, the power level of the first signal input to the first amplifying element 111 and the power level of the third signal input to the third amplifying element 164 are both above the reference power level. That is, when the power level of the first signal input to the first amplifying element 111 becomes above the reference power level, the first amplifying element 111 amplifies the first signal to output a first amplified signal. Similarly, when the power level of the third signal input to the third amplifying element 164 becomes above the reference power level, the third amplifying element 164 amplifies the third signal to output a third amplified signal. On the other hand, regardless of the power level of the second signal input to the second amplifying element 112, the second amplifying element 112 amplifies the second signal to output a second amplified signal. Furthermore, regardless of the power level of the fourth signal input to the fourth amplifying element 165, the fourth amplifying element 165 amplifies the fourth signal to output a fourth amplified signal.

[0224] Here, the impedance of the first amplifying element 111 is assumed to be Z1, the impedance of the second amplifying element 112 is assumed to be Z2, the impedance of the third amplifying element 164 is assumed to be Z3, and the impedance of the fourth amplifying element 165 is assumed to be Z4. Furthermore, the output voltage of each of the first amplifying element 111, the second amplifying element 112, the third amplifying element 164, and the fourth amplifying element 165 is assumed to be V0, and the voltage across the primary winding 141 of the transformer 140 of each of the first combining circuit 14A and the second combining circuit 14B (hereinafter referred to as the "primary voltage") is assumed to be V. 11 Let the voltage across the secondary winding 142 of the transformer 140 of the first synthesis circuit 14A and the second synthesis circuit 14B (hereinafter referred to as "secondary voltage") be V. 21 Furthermore, the current flowing through the primary winding 141 of the first combining circuit 14A and the second combining circuit 14B (hereinafter referred to as the "primary current") is assumed to be i. 11 Let i be the current flowing through the secondary winding 142 of the first combining circuit 14A and the second combining circuit 14B (hereinafter referred to as "secondary current"). 21 Furthermore, the turns ratio of the primary winding 141 to the secondary winding 142 of each of the first synthesis circuit 14A and the second synthesis circuit 14B is assumed to be 1:m.

[0225] Here, the phase of the first amplified signal (voltage signal) output from the first amplifying element 111 is opposite to the phase of the third amplified signal (voltage signal) output from the third amplifying element 164. Furthermore, the phase of the second amplified signal (voltage signal) output from the second amplifying element 112 is opposite to the phase output from the fourth amplifying element 165. Therefore, the primary voltage V applied to the primary winding 141 of the transformer 140 of each of the first combining circuit 14A and the second combining circuit 14B... 11 As shown in equation (10).

[0226] [Formula 10]

[0227] V 11 =2×V0…(10)

[0228] Therefore, the secondary voltage V applied to the secondary winding 142 of the transformer 140 of the first synthesis circuit 14A and the second synthesis circuit 14B is... 21 As shown in equation (11).

[0229] [Formula 11]

[0230] V 21 =m×V 11 =2×m×V0…(11)

[0231] In addition, the secondary current i flowing through the secondary winding 142 of the transformer 140 of the first synthesis circuit 14A and the second synthesis circuit 14B is... 21 As shown in equation (12).

[0232] [Formula 12]

[0233]

[0234] Here, when the resistance value of the load connected to the secondary winding 142 of the first synthesis circuit 14A and the secondary winding 142 of the second synthesis circuit 14B connected in series with each other is set to RL, the resistance value RL is as shown in equation (13).

[0235] [Formula 13]

[0236]

[0237] Therefore, during the first operation, the impedance Z2 of the second amplifying element 112 and the impedance Z4 of the fourth amplifying element 165 are respectively as shown in equation (14).

[0238] [Formula 14]

[0239]

[0240] During the first operation, the impedance Z2 of the second amplifying element 112 and the impedance Z4 of the fourth amplifying element 165 are both low, for example, 5Ω to 10Ω.

[0241] (2.2) Second action

[0242] During the second operation of the power amplifier circuit 1c, the input power to the first amplifying element 111 and the third amplifying element 164 decreases, and the output power of the first amplifying element 111 and the third amplifying element 164 approaches zero. In the power amplifier circuit 1c according to Embodiment 3, a λ / 4 line (first phase adjustment circuit 117A) is provided on the first signal path R1 connected to the first amplifying element 111, and a λ / 4 line (second phase adjustment circuit 117B) is provided on the third signal path R3 connected to the third amplifying element 164. Therefore, both ends of the primary winding 141 of the transformer 140 of the first combining circuit 14A become short-circuited. At this time, since the impedance Z1 of the first amplifying element 111 is always large, the first amplifying element 111 becomes disconnected from the first signal path R1. In addition, since the impedance Z3 of the third amplifying element 164 is always large, the third amplifying element 164 becomes disconnected from the third signal path R3.

[0243] At this time, the primary voltage V applied to the primary winding 141 of the transformer 140 in the second synthesis circuit 14B is... 11 As shown in equation (15).

[0244] [Formula 15]

[0245] V 11 =2×V0…(15)

[0246] Therefore, the secondary voltage V applied to the secondary winding 142 of the transformer 140 in the second synthesis circuit 14B... 21 As shown in equation (16).

[0247] [Formula 16]

[0248] V 21 =m×V 11 =2×m×V0…(16)

[0249] Regarding the secondary current i flowing through the secondary winding 142 of the transformer 140 in the second synthesis circuit 14B 21 As in the first operation, the resistance value R of the load connected to the secondary winding 142 is the same. L As shown in equation (17).

[0250] [Formula 17]

[0251]

[0252] Therefore, during the second operation, the impedance Z2 of the second amplifying element 112 and the impedance Z4 of the fourth amplifying element 165 are as shown in equation (18).

[0253] [Formula 18]

[0254]

[0255] In summary, according to equations (14) and (18), the impedance Z2 of the second amplifying element 112 during the second operation becomes twice the impedance Z2 of the second amplifying element 112 during the first operation. Furthermore, according to equations (14) and (18), the impedance Z4 of the fourth amplifying element 165 during the second operation becomes twice the impedance Z4 of the fourth amplifying element 165 during the first operation. Therefore, compared to the first operation, the amplification efficiency of the power amplifier circuit 1c can be improved during the second operation. That is, according to the power amplifier circuit 1c of Embodiment 3, the decrease in amplification efficiency can be suppressed.

[0256] In the power amplifier circuit 1c according to Embodiment 3, the first phase adjustment circuit 117A is provided in the first signal path R1, but is not limited thereto. The first phase adjustment circuit 117A may also be provided in the second signal path R2, for example. That is, the second signal path R2 may also be a first specific signal path. Furthermore, in the power amplifier circuit 1c according to Embodiment 3, the second phase adjustment circuit 117B is provided in the third signal path R3, but is not limited thereto. The second phase adjustment circuit 117B may also be provided in the fourth signal path R4, for example. That is, the fourth signal path R4 may also be a second specific signal path.

[0257] (Implementation Method 4)

[0258] Reference Figure 10 The power amplifier circuit 1d and the high-frequency circuit 7d involved in Embodiment 4 will be described below. Regarding the power conversion circuit 1d and the high-frequency circuit 7d involved in Embodiment 4, the same structural elements as the power conversion circuit 1 and the high-frequency circuit 7 involved in Embodiment 1 will be marked with the same reference numerals and the description will be omitted.

[0259] like Figure 10 As shown, the high-frequency circuit 7d according to Embodiment 4 includes a power amplifier circuit 1d, a first power supply circuit 2, a second power supply circuit 3, and a filter circuit 4 (see reference). Figure 2 Furthermore, the first power supply circuit 2, the second power supply circuit 3, and the filter circuit 4 are the same as the first power supply circuit 2, the second power supply circuit 3, and the filter circuit 4 of the high-frequency circuit 7 involved in Embodiment 1 described above, and their descriptions are omitted here.

[0260] like Figure 10 As shown, the power amplifier circuit 1d according to Embodiment 4 includes an amplification section 12 of the drive stage (see reference). Figure 1 ), the final stage amplifier section 11d and the output matching circuit 15 (see reference) Figure 1 Furthermore, the amplification section 12 and output matching circuit 15 of the drive stage are the same as those of the power amplifier circuit 1 according to Embodiment 1 described above, and will not be described here.

[0261] The final stage amplification section 11d has a first amplifying element 111 and a second amplifying element 112. Additionally, the final stage amplification section 11d also has multiple (e.g., two) capacitors 113 and 114. Furthermore, the final stage amplification section 11d also has a phase adjustment circuit 117. The first amplifying element 111 and the second amplifying element 112 are, for example, npn-type bipolar transistors.

[0262] The first amplifying element 111 has a first base terminal, a first collector terminal, and a first emitter terminal. The first amplifying element 111 amplifies a first signal (high-frequency signal) input to the first base terminal to output a first amplified signal from the first collector terminal. The first emitter terminal is connected to ground. In other words, the first emitter terminal is directly or indirectly connected to ground. That is, the first emitter terminal is grounded (emitter grounded). The first collector terminal is connected to the first power supply circuit 2 via the ET terminal 101, thereby applying (providing) a first power supply voltage V1. Additionally, the first collector terminal is connected to the second connection point P2 via a capacitor 113. Furthermore, the first base terminal is connected to the first connection point P1.

[0263] The second amplifying element 112 has a second base terminal, a second collector terminal, and a second emitter terminal. The second amplifying element 112 amplifies the second signal (high-frequency signal) input to the second base terminal to output a second amplified signal from the second collector terminal. The second emitter terminal is connected to ground. In other words, the second emitter terminal is directly or indirectly connected to ground. That is, the second emitter terminal is grounded (emitter grounded). The second collector terminal is connected to the second power supply circuit 3 via the APT terminal 102, thereby applying (providing) a second power supply voltage V2. Additionally, the second collector terminal is connected to the second connection point P2 via the phase adjustment circuit 117 and the capacitor 114. Furthermore, the second base terminal is connected to the first connection point P1. That is, the first base terminal of the first amplifying element 111 and the second base terminal of the second amplifying element 112 are connected to each other at the first connection point P1. Furthermore, the second connection point P2 is the point connecting the first signal path R1 traversed by the first amplified signal output from the first amplifying element 111 and the second signal path R2 traversed by the second amplified signal output from the second amplifying element 112. In the power amplifier circuit 1d according to embodiment 4, the phase adjustment circuit 117 is provided in the second signal path R2, and the second signal path R2 is a specific signal path.

[0264] The phase adjustment circuit 117 includes, for example, a λ / 4 line. The phase adjustment circuit 117 adjusts the phase of the second amplified signal passing through the second signal path R2. More specifically, the phase adjustment circuit 117 lags the phase of the second amplified signal by 90°.

[0265] In the power amplifier circuit 1d according to Embodiment 4, the input signal input to the power amplifier circuit 1d is divided into a first signal and a second signal after passing through the first connection point P1. Therefore, the first signal and the second signal are the same signal. "The first signal and the second signal are the same" means that at least the phase of the first signal is the same as the phase of the second signal. In addition, "the phase of the first signal and the phase of the second signal are the same" includes not only the case where the phase of the first signal and the phase of the second signal are strictly the same, but also the case where the phase of the second signal converges within ±5% of the phase of the first signal.

[0266] In the power amplifier circuit 1d according to Embodiment 4, the first amplified signal passing through the first signal path R1 and the second amplified signal passing through the second signal path R2 are combined at the second connection point P2. In the power amplifier circuit 1d according to Embodiment 4, the second amplified signal output from the second amplifying element 112 passes through the phase adjustment circuit 117, thereby causing the phase of the second amplified signal to lag behind the phase of the first amplified signal by 90°.

[0267] In the power amplifier circuit 1d according to Embodiment 4, the impedance of the second amplifying element 112 during the second operation, in which only the second amplifying element 112 operates, can be made greater than the impedance of the second amplifying element 112 during the first operation, in which both the first amplifying element 111 and the second amplifying element 112 operate. Therefore, compared to the first operation, the amplification efficiency of the power amplifier circuit 1d can be improved during the second operation. That is, according to the power amplifier circuit 1d according to Embodiment 4, the decrease in amplification efficiency can be suppressed.

[0268] In the power amplifier circuit 1d according to embodiment 4, the phase adjustment circuit 117 is provided in the second signal path R2, but it is not limited thereto. The phase adjustment circuit 117 may also be provided in the first signal path R1, for example. That is, the first signal path R1 may be a specific signal path.

[0269] (Way)

[0270] The following methods are disclosed in this specification.

[0271] The power amplifier circuit (1; 1a to 1d) according to the first embodiment includes a multi-stage amplification section (10; 10a to 10d), an ET terminal (101), and an APT terminal (102). The multi-stage amplification section (10; 10a to 10d) includes a final stage amplification section (11; 11a to 11d). The final stage amplification section (11; 11a to 11d) has a first amplification element (111) and a second amplification element (112) connected in parallel with each other. The first amplification element (111) is connected to the ET terminal (101). The second amplification element (112) is connected to the APT terminal (102).

[0272] According to this method, higher speed operation of the power amplifier circuit (1; 1a to 1d) can be achieved.

[0273] According to the first method, in the power amplifier circuit (1; 1a to 1d) involved in the second method, the signal input to the ET terminal (101) is a signal that changes in a manner that follows the envelope of the high-frequency signal input to the first amplifying element (111). The signal input to the APT terminal (102) is a signal that changes in accordance with the average amplitude of the high-frequency signal detected according to a specified period (T1, T2, T3).

[0274] According to this method, higher speed operation of the power amplifier circuit (1; 1a to 1d) can be achieved.

[0275] According to the first method, in the power amplifier circuit (1; 1a to 1d) involved in the third method, a first power supply voltage (V1) is applied to the ET terminal (101), which changes in accordance with the amplitude of the high-frequency signal input to the first amplifying element (111). A second power supply voltage (V2) is applied to the APT terminal (102), which changes in accordance with the change in the amplitude of the high-frequency signal input to the second amplifying element (112) and at a frequency lower than that of the first power supply voltage (V1).

[0276] According to this method, higher speed operation of the power amplifier circuit (1; 1a to 1d) can be achieved.

[0277] According to any one of the first to third methods, in the power amplifier circuit (1; 1a) involved in the fourth method, the size of the first amplifying element (111) is smaller than the size of the second amplifying element (112).

[0278] According to this method, the responsiveness of the first amplifying element (111) is improved.

[0279] According to any one of the first to third methods, in the power amplifier circuit (1; 1a) involved in the fifth method, the size of the first amplifying element (111) is larger than the size of the second amplifying element (112).

[0280] According to this method, the power loss of the first amplifying element (111) can be minimized.

[0281] According to any one of the first to fifth embodiments, in the power amplifier circuit (1; 1a) involved in the sixth embodiment, the multi-stage amplification section (10; 10a) further includes a driver stage amplification section (12; 12a). The driver stage amplification section (12; 12a) is connected to the APT terminal (102).

[0282] According to this method, it is possible to achieve higher speed operation of the power amplifier circuit (1; 1a) while suppressing the decrease in responsiveness of the amplification section (12; 12a) of the drive stage.

[0283] According to any one of the first to sixth methods, in the power amplifier circuit (1; 1a) involved in the seventh method, the first amplifying element (111) and the second amplifying element (112) constitute a differential amplifier circuit (20; 20a).

[0284] According to this method, a differential amplifier circuit (20; 20a) can be implemented with a simple structure.

[0285] According to the seventh method, the power amplifier circuit (1) involved in the eighth method also includes a transformer (140). The transformer (140) is connected to the output terminal of the differential amplifier circuit (20).

[0286] This method enables high-frequency signals to have a wide bandwidth.

[0287] According to any one of the first to third methods, in the power amplifier circuit (1b, 1c, 1d) involved in the ninth method, when the power level of the first signal input to the first amplifying element (111) becomes above the reference power level, the first amplifying element (111) amplifies the first signal to output a first amplified signal. Regardless of the power level of the second signal input to the second amplifying element (112), the second amplifying element (112) amplifies the second signal to output a second amplified signal.

[0288] This method can improve amplification efficiency.

[0289] According to the ninth embodiment, the power amplifier circuit (1b) involved in the tenth embodiment further includes a demultiplexer (13), a combining circuit (14), and a phase adjustment circuit (117). The demultiplexer (13) divides the input signal into a first signal and a second signal with a phase different from that of the first signal. The combining circuit (14) includes a transformer (140) that combines the first amplified signal and the second amplified signal. The phase adjustment circuit (117) is located on a specific signal path and adjusts the phase of the signal passing through the specific signal path. The specific signal path is one of the first signal path (R1) through which the first amplified signal passes and the second signal path (R2) through which the second amplified signal passes. The first signal path (R1) and the second signal path (R2) are connected to each other via the combining circuit (14).

[0290] According to this method, the phase of the first amplified signal can be made opposite to the phase of the second amplified signal. As a result, even harmonics of the output signal can be eliminated, and the amplitude of the output signal can be amplified many times.

[0291] According to the ninth method, the power amplifier circuit (1c) involved in the eleventh method further comprises: a first splitter (13A), a second splitter (13B), a third amplifying element (164), a fourth amplifying element (165), a first combining circuit (14A), a second combining circuit (14B), a first phase adjustment circuit (117A), and a second phase adjustment circuit (117B). The first splitter (13A) divides the first input signal into a first signal and a third signal with a phase different from the first signal. The second splitter (13B) divides the second input signal into a second signal and a fourth signal with a phase different from the second signal. The third amplifying element (164) is connected in parallel with the first amplifying element (111) and amplifies the third signal to output a third amplified signal. The fourth amplifying element (165) is connected in parallel with the second amplifying element (112) and amplifies the fourth signal to output a fourth amplified signal. The first combining circuit (14A) includes a transformer (140) and combines the first amplified signal and the third amplified signal. The second synthesis circuit (14B) includes a transformer (140) that synthesizes the second amplified signal and the fourth amplified signal. A first phase adjustment circuit (117A) is located in a first specific signal path and adjusts the phase of the signal passing through that path. The first specific signal path is either the first signal path (R1) through which the first amplified signal passes or the second signal path (R2) through which the second amplified signal passes. The second phase adjustment circuit (117B) is located in the second specific signal path and adjusts the phase of the signal passing through that path. The second specific signal path is either the third signal path (R3) through which the third amplified signal passes or the fourth signal path (R4) through which the fourth amplified signal passes.

[0292] This method can further improve amplification efficiency.

[0293] According to the ninth embodiment, the power amplifier circuit (1d) involved in the twelfth embodiment further includes a phase adjustment circuit (117). The phase adjustment circuit (117) is located in a specific signal path and adjusts the phase of the signal passing through the specific signal path. The specific signal path is either the first signal path (R1) through which the first amplified signal passes or the second signal path (R2) through which the second amplified signal passes. The first signal and the second signal are the same signal. The first signal path (R1) and the second signal path (R2) are directly connected.

[0294] According to this method, signals can be amplified without using transformers, thus reducing the number of components.

[0295] The high-frequency circuit (7; 7a) involved in the thirteenth method includes: a power amplifier circuit (1; 1a to 1d) of any one of the first to twelfth methods; a first power supply circuit (2); and a second power supply circuit (3). The first power supply circuit (2) is connected to the ET terminal (101) and generates a first power supply voltage (V1), which changes in accordance with the amplitude of the high-frequency signal input to the first amplifying element (111). The second power supply circuit (3) is connected to the APT terminal (102) and generates a second power supply voltage (V2), which changes in accordance with the change in the amplitude of the high-frequency signal input to the second amplifying element (112) and changes at a frequency lower than the frequency of the first power supply voltage (V1).

[0296] According to this method, higher speed operation of the power amplifier circuit (1; 1a to 1d) can be achieved.

[0297] The communication device (8) involved in the fourteenth method includes the high-frequency circuit (7; 7a to 7d) and the signal processing circuit (5) of the thirteenth method. The signal processing circuit (5) processes the high-frequency signal and outputs it to the high-frequency circuit (7; 7a to 7d). The power amplifier circuit (1; 1a to 1d) of the high-frequency circuit (7; 7a to 7d) amplifies the high-frequency signal input from the signal processing circuit (5).

[0298] According to this method, higher speed operation of the power amplifier circuit (1; 1a to 1d) can be achieved.

[0299] Explanation of reference numerals in the attached figures

[0300] 1. 1a, 1b, 1c, 1d: Power amplifier circuit; 2: First power supply circuit; 3: Second power supply circuit; 4: Filter circuit; 5: Signal processing circuit; 6: Antenna; 7. 7a, 7b, 7c, 7d: High-frequency circuit; 8: Communication device; 10. 10a, 10b, 10c, 10d: Multi-stage amplification section; 11. 11a, 11b, 11c, 11d: Final stage amplification section; 12. 12a, 12c: Driver stage amplification section; 13: Demultiplexer; 13A: First demultiplexer; 13B: Second demultiplexer; 14: Synthesizer circuit ; 14A: First synthesizer circuit; 14B: Second synthesizer circuit; 15: Output matching circuit; 17: Demultiplexer; 20, 20a, 20b, 20c, 20d: Differential amplifier circuit; 51: RF signal processing circuit; 52: Baseband signal processing circuit; 71: Signal input terminal; 72: Antenna terminal; 101: ET terminal; 102: APT terminal; 111: First amplifying element; 112: Second amplifying element; 113, 114: Capacitors; 115, 116: Matching circuit; 117: Phase adjustment circuit; 117A: First Phase adjustment circuit; 117B: Second phase adjustment circuit; 118, 119, 120: Capacitors; 121: Amplifying element; 122: Capacitor; 123: Matching circuit; 124: Amplifying element; 125: Capacitor; 130: Transformer; 131: Primary winding; 132: Secondary winding; 133: Capacitor; 134, 135, 136, 137, 138: Capacitors; 140: Transformer; 141: Primary winding; 142: Secondary winding; 143, 144, 145, 146: Capacitors; 151, 152: Inductor; 153, 154: Capacitor; 161, 162, 163: Matching circuit; 164: Third amplifying element; 165: Fourth amplifying element; 171: Transformer; 172, 173: Capacitor; 174: Resistor; 1711: Primary winding; 1712: Secondary winding; M1, M2: Neutral point; P1, P2: Connection point; R1: First signal path; R2: Second signal path; R3: Third signal path; R4: Fourth signal path; V1: First power supply voltage; V2: Second power supply voltage; V3: Third power supply voltage.

Claims

1. A power amplifier circuit, comprising: A multi-stage amplification section, including the final stage amplification section; Envelope tracking terminal, i.e., ET terminal; and The average power tracking terminal is also known as the APT terminal. in, The final stage amplification section has a first amplification element and a second amplification element connected in parallel with each other. The first amplifying element is connected to the ET terminal. The second amplifying element is connected to the APT terminal. When the power level of the first signal input to the first amplifying element becomes above the reference power level, the first amplifying element amplifies the first signal to output a first amplified signal. Regardless of the power level of the second signal input to the second amplifying element, the second amplifying element amplifies the second signal to output a second amplified signal.

2. The power amplifier circuit according to claim 1, wherein, The signal input to the ET terminal is a signal that changes in a manner that follows the envelope of the high-frequency signal input to the first amplifying element. The signal input to the APT terminal is a signal that changes in accordance with the average amplitude of the high-frequency signal detected during a specified period.

3. The power amplifier circuit according to claim 1, wherein, A first power supply voltage is applied to the ET terminal, and the first power supply voltage changes accordingly with the amplitude of the high-frequency signal input to the first amplifying element. A second power supply voltage is applied to the APT terminal, and the second power supply voltage changes accordingly to the amplitude of the high-frequency signal input to the second amplifying element, and changes at a frequency lower than that of the first power supply voltage.

4. The power amplifier circuit according to any one of claims 1 to 3, wherein, The size of the first amplifying element is smaller than the size of the second amplifying element.

5. The power amplifier circuit according to any one of claims 1 to 3, wherein, The size of the first amplifying element is larger than the size of the second amplifying element.

6. The power amplifier circuit according to any one of claims 1 to 3, wherein, The multi-stage amplification section also includes a driver-stage amplification section. The amplification section of the drive stage is connected to the APT terminal.

7. The power amplifier circuit according to any one of claims 1 to 3, wherein, The first amplifying element and the second amplifying element constitute a differential amplifier circuit.

8. The power amplifier circuit according to claim 7, wherein, It also includes a transformer connected to the output terminal of the differential amplifier circuit.

9. The power amplifier circuit according to claim 1, wherein, It also has: A wavelength division multiplexer (WDM) divides an input signal into a first signal and a second signal whose phase differs from that of the first signal. A combining circuit, including a transformer, combines the first amplified signal and the second amplified signal; as well as A phase adjustment circuit is disposed in a specific signal path that is one of the signal paths traversed by the first amplified signal and the second amplified signal, and adjusts the phase of the signal passing through the specific signal path. The first signal path and the second signal path are connected to each other via the synthesis circuit.

10. The power amplifier circuit according to claim 1, wherein, It also has: A first wave divider divides a first input signal into the first signal and a third signal whose phase is different from that of the first signal; The second demultiplexer divides the second input signal into the second signal and a fourth signal whose phase is different from that of the second signal; The third amplifying element is connected in parallel with the first amplifying element to amplify the third signal and output the third amplified signal. A fourth amplifying element, which is connected in parallel with the second amplifying element, amplifies the fourth signal to output a fourth amplified signal; A first combining circuit includes a transformer to combine the first amplified signal and the third amplified signal; The second synthesis circuit includes a transformer, which synthesizes the second amplified signal and the fourth amplified signal; A first phase adjustment circuit is disposed in a first specific signal path, which is one of the signal paths of the first signal path through which the first amplified signal passes and the second signal path through which the second amplified signal passes, to adjust the phase of the signal passing through the first specific signal path. as well as The second phase adjustment circuit is disposed in a second specific signal path, which is one of the signal paths of the third signal path through which the third amplified signal passes and the fourth signal path through which the fourth amplified signal passes, and adjusts the phase of the signal passing through the second specific signal path.

11. The power amplifier circuit according to claim 1, wherein, It also includes a phase adjustment circuit, which is disposed in a specific signal path that is one of the signal paths traversed by the first amplified signal and the second amplified signal, and adjusts the phase of the signal passing through the specific signal path. The first signal and the second signal are the same signal. The first signal path is directly connected to the second signal path.

12. A high-frequency circuit, comprising: The power amplifier circuit according to any one of claims 1 to 11; A first power supply circuit, connected to the ET terminal, generates a first power supply voltage, which changes accordingly with the amplitude of the high-frequency signal input to the first amplifying element; and A second power supply circuit, connected to the APT terminal, generates a second power supply voltage that changes in response to the amplitude of the high-frequency signal input to the second amplifying element and at a frequency lower than that of the first power supply voltage.

13. A communication device comprising: The high-frequency circuit according to claim 12; and A signal processing circuit processes the high-frequency signal and outputs it to the high-frequency circuit. in, The power amplifier circuit of the high-frequency circuit amplifies the high-frequency signal input from the signal processing circuit.

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