A semiconductor structure and a method of fabricating the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate; forming a plurality of bit lines parallel to each other and extending along a first direction above the substrate, the first direction being parallel to the substrate plane; forming a plurality of word lines parallel to each other and extending along a second direction above the bit lines, the second direction being parallel to the substrate plane, and the projection of the second direction and the first direction on the substrate plane intersecting; forming a plurality of active pillars penetrating the word lines, the active pillars being perpendicular to the substrate plane, the sidewall of the active pillars being surrounded by the word lines, and the bottom of the active pillars being connected to the bit lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] With technological advancements, semiconductor devices are becoming increasingly smaller, constantly evolving towards miniaturization and higher integration. Dynamic random access memory (DRAM), as a semiconductor device that allows for high-speed, random data writing and reading, is widely used in data storage devices. However, the fabrication methods for DRAM still present many challenges that require improvement. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a plurality of mutually parallel bit lines extending along a first direction above the substrate, the first direction being parallel to a plane of the substrate; forming a plurality of mutually parallel word lines extending along a second direction above the bit lines, the second direction being parallel to a plane of the substrate, and the second direction intersecting the projection of the first direction onto the substrate; forming a plurality of active pillars penetrating the word lines, the active pillars being perpendicular to the plane of the substrate, the sidewalls of the active pillars being surrounded by the word lines, and the bottom of the active pillars being connected to the bit lines.

[0004] In some embodiments, forming a plurality of mutually parallel bit lines extending along a first direction above the substrate includes: depositing a first dielectric layer above the substrate; patterning the first dielectric layer to form a plurality of mutually parallel first trenches extending along the first direction; and forming the bit lines within the first trenches.

[0005] In some embodiments, forming multiple word lines that are parallel to each other and extend along a second direction above the bit lines includes: sequentially depositing a second dielectric layer, a word line material layer, and a third dielectric layer on the surfaces of the bit lines and the first dielectric layer; etching the third dielectric layer, the word line material layer, and the second dielectric layer from top to bottom to form multiple second trenches that are parallel to each other and extend along the second direction, wherein the patterned word line material layer constitutes the word lines; and filling the second trenches with a fourth dielectric layer.

[0006] In some embodiments, forming a plurality of active pillars penetrating the word lines includes: forming a plurality of vias penetrating the second dielectric layer, the word lines, and the third dielectric layer, the vias exposing the bit lines; forming a gate dielectric layer on the sidewalls of the vias; and filling the vias with an amorphous material layer to form an active pillar, the active pillar including a first electrode, a channel region, and a second electrode distributed from bottom to top, wherein the second dielectric layer surrounds the sidewalls of the first electrode, the word lines surround the sidewalls of the channel region, and the third dielectric layer surrounds the sidewalls of the second electrode.

[0007] In some embodiments, filling the via with an amorphous material layer to form an active pillar includes: depositing a first amorphous material layer covering the surface of the gate dielectric layer and the upper surface of the bit line, the first amorphous material layer having a first doping concentration; and depositing a second amorphous material layer covering the surface of the first amorphous material layer and filling the via, the second amorphous material layer having a second doping concentration, wherein the first doping concentration is greater than the second doping concentration.

[0008] In some embodiments, after forming a plurality of active posts through the word lines, the method further includes: forming an isolation layer on the surface of the third dielectric layer and a plurality of contact holes through the isolation layer, the contact holes exposing the upper surface of the second electrode; filling the contact holes with a conductive material to form contact plugs; and forming a storage element above the contact plugs, the storage element being electrically connected to the second electrode of the active posts through the contact plugs.

[0009] In some embodiments, forming an isolation layer and a plurality of contact holes through the isolation layer on the surface of the third dielectric layer includes: depositing the isolation layer on the surface of the third dielectric layer; patterning the isolation layer to form contact holes that expose the upper surface of the second electrode.

[0010] In some embodiments, forming an isolation layer and a plurality of contact holes through the isolation layer on the surface of the third dielectric layer includes: depositing a first isolation layer on the surface of the third dielectric layer; etching the first isolation layer along a first direction to form a plurality of first isolation barriers extending along the first direction, the first isolation barriers exposing the upper surface of the second electrode; depositing a sacrificial layer that fills the gaps between adjacent first isolation barriers; etching the sacrificial layer and the first isolation barriers along a second direction to form a plurality of wall-like structures extending along a second direction, the plurality of wall-like structures exposing the upper surface of the third dielectric layer; depositing a second isolation layer that fills the gaps between adjacent wall-like structures to form a plurality of second isolation barriers extending along the second direction, the first isolation barriers and the second isolation barriers intersecting each other to define a plurality of contact holes; and removing the sacrificial layer.

[0011] In some embodiments, after depositing the second isolation layer, the method further includes: performing a circular enlargement process on the contact hole.

[0012] In some embodiments, filling the contact hole with a conductive material to form a contact plug includes: depositing a first conductive material that covers the sidewall of the contact hole and the upper surface of the second electrode; and depositing a second conductive material that covers the surface of the first conductive material and fills the contact hole.

[0013] This disclosure also provides a semiconductor structure, including: a substrate, and a memory array region located on the substrate; the memory array region includes: bit lines, word lines, active pillars, and memory elements; a plurality of bit lines are parallel to each other and extend along a first direction, the first direction being parallel to the substrate plane; a plurality of word lines are parallel to each other and extend along a second direction, the word lines being located above the bit lines, the second direction being parallel to the substrate plane, and the second direction intersecting the projection of the first direction onto the substrate; an active pillar passes through the word lines, the active pillar is perpendicular to the substrate plane, the sidewall of the active pillar is surrounded by the word lines, the bottom of the active pillar is connected to the bit lines, and the active pillar comprises an amorphous material; a memory element is located above the active pillar, and the memory element is electrically connected to the top of the active pillar.

[0014] In some embodiments, the active pillar includes: a first amorphous material layer and a second amorphous material layer, the first amorphous material layer covering the side surface and bottom surface of the second amorphous material layer, the first amorphous material layer having a first doping concentration, and the second amorphous material layer having a second doping concentration; wherein the first doping concentration is greater than the second doping concentration.

[0015] In some embodiments, the active post includes a first electrode, a channel region, and a second electrode distributed from bottom to top, and the first electrode, the channel region, and the second electrode have the same conductivity type.

[0016] In some embodiments, the device further includes: a first dielectric layer, wherein the bit line is located within the first dielectric layer; a second dielectric layer, located above the first dielectric layer and surrounding the sidewall of the first electrode; a third dielectric layer, located above the word line and surrounding the sidewall of the second electrode; a fourth dielectric layer, located between any two adjacent word lines to isolate adjacent word lines; and a gate dielectric layer, located between the word line and the active post, wherein the gate dielectric layer surrounds the sidewall of the first electrode, the sidewall of the channel region, and the sidewall of the second electrode.

[0017] In some embodiments, the substrate includes a plurality of sequentially stacked memory array regions.

[0018] In some embodiments, the system further includes: a peripheral circuit region formed on the substrate surface, the memory array region formed on the peripheral circuit region, and the peripheral circuit region including peripheral devices and metal interconnects.

[0019] In this embodiment, bit lines are first fabricated above the substrate, word lines are formed above the bit lines, and then active pillars are formed through the word lines. This reduces bit line resistance and simplifies the fabrication process for word lines and bit lines. Subsequently, contact plugs and memory elements can be directly formed above the active pillars. Compared to the process of forming active pillars first and then word lines and bit lines, this significantly improves the integration density of the semiconductor structure, while also reducing the fabrication difficulty and height of contact plugs, and allowing for a shorter distance between the memory elements and the active pillars. Furthermore, using amorphous materials to fabricate the active pillars can reduce turn-off leakage current.

[0020] Details of one or more embodiments of this disclosure will be set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0023] Figures 2a to 2p This disclosure provides a schematic diagram of a semiconductor structure during its fabrication process.

[0024] Figures 3a to 3g This is a schematic diagram of the fabrication process of another semiconductor structure provided in this embodiment of the present disclosure;

[0025] Figure 4 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0026] Figure label:

[0027] 21-Substrate; 22-First dielectric layer; 23-Bit line; 231-First trench; 24-Second dielectric layer; 25-Word line; 251-Word line material layer; 26-Third dielectric layer; 27-Fourth dielectric layer; 271-Second trench; 28-Gate dielectric layer; 29-Amorphous material layer; 291-First amorphous material layer; 292-Second amorphous material layer; 30-Active pillar; 301-First electrode; 302-Channel region ; 303-Second electrode; 30'-Through hole; 31-Isolation layer; 311-First isolation layer; 3111-First isolation fence; 312-Second isolation layer; 3121-Second isolation fence; 32-Conductive material; 321-First conductive material; 322-Second conductive material; 33-Contact plug; 331-Contact hole; 34-Storage element; 35-Sacrificial layer; 351-Wall structure; 40-Storage array area. Detailed Implementation

[0028] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] Vertical gate-all-around (VGAA) devices offer advantages in miniaturization, high performance, and low power consumption, and are considered a key core technology for next-generation integrated circuits. Due to their greater integration freedom in the vertical direction, VGAA devices allow for increased design space for gates and source / drain components, reduced device area, easier vertical stacking of multi-layer devices, and further increased integration density through novel wiring methods. Therefore, they have become promising foundational devices for logic and memory chip manufacturing technologies such as CMOS and high-density DRAM.

[0035] However, the current fabrication process of vertical full-ring gate (VGAA) is complex, the structure occupies a large volume, and its size miniaturization and electrical performance still need to be improved.

[0036] Based on the above, in order to improve the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure, see attached figure. Figure 1 The preparation methods include:

[0037] Step 101: Provide a substrate;

[0038] Step 102: Form multiple parallel bit lines above the substrate that extend along a first direction, the first direction being parallel to the substrate plane;

[0039] Step 103: Form multiple word lines that are parallel to each other and extend along a second direction above the bit line. The second direction is parallel to the substrate plane and intersects with the projection of the first direction onto the substrate.

[0040] Step 104: Form multiple active pillars that penetrate word lines. The active pillars are perpendicular to the substrate plane, the sidewalls of the active pillars are surrounded by word lines, and the bottom of the active pillars are connected to the bit lines.

[0041] In this embodiment, bit lines are first fabricated above the substrate, word lines are formed above the bit lines, and then active pillars are formed through the word lines. This reduces bit line resistance and simplifies the fabrication process for word lines and bit lines. Subsequently, contact plugs and memory elements can be directly formed above the active pillars. Compared to the process of forming active pillars first and then word lines and bit lines, this significantly improves the integration density of the semiconductor structure, reduces the fabrication difficulty and height of contact plugs, and allows for a shorter distance between the memory elements and the active pillars. Furthermore, using amorphous materials to fabricate the active pillars can reduce turn-off leakage current.

[0042] Figures 2a-2pThis is a schematic diagram of a semiconductor structure during the fabrication process provided in this disclosure. The fabrication method of the semiconductor structure provided in this disclosure will be further described in detail below with reference to the accompanying drawings. In the detailed description of the embodiments of this disclosure, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the usual proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this application.

[0043] First, as attached Figure 2a As shown, step 101 is performed to provide a substrate 21. The substrate 21 may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate 21 is a silicon substrate, which may be doped or undoped. In other embodiments, the substrate 21 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate, and may also be a multilayer structure, such as Si / SiGe.

[0044] Next, as attached Figures 2b-2d As shown, in step 102, multiple parallel bit lines extending along a first direction are formed above the substrate 21. The first direction is parallel to the substrate plane.

[0045] In some embodiments, before forming a plurality of mutually parallel bit lines extending in a first direction above substrate 21, the method further includes forming a peripheral circuit region (not shown) on the surface of the substrate, the peripheral circuit region including peripheral devices and metal interconnects. Subsequent processes may form a memory array region above the peripheral circuit region. The peripheral circuit region may include peripheral circuitry, which may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array region. Peripheral devices may include one or more of page buffers, decoders (e.g., row decoders or column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). Subsequent processes of this disclosure are compatible with the process of forming the peripheral circuit region on the substrate, thus enabling the DRAM peripheral circuitry to be moved below the memory array region and the integration of stacked DRAM cells to further increase density.

[0046] In some embodiments, see Appendix Figures 2b-2dThe process involves forming multiple parallel bit lines extending along a first direction above a substrate 21, including: depositing a first dielectric layer 22 above the substrate 21; patterning the first dielectric layer 22 to form multiple parallel first trenches 231 extending along the first direction; and forming bit lines 23 within the first trenches 231. In this embodiment, forming the bit lines first effectively reduces the contact resistance of the bit lines and simplifies the bit line formation process. Compared to the process of forming active pillars first and then forming bit lines, the presence of active pillars makes the etching, film deposition, ion implantation, and heat treatment of metal silicide bit lines at the bottom of the active pillars more challenging, and the contact resistance between the formed bit lines and the active pillars is also higher.

[0047] For details, please see the appendix. Figure 2b First, a first dielectric layer 22 is deposited over the substrate. The material of the first dielectric layer includes, but is not limited to, oxides, nitrides, and oxynitrides. In some specific embodiments, the material of the first dielectric layer may be, for example, silicon oxide. The first dielectric layer 22 can be formed using processes such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). Optionally, after depositing the first dielectric layer 22 over the substrate, a planarization process, such as chemical mechanical polishing (CMP) and / or etching, can be used to planarize the upper surface of the first dielectric layer 22.

[0048] Next, see Appendix Figure 2c The first dielectric layer 22 is patterned to form a plurality of parallel first trenches 231 extending along a first direction. The patterning process includes, but is not limited to, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP). Here, the first trenches 231 can be formed by wet etching, dry etching, or a combination thereof.

[0049] Then, see appendix. Figure 2d A bit line 23 is formed within the first trench. The bit line 23 comprises a conductive material, including but not limited to tungsten, copper, titanium, tantalum, titanium nitride, tantalum nitride, metal silicide, metal alloy, or any combination thereof. The bit line 23 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering.

[0050] Then, as attached Figure 2e-2g As shown, in step 103, multiple parallel word lines extending along a second direction are formed above bit line 23, intersecting with the first direction. In practice, the second direction can be perpendicular to the first direction to further improve integration density.

[0051] In some embodiments, as shown in the appendix Figure 2e-2gAs shown, multiple parallel word lines extending along a second direction are formed above the bit line, including: sequentially depositing a second dielectric layer 24, a word line material layer 251, and a third dielectric layer 26 on the surface of the bit line 23 and the first dielectric layer; etching the third dielectric layer 26, the word line material layer 251, and the second dielectric layer 24 from top to bottom to form multiple parallel second trenches 271 extending along the second direction; the patterned word line material layer 251 constitutes the word line 25; and filling the second trenches 271 with a fourth dielectric layer 27. In this embodiment, the word lines are formed first, followed by the active pillars, which simplifies the word line formation process. Compared to the process of forming active pillars first and then the word lines, the presence of active pillars makes the etching and film deposition processes around them more challenging.

[0052] For details, please see the appendix. Figure 2e First, a second dielectric layer 24, a word line material layer 251, and a third dielectric layer 26 are sequentially deposited on the surfaces of bit line 23 and the first dielectric layer 22. The word line material layer 251 comprises a conductive material, including but not limited to tungsten, copper, titanium, tantalum, titanium nitride, tantalum nitride, metal silicides, metal alloys, or any combination thereof. The materials of the second dielectric layer 24 and the third dielectric layer 26 include, but are not limited to, oxides, nitrides, and oxynitrides. The second dielectric layer 24, the word line material layer 251, and the third dielectric layer 26 can be formed using one or more thin-film deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. Optionally, after sequentially depositing each film layer, a planarization process, such as chemical mechanical polishing (CMP) and / or etching, can be used to planarize the upper surface of each film layer.

[0053] Next, see Appendix Figure 2f The third dielectric layer 26, the word line material layer 251, and the second dielectric layer 24 are etched from top to bottom to form multiple parallel second trenches 271 extending along a second direction. The patterned word line material layer 251 constitutes the word line 25. Here, the etching process can be wet etching, dry etching, or a combination thereof. The etching process includes, but is not limited to, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).

[0054] Then, see appendix. Figure 2g A fourth dielectric layer 27 is filled within the second trench 271. The material of the fourth dielectric layer 27 includes, but is not limited to, oxides, nitrides, and oxynitrides, such as silicon oxide. The fourth dielectric layer 27 can be formed using one or more thin-film deposition processes, such as atomic layer deposition (ALD) and chemical vapor deposition (CVD). Optionally, after filling the second trench 271 with the fourth dielectric layer 27, a planarization process, such as chemical mechanical polishing (CMP) and / or etching, can be used to make the upper surface of the fourth dielectric layer 27 coplanar with the upper surface of the third dielectric layer 26.

[0055] In some embodiments, see Appendix Figure 2g The materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer can be the same.

[0056] Then, as attached Figure 2h-2k As shown, step 104 is performed to form multiple active pillars that penetrate word lines. The active pillars extend in a direction perpendicular to the substrate plane, the sidewalls of the active pillars are surrounded by word lines, and the bottom of the active pillars are connected to the bit lines.

[0057] In some embodiments, as shown in the appendix Figure 2h-2k As shown, a plurality of active pillars are formed through word lines, including: forming a plurality of vias 30' through the second dielectric layer 24, word lines 25 and third dielectric layer 26, the vias 30' exposing bit lines 23; forming a gate dielectric layer 28 on the sidewall of the vias 30'; filling the vias 30' with an amorphous material layer to form active pillars 30, the active pillars 30 including a first electrode 301, a channel region 302 and a second electrode 303 distributed from bottom to top, wherein the second dielectric layer 24 surrounds the sidewall of the first electrode 301, the word lines 25 surround the sidewall of the channel region 302 and the third dielectric layer 26 surrounds the sidewall of the second electrode 303.

[0058] Specifically, firstly, as shown in the attached document... Figure 2h As shown, multiple vias 30' are formed penetrating the second dielectric layer 24, word lines 25, and the third dielectric layer 26, exposing bit lines 23. These vias 30' can be formed by wet etching, dry etching, or a combination thereof.

[0059] Next, as attached Figure 2i As shown, a gate dielectric layer 28 is formed on the sidewall of the via 30'. The material of the gate dielectric layer 28 includes, but is not limited to, oxides, nitrides, oxynitrides, and other insulating materials. In some specific embodiments, the material of the gate dielectric layer can be one or a combination of alumina, silicon oxide, and silicon nitride.

[0060] Then, as attached Figure 2j and attached Figure 2kAs shown, an amorphous material layer 29 is filled within the via 30' to form an active pillar 30. The active pillar 30 includes a first electrode 301, a channel region 302, and a second electrode 303 distributed from bottom to top. A second dielectric layer 24 surrounds the sidewall of the first electrode 301, a word line 25 surrounds the sidewall of the channel region 302, and a third dielectric layer 25 surrounds the sidewall of the second electrode 303. Here, the first electrode 301, the channel region 302, and the second electrode 303 can be used as the first source / drain region, the channel region, and the second source / drain region of a transistor, respectively. Amorphous materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), or combinations thereof. In a specific embodiment, the material of the active pillar includes indium gallium zinc oxide (IGZO), which refers to an oxide containing In, Ga, and Zn as its main components, and may also contain metal elements other than In, Ga, and Zn. For example, it may also include one or more of tin (Sn), hafnium (Hf), zirconium (Zr), titanium (Ti), scandium (Sc), yttrium (Y), and lanthanides (e.g., cerium (Ce), neodymium (Nd), gadolinium (Gd)). Using amorphous materials to fabricate active pillars can effectively reduce turn-off leakage current and reduce overall leakage current. For example, IGZO-based thin-film transistors (IGZO TFTs) can maintain the current 64-millisecond refresh rate and possess extremely low It. OFF (<10 -22 (A / μm) represents a solution for reducing DRAM cell leakage. In practice, IGZO can be deposited using PEALD, and the precursors for IGZO include, but are not limited to, InO. x GaO x and ZnO x In this embodiment, word lines are first formed, then the word lines are etched to form through-holes, and active pillars of amorphous material are formed within the through-holes. Compared to depositing amorphous material, the process of etching amorphous material to form active pillars can solve the etching problems of amorphous material, thereby affecting the performance of the active pillars. Etching problems of amorphous materials include, for example, very high maintenance costs for the dry etching equipment body, peripheral gas supply system, chlorine-containing waste gas treatment, power consumption, etc., and problems such as short equipment lifespan due to particulate contamination; since wet etching is isotropic, there are problems such as mask biting (edge ​​biting). In some other embodiments, the material of the active pillars includes polycrystalline silicon.

[0061] In some embodiments, the first electrode, the channel region, and the second electrode have the same conductivity type. This forms a junction-less transistor, simplifying the fabrication process, reducing leakage current, and improving current drive capability.

[0062] In some embodiments, append Figure 2j and attached Figure 2kThe process involves filling the via with an amorphous material layer to form an active pillar, including: depositing a first amorphous material layer 291, which covers the surface of the gate dielectric layer 28 and the upper surface of the bit line 23, and has a first doping concentration; and depositing a second amorphous material layer 292, which covers the surface of the first amorphous material layer 291 and fills the via 30', and has a second doping concentration, wherein the first doping concentration is greater than the second doping concentration. This results in a Gaussian doping distribution with high sidewall concentration and low center concentration during subsequent high-temperature processes, achieving better junction-less electrical properties.

[0063] See appendix Figure 2j First, a first amorphous material layer 291 is deposited, which covers the surface of the gate dielectric layer 28 and the upper surface of the bit line. The first amorphous material layer has a first doping concentration.

[0064] Next, see Appendix Figure 2k A second amorphous material layer 292 is deposited, which covers the surface of the first amorphous material layer 291 and fills the via 30'. The second amorphous material layer 292 has a second doping concentration, wherein the first doping concentration is greater than the second doping concentration.

[0065] In some embodiments, see Appendix Figure 2l-2p After forming multiple active pillars with through-word lines, the method further includes: forming an isolation layer 31 and multiple contact holes 331 through the isolation layer 31 on the surface of the third dielectric layer 26, the contact holes 331 exposing the upper surface of the second electrode 303; filling the contact holes with conductive material 29 to form contact plugs 33; forming a storage element 34 above the contact plugs 33, the storage element being electrically connected to the second electrode 303 of the active pillar 30 through the contact plugs 34.

[0066] Specifically, first, see the appendix. Figure 2l and attached Figure 2m An isolation layer 31 and a plurality of contact holes 331 penetrating the isolation layer 31 are formed on the surface of the third dielectric layer 26, and the contact holes 331 expose the upper surface of the active post 30.

[0067] In some embodiments, see Appendix Figure 2l and attached Figure 2m An isolation layer and multiple contact holes penetrating the isolation layer are formed on the surface of the third dielectric layer, including: depositing an isolation layer 31 on the surface of the third dielectric layer 26; and depositing an isolation layer on the surface of the third dielectric layer.

[0068] See appendix Figure 2lFirst, an isolation layer 31 is deposited on the surface of the third dielectric layer 26. The isolation layer includes, but is not limited to, oxides, nitrides, oxynitrides, etc., and may be, for example, silicon nitride. In some embodiments, the isolation layer 31 is made of the same material as the third dielectric layer 26.

[0069] Next, see Appendix Figure 2m A patterned isolation layer 31 forms contact holes 331, which expose the upper surface of the active pillar 30. The contact holes 331 can be formed by wet etching, dry etching, or a combination thereof. In practice, a mask layer can be formed above the isolation layer, and a photoresist layer (PR) can be formed above the mask layer. The photoresist layer is patterned to expose the mask layer, and the mask layer and isolation layer are etched using the patterned photoresist layer as a mask. Here, the mask layer can be a hard mask. The patterning process of the photoresist layer specifically involves steps such as exposure, development, and resist stripping to pattern the photoresist layer.

[0070] It should be understood that the above is one embodiment of forming the isolation layer 31 and a plurality of contact holes 331 penetrating the isolation layer 31. The contact holes are formed by first depositing the isolation layer and then patterning the isolation layer. Thus, the shape of the contact holes can be controlled through the patterning process. It should be understood that the embodiment of forming the isolation layer 31 and the plurality of contact holes 331 penetrating the isolation layer 31 is not limited to this. For other embodiments, see the appendix. Figures 3a-3g The method involves forming an isolation layer and multiple contact holes penetrating the isolation layer on the surface of a third dielectric layer, including: depositing a first isolation layer 311 on the surface of the third dielectric layer; etching the first isolation layer 311 along a first direction to form multiple first isolation barriers 3111 extending along the first direction, the first isolation barriers 3111 exposing the upper surface of the second electrode 303; depositing a sacrificial layer 35, the sacrificial layer 35 filling the gaps between adjacent first isolation barriers 3111; etching the sacrificial layer 35 and the first isolation barriers 3111 along a second direction to form multiple wall-like structures 351 extending along the second direction, the multiple wall-like structures 351 exposing the upper surface of the third dielectric layer 26; depositing a second isolation layer 312, the second isolation layer 312 filling the gaps between adjacent wall-like structures 351 to form multiple second isolation barriers 3121 extending along the second direction, the first isolation barriers 3111 and the second isolation barriers 3121 intersecting each other to define multiple contact holes 331; and removing the sacrificial layer. Thus, by using alternating isolation barriers to form contact holes, the number of photomasks can be saved by utilizing the photomasks used to form bit lines and word lines in the preceding process. It should be understood that in other embodiments, multiple layers can be stacked on the isolation layer, and then patterned twice in different directions to transfer the hole-like pattern at the intersection to the isolation layer to be etched, ultimately forming the contact hole.

[0071] For details, please refer to the appendix first. Figure 3aA first isolation layer 311 is deposited on the surface of the third dielectric layer 26. The first isolation layer 311 includes, but is not limited to, oxides, nitrides, oxynitrides, etc., and may be silicon nitride, for example.

[0072] Then, see appendix. Figure 3b The first isolation layer 311 is etched along a first direction to form a plurality of first isolation barriers 3111 extending along the first direction, with the first isolation barriers 3111 exposing the upper surface of the second electrode 303. Here, the first isolation layer 311 can be etched by wet etching, dry etching, or a combination thereof. It should be understood that the first isolation layer 311 can be etched along a second direction to form a plurality of first isolation barriers 3111 extending along the second direction, with the second isolation barriers 3111 exposing the upper surface of the active post 30.

[0073] Next, as attached Figure 3c As shown, a sacrificial layer 35 is deposited, filling the gaps between adjacent first isolation barriers 3111. The formation process of the sacrificial layer 35 includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof. In one specific embodiment, the sacrificial layer 35 is formed by spin-on dielectric (SOD) technology. The material of the sacrificial layer 35 includes, but is not limited to, oxides, such as silicon oxide.

[0074] Next, see the appendix. Figure 3d The sacrificial layer 35 and the first isolation barrier 3111 are etched along the second direction to form a plurality of wall-like structures 351 extending along the second direction, and the plurality of wall-like structures 351 expose the upper surface of the third dielectric layer 26.

[0075] Next, see Appendix Figure 3e and attached Figure 3f A second isolation layer 312 is deposited, filling the gaps between adjacent wall-like structures 251 to form a plurality of second isolation fences 3121 extending along a second direction. The first isolation fences 3111 and the second isolation fences 3121 intersect to define a plurality of contact holes 331. The second isolation layer 312 includes, but is not limited to, oxides, nitrides, oxynitrides, etc., for example, silicon nitride. In practice, the materials of the first isolation layer 311 and the second isolation layer 312 can be the same.

[0076] Then, see appendix. Figure 3f Remove the sacrificial layer 35.

[0077] In some embodiments, see Appendix Figure 3gAfter depositing the second isolation layer, the method further includes: circularizing and enlarging the contact holes. In practice, a mask layer with multiple discrete patterned holes can be deposited above the second isolation layer, each patterned hole corresponding one-to-one with a contact hole, transferring the patterned holes into the isolation layer. This makes the contact holes circular, elliptical, or other shapes with sharp corners removed, preventing charge concentration at the corners from causing leakage. Here, circularizing and enlarging can be performed using wet etching or dry etching. In other embodiments, the circularizing and enlarging process can simultaneously remove the sacrificial layer within the contact holes.

[0078] Next, see Appendix Figure 2n and attached Figure 2o Conductive material 32 is filled into the contact hole 331 to form a contact plug 33.

[0079] In some embodiments, as shown in the appendix Figure 2n and attached Figure 2o The process of filling the contact hole with conductive material 32 to form a contact plug 33 includes: depositing a first conductive material 321, which covers the sidewall of the contact hole 331 and the upper surface of the second electrode 303; and depositing a second conductive material 322, which covers the surface of the first conductive material 321 and fills the contact hole 331. In this embodiment, the memory element is subsequently formed directly above the contact plug, eliminating the need for a metal redistribution layer. This effectively reduces the fabrication height of the contact plug, decreases the difficulty of subsequent processes, and shortens the distance between the memory element and the second electrode of the active post.

[0080] Specifically, first, see the appendix. Figure 2n A first conductive material 321 is deposited, which covers the sidewall of the contact hole 331 and the upper surface of the second electrode 303. In actual operation, the first conductive material 321 is electrically connected to the second electrode 303 of the active post 30.

[0081] Next, see Appendix Figure 2o A second conductive material 322 is deposited, which covers the surface of the first conductive material 321 and fills the contact hole 331.

[0082] The first conductive material 321 and the second conductive material 322 can be formed using processes such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, and sputtering. The first conductive material 321 and the second conductive material 322 include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. In one specific embodiment, the first conductive material is titanium (Ti) or titanium nitride (TiN), and the second conductive material is tungsten (W).

[0083] Finally, see appendix. Figure 2p A storage element 34 is formed above the contact plug 331, and the storage element 34 is electrically connected to the second electrode 303 of the active post 30 via the contact plug 331. The storage element 34 includes, for example, a storage capacitor. The storage capacitor can be formed using semiconductor processes. The storage capacitor further includes a lower electrode plate (not shown), a capacitor dielectric layer (not shown), and an upper electrode plate (not shown). The lower electrode plate is electrically connected to the second electrode 303 of the active post 30, and the capacitor dielectric layer and the upper electrode plate are sequentially formed on the lower electrode plate. In practical operation, the storage capacitor can be a double-sided capacitor, that is, the capacitor dielectric layer and the upper electrode plate are sequentially formed on two opposite surfaces of the lower electrode plate, thereby forming two capacitors on both sides of the lower electrode plate, which is beneficial to increasing the capacitance value of the storage capacitor. The capacitor dielectric layer can be formed using a high-k dielectric material, such as alumina (Al2O3) or zirconium oxide (ZrO).

[0084] This disclosure also provides a semiconductor structure, see appendix. Figure 2pThe system includes: a substrate 21 and a memory array region 40 located on the substrate 21; the memory array region 40 includes: bit lines 23, word lines 25, active pillars 30, and memory elements 34; multiple bit lines 23 are parallel to each other and extend along a first direction, which is parallel to the plane of the substrate 21; multiple word lines 25 are parallel to each other and extend along a second direction, with the word lines 25 located above the bit lines 23, the second direction being parallel to the plane of the substrate and intersecting the projection of the first direction onto the substrate; active pillars 30 penetrate the word lines 25, are perpendicular to the plane of the substrate 21, have sidewalls surrounded by word lines 25, and have bottoms connected to the bit lines 23; the active pillars 30 are made of amorphous material; and memory elements 34 are located above the active pillars 30 and are electrically connected to the top of the active pillars 30. In actual operation, the second direction can be perpendicular to the first direction to further improve integration density. Here, amorphous materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), or combinations thereof. In one specific embodiment, the active pillar material includes indium gallium zinc oxide (IGZO), which refers to an oxide containing In, Ga, and Zn as its main components, and may also contain metal elements other than In, Ga, and Zn. For example, it may also include one or more of tin (Sn), hafnium (Hf), zirconium (Zr), titanium (Ti), scandium (Sc), yttrium (Y), and lanthanides (e.g., cerium (Ce), neodymium (Nd), gadolinium (Gd)). Using amorphous materials to fabricate active pillars can effectively reduce turn-off leakage current. For example, IGZO-based thin-film transistors (IGZO TFTs) can maintain a refresh time of 64 milliseconds and have extremely low Ig. OFF (<10 -22 A / μm represents a solution for reducing DRAM cell leakage.

[0085] In some embodiments, see Appendix Figure 2p The active pillar includes a first amorphous material layer 291 and a second amorphous material layer 292. The first amorphous material layer 291 covers the sides and bottom of the second amorphous material layer 292. The first amorphous material layer 291 has a first doping concentration, and the second amorphous material layer 292 has a second doping concentration; wherein the first doping concentration is greater than the second doping concentration. In this way, a Gaussian doping distribution will be formed in the subsequent high-temperature process, with a high concentration on the sidewalls and a low concentration in the middle, achieving better junction-less electrical properties.

[0086] In some embodiments, see Appendix Figure 2pThe active pillar 30 includes a first electrode 301, a channel region 302, and a second electrode 303 distributed from bottom to top, and the first electrode 301, the channel region 302, and the second electrode 303 have the same conductivity type. In this way, a junction-less transistor is formed, which simplifies the fabrication process, reduces leakage current, and improves current drive capability.

[0087] In some embodiments, see Appendix Figure 2p The semiconductor structure also includes: a first dielectric layer 22 (see Appendix) Figure 2g Bit line 23 is located within the first dielectric layer 22; the second dielectric layer 24 (see Appendix) Figure 2g The third dielectric layer 26 (see Appendix) is located above the first dielectric layer 22 and surrounds the sidewall of the first electrode 301; Figure 2g ), located above the word line and surrounding the sidewall of the second pole 303; fourth dielectric layer 27 (see appendix) Figure 2g ), located between any two adjacent word lines 25 to isolate adjacent word lines 25; gate dielectric layer 28, located between word lines 25 and active pillars 30, and gate dielectric layer 28 surrounds the sidewall of the first pole 301, the sidewall of the channel region 302 and the sidewall of the second pole 303.

[0088] In some embodiments, see Appendix Figure 4 The substrate 21 includes a plurality of sequentially stacked memory array regions 40. For example, attached... Figure 4 The semiconductor structure shown consists of two memory array regions 40 stacked on a substrate. In other embodiments, the substrate 21 may include three or more sequentially stacked memory array regions 40. This can further improve storage density and space utilization.

[0089] In some embodiments, the semiconductor structure further includes: a peripheral circuit region (not shown) formed on the substrate surface, and a memory array region formed on the peripheral circuit region. The peripheral circuit region includes peripheral devices and metal interconnects. The peripheral circuit region may include peripheral circuitry, which may include any suitable digital, analog, and / or mixed-signal circuitry to facilitate the operation of the memory array region. Peripheral devices may include one or more of page buffers, decoders (e.g., row decoders or column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of circuitry (e.g., transistors, diodes, resistors, or capacitors). This allows the peripheral circuit region to be moved below the memory array region, reducing the interconnect paths between the peripheral circuit region and the memory array region, while further increasing density.

[0090] In summary, the embodiments of this disclosure first fabricate bit lines above the substrate, then form word lines above the bit lines, and finally form active pillars that penetrate the word lines. This reduces bit line resistance and simplifies the fabrication process for word lines and bit lines. Subsequently, contact plugs and memory elements can be directly formed above the active pillars. Compared to the process of forming active pillars first and then word lines and bit lines, this significantly improves the integration density of the semiconductor structure, reduces the fabrication difficulty and height of contact plugs, and allows for a shorter distance between the memory elements and the active pillars. Furthermore, using amorphous materials to fabricate the active pillars can reduce turn-off leakage current.

[0091] The semiconductor structure provided in this disclosure can be applied to memory structures, including but not limited to three-dimensional dynamic random access memory (3D DRAM).

[0092] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0093] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; Forming multiple parallel bit lines extending along a first direction above the substrate includes: depositing a first dielectric layer above the substrate; patterning the first dielectric layer to form multiple parallel first trenches extending along the first direction; forming the bit lines within the first trenches; the first direction being parallel to the substrate plane. Forming multiple parallel word lines extending along a second direction above the bit lines includes: sequentially depositing a second dielectric layer, a word line material layer, and a third dielectric layer on the surfaces of the bit lines and the first dielectric layer; etching the third dielectric layer, the word line material layer, and the second dielectric layer from top to bottom to form multiple parallel second trenches extending along the second direction; the patterned word line material layer constitutes the word lines; filling the second trenches with a fourth dielectric layer; the second direction is parallel to the substrate plane, and the second direction intersects the projection of the first direction onto the substrate; Forming multiple active pillars penetrating the word lines, the active pillars being perpendicular to the substrate plane, the sidewalls of the active pillars being surrounded by the word lines, and the bottom of the active pillars being connected to the bit lines; comprising: forming multiple vias penetrating the second dielectric layer, the word lines, and the third dielectric layer, the vias exposing the bit lines; forming a gate dielectric layer on the sidewalls of the vias; filling the vias with an amorphous material layer to form the active pillars, the active pillars comprising a first electrode, a channel region, and a second electrode distributed from bottom to top, wherein the second dielectric layer surrounds the sidewalls of the first electrode, the word lines surround the sidewalls of the channel region, and the third dielectric layer surrounds the sidewalls of the second electrode; The method of filling the via with an amorphous material layer to form an active pillar includes: depositing a first amorphous material layer, the first amorphous material layer covering the surface of the gate dielectric layer and the upper surface of the bit line, the first amorphous material layer having a first doping concentration; and depositing a second amorphous material layer, the second amorphous material layer covering the surface of the first amorphous material layer and filling the via, the second amorphous material layer having a second doping concentration, wherein the first doping concentration is greater than the second doping concentration.

2. The preparation method according to claim 1, characterized in that, After forming multiple active pillars that run through the word lines, the method further includes: An isolation layer and a plurality of contact holes are formed on the surface of the third dielectric layer, the contact holes exposing the upper surface of the second electrode; The contact hole is filled with conductive material to form a contact plug; A storage element is formed above the contact plug, and the storage element is electrically connected to the second pole of the active post through the contact plug.

3. The preparation method according to claim 2, characterized in that, An isolation layer and a plurality of contact holes penetrating the isolation layer are formed on the surface of the third dielectric layer, including: An isolation layer is deposited on the surface of the third dielectric layer; The isolation layer is patterned to form contact holes that expose the upper surface of the second electrode.

4. The preparation method according to claim 2, characterized in that, An isolation layer and a plurality of contact holes penetrating the isolation layer are formed on the surface of the third dielectric layer, including: A first isolation layer is deposited on the surface of the third dielectric layer; The first isolation layer is etched along the first direction to form a plurality of first isolation fences extending along the first direction, the first isolation fences exposing the upper surface of the second pole; A sacrificial layer is deposited, which fills the gaps between adjacent first isolation fences; The sacrificial layer and the first isolation barrier are etched along the second direction to form a plurality of wall-like structures extending along the second direction, the plurality of wall-like structures exposing the upper surface of the third dielectric layer; A second isolation layer is deposited, which fills the gaps between adjacent wall-like structures to form a plurality of second isolation fences extending along a second direction, wherein the first isolation fences and the second isolation fences intersect each other to define a plurality of contact holes; Remove the sacrificial layer.

5. The preparation method according to claim 4, characterized in that, After depositing the second isolation layer, the method further includes: The contact hole is rounded and enlarged.

6. The preparation method according to claim 2, characterized in that, Filling the contact hole with conductive material to form a contact plug includes: A first conductive material is deposited, which covers the sidewalls of the contact hole and the upper surface of the second electrode; A second conductive material is deposited, which covers the surface of the first conductive material and fills the contact hole.

7. A semiconductor structure, characterized in that, include: Substrate, and storage array region located on the substrate; The storage array area includes: bit lines, word lines, active pillars, and storage elements; The plurality of bit lines are parallel to each other and extend along a first direction, the first direction being parallel to the substrate plane; The word lines are parallel to each other and extend along a second direction, the word lines are located above the bit lines, the second direction is parallel to the substrate plane, and the second direction intersects the projection of the first direction onto the substrate; The active pillar extends through the word line, is perpendicular to the substrate plane, has its sidewalls surrounded by the word line, and its bottom is connected to the bit line. The active pillar is made of amorphous material. A storage element is located above the active post, and the storage element is electrically connected to the top of the active post; The active column includes: A first amorphous material layer and a second amorphous material layer, wherein the first amorphous material layer covers the side surface and bottom surface of the second amorphous material layer, the first amorphous material layer has a first doping concentration, and the second amorphous material layer has a second doping concentration; wherein the first doping concentration is greater than the second doping concentration.

8. The semiconductor structure according to claim 7, characterized in that, The active post includes a first electrode, a channel region, and a second electrode distributed from bottom to top, and the first electrode, the channel region, and the second electrode have the same conductivity type.

9. The semiconductor structure according to claim 8, characterized in that, Also includes: A first dielectric layer, wherein the bit line is located within the first dielectric layer; The second dielectric layer is located above the first dielectric layer and surrounds the sidewall of the first electrode; A third dielectric layer is located above the word line and surrounds the sidewall of the second pole; A fourth dielectric layer is located between any two adjacent word lines to isolate adjacent word lines; A gate dielectric layer is located between the word line and the active post, and the gate dielectric layer surrounds the sidewall of the first electrode, the sidewall of the channel region, and the sidewall of the second electrode.

10. The semiconductor structure according to claim 7, characterized in that, The substrate includes a plurality of storage array regions stacked sequentially.

11. The semiconductor structure according to claim 7, characterized in that, Also includes: A peripheral circuit region is formed on the surface of the substrate, and a memory array region is formed on the peripheral circuit region. The peripheral circuit region includes peripheral devices and metal interconnects.

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