Anti-fuse array structure, programming method, reading method, and memory

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a kind of anti-fuse array structure, programming method, reading method and memory, comprising: substrate and the multiple anti-fuse cell structures of array arrangement formed on substrate;Each anti-fuse cell structure includes: first selection transistor and first anti-fuse device, first selection transistor is connected bit line by first doped region, first selection transistor and first anti-fuse device share second doped region, first doped region and second doped region are arranged at the opposite sides of first selection transistor gate;In the first direction, the first anti-fuse device of same row anti-fuse cell structure is connected with the same first programming wire, and the first selection transistor of the same row first anti-fuse cell structure is connected with the same first word line;In the second direction, the first doped region of same column anti-fuse cell structure is connected with the same bit line;And the first word line of at least N row anti-fuse cell structure is connected, to simplify the control end of anti-fuse array structure.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and in particular to an antifuse array structure, programming method, reading method, and memory. Background Technology

[0002] An anti-fuse is a one-time programmable device (OTP) widely used in memories such as Dynamic Random Access Memory (DRAM). An anti-fuse is a semiconductor device consisting of two conductive layers and a dielectric layer between them. When unprogrammed, the two conductive layers are separated by the dielectric layer, and the antifuse is open. During programming, an applied high voltage causes the dielectric layer to break down, creating an electrical connection between the two conductive layers, short-circuiting or blowing the antifuse. This blowing process is physically one-time, permanent, and irreversible. The open and blown states of the antifuse can represent the logic value "0" and the logic value "1," respectively.

[0003] An antifuse structure typically includes multiple antifuse units. Each antifuse unit usually includes a select transistor and an antifuse device. For example, when each antifuse unit has one select transistor and one antifuse transistor, the antifuse transistor and the select transistor are connected in series. However, controlling an antifuse unit requires the gate of the antifuse transistor, the gate of the select transistor, and the source of the select transistor to simultaneously meet the set requirements. Therefore, the control method of the antifuse unit is relatively complex, which is not conducive to the popularization and application of antifuse structures. Summary of the Invention

[0004] This disclosure provides an antifuse array structure, programming method, reading method, and memory to simplify the control terminal of the antifuse array structure.

[0005] One embodiment of this disclosure provides an antifuse array structure, including: a substrate, and a plurality of antifuse unit structures formed on the substrate, the plurality of antifuse unit structures being arranged in an array; each antifuse unit structure includes: a first selection transistor and a first antifuse device, wherein the first selection transistor is connected to a bit line through a first doped region, the first selection transistor and the first antifuse device share a second doped region, the first doped region and the second doped region are disposed on opposite sides of the gate of the first selection transistor; in a first direction, the first antifuse devices of the same row of antifuse unit structures are connected to the same first programming wire, and the first selection transistors of the same row of first antifuse unit structures are connected to the same first word line; in a second direction, the first doped regions of the same column of antifuse unit structures are connected to the same bit line; and the first word lines of at least N rows of antifuse unit structures are connected, where N is an integer greater than or equal to 2.

[0006] In some embodiments, the first word lines of every N rows of antifuse unit structures are connected, and N is an even number.

[0007] In some embodiments, the first word lines of all rows of the antifuse cell structure are connected.

[0008] In some embodiments, the gate of the first select transistor is connected to the first word line, and the gate of the first antifuse device is connected to the first programming wire.

[0009] In some embodiments, the first doped region includes either the source or the drain of the first select transistor, and the second doped region includes the other of the source or the drain of the first select transistor.

[0010] In some embodiments, the antifuse cell structure further includes: a second selection transistor and a second antifuse device, wherein the second selection transistor is connected to a bit line through a first doped region, the first selection transistor and the second selection transistor share the first doped region, and the second selection transistor and the second antifuse device share a third doped region; in a first direction, the second antifuse devices of the same row of antifuse cell structures are connected to a second programming wire, and the second selection transistors of the same row of antifuse cell structures are connected to a second word line; in a second direction, the second word lines of at least M rows of antifuse cell structures are connected together, where M is an integer greater than or equal to 2.

[0011] In some embodiments, the second word lines of each M rows of antifuse unit structures are connected, and M is an even number.

[0012] In some embodiments, at least one first character line is connected to at least one second character line.

[0013] In some embodiments, all first word lines of a row are connected to all second word lines of a row.

[0014] In some embodiments, the first selection transistor and the second selection transistor are arranged in a centrally symmetrical manner, and the first antifuse device and the second antifuse device are arranged in a centrally symmetrical manner.

[0015] In some embodiments, the gate of the first select transistor is connected to the first word line, and the gate of the first antifuse device is connected to the first programming wire; the gate of the second select transistor is connected to the second word line, and the gate of the second antifuse device is connected to the second programming wire.

[0016] In some embodiments, the first doped region includes one of the source or drain of the first select transistor and one of the source or drain of the second select transistor, the second doped region includes the other of the source or drain of the first select transistor, and the third doped region includes the other of the source or drain of the second select transistor.

[0017] Another embodiment of this disclosure also provides a programming method, employing an antifuse array structure according to any one of the above embodiments, comprising: obtaining a target antifuse device to be programmed in the antifuse array structure, and a word line, programming wire, and bit line corresponding to the target antifuse device; applying an enable voltage to the word line corresponding to the target antifuse device to turn on the select transistor corresponding to the target antifuse device; applying a programming voltage to the programming wire corresponding to the target antifuse device; and applying a zero voltage to the bit line corresponding to the target antifuse device, wherein the programming voltage is greater than the breakdown voltage of the target antifuse device.

[0018] Another embodiment of this disclosure also provides a reading method, employing an antifuse array structure according to any one of the above embodiments, comprising: acquiring the target antifuse device to be read in the antifuse array structure, and the word line, programming wire, and bit line corresponding to the target antifuse device; applying a turn-on voltage to the word line corresponding to the target antifuse device to turn on the selection transistor corresponding to the target antifuse device; applying a read voltage to the programming wire corresponding to the target antifuse device; applying zero voltage to the bit line corresponding to the target antifuse device, wherein the read voltage is less than the breakdown voltage of the target antifuse device; reading the current flowing through the target antifuse device; and determining the stored data of the target antifuse device based on the magnitude of the current.

[0019] Another embodiment of this disclosure also provides a memory including at least one antifuse array structure of any of the above embodiments.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: an antifuse array structure is formed by arranging antifuse unit structures in an array, wherein the antifuse unit structure includes a first selection transistor and a first antifuse device connected in series. In the first direction, all first antifuse devices share the same first programming wire, and all first selection transistors share the same first word line. In the second direction, the first doped regions of all first selection transistors share the same bit line, and the first word lines of at least two rows of antifuse unit structures are connected. That is, at least two rows of first selection transistors can share a first word line control terminal, thereby reducing the control terminals of the antifuse array structure and reducing the timing complexity of the antifuse array structure programming process.

[0021] Furthermore, each antifuse cell structure may include a first selection transistor and a first antifuse device connected in series, as well as a second selection transistor and a second antifuse device connected in series. Thus, each antifuse cell structure includes two sets of selection transistors and antifuse devices, improving the integration density of the antifuse array structure and the control capability of the antifuse cell structure. Specifically, the first word lines of at least two rows of antifuse cell structures are connected, and the second word lines of at least two rows of antifuse cell structures are connected. That is, at least two rows of first selection transistors can share a first word line control terminal, and at least two rows of second selection transistors can share a second word line control terminal. This reduces the number of control terminals for the antifuse array structure by at least two word lines, thereby reducing the timing complexity of the antifuse array structure programming process. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of an antifuse unit structure provided in an embodiment of the present disclosure;

[0024] Figure 2 and Figure 3 This is a schematic diagram of an antifuse array structure formed by an antifuse unit structure according to an embodiment of the present disclosure;

[0025] Figure 4 This is a schematic diagram of another antifuse unit structure provided in an embodiment of the present disclosure;

[0026] Figure 5 and Figure 6 This is a schematic diagram of an antifuse array structure formed by another antifuse unit structure provided in the embodiments of this disclosure. Detailed Implementation

[0027] Current antifuse array structures suffer from numerous control ports and complex control methods.

[0028] One embodiment of this disclosure provides an antifuse array structure to reduce the number of control terminals in the antifuse array structure and reduce the timing complexity of the antifuse array structure programming process.

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Figure 1 This is a schematic diagram of an antifuse unit structure provided in an embodiment of the present disclosure. Figure 2 and Figure 3 This is a schematic diagram of an antifuse array structure formed by an antifuse unit structure according to an embodiment of the present disclosure. Figure 4 This is a schematic diagram of another antifuse unit structure provided in an embodiment of the present disclosure. Figure 5 and Figure 6 This is a schematic diagram of an antifuse array structure formed by another antifuse unit structure provided in an embodiment of this disclosure. The antifuse array structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0031] refer to Figure 1 and Figure 2 An antifuse array structure includes: a substrate (not shown in the figure), and a plurality of antifuse unit structures 10 formed on the substrate, the plurality of antifuse unit structures 10 being arranged in an array; each antifuse unit structure 10 includes: a first selection transistor 100 and a first antifuse device 200, wherein the first selection transistor 100 is connected to a bit line BL through a first doped region 101, the first selection transistor 100 and the first antifuse device 200 share a second doped region 102, and the first doped region 101 and the second doped region 102 are disposed in... The first selection transistor 100 has its gate 110 on opposite sides; in the first direction X, the first antifuse devices 200 of the same row of antifuse unit structures 10 are connected to the same first programming line 1PGM, and the first selection transistors 100 of the same row of first antifuse unit structures 10 are connected to the same first word line 1WL; in the second direction Y, the first doped regions 101 of the same column of antifuse unit structures 10 are connected to the same bit line BL; and at least N rows of antifuse unit structures 10 have their first word lines 1WL connected, where N is an integer greater than or equal to 2.

[0032] In some embodiments, N can be 3, 4, 6, 7 or 9, etc., but is not limited thereto.

[0033] An antifuse array structure is formed by arranging antifuse unit structures 10 in an array. The antifuse unit structure 10 includes first selection transistors 100 and first antifuse devices 200 connected in series. In the first direction X, all first antifuse devices 200 share the same first programming wire 1PGM, and all first selection transistors 100 share the same first word line 1WL. In the second direction Y, the first doped regions 101 of all first selection transistors 100 share the same bit line BL, and at least two rows of first word lines 1WL of the antifuse unit structure 10 are connected. That is, at least two rows of first selection transistors 100 can share a first word line 1WL control terminal, so as to reduce the control terminals of the antifuse array structure and reduce the timing complexity of the antifuse array structure programming process.

[0034] It is important to note that Figure 1 In the following description, the example given is that multiple antifuse unit structures 10 are arranged in an array in the first direction X and the second direction Y, and the angle between the first direction X and the second direction Y is 90°. This does not constitute a limitation on this embodiment. In other embodiments, the angle between the first direction X and the second direction Y can also be 20°, 40°, 60° or 80°.

[0035] It should be noted that, Figure 2 This is a partial schematic diagram of the antifuse array structure provided in this embodiment. It is only used to illustrate the arrangement of the antifuse array in this embodiment and does not constitute a limitation on the number of bit lines BL, first word lines 1WL, and first programming wires 1PGM. In specific use, the number of bit lines BL, first word lines 1WL, and first programming wires 1PGM can be selected according to the required storage array capacity. Furthermore, Figure 2 The numbers before "WL, PGM" are used to distinguish parameters such as "first" and "second". For example, "1WL" represents the first word line. The values ​​following "BL, WL, PGM" are only used to distinguish different bit lines BL, word lines WL, and programming wires PGM.

[0036] For the first selection transistor 100, its gate 110 is connected to the first word line 1WL. One of the source or drain of the first selection transistor 100 is located in the first doped region 101, and the other is located in the second doped region 102. The first selection transistor 100 and the first antifuse device 200 share the second doped region 102. This allows the first antifuse device 200 to be electrically connected to the bit line BL after the first selection transistor 100 is turned on, thus enabling the first antifuse device 200 to be programmed or read.

[0037] The first antifuse device 200 can be an antifuse transistor or an antifuse capacitor structure. When the first antifuse device 200 is a transistor, its gate 203 is connected to the first programming line 1PGM, one of its source or drain is located within the second doped region 102, and the other of its source or drain is either floating or connected to the first programming line 1PGM. When the first antifuse device 200 is a capacitor structure, one of its plates is connected to the first programming line 1PGM, and the other plate is connected to the second doped region 102. For example, by controlling the voltage on the first word line 1WL and the bit line BL, the first selection transistor 100 can be turned on, making the first antifuse device 200 electrically connected to the bit line BL. Furthermore, a programming voltage can be applied to the first programming line 1PGM to break down the first antifuse device 200, thereby realizing the programming of the first antifuse device 200. In addition, the first selection transistor 100 can be turned on by controlling the voltage on the first word line 1WL and the bit line BL, so that the first antifuse device 200 is electrically connected to the bit line BL. Furthermore, a read voltage is applied to the first programming wire 1PGM. The magnitude of the current flowing through the first antifuse device 200 can be used to determine whether the first antifuse device 200 is broken down, thereby obtaining the 1 bit of binary data stored in the first antifuse device 200.

[0038] refer to Figure 2 In some embodiments, the first word lines 1WL of every N rows of antifuse unit structures 10 are connected, and N is an even number. In this embodiment, N equals 2, that is, the first word lines 1WL of every 2 rows of antifuse unit structures 10 are connected; in other embodiments, N can be 4, 8 or 10, that is, the first word lines 1WL of every 4 rows, every 8 rows or every 10 rows of antifuse unit structures 10 are connected. This embodiment does not constitute a limitation on the number of rows in which the first word lines 1WL of the antifuse unit structures 10 are connected.

[0039] In other embodiments, N can also be an odd number, even if the first word lines of every 3, 5, or 7 rows of antifuse cell structures are connected. It is understood that, depending on the specific application, different connection methods can be selected based on the total number of rows of the first word lines of the antifuse cell structure to simplify the control of the antifuse array structure.

[0040] In some embodiments, the first word lines in antifuse unit structures with different numbers of rows can be connected. For example, when there are a total of 8 rows of antifuse unit structures, the first word lines of the antifuse unit structures in rows 1 to 3 are connected, and the first word lines of the antifuse unit structures in rows 4 to 8 are connected; or, the first word lines of the antifuse unit structures in rows 1, 3, and 5 are connected, and the first word lines of the antifuse unit structures in rows 2, 4, 6, 7, and 8 are connected. It is understood that when the first word lines of at least 2 rows of antifuse unit structures are connected, at least one first word line control terminal can be reduced. Different first word line connection methods can form different control methods. Specifically, the design can be carried out according to the actual use situation. This embodiment does not limit the specific way of connecting the first word lines.

[0041] It should be noted that in this embodiment, the method of connecting the first word lines is to connect their ends; in other embodiments, the method of connecting the first word lines can also be to connect their midpoints, or to connect the head of one first word line to the tail of another. The specific connection method can be adjusted according to the specific actual situation to connect the first word lines, thereby realizing that the connected first word lines are electrically connected to each other to share the same control terminal.

[0042] Further, refer to Figure 3 In some embodiments, the first word lines 1WL of all rows of antifuse cell structures 10 are connected. Connecting the first word lines 1WL of all antifuse cell structures 10 significantly reduces the number of control terminals of the first word lines 1WL of the first select transistors 100, retaining only one set of control terminals for the first select transistors 100, thus reducing the timing complexity of the overall control of the antifuse array structure. By selecting the first word line 1WL and the bit line BL, a column of first select transistors 100 corresponding to the first antifuse device 200 that needs to be programmed or read can be selected. Then, the first antifuse device 200 that needs to be programmed or read can be operated through the corresponding first programming wire 1PGM.

[0043] refer to Figure 4 and Figure 5In some embodiments, the antifuse unit structure 10 further includes: a second selection transistor 111 and a second antifuse device 222, wherein the second selection transistor 111 is connected to the bit line BL through a first doped region 101, the first selection transistor 100 and the second selection transistor 111 share the first doped region 101, and the second selection transistor 111 and the second antifuse device 222 share a third doped region 103; in the first direction X, the second antifuse devices 222 of the same row of antifuse unit structures 10 are connected to the second programming wire 2PGM, and the second selection transistors 111 of the same row of antifuse unit structures 10 are connected to the second word line 2WL; in the second direction Y, at least M rows of antifuse unit structures 10 are connected to each other, where M is an integer greater than or equal to 2.

[0044] In some embodiments, M can be 4, 6, 5, or 9.

[0045] An antifuse array structure is formed by arranging antifuse unit structures 10 in an array. Each antifuse unit structure 10 includes a first selection transistor 100 and a first antifuse device 200 connected in series, as well as a second selection transistor 111 and a second antifuse device 222 connected in series. That is, each antifuse unit structure 10 includes two sets of selection transistors and antifuse devices, thereby improving the integration density of the antifuse array structure and the control capability of the antifuse unit structure 10. At least two rows of antifuse unit structures 10 have their first word lines 1WL connected, and at least two rows of antifuse unit structures 10 have their second word lines 2WL connected. This means that at least two rows of first selection transistors 100 can share a first word line 1WL control terminal, and at least two rows of second selection transistors 111 can share a second word line 2WL control terminal. This reduces the number of control terminals for at least two word lines in the antifuse array structure, thereby reducing the timing complexity of the antifuse array structure programming process.

[0046] It should be noted that, Figure 5 This is a partial schematic diagram of the antifuse array structure provided in this embodiment. It is only used to illustrate the arrangement of the antifuse matrix in this embodiment and does not constitute a limitation on the number of bit lines (BL), word lines (WL), and programming wires (PGM). In specific use, the number of bit lines (BL), word lines (WL), and programming wires (PGM) can be selected according to the required storage array capacity. Furthermore, Figure 5 The numbers before "WL, PGM" are used to distinguish parameters such as "first" and "second". For example, "1WL" represents the first word line and "2WL" represents the second word line. The values ​​following "BL, WL, PGM" are only used to distinguish different bit lines BL, word lines WL, and programming wires PGM.

[0047] For the second selection transistor 111, its gate 223 is connected to the second word line 2WL. One of the source or drain of the second selection transistor 111 is located in the first doped region 101, and the other of the source or drain is located in the third doped region 103. The second selection transistor 111 and the second antifuse device 222 share the third doped region 103. This allows the second antifuse device 222 to be electrically connected to the bit line BL after the second selection transistor 111 is turned on, thus enabling the second antifuse device 222 to be programmed or read.

[0048] The second antifuse device 222 can be an antifuse transistor or an antifuse capacitor. When the second antifuse device 222 is a transistor, its gate 223 is connected to the second programming line 2PGM, one of its source or drain is located within the third doped region 103, and the other of its source or drain is either floating or connected to the second programming line 2PGM. When the second antifuse device 222 is a capacitor, one of its plates is connected to the second programming line 2PGM, and the other plate is connected to the third doped region 103. For example, by controlling the voltage on the second word line 2WL and the bit line BL, the second selection transistor 111 can be turned on, making the first antifuse device 222 electrically connected to the bit line BL. Furthermore, a programming voltage can be applied to the second programming line 2PGM to break down the second antifuse device 222, thereby realizing the programming of the second antifuse device 222. Additionally, by controlling the voltage on the second word line 2WL and the bit line BL, the second selection transistor 111 can be turned on, making the second antifuse device 222 electrically connected to the bit line BL. Furthermore, by applying a read voltage to the second programming wire 2PGM, the magnitude of the current flowing through the second antifuse device 222 can be used to determine whether the second antifuse device 222 has been broken down, thereby obtaining the 1 bit of binary data stored in the second antifuse device 222.

[0049] In some embodiments, the first selection transistor and the second selection transistor are arranged in a centrally symmetrical manner, as are the first antifuse device and the second antifuse device. It is understood that a centrally symmetrical structure allows for a more regular arrangement of the antifuse unit structure, thus facilitating the fabrication of the antifuse array structure. In this embodiment, the first antifuse device, the first selection transistor, the second selection transistor, and the second antifuse device are arranged sequentially along the second direction; in other embodiments, the first antifuse device, the first selection transistor, the second selection transistor, and the second antifuse device can be arranged centrally symmetrically along other directions, for example, directions with an angle of 30°, 45°, or 60° to the first direction, thereby increasing the arrangement density of the antifuse unit structure and improving the integration density of the antifuse array structure.

[0050] Continue to refer to Figure 5 In some embodiments, the second word lines 2WL of every M rows of antifuse unit structures 10 are connected, and M is an even number. In this embodiment, M equals 2, meaning that the second word lines 2WL of every 2 antifuse unit structures are connected; in other embodiments, M can be 4, 8, or 10, meaning that the second word lines 2WL of every 4 rows, every 8 rows, or every 10 rows of antifuse unit structures 10 are connected. This embodiment does not constitute a limitation on the number of rows in which the second word lines 2WL of the antifuse unit structures 10 are connected. Furthermore, in this embodiment, the number of rows in which the first word lines 1WL are connected can be the same as the number of rows in which the second word lines 2WL are connected; in other embodiments, the number of rows in which the first word lines 1WL are connected can be different from the number of rows in which the second word lines 2WL are connected. This embodiment does not constitute a limitation on the relationship between the number of rows in which the first word lines 1WL are connected and the number of rows in which the second word lines 2WL are connected.

[0051] In other embodiments, M can also be an odd number, even if the second word lines of every 3, 5, or 7 rows of antifuse cell structures are connected. It is understood that, depending on the specific application, different connection methods can be selected based on the total number of rows of the second word lines of the antifuse cell structure to simplify the control of the antifuse array structure.

[0052] In some embodiments, the second word lines of antifuse unit structures with different numbers of rows can be connected. For example, when there are a total of 8 rows of antifuse unit structures, the second word lines of the antifuse unit structures in rows 1 to 3 are connected, and the second word lines of the antifuse unit structures in rows 4 to 8 are connected; or, the second word lines of the antifuse unit structures in rows 1, 3, and 5 are connected, and the second word lines of the antifuse unit structures in rows 2, 4, 6, 7, and 8 are connected. It is understood that when the second word lines of 2 rows of antifuse unit structures are connected, at least one second word line control terminal can be reduced. Different second word line connection methods can form different control methods. Specifically, the design can be carried out according to the actual use situation. This embodiment does not limit the specific way of sharing the second word line.

[0053] It should be noted that in this embodiment, the connection method of the first character line is the same as that of the second character line; in other embodiments, the connection method of the first character line and the second character line may be different. Specifically, the connection method can be adjusted according to actual needs to suit the corresponding control method. This embodiment does not excessively limit the connection method of the first character line and the second character line. Furthermore, the connection methods of the first or second character lines provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of first or second character line connection.

[0054] In some embodiments, at least one row of first word lines is connected to at least one row of second word lines. It is understood that for an antifuse cell structure, when the first and second word lines are connected (i.e., sharing the same control terminal), when the common word line control terminal is turned on, both the first and second antifuse devices in the same antifuse cell structure are connected to the bit lines. Programming or reading of the first or second antifuse device can then be achieved by selecting either the first or second programming wire. Therefore, when at least one row of first word lines is connected to at least one row of second word lines, the number of control terminals on the word lines can be further reduced, thereby reducing the complexity of controlling the antifuse array structure.

[0055] Further, refer to Figure 6In some embodiments, all first word lines 1WL and second word lines 2WL are connected in the second direction Y. Connecting all first word lines 1WL and second word lines 2WL of the antifuse unit structure 10 can significantly reduce the number of word line control terminals of the first selection transistor 100 and the second selection transistor 111, retaining only one set of control terminals for the first selection transistor 100 and the second selection transistor 111, thus reducing the timing complexity of the overall control of the antifuse array structure. By selecting the word line WL and the bit line BL, a column of first selection transistors 100 and second selection transistors 111 corresponding to the first antifuse device 200 that needs to be programmed or read can be selected. Then, by using the corresponding first programming wire 1PGM or second programming wire 2PGM, the first antifuse device 200 or the second antifuse device 222 that needs to be programmed or read can be operated.

[0056] It should be noted that in this embodiment, the method of connecting the second digit lines is to connect their ends; in other embodiments, the method of connecting the second digit lines can also be to connect their midpoints, or to connect the head of one second digit line to the tail of another. The specific connection method can be adjusted according to the specific actual situation to make the second digit lines connected, thereby realizing that the connected second digit lines are electrically connected to each other to share the same control terminal.

[0057] Based on the structure of the antifuse unit structure in the above embodiments, which can have two sets of select transistors and antifuse devices, further, in some embodiments, each antifuse unit structure can include multiple sets of series-connected select transistors and antifuse devices. For example, when there are 4 sets of series-connected select transistors and antifuse devices in each antifuse unit structure, for one antifuse unit structure, the four antifuse devices are connected to different programming lines. When all the word lines of the select transistors are connected, only one word line control terminal remains. After the bit line is selected, the select transistors in the antifuse unit structure of the corresponding target antifuse device column are all turned on. At this time, it is only necessary to control the programming line of the corresponding antifuse device to control the programming and reading of the target antifuse device, thereby increasing the integration density of the antifuse array structure and improving the control capability of the antifuse array structure.

[0058] It is understandable that in the actual arrangement of the antifuse array structure, word lines, bit lines, and programming wires can be in the form of polygonal lines or wavy lines, so as to match the different arrangement of the antifuse unit structure within the antifuse array structure, thereby enabling the antifuse unit structure to form the densest arrangement and increasing the integration density of the antifuse array structure.

[0059] It should be noted that the specific connection methods of the "source" and "drain" defined above do not constitute a limitation on the embodiments of this application. In other embodiments, the connection method of "drain" replacing "source" and "source" replacing "drain" can be used. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problem proposed in this application, but this does not mean that there are no other units in this embodiment.

[0060] The antifuse array structure provided in this embodiment is formed by arranging antifuse unit structures in an array. Each antifuse unit structure includes a first selection transistor and a first antifuse device connected in series. In a first direction, all first antifuse devices share the same first programming wire, and all first selection transistors share the same first word line. In a second direction, the first doped regions of all first selection transistors share the same bit line, and the first word lines of at least two rows of antifuse unit structures are connected. That is, at least two rows of first selection transistors can share a first word line control terminal, thereby reducing the number of control terminals in the antifuse array structure and reducing the timing complexity of the antifuse array structure programming process.

[0061] Another embodiment of this disclosure provides a programming method that uses the antifuse array structure provided in the above embodiments to reduce the timing complexity of the antifuse array structure programming process.

[0062] It should be noted that for the parts that are the same as or corresponding to those in the above embodiments, please refer to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0063] The programming method provided in this embodiment includes: obtaining the target antifuse device to be programmed in the antifuse array structure, as well as the word line, programming wire, and bit line corresponding to the target antifuse device; applying an enable voltage to the word line corresponding to the target antifuse device to turn on the select transistor corresponding to the target antifuse device; applying a programming voltage to the programming wire corresponding to the target antifuse device; and applying a zero voltage to the bit line corresponding to the target antifuse device, wherein the programming voltage is greater than the breakdown voltage of the target antifuse device.

[0064] Another embodiment of this disclosure provides a reading method that uses the antifuse array structure provided in the above embodiments to reduce the timing complexity of the antifuse array structure programming process.

[0065] The reading method provided in this embodiment includes: acquiring the target antifuse device to be read in the antifuse array structure, as well as the word line, programming wire, and bit line corresponding to the target antifuse device; applying an enable voltage to the word line corresponding to the target antifuse device to turn on the selection transistor corresponding to the target antifuse device; applying a read voltage to the programming wire corresponding to the target antifuse device; and applying zero voltage to the bit line corresponding to the target antifuse device, wherein the read voltage is less than the breakdown voltage of the target antifuse device; reading the current flowing through the target antifuse device; and determining the stored data of the target antifuse device based on the magnitude of the current.

[0066] In another embodiment of this disclosure, a memory is provided, including at least one antifuse array structure provided in the above embodiments, to reduce the number of control terminals of the antifuse array structure and reduce the timing complexity of the antifuse array structure programming process.

[0067] Specifically, memory can be a storage cell or device based on a semiconductor device or component. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0068] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. An antifuse array structure, characterized in that, include: A substrate, and a plurality of antifuse unit structures formed on the substrate, wherein the plurality of antifuse unit structures are arranged in an array; Each of the aforementioned antifuse unit structures includes: A first selection transistor and a first antifuse device, wherein the first selection transistor is connected to a bit line through a first doped region, the first selection transistor and the first antifuse device share a second doped region, and the first doped region and the second doped region are disposed on opposite sides of the gate of the first selection transistor; In the first direction, the first antifuse devices of the same row of the antifuse unit structure are connected to the same first programming wire, and the first selection transistors of the same row of the antifuse unit structure are connected to the same first word line; In the second direction, the first doped regions of the same column of the antifuse unit structure are connected to the same bit line; and at least N rows of the first word lines of the antifuse unit structure are connected, where N is an integer greater than or equal to 2.

2. The antifuse array structure as described in claim 1, characterized in that, The first word lines of each of the N rows of the antifuse unit structure are connected, and N is an even number.

3. The antifuse array structure as described in claim 2, characterized in that, The first word lines of all rows of the antifuse unit structure are connected.

4. The antifuse array structure as described in claim 1, characterized in that, The gate of the first select transistor is connected to the first word line, and the gate of the first antifuse device is connected to the first programming wire.

5. The antifuse array structure as described in claim 1, characterized in that, The first doped region includes either the source or the drain of the first selected transistor, and the second doped region includes the other of the source or the drain of the first selected transistor.

6. The antifuse array structure as described in claim 1, characterized in that, The antifuse unit structure also includes: The second selection transistor and the second antifuse device are provided, wherein the second selection transistor is connected to the bit line through the first doped region, the first selection transistor and the second selection transistor share the first doped region, and the second selection transistor and the second antifuse device share the third doped region. In the first direction, the second antifuse device in the same row of the antifuse unit structure is connected to the second programming wire, and the second selection transistor in the same row of the antifuse unit structure is connected to the second word line; In the second direction, at least M rows of the second word lines of the antifuse unit structure are connected, where M is an integer greater than or equal to 2.

7. The antifuse array structure as described in claim 6, characterized in that, The second word lines of each of the M rows of the antifuse unit structure are connected, and M is an even number.

8. The antifuse array structure as described in claim 6, characterized in that, At least one line of the first character line is connected to at least one line of the second character line.

9. The antifuse array structure as described in claim 8, characterized in that, The first character line of all rows is connected to the second character line of all rows.

10. The antifuse array structure as described in claim 6, characterized in that, The first selection transistor and the second selection transistor are arranged in a centrally symmetrical manner, and the first antifuse device and the second antifuse device are arranged in a centrally symmetrical manner.

11. The antifuse array structure as described in claim 6, characterized in that, The gate of the first select transistor is connected to the first word line, and the gate of the first antifuse device is connected to the first programming wire; the gate of the second select transistor is connected to the second word line, and the gate of the second antifuse device is connected to the second programming wire.

12. The antifuse array structure as described in claim 6, characterized in that, The first doped region includes one of the source or drain of the first select transistor and one of the source or drain of the second select transistor, the second doped region includes the other of the source or drain of the first select transistor, and the third doped region includes the other of the source or drain of the second select transistor.

13. A programming method applied to the antifuse array structure as described in any one of claims 1 to 12, comprising: Obtain the target antifuse device to be programmed in the antifuse array structure, as well as the word line, programming wire and bit line corresponding to the target antifuse device; An enable voltage is applied to the word line corresponding to the target antifuse device to turn on the select transistor corresponding to the target antifuse device, a programming voltage is applied to the programming wire corresponding to the target antifuse device, and a zero voltage is applied to the bit line corresponding to the target antifuse device, wherein the programming voltage is greater than the breakdown voltage of the target antifuse device.

14. A reading method, applied to the antifuse array structure as described in any one of claims 1 to 12, comprising: Obtain the target antifuse device to be read in the antifuse array structure, as well as the word line, programming wire and bit line corresponding to the target antifuse device; An enable voltage is applied to the word line corresponding to the target antifuse device to turn on the select transistor corresponding to the target antifuse device; a read voltage is applied to the programming line corresponding to the target antifuse device; and a zero voltage is applied to the bit line corresponding to the target antifuse device, wherein the read voltage is less than the breakdown voltage of the target antifuse device. Read the current flowing through the target antifuse device; Based on the magnitude of the current, the stored data of the target antifuse device is determined.

15. A memory comprising at least one of the antifuse array structures according to any one of claims 1 to 12.

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