Semiconductor structure and methods for preparing semiconductor structures

Abstract

This disclosure relates to a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure includes: a substrate; semiconductor pillars located on the substrate, each semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; word lines covering a portion of the sidewalls of the semiconductor pillars in the channel region and exposing the remaining sidewalls of the semiconductor pillars in the channel region; and a conductive layer electrically connected to at least a portion of the exposed sidewalls of the semiconductor pillars in the channel region, and the conductive layer being used for electrical connection to a ground terminal. This disclosure is beneficial for suppressing the floating body effect of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0002] In field-effect transistors (FETs), the floating body effect is common. This effect occurs when holes accumulate in the channel, creating a voltage that increases the drain current. The floating body effect causes a warping of the device's output characteristic curve, known as the Kink effect. The Kink effect has numerous adverse effects on device and circuit performance and reliability.

[0003] As the integration density of semiconductor devices increases, the size of memory devices such as dynamic random access memory (DRAM) is becoming smaller and smaller. Therefore, the structure of 3D DRAM is receiving increasing attention. In the 3D DRAM structure, semiconductor pillars are usually formed in a horizontal stack, and word lines or bit lines are usually arranged in a stepped manner to save space and improve integration density.

[0004] However, the current semiconductor structure is more prone to the buoyancy effect. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for preparing the semiconductor structure, which at least helps to suppress the buoyancy effect of the semiconductor structure.

[0006] This disclosure provides a semiconductor structure, including: a substrate; a semiconductor pillar on the substrate, the semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; a word line, the word line covering a portion of the side surface of the semiconductor pillar in the channel region and exposing the remaining portion of the side surface of the semiconductor pillar in the channel region; and a conductive layer, the conductive layer being electrically connected to at least a portion of the side surface of the exposed semiconductor pillar in the channel region, and the conductive layer being used for electrical connection to a ground terminal.

[0007] In some embodiments, the semiconductor pillar has a rectangular cross-sectional shape in the direction perpendicular to the doped region pointing to the channel region, with the word line exposed on one side of the semiconductor pillar.

[0008] In some embodiments, the semiconductor pillars are parallel to the substrate surface, the word lines are parallel to the substrate surface, and the conductive layer is disposed opposite to the word lines. The system further includes: conductive pillars, which are perpendicular to the substrate surface, electrically connected to the conductive layer, and used for grounding.

[0009] In some embodiments, the material of the conductive layer is the same as the material of the conductive pillar.

[0010] In some embodiments, the material of the conductive layer includes at least one of polycrystalline silicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, and titanium silicide.

[0011] In some embodiments, a plurality of semiconductor pillars stacked in a direction away from the substrate and a plurality of word lines are provided on the substrate surface, wherein a portion of the side surface of the semiconductor pillars covering the channel region of the semiconductor pillars is electrically connected to the conductive layer.

[0012] In some embodiments, the semiconductor structure further includes conductive pillars electrically connected to a plurality of conductive layers, and the conductive pillars are used for electrical connection to ground.

[0013] In some embodiments, it further includes a bit line electrically connected to the end of a semiconductor pillar of a doped region.

[0014] Accordingly, this disclosure also provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a semiconductor pillar on the substrate, the semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; forming a word line, the word line covering a portion of the side surface of the semiconductor pillar in the channel region and exposing the remaining portion of the side surface of the semiconductor pillar in the channel region; forming a conductive layer, the conductive layer being electrically connected to at least a portion of the side surface of the exposed semiconductor pillar in the channel region, and the conductive layer being used for electrical connection to a ground terminal.

[0015] In some embodiments, the method of forming a conductive layer and a word line includes: forming at least two initial semiconductor pillars stacked in a direction away from the substrate on a substrate; forming a first sacrificial layer located between adjacent initial semiconductor pillars and covering at least the surface of the initial semiconductor pillars in the channel region; etching the top surface of the initial semiconductor pillars corresponding to the first sacrificial layer to form semiconductor pillars and expose the top surface of the semiconductor pillars; forming a word line on the top surface of the semiconductor pillars in the channel region; removing the first sacrificial layer to expose a portion of the bottom surface of the semiconductor pillars; forming a conductive layer on the bottom surface of the semiconductor pillars in the channel region, wherein the conductive layer located on the bottom surface of a semiconductor pillar and the word line located on the top surface of an adjacent semiconductor pillar are adjacent in a direction perpendicular to the substrate.

[0016] In some embodiments, the substrate is a silicon substrate, and the method of forming the first sacrificial layer includes: forming an initial sacrificial layer located between adjacent initial semiconductor pillars, the initial sacrificial layer being made of a first silicon germanide material; removing a portion of the initial sacrificial layer to form a first groove, the first groove exposing a portion of the bottom surface of the initial semiconductor pillars; and forming the first sacrificial layer in the first groove, the material of the first sacrificial layer being different from the material of the initial sacrificial layer.

[0017] In some embodiments, the method of etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer includes: forming a second sacrificial layer stacked with the initial sacrificial layer, the material of the second sacrificial layer being a second silicon germanide, the germanium content in the second silicon germanide being lower than the germanium content in the first silicon germanide, and the second sacrificial layer contacting the top surface of the initial semiconductor pillar to remove a portion of the initial sacrificial layer to form the first sacrificial layer; removing a portion of the second sacrificial layer to expose the top surface of the initial semiconductor pillar; and etching the top surface of the initial semiconductor pillar to form the semiconductor pillar.

[0018] In some embodiments, the method further includes forming a first dielectric layer located between adjacent word lines and the conductive layer in a direction perpendicular to the substrate.

[0019] In some embodiments, the material of the first dielectric layer includes a low-k dielectric material.

[0020] In some embodiments, a plurality of semiconductor pillars are arranged in an array on the substrate surface, and the plurality of semiconductor pillars are disposed in the same layer. Word lines cover a portion of the side surface of each channel region of semiconductor pillars in a row of semiconductor pillars arranged along a first direction. The method of forming word lines includes: forming an isolation structure located between adjacent semiconductor pillars along the first direction and covering the side surface of the semiconductor pillars in the channel region; etching the top surface of the isolation structure between adjacent semiconductor pillars until the isolation structure has a preset thickness; and forming word lines on the top surface and a portion of the side surface of the semiconductor pillars in the channel region.

[0021] The technical solution provided in this disclosure has at least the following advantages:

[0022] In the semiconductor structure provided in this embodiment, the semiconductor pillar has a channel region and a first doped region and a second doped region located on opposite sides of the channel region; the word line covers part of the side surface of the semiconductor pillar in the channel region and exposes the remaining side surface of the semiconductor pillar in the channel region, so that the exposed side surface of the semiconductor pillar can be used for grounding; the conductive layer is electrically connected to the exposed side surface of the semiconductor pillar in the channel region, and the conductive layer is used to be electrically connected to the ground terminal, so that the charge accumulated in the channel region can be discharged to the ground terminal through the conductive layer, thereby preventing the generation of the floating body effect. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0025] Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 3 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0027] Figures 4 to 32 A schematic diagram of the structure corresponding to each step in the method for preparing a semiconductor structure provided in another embodiment of this disclosure. Detailed Implementation

[0028] As can be seen from the background technology, there is a potential problem of buoyancy effect in current semiconductor structures.

[0029] Analysis revealed that one reason for the floating body effect in semiconductor structures is that, for field-effect transistors (FETs), under a sufficiently high drain voltage, electrons in the channel gain enough energy in the high-field region of the drain to generate electron-hole pairs through collisional ionization. Holes then move towards the channel region where the potential is lowered. Due to the high potential barrier at the gate-source junction, holes accumulate in the channel region, thus raising the potential of the channel region and forward biasing the gate-source junction. The positive potential on the floating body lowers the threshold voltage and increases the drain current, thereby producing the floating body effect.

[0030] This disclosure provides a semiconductor structure in which word lines cover a portion of the semiconductor pillar sidewalls of the channel region, while exposing the remaining portion of the semiconductor pillar sidewalls in the channel region. This allows the word lines located on the semiconductor pillar sidewalls in the channel region to be used to control the conduction of the channel, and the exposed semiconductor pillar sidewalls in the channel region to be used for grounding. A conductive layer is electrically connected to the exposed semiconductor pillar sidewalls in the channel region, and the conductive layer is also electrically connected to the ground terminal. This allows the charge accumulated in the channel region to be discharged to the ground terminal through the conductive layer, thereby preventing the generation of a floating body effect.

[0031] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0032] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0033] refer to Figures 1 to 3 The semiconductor structure includes: a substrate; semiconductor pillars 10 located on the substrate, the semiconductor pillars 10 having a channel region 11 and doped regions 12 located on opposite sides of the channel region 11; word lines 101 covering a portion of the sidewalls of the semiconductor pillars 10 in the channel region 11 and exposing the remaining portion of the sidewalls of the semiconductor pillars 10 in the channel region 11; and a conductive layer 102 electrically connected to at least a portion of the exposed sidewalls of the semiconductor pillars 10 in the channel region 11, and the conductive layer 102 being used for electrical connection to a ground terminal.

[0034] The conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charge in the channel region 11 can be transferred to the conductive layer 102 and then discharged to the ground through the conductive layer 102. This can prevent the problem of buoyancy effect caused by excessive charge accumulation in the channel region 11.

[0035] The substrate is made of a semiconductor material. In some embodiments, the substrate is made of silicon. In other embodiments, the substrate may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0036] The semiconductor pillar 10 may be made of the same material as the substrate. In some embodiments, the semiconductor pillar 10 may be made of silicon.

[0037] The channel region 11 and the doped regions 12 located on both sides of the channel region 11 can be used to form a transistor, wherein the doped regions 12 located on both sides of the channel region 11 can serve as either the source or the drain of the transistor. The word line 101 can serve as the gate of the semiconductor structure, used to conduct the channel region 11 based on a control signal, realizing carrier transport between the source and drain. In some embodiments, the doped ion type of the channel region 11 can be different from that of the doped ion type of the doped region 12, thereby forming a junction transistor. For example, the doped ion type in the channel region 11 can be P-type, and the doped ion type in the doped region 12 can be N-type, forming an NMOS transistor. When the semiconductor structure forms an NMOS transistor, electrons move in the channel. Electrons in the channel gain sufficient energy in the high field region at the drain end to generate electron-hole pairs, causing holes to move towards the lower potential channel region 11. That is, holes move from the drain to the source. Due to the high potential barrier of the gate-source junction, holes accumulate in the channel region 11. Therefore, by electrically connecting the conductive layer 102 to the side of the semiconductor pillar 10 exposed in the channel region 11, when a hole moves from the drain to the source into the channel region 11, it will be discharged to the ground through the conductive layer 102, thereby avoiding the floating body effect.

[0038] In other embodiments, the dopant ion type of the channel region 11 may also be the same as that of the dopant ion type of the dopant region 12, forming a junctionless transistor.

[0039] In some embodiments, the semiconductor pillar 10 has a rectangular cross-sectional shape in the direction perpendicular to the doped region 12 and pointing towards the channel region 11, with the word line 101 exposed on one side of the semiconductor pillar 10. That is, the word line 101 is arranged around three sides of the semiconductor pillar 10, thus increasing the contact area between the word line 101 and the semiconductor pillar 10 of the channel region 11. This increases the area and length of the formed channel, enhances the control capability of the word line 101 over the channel, and also helps reduce leakage current. The word line 101 is positioned to expose one side of the semiconductor pillar 10 for electrical connection with the conductive layer 102. The exposed side of the word line 101 is directly opposite the word line 101, and the conductive layer 102 is electrically connected to the exposed side. This results in a larger distance between the conductive layer 102 and the word line 101, preventing the conductive layer 102 from forming an electrical connection with the word line 101 due to excessively close proximity during the actual fabrication process. Specifically, in some embodiments, the word line 101 can completely cover three sides of the semiconductor pillar 10 to increase the contact area between the word line 101 and the semiconductor pillar 10. In other embodiments, the word line 101 can also cover the side of the semiconductor pillar 10 opposite to the exposed side of the semiconductor pillar 10, and partially cover the remaining two sides of the semiconductor pillar 10, resulting in a larger distance between the word line 101 and the exposed side of the semiconductor pillar 10. Therefore, when the conductive layer 102 forms an electrical connection with the exposed side of the semiconductor pillar 10, the distance between the conductive layer 102 and the word line 101 is greater, further preventing the problem of contact between the conductive layer 102 and the word line 101.

[0040] In some embodiments, the semiconductor pillar 10 is parallel to the substrate surface, the word line 101 is parallel to the substrate surface, and the conductive layer 102 is disposed opposite to the word line 101. The system also includes a conductive pillar 103, which is perpendicular to the substrate surface, electrically connected to the conductive layer 102, and used for grounding. The arrangement of the semiconductor pillar 10 and the word line 101 parallel to the substrate surface reduces the size occupied by the semiconductor pillar 10 and word line 101 in the direction perpendicular to the substrate, thereby facilitating the formation of a stacked structure of the semiconductor pillar 10 and improving the integration density of the formed semiconductor structure. The arrangement of the conductive layer 102 opposite to the word line 101 prevents electrical contact between the conductive layer 102 and the word line 101 due to excessive proximity. Since the word line 101 is parallel to the substrate surface, the conductive layer 102 is also parallel to the substrate surface. However, given the small overall size of the semiconductor structure, when the conductive layer 102 is parallel to the substrate surface, it may prevent the conductive layer 102 from being grounded. Based on this, conductive pillars 103 are provided, which are perpendicular to the substrate surface, that is, perpendicular to the conductive layer 102. This not only makes it easy for the conductive pillars 103 to form an electrical connection with the ground, but also allows the charge transmitted in the conductive layer 102 to be discharged to the ground through the conductive pillars 103. Furthermore, it helps to reduce the process difficulty of fabricating semiconductor structures.

[0041] In some embodiments, the material of the conductive layer 102 is the same as the material of the conductive pillar 103. By making the material of the conductive layer 102 the same as the material of the conductive pillar 103, the charge transport capabilities of the conductive layer 102 and the conductive pillar 103 are similar or identical. This allows for a faster charge transport rate when the charge is transferred from the conductive layer 102 to the conductive pillar 103, enabling the charge accumulated in the channel region 11 to be discharged to the ground more quickly, avoiding a floating body effect and maintaining the normal performance of the semiconductor structure.

[0042] In some embodiments, the material of the conductive layer 102 includes at least one of polycrystalline silicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, and titanium silicide. In some embodiments, the substrate is a silicon substrate, and the material of the semiconductor pillar 10 is the same as that of the substrate, i.e., the material of the semiconductor pillar 10 is silicon. This results in the conductive layer 102 having the same elements as the semiconductor pillar 10, meaning the material properties of the conductive layer 102 are similar to those of the semiconductor pillar 10. Therefore, when charge is transferred from the semiconductor pillar 10 deposited in the channel region 11 to the conductive layer 102, the resistance to charge transfer is lower due to the similarity between the material properties of the conductive layer 102 and the semiconductor pillar 10, which facilitates rapid charge dissipation.

[0043] In some embodiments, a plurality of semiconductor pillars 10 stacked along a direction away from the substrate and a plurality of word lines 101 are disposed on the substrate surface. A portion of the side surface of the semiconductor pillar 10 covers the channel region 11 within the semiconductor pillar 10, and at least a portion of the side surface of the semiconductor pillar 10 with exposed channel regions 11 is electrically connected to the conductive layer 102. Each semiconductor pillar 10 is used to form a transistor. By stacking multiple semiconductor pillars 10 on the substrate surface, multiple transistors can be formed. The stacked semiconductor pillars 10 occupy a smaller size, which is beneficial for improving the integration density of the formed semiconductor structure. When there are multiple semiconductor pillars 10, the channel region 11 of each semiconductor pillar 10 needs to be electrically connected to the word line 101, so that the word line 101 can control the conduction of the channel region 11. To reduce the area occupied by the word lines 101, the word lines 101 are disposed parallel to the substrate surface, thereby reducing the size of the word lines 101 in the direction perpendicular to the substrate surface, and thus reducing the overall size of the semiconductor structure. Based on this, in the stacked semiconductor pillars 10, each semiconductor pillar 10 corresponds to a word line 101, that is, each word line 101 is electrically connected to the channel region 11 in each semiconductor pillar 10. This allows for control of the channel region 11 of each semiconductor pillar 10 while maintaining a small semiconductor structure size. Since the conductive layer 102 is disposed opposite to the word line 101, when the word line 101 is parallel to the substrate surface, the conductive layer 102 is parallel to the substrate, thereby preventing electrical contact between the conductive layer 102 and the word line 101. Based on this, in the stacked semiconductor pillars 10, the side of each exposed channel region 11 of the semiconductor pillar 10 is electrically connected to a conductive layer 102, so that no electrical contact is formed between the stacked semiconductor pillars 10, thus preventing electrical interference. Furthermore, the charge accumulated in each channel region 11 can be discharged to ground through the conductive layer 102.

[0044] In some embodiments, the semiconductor structure further includes a conductive pillar 103, which is electrically connected to multiple conductive layers 102 and is used for electrical connection to ground. When multiple stacked semiconductor pillars 10 are disposed on the substrate surface, each semiconductor pillar 10 corresponds to a conductive layer 102, and the conductive layers 102 are disposed parallel to the substrate surface, which is equivalent to the conductive layers 102 being stacked. Since the conductive pillar 103 is disposed perpendicular to the conductive layer 102 and is used to ground the conductive layer 102, and the conductive pillar 103 does not form an electrical connection with the semiconductor pillar 10, there is no need to consider whether an electrical contact will be formed between the conductive pillar 103 and the semiconductor pillar 10. Therefore, only one conductive pillar 103 can be electrically connected to multiple stacked conductive layers 102, which greatly reduces the size of the conductive pillar 103 compared to one conductive pillar 103 corresponding to one conductive layer 102, thereby reducing the size of the semiconductor structure. Furthermore, the charge transmitted in each conductive layer 102 can be discharged to ground through the same conductive pillar 103.

[0045] In some embodiments, the side of the semiconductor pillar 10 away from the substrate forms an electrical connection with the word line 101, and the side of the semiconductor pillar 10 facing the substrate forms an electrical connection with the conductive layer 102. When multiple stacked semiconductor pillars 10 are disposed on the substrate surface, the word line 101 corresponding to one semiconductor pillar 10 will be disposed adjacent to the conductive layer 102 corresponding to the adjacent semiconductor pillar 10. Based on this, in some embodiments, a first dielectric layer 104 is further included, which is located between adjacent word lines 101 and conductive layers 102 to isolate adjacent word lines 101 and conductive layers 102, preventing electrical interference caused by the word lines 101 and conductive layers 102 forming an electrical connection. Specifically, in some embodiments, the material of the first dielectric layer 104 can be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 can also be a nitride, such as silicon nitride.

[0046] In some embodiments, the system further includes a bit line 105 electrically connected to the end of a semiconductor pillar 10 of a doped region 12. This allows the bit line 105 to draw out electrical signals from the doped region 12 located on one side of the channel region 11. Furthermore, because the end of the semiconductor pillar 10 has a large operating space, the fabrication process for the bit line 105 at the end of the semiconductor pillar 10 is simplified, which helps improve the yield of the semiconductor structure.

[0047] In some embodiments, a plurality of arrayed semiconductor pillars 10 are disposed on the substrate surface, and the plurality of semiconductor pillars 10 are disposed in the same layer. Word lines 101 cover a portion of the side surface of each channel region 11 of a row of semiconductor pillars 10 arranged along a first direction X. In a column of semiconductor pillars 10 arranged along a second direction Y, a doped region 12 in two adjacent semiconductor pillars 10 is electrically connected to the same word line 105. The first direction X is parallel to the substrate surface, and the second direction Y is the stacking direction of the plurality of semiconductor pillars 10. The first direction X is different from the second direction Y. Distributing a plurality of arrayed semiconductor pillars 10 on the substrate surface is beneficial to increasing the arrangement density of the semiconductor pillars 10, thereby increasing the integration density of the semiconductor pillars 10. The plurality of arrayed semiconductor pillars 10 are disposed in the same layer, that is, the arrayed semiconductor pillars 10 are not stacked. When the substrate surface has a plurality of stacked semiconductor pillars 10, the stacked semiconductor pillars 10 are not in the same layer. In the stacked semiconductor pillars 10, each semiconductor pillar 10 is located in a layer with a plurality of arrayed semiconductor pillars 10. In other words, when multiple semiconductor pillars 10 are provided on the substrate surface, the multiple semiconductor pillars 10 can be respectively disposed in different layers, and the semiconductor pillars 10 in each layer are arranged in an array. The arrayed semiconductor pillars 10 can be stacked, which can further increase the arrangement density of the semiconductor pillars 10 and make the integration of the semiconductor pillars 10 higher.

[0048] In each layer of arrayed semiconductor pillars 10, the arrangement direction of the semiconductor pillars 10 is parallel to the substrate surface, and the word line 101 is also parallel to the substrate surface. Therefore, the word line 101 can be configured to cover part of the semiconductor pillar 10 side of each channel region 11 in a row of semiconductor pillars 10 arranged along the first direction X. That is, multiple semiconductor pillars 10 arranged along the first direction X can share the same word line 101. In this way, the volume of the formed word line 101 can be saved, thereby reducing the overall size of the semiconductor structure.

[0049] Bit line 105 is positioned perpendicular to word line 101, meaning that bit line 105 is aligned with the stacking direction of the plurality of semiconductor pillars 10. Therefore, bit line 105 can be electrically connected to one of the doped regions 12 in a row of semiconductor pillars 10 arranged along the second direction Y, allowing the stacked semiconductor pillars 10 to share the same bit line 105. This further reduces the volume occupied by bit line 105, thereby further reducing the overall size of the semiconductor structure.

[0050] In some embodiments, bit line 105 may include a barrier layer, a conductive portion, and an insulating layer sequentially stacked along a direction away from semiconductor pillar 10. In some embodiments, the conductive portion may be a metallic material, such as any one of tungsten, copper, or aluminum; in other embodiments, the conductive portion may be a semiconductor material, such as polysilicon. The barrier layer prevents interdiffusion between the conductive portion and the doped region 12; the barrier layer may be made of titanium nitride. The insulating layer isolates the conductive portion from other conductive devices in the semiconductor structure; the insulating layer may be made of silicon oxide or silicon nitride.

[0051] In some embodiments, the material of the word line 101 may be at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0052] In some embodiments, the system may further include a gate dielectric layer 106, located between the word line 101 and the semiconductor pillars 10 of the channel region 11. The gate dielectric layer 106 isolates the word line 101 from the semiconductor pillars 10 of the channel region 11. Located on the surface of the semiconductor pillars 10 of the channel region 11, the gate dielectric layer 106 enables the transistor formed by the semiconductor pillars 10 to become a low-voltage device. In other words, the presence of the gate dielectric layer 106 allows the transistor to be turned on and data to be written by applying a relatively small voltage, thereby improving the performance of the semiconductor structure. In some embodiments, the material of the gate dielectric layer 106 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. The system also includes a barrier layer 107, located between the gate dielectric layer 106 and the word line 101, preventing ions in the gate dielectric layer 106 and the word line 101 from interdiffusion. The material of the barrier layer 107 may include titanium nitride.

[0053] In some embodiments, the system further includes a capacitor structure 108 electrically connected to another doped region 12 in the semiconductor pillar 10. The bit line 105 and the capacitor structure 108 are electrically connected to the two doped regions 12 in the semiconductor pillar 10, respectively. Specifically, the capacitor structure 108 may include a lower electrode layer (not shown), a capacitor dielectric layer (not shown), and an upper electrode layer (not shown) stacked sequentially along a direction away from the semiconductor pillar 10. The materials of the lower electrode layer and the upper electrode layer may be the same, and both materials may be at least one of platinum nickelide, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium. In other embodiments, the materials of the lower electrode layer and the upper electrode layer may be different. The capacitor dielectric layer may be made of high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, and titanium oxide.

[0054] In the semiconductor structure technical solution provided in the above embodiment, a word line 101 is provided to cover part of the semiconductor side surface of the channel region 11 and expose the remaining part of the semiconductor pillar 10 side surface of the channel region 11. In this way, the word line 101 located on the side surface of the semiconductor pillar 10 in the channel region 11 can be used to control the conduction of the channel region 11. The conductive layer 102 is electrically connected to the exposed side surface of the semiconductor pillar 10 in the channel region 11, and the conductive layer 102 is used to be electrically connected to the ground terminal, so that the charge accumulated in the channel region 11 can be discharged to the ground terminal through the conductive layer 102, thereby preventing the generation of the floating body effect.

[0055] Accordingly, this disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided in the above embodiments. The semiconductor structure provided in an embodiment of this disclosure will be described in detail below with reference to the accompanying drawings.

[0056] Figure 6Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the aa' direction.

[0057] refer to Figure 4 as well as Figure 6 A substrate 100 is provided, and in some embodiments, the material of the substrate 100 is silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0058] refer to Figures 7 to 32 A semiconductor pillar 10 is formed on a substrate 100. The semiconductor pillar 10 has a channel region 11 and doped regions 12 located on opposite sides of the channel region 11. A word line 101 is formed, which covers a portion of the side surface of the semiconductor pillar 10 in the channel region 11 and exposes the remaining portion of the side surface of the semiconductor pillar 10 in the channel region 11. A conductive layer 102 is formed, which is electrically connected to at least a portion of the exposed side surface of the semiconductor pillar 10 in the channel region 11, and is used for electrical connection to a ground terminal.

[0059] The conductive layer 102 is electrically connected to the side of the semiconductor pillar 10 of the exposed channel region 11, so that the charge in the channel region 11 can be transferred to the conductive layer 102 and then discharged to the ground through the conductive layer 102. This can prevent the problem of buoyancy effect caused by excessive charge accumulation in the channel region 11.

[0060] In some embodiments, the number of semiconductor pillars 10 can be multiple, thereby increasing the integration density of the semiconductor structure. In some embodiments, the material of the semiconductor pillars 10 can be the same as the material of the substrate 100. The doped regions 12 on both sides of the channel region 11 can serve as the source and drain of the transistor, and the word line 101 can serve as the gate of the transistor for controlling the conduction of the source and drain. In some embodiments, the dopant ion type of the doped region 12 can be the same as the dopant ion type of the channel region 11, so that the transistor formed is a junctionless transistor. In other embodiments, the dopant ion type of the doped region 12 is different from the dopant ion type of the channel region 11, so that the transistor formed is a junction transistor.

[0061] In some embodiments, the method of forming a conductive layer and word lines includes:

[0062] refer to Figure 6 At least two initial semiconductor pillars 20 are formed on the substrate 100 in a direction away from the substrate 100. In this way, multiple stacked semiconductor pillars can be formed, and each semiconductor pillar can be used to form a transistor, thereby improving the integration of the semiconductor structure.

[0063] In some embodiments, a plurality of semiconductor pillars 10 arranged in an array may also be formed in the substrate 100, the plurality of semiconductor pillars 10 arranged in the same layer, and the multi-layer array of semiconductor pillars 10 may be stacked. Based on this, refer to Figure 4 as well as Figure 5 In some embodiments, the substrate 100 can be divided into a first region 1 and a second region 2, and multilayer stacked semiconductor pillars 10 can be formed in the first region 1 and the second region 2, respectively. The method for forming the first region 1 and the second region 2 may include: patterning the surface of the initial semiconductor pillar 20 to define the positions of the first region 1 and the second region 2; specifically, a first mask layer 21 can be formed on the top surface of the initial semiconductor pillar 20, exposing the area to be etched; in some embodiments, a capping layer 22 is formed on top of the initial semiconductor pillar 20 to protect it; the capping layer 22 may be a silicon oxide layer and a silicon nitride layer stacked in a direction away from the substrate 100, therefore, the first mask layer 21 can be formed on the surface of the capping layer 22; in some embodiments, an etching process is performed on the patterned initial semiconductor pillar 20 to form the first region 1 and the second region 2. It is worth noting that the process method for forming the semiconductor pillars 10 in the first region 1 and the second region 2 can be the same; the following description will use the formation of multiple semiconductor pillars 10 in the first region 1 as an example.

[0064] Figure 7 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 8 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the bb' direction; Figure 9 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 10 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the bb' direction.

[0065] refer to Figures 4 to 10 A first sacrificial layer 23 is formed, located between adjacent initial semiconductor pillars 20, and at least covering the surface of the initial semiconductor pillars 20 in the channel region 11. The first sacrificial layer 23, located on the surface of the initial semiconductor pillars 20 in the channel region 11, reserves space for the subsequent formation of the conductive layer 102, ensuring that the process of forming the word line 101 does not damage the surface of the initial semiconductor pillars 20 covered by the first sacrificial layer 23. This allows for good electrical contact between the subsequently formed semiconductor layer and the surface of the semiconductor pillars 10 in the channel region 11.

[0066] In some embodiments, the substrate 100 is a silicon substrate, and the method for forming the first sacrificial layer 23 includes:

[0067] refer to Figure 6 An initial sacrificial layer 24 is formed, located between adjacent initial semiconductor pillars 20. The material of the initial sacrificial layer 24 includes first silicon germanide. Since the substrate 100 is a silicon substrate, the material of the initial sacrificial layer 24 includes first silicon germanide, so that the initial sacrificial layer 24 and the substrate 100 have the same silicon element, thereby matching the lattice constant of the silicon substrate and the silicon germanide. Therefore, when forming alternating initial semiconductor pillars 20 and the first sacrificial layer 23 on the substrate 100 using an epitaxial process, silicon germanide can be grown more easily using silicon in the silicon substrate, simplifying the fabrication process. Furthermore, the boundary between the formed first sacrificial layer 23 and the initial semiconductor pillars 20 is clear, which facilitates the subsequent complete removal of the first sacrificial layer 23 located on the surface of the initial semiconductor pillars 20.

[0068] refer to Figures 7 to 8 A portion of the initial sacrificial layer 24 is removed to form a first groove 26, exposing a portion of the bottom surface of the initial semiconductor pillar 20. Thus, the first sacrificial layer 23 subsequently formed in the first groove 26 can cover the bottom surface of the initial semiconductor pillar 20. In some embodiments, an etching process can be used to remove a portion of the initial sacrificial layer 24. Since the material of the initial sacrificial layer 24 is different from the material of the initial semiconductor layer, selective etching can be achieved by utilizing the different etching selectivity ratios of the initial sacrificial layer 24 and the initial semiconductor layer in the etching process. Specifically, the etching process can be either dry etching or wet etching. Removing only a portion of the initial sacrificial layer 24 leaves the remaining sacrificial layer located between adjacent initial semiconductor pillars 20, serving a supporting and isolating function.

[0069] refer to Figures 7 to 9 A first sacrificial layer 23 is formed in the first groove 26. The material of the first sacrificial layer 23 is different from that of the initial sacrificial layer 24. Considering that the first sacrificial layer 23 is used to reserve space for the subsequent formation of the conductive layer 102, the first sacrificial layer 23 needs to have greater hardness to prevent process damage to the first sacrificial layer 23 during the subsequent formation of the word line 101. Since the material of the initial sacrificial layer 24 is first silicon germanide, it is easier to form first silicon germanide on the surface of the silicon substrate compared to other materials. Therefore, the initial sacrificial layer 24 is first formed on the substrate 100, thereby forming a structure in which the initial sacrificial layer 24 and the initial semiconductor pillar 20 are stacked. The initial sacrificial layer 24 reserves space for the subsequent formation of the first sacrificial layer 23. Then, the initial sacrificial layer 24 is removed, and the first sacrificial layer 23 is formed in the original position of the first sacrificial layer 23. The first sacrificial layer 23 reserves space for the subsequent formation of the conductive layer 102. In this way, the quality of the semiconductor structure formed in each process step is high, thereby resulting in a high yield of the final semiconductor structure.

[0070] In some embodiments, a first sacrificial layer 23 may be formed in the first groove 26 using a deposition process, such as either a thermal oxidation process or an atomic layer deposition process. The material of the first sacrificial layer 23 may be silicon nitride.

[0071] Figure 11 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 12 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the bb' direction; Figure 13 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 14 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the bb' direction.

[0072] refer to Figures 11 to 14 After the first sacrificial layer 23 is formed, the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is etched to form the semiconductor pillar 10 and expose the top surface of the semiconductor pillar 10. That is, the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is thinned. On the one hand, this helps to reduce the size of the semiconductor pillar 10, and on the other hand, it can reserve enough space for the subsequent formation of word lines 101 on the top surface of the semiconductor pillar 10.

[0073] Because an initial sacrificial layer 24 is formed between the silicon substrate surface and the initial semiconductor pillar 20 using an epitaxial process, and because the atomic radius of germanium atoms is larger than that of silicon atoms, the thickness of the first silicon germanide layer epitaxially formed on the silicon substrate is relatively small due to stress and lattice defects. To form a thicker initial sacrificial layer 24, the thickness of the pre-formed initial semiconductor pillar 20 needs to be larger, thus resulting in a thicker initial sacrificial layer 24 epitaxially formed on the surface of the initial semiconductor pillar 20. Therefore, subsequent etching of the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 is required to ensure that the thickness of the formed semiconductor pillar 10 meets the requirements.

[0074] Since the first sacrificial layer 23 covers the surface of the initial semiconductor pillar 20 of the channel region 11, after etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23, the exposed top surface of the semiconductor pillar 10 becomes the top surface of the semiconductor pillar 10 of the channel region 11. Thus, when word lines 101 are subsequently formed on the exposed top surface of the semiconductor pillar 10, the word lines 101 can be electrically connected to the surface of the semiconductor pillar 10 of the channel region 11.

[0075] In some embodiments, a method for etching the top surface of the initial semiconductor pillar 20 corresponding to the first sacrificial layer 23 includes:

[0076] refer to Figure 6A second sacrificial layer 25 is formed and stacked with the initial sacrificial layer 24. The material of the second sacrificial layer 25 is second silicon germanide, and the germanium content in the second silicon germanide is lower than that in the first silicon germanide. The second sacrificial layer 25 is in contact with the top surface of the initial semiconductor pillar 20. The etching amount of silicon germanide is related to the germanium content in the silicon germanide. When the germanium content in the silicon germanide is higher, the etching of silicon germanide is more difficult, that is, the etching amount of silicon germanide is smaller. By setting the germanium content of the second silicon germanide to be lower than that of the first silicon germanide, when etching the first silicon germanide, the etching selectivity ratio between the first silicon germanide and the second silicon germanide can be used to ensure that the etching process does not etch the second silicon germanide adjacent to the first silicon germanide, thereby ensuring that the morphology of the formed first sacrificial layer 23 meets the expectations.

[0077] It is understood that in some other embodiments, the germanium content in the first silicon germanide may also be less than the germanium content in the second silicon germanide, as long as the germanium content in the first silicon germanide is different from the germanium content in the second silicon germanide.

[0078] refer to Figures 7 to 10 A portion of the initial sacrificial layer 24 is removed to form the first sacrificial layer 23.

[0079] refer to Figures 11 to 12 The second sacrificial layer 25 is partially removed to expose the top surface of the initial semiconductor pillar 20. In other words, before etching the top surface of the initial semiconductor pillar 20, the second sacrificial layer 25 is etched first to expose the top surface of the semiconductor pillar 10. Compared to directly etching the top surface of the initial semiconductor pillar 20 in contact with the first sacrificial layer 23 without forming the second sacrificial layer 25, the etching process for the initial semiconductor pillar 20 is simpler, and the top surface of the semiconductor pillar 10 formed after etching is flatter and more in line with expectations. This is because, after etching the second sacrificial layer 25, the top surface of the initial semiconductor pillar 20 is exposed, allowing the gas or solution used in the etching process to uniformly contact the top surface of the initial semiconductor pillar 20. Furthermore, the contact area between the etching gas or liquid and the top surface of the semiconductor pillar 10 is larger, which is beneficial for the etching process and results in a flatter top surface morphology for the formed semiconductor pillar 10.

[0080] refer to Figures 13 to 14 The top surface of the initial semiconductor pillar 20 is etched to form the semiconductor pillar 10.

[0081] refer to Figures 15 to 32After exposing the top surface of the semiconductor pillar 10, a word line 101 is formed on the top surface of the semiconductor pillar 10 in the channel region 11. The formed word line 101 can also cover at least part of the two sides connected to the top surface of the semiconductor pillar 10, so that the word line 101 surrounds at least part of the sides of the semiconductor pillar 10 in the channel region 11. The remaining side of the semiconductor pillar 10 in the channel region 11 can be used to electrically connect to the ground terminal, so that the charge accumulated in the channel region 11 can be discharged to the ground terminal.

[0082] In some embodiments, a plurality of semiconductor pillars 10 arranged in an array are disposed on the surface of the substrate 100, and the plurality of semiconductor pillars 10 are disposed in the same layer. A word line 101 covers a portion of the side surface of each channel region 11 of a row of semiconductor pillars 10 arranged along the first direction X. The method for forming the word line 101 includes:

[0083] Figure 16 Corresponding to Figure 15 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 17 Corresponding to Figure 15 A schematic diagram of the cross-sectional structure along the bb' direction; Figure 19 Corresponding to Figure 18 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 20 Corresponding to Figure 18 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 22 Corresponding to Figure 5 A schematic diagram of the cross-sectional structure along the aa' direction.

[0084] refer to Figures 15 to 22 An isolation structure 29 is formed, which is located between adjacent semiconductor pillars 10 along the first direction X and covers the side surface of the channel region 11 semiconductor pillars 10. The isolation structure 29 is used to isolate adjacent semiconductor pillars 10 so that no electrical contact is formed between adjacent semiconductor pillars 10 along the first direction X.

[0085] Specifically, the method of forming the isolation structure 29 may include:

[0086] refer to Figures 15 to 17A second dielectric layer 27 is formed on the top surface of each semiconductor pillar 10. The second dielectric layer 27 fills the gap between the semiconductor pillar 10 and the first sacrificial layer 23, reserving space for the subsequent formation of word lines 101. The second dielectric layer 27 prevents the formation of the isolation structure 29 between the top surface of the semiconductor pillar 10 and the first sacrificial layer 23 when the material of the isolation structure 29 is subsequently deposited to form the isolation structure 29. Specifically, in some embodiments, the second dielectric layer 27 can be formed using a deposition process. When the material of the first sacrificial layer 23 is silicon nitride, the material of the second dielectric layer 27 can be a low-k dielectric material. The low-k dielectric material and the silicon nitride material have a large etching selectivity ratio. Thus, when the second dielectric layer 27 needs to be removed to form the word lines 101, the etching selectivity ratio can be used to remove only the second dielectric layer 27 while retaining the first sacrificial layer 23.

[0087] refer to Figures 18 to 19 The top surface of the top semiconductor pillars 10 is patterned to define the positions of the arrayed semiconductor pillars 10. Specifically, a second mask layer 28 can be formed on the top surface of the top semiconductor pillars 10, exposing the top surface of the semiconductor pillars 10 to be etched. In some embodiments, before forming the second mask layer 28, the silicon nitride layer in the capping layer 22 can be removed, leaving only the silicon oxide layer, which facilitates the etching process. After removing the silicon nitride layer, the second mask layer 28 is formed on the surface of the silicon oxide layer.

[0088] refer to Figure 20 The top surface of the patterned semiconductor pillar 10 is etched to form an array of semiconductor pillars 10, wherein multiple semiconductor pillars 10 are arranged at intervals along a first direction X, and there are gaps between adjacent semiconductor pillars 10.

[0089] refer to Figures 21 to 22 An isolation material is deposited between adjacent semiconductor pillars 10 using a deposition process to form an isolation structure 29. The isolation structure 29 fills the gap between adjacent semiconductor pillars 10 and covers the side surface of each semiconductor pillar 10. Specifically, in some embodiments, the material of the isolation structure 29 may be silicon oxide.

[0090] Figure 24 Corresponding to Figure 23 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 25 Corresponding to Figure 23 A schematic diagram of the cross-sectional structure along the bb' direction.

[0091] After forming the isolation structure 29, refer to Figures 23 to 25 Remove the second dielectric layer 27 to expose the top surface of the semiconductor pillar 10 and the bottom surface of the first sacrificial layer 23. In this way, word lines 101 can be formed on the exposed top surface of the semiconductor pillar 10.

[0092] Figure 27 Corresponding to Figure 26 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 28 Corresponding to Figure 26 A schematic diagram of the cross-sectional structure along the bb' direction.

[0093] refer to Figures 26 to 28 Word lines 101 are formed on the top surface and part of the side surface of the semiconductor pillars 10 in the channel region 11. Specifically, before forming the word lines 101, the top surface of the isolation structure 29 between adjacent semiconductor pillars 10 is etched until the isolation structure 29 has a predetermined thickness, thereby creating a gap between adjacent semiconductor pillars 10, and only etching a portion of the isolation structure 29 between adjacent semiconductor pillars 10, so that the remaining portion of the isolation structure 29 between the semiconductor pillars 10 can still function as an isolation layer. Thus, when word line 101 material is deposited on the top surface of the semiconductor pillars 10 to form word lines 101, word lines 101 can also be formed on the side surface of the semiconductor pillars 10, so that the word lines 101 can cover the top surface of the semiconductor pillars 10 and the part of the side surface connected to the top surface.

[0094] In some embodiments, when the material of the isolation structure 29 is silicon oxide, in the step of etching the isolation structure 29 between adjacent semiconductor pillars 10, a portion of the isolation structure 29 located on the side of the semiconductor pillar 10 can be retained, so that the isolation structure 29 located on the side of the semiconductor pillar 10 can serve as the gate dielectric layer 106.

[0095] In some embodiments, the method of forming word line 101 includes forming a gate dielectric layer 106 on the exposed top surface of semiconductor pillar 10, and the gate dielectric layer 106 is connected to the isolation structure 29 located on the side of semiconductor pillar 10. In some embodiments, a deposition process can be used to form the gate dielectric layer 106 on the top surface of semiconductor pillar 10, and the material of the gate dielectric layer 106 can be silicon oxide.

[0096] A barrier layer 107 is formed on the surface of the gate dielectric layer 106 using a deposition process. In some embodiments, the material of the barrier layer 107 may be silicon nitride.

[0097] Word lines 101 are formed on the surface of the gate dielectric layer 106 using a deposition process. The material of word lines 101 can be at least one of tungsten, molybdenum, titanium, cobalt, or ruthenium.

[0098] Understandably, since the removal of the second dielectric layer 27 exposes the first sacrificial layer 23 and the top surface of the semiconductor pillar 10, when the gate dielectric layer 106 and word line 101 are formed on the top surface of the semiconductor pillar 10 using a deposition process, the first gate dielectric layer 32 and the first word line 31 are also formed on the bottom surface of the first sacrificial layer 23. To facilitate the subsequent removal of the first gate dielectric layer 32 and the first word line 31 located on the bottom surface of the first sacrificial layer 23, the deposition process is stopped when the thickness of the word line 101 on the top surface of the semiconductor pillar 10 meets expectations. An initial dielectric layer 30 is then formed between the word line 101 on the top surface of the semiconductor pillar 10 and the first word line 31 on the bottom surface of the first sacrificial layer 23 to isolate the word line 101 on the top surface of the semiconductor pillar 10 from the first word line 31 on the bottom surface of the first sacrificial layer 23. Thus, when the first gate dielectric layer 32 and the first word line 31 on the bottom surface of the first sacrificial layer 23 are subsequently removed, the presence of the initial dielectric layer 30 can protect the word line 101 and the first sacrificial layer 23 located on the top surface of the semiconductor pillar 10.

[0099] Figure 29 Corresponding to Figure 26 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 30 Corresponding to Figure 26 A schematic diagram of the cross-sectional structure along the bb' direction.

[0100] refer to Figures 29 to 30 After forming word line 101, the first sacrificial layer 23 is removed to expose part of the bottom surface of semiconductor pillar 10. The exposed bottom surface of semiconductor pillar 10 can be used to form conductive layer 102, thereby making conductive layer 102 electrically connected to the surface of semiconductor pillar 10 of part of channel region 11. Conductive layer 102 is used for grounding, so that the charge accumulated in channel region 11 can be discharged to ground through conductive layer 102.

[0101] Figure 31 Corresponding to Figure 26 A schematic diagram of the cross-sectional structure along the aa' direction; Figure 32 Corresponding to Figure 26 A schematic diagram of the cross-sectional structure along the bb' direction.

[0102] refer to Figures 31 to 32 A conductive layer 102 is formed on the bottom surface of the semiconductor pillar 10 in the channel region 11, and the conductive layer 102 located on the bottom surface of one semiconductor pillar 10 is adjacent to the word line 101 located on the top surface of the adjacent semiconductor pillar 10 in a direction perpendicular to the substrate. Since multiple semiconductor pillars 10 are stacked, and the conductive layer 102 is located on the bottom surface of the semiconductor pillar 10 and the word line 101 is located on the top surface of the semiconductor pillar 10, the conductive layer 102 of one semiconductor pillar 10 is adjacent to the word line 101 of the other semiconductor pillar 10 between two adjacent semiconductor pillars 10.

[0103] To prevent adjacent word lines 101 from forming electrical contacts with the conductive layer 102, some embodiments further include forming a first dielectric layer 104 located between adjacent word lines 101 and conductive layers 102 in a direction perpendicular to the substrate. The material of the first dielectric layer 104 can be the same as that of the initial dielectric layer 30. This is because the initial dielectric layer 30 is located between adjacent semiconductor pillars 10, thus eliminating the need to remove the initial dielectric layer 30 formed in the aforementioned steps, which saves process steps and material used to form the first dielectric layer 104. Specifically, in some embodiments, the material of the first dielectric layer 104 can be a low-k dielectric material. In other embodiments, the material of the first dielectric layer 104 can also be a nitride, such as silicon nitride.

[0104] In some embodiments, before forming the conductive layer 102, the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23 may be removed, while the initial dielectric layer 30 is retained. This prevents process damage to the conductive layer 102 that might occur when the gate dielectric layer 106 and the word line 101 on the bottom surface of the first sacrificial layer 23 are subsequently removed due to the formation of the conductive layer 102 on the surface of the gate dielectric layer 106 on the bottom surface of the first sacrificial layer 23.

[0105] In some embodiments, after removing the first word line 31 and the first gate dielectric layer 32 located on the bottom surface of the first sacrificial layer 23, material of the first dielectric layer 104 can be deposited on the top surface of the initial dielectric layer 30, thereby forming the first dielectric layer 104 together with the initial dielectric layer 30.

[0106] In some embodiments, a conductive layer 102 may be formed on the bottom surface of the semiconductor pillar 10 in the channel region 11 using a deposition process. Due to the presence of the initial dielectric layer 30, the formed conductive layer 102 will not make electrical contact with the word line 101 on the top surface of the other semiconductor pillar 10. In some embodiments, the material of the conductive layer 102 may be polycrystalline silicon or at least one of doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, and titanium silicide.

[0107] In the semiconductor structure fabrication method provided in the above embodiments, the formed word line 101 covers part of the side surface of the semiconductor pillar 10 in the channel region 11 and exposes the remaining part of the side surface of the semiconductor pillar 10 in the channel region 11, so that the word line 101 located on the side surface of the semiconductor pillar 10 in the channel region 11 can be used to control the conduction of the channel, and the exposed side surface of the semiconductor pillar 10 in the channel region 11 can be used for grounding; the formed conductive layer 102 is electrically connected to the exposed side surface of the semiconductor pillar 10 in the channel region 11, and the conductive layer 102 is used to be electrically connected to the ground terminal, so that the charge accumulated in the channel region 11 can be discharged to the ground terminal through the conductive layer 102, thereby preventing the generation of the floating body effect.

[0108] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A semiconductor pillar is formed on the substrate, the semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; A word line is formed, which covers a portion of the semiconductor pillar sidewalls of the channel region and exposes the remaining portion of the semiconductor pillar sidewalls of the channel region; A conductive layer is formed, the conductive layer being electrically connected to at least a portion of the side surface of the exposed semiconductor pillar of the channel region, and the conductive layer being used for electrical connection to ground. The method of forming the conductive layer and the word line includes: At least two initial semiconductor pillars are formed on the substrate and stacked in a direction away from the substrate; A first sacrificial layer is formed, the first sacrificial layer being located between adjacent initial semiconductor pillars, and the first sacrificial layer at least covering the surface of the initial semiconductor pillars in the channel region; The top surface of the initial semiconductor pillar corresponding to the first sacrificial layer is etched to form a semiconductor pillar and expose the top surface of the semiconductor pillar; A word line is formed on the top surface of the semiconductor pillar in the channel region; Remove the first sacrificial layer to expose part of the bottom surface of the semiconductor pillar; The conductive layer is formed on the bottom surface of the semiconductor pillar in the channel region, and the conductive layer located on the bottom surface of one of the semiconductor pillars is adjacent to the word line located on the top surface of the adjacent semiconductor pillar in a direction perpendicular to the substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate is a silicon substrate, and the method for forming the first sacrificial layer includes: An initial sacrificial layer is formed, the initial sacrificial layer being located between adjacent initial semiconductor pillars, the material of the initial sacrificial layer comprising a first silicon germanide; A portion of the initial sacrificial layer is removed to form a first groove, which exposes a portion of the bottom surface of the initial semiconductor pillar. A first sacrificial layer is formed in the first groove, and the material of the first sacrificial layer is different from that of the initial sacrificial layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The method for etching the top surface of the initial semiconductor pillar corresponding to the first sacrificial layer includes: A second sacrificial layer is formed and stacked with the initial sacrificial layer. The material of the second sacrificial layer is a second silicon germanide, the germanium content in the second silicon germanide is lower than the germanium content in the first silicon germanide, and the second sacrificial layer is in contact with the top surface of the initial semiconductor pillar. A portion of the initial sacrificial layer is removed to form the first sacrificial layer; Remove part of the second sacrificial layer to expose the top surface of the initial semiconductor pillar; The top surface of the initial semiconductor pillar is etched to form the semiconductor pillar.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: A first dielectric layer is formed, which is located between the word line and the conductive layer in a direction perpendicular to the substrate.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The material of the first dielectric layer includes: a low-k dielectric material.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The substrate surface is provided with a plurality of semiconductor pillars arranged in an array, and the plurality of semiconductor pillars are disposed in the same layer. The word line covers a portion of the side surface of each channel region of a row of semiconductor pillars arranged along a first direction. The method for forming the word line includes: An isolation structure is formed between adjacent semiconductor pillars along the first direction and covers the sidewalls of the semiconductor pillars in the channel region; The top surface of the isolation structure between adjacent semiconductor pillars is etched until the isolation structure has a predetermined thickness; Word lines are formed on the top surface and part of the side surface of the semiconductor pillar in the channel region.

7. A semiconductor structure formed using the method for preparing a semiconductor structure according to any one of claims 1-6, characterized in that, include: Base; A semiconductor pillar located on the substrate, the semiconductor pillar having a channel region and doped regions located on opposite sides of the channel region; Word lines, wherein the word lines cover a portion of the semiconductor pillar sidewalls of the channel region and expose the remaining portion of the semiconductor pillar sidewalls of the channel region; A conductive layer is electrically connected to at least a portion of the side surface of the exposed semiconductor pillar of the channel region, and the conductive layer is used for electrical connection to ground.

8. The semiconductor structure according to claim 7, characterized in that, In the direction perpendicular to the doped region pointing towards the channel region, the cross-sectional shape of the semiconductor pillar is rectangular, and the word line exposes one side of the semiconductor pillar.

9. The semiconductor structure according to claim 7, characterized in that, The semiconductor pillar is parallel to the substrate surface, the word line is parallel to the substrate surface, and the conductive layer is disposed opposite to the word line. The system also includes a conductive pillar, which is perpendicular to the substrate surface, electrically connected to the conductive layer, and used for grounding.

10. The semiconductor structure according to claim 9, characterized in that, The conductive layer is made of the same material as the conductive pillar.

11. The semiconductor structure according to claim 7 or 10, characterized in that, The material of the conductive layer includes at least one of polycrystalline silicon or polycrystalline silicon or doped silicon, doped germanium, titanium nitride, tantalum nitride, tungsten, titanium, tantalum, copper, aluminum, silver, gold, tungsten silicide, cobalt silicide, and titanium silicide.

12. The semiconductor structure according to claim 7, characterized in that, The substrate surface is provided with a plurality of semiconductor pillars stacked in a direction away from the substrate and a plurality of word lines, wherein the word lines cover a portion of the side surface of the semiconductor pillars in the channel region, and at least a portion of the side surface of the semiconductor pillars in the exposed channel region is electrically connected to the conductive layer.

13. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure further includes conductive pillars that are electrically connected to the plurality of conductive layers and are used for electrical connection to ground.

14. The semiconductor structure according to claim 12, characterized in that, Also includes: Bit lines are electrically connected to the semiconductor pillar ends of the doped region.

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