Display panel and manufacturing method thereof, and display device

Abstract

The embodiment of the present application provides a display panel and a method for preparing the same, and a display device. The display panel includes a base substrate, a driver device layer, a first flat layer, a light-emitting device layer, and a color filter layer stacked in sequence; the first flat layer has a first via hole exposing the driver device layer; the light-emitting device layer includes: a light-emitting device connected to the driver device layer through the first via hole, and a pixel defining structure enclosed around the light-emitting device; the pixel defining structure includes: a first pixel defining substructure filling the first via hole, and a second pixel defining substructure covering at least part of the first pixel defining substructure. The embodiment of the present application adopts a stacked multi-layer pixel defining substructure, which can realize multiple leveling of the multi-layer pixel defining substructure during the preparation process, effectively fill the step difference caused by the first via hole, improve the flatness of the pixel defining area in the light-emitting device layer, reduce the probability of irregular reflection in the display panel using COE technology, and improve the color separation performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display panel and a method for preparing the same, and a display device. Background Art

[0002] POL-Less is non-polarized technology, and COE (Color On Encapsulation, integrating color film or color filter into the encapsulation layer) technology is one of the representatives. COE technology has its own low power consumption, high color gamut, and strong controllability, which has great advantages over circular polarizers.

[0003] The COE structure can improve the transmittance. Its own light transmittance will allow more light to be emitted from the inside, and will also reflect the internal messy reflected light out from the pixel hole, which is prone to irregular reflection, affecting color separation and other defects that deteriorate the optical effect in the black state. Summary of the invention

[0004] In view of the shortcomings of the existing methods, the present application proposes a display panel and a method for preparing the same, and a display device, so as to solve the technical problem that the existing COE technology is prone to irregular reflection and affects color separation.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising a base substrate, a driving device layer, a first flat layer, a light emitting device layer and a color filter layer stacked in sequence;

[0006] The first planar layer has a first via hole exposing the driving device layer;

[0007] The light emitting device layer comprises: a light emitting device connected to the driving device layer through a first via hole, and a pixel defining structure enclosed around the light emitting device;

[0008] The pixel defining structure includes: a first pixel defining substructure filling the first via hole, and a second pixel defining substructure covering at least a portion of the first pixel defining substructure.

[0009] Optionally, the light emitting device comprises: an anode layer connected to the driving device layer through a first via hole, and a light emitting layer and a cathode layer sequentially located on a side of the anode layer away from the base substrate;

[0010] The first pixel defining substructure also covers a portion of the anode layer.

[0011] Optionally, the color filter layer includes a plurality of color filter films, and an orthographic projection of the first via hole on the base substrate overlaps with an orthographic projection of a corresponding color filter film on the base substrate.

[0012] Optionally, the first pixel defining substructure also covers a portion of the first planar layer.

[0013] Optionally, the first pixel defining substructure includes: a first flat region, and a first inclined region located at the periphery of the first flat region;

[0014] The first flat area has a first surface away from the substrate, and the first surface is parallel to the plane where the substrate is located; the first inclined area has a second surface away from the substrate, and the second surface intersects with the plane where the substrate is located;

[0015] The orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first flat area of ​​the first pixel defining substructure on the substrate.

[0016] Optionally, a dimension of the first slope region of the first pixel defining substructure along a first direction is not less than 0.5 micrometers, and the first direction is parallel to a plane where the substrate is located;

[0017] And / or, a dimension of the first slope region of the first pixel defining substructure along a second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the substrate is located.

[0018] Optionally, the orthographic projection of the second pixel defining substructure on the substrate is located within the orthographic projection of the first pixel defining substructure on the substrate, and the size of the edge of the orthographic projection of the second pixel defining substructure on the substrate and the edge of the orthographic projection of the first pixel defining substructure on the substrate along the first direction is not less than 0.5 microns.

[0019] Optionally, the light emitting device comprises: an anode layer connected to the first via hole, and a light emitting layer and a cathode layer sequentially located on a side of the anode layer away from the base substrate;

[0020] The second pixel defining substructure also covers a portion of the anode layer, and / or the second pixel defining substructure is in direct contact with the anode layer.

[0021] Optionally, the second pixel defining substructure also covers a portion of the first planar layer, and / or the second pixel defining substructure is in direct contact with the first planar layer.

[0022] Optionally, the second pixel defining substructure includes: a second flat region, and a second inclined region located at the periphery of the second flat region;

[0023] The orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the second flat area of ​​the second pixel defining substructure on the base substrate.

[0024] Optionally, a dimension of the second slope region of the second pixel defining substructure along a second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the substrate is located.

[0025] In a second aspect, an embodiment of the present application provides a display device, comprising: a display panel as provided in the first aspect above.

[0026] In a third aspect, an embodiment of the present application provides a method for preparing a display panel, comprising:

[0027] Sequentially preparing a driving device layer and a first planar layer on one side of the substrate;

[0028] Prepare a first via hole in the first flat layer to expose the driving device layer;

[0029] An anode layer connected to the driving device layer through a first via hole is prepared on a side of the first flat layer away from the substrate;

[0030] A first pixel defining substructure filling the first via hole and a second pixel defining substructure covering at least a portion of the first pixel defining substructure are sequentially prepared on a side of the first planar layer away from the base substrate to form a pixel defining structure;

[0031] A light-emitting layer and a cathode layer are sequentially prepared on a side of the anode layer away from the substrate to form a light-emitting device; a film layer structure including the light-emitting device and a pixel defining structure surrounding the light-emitting device forms a light-emitting device layer;

[0032] A color filter layer is prepared on a side of the light emitting device layer away from the substrate.

[0033] Optionally, a first pixel defining substructure filling the first via hole is prepared on a side of the first planar layer away from the base substrate, including:

[0034] Filling a first pixel defining material in the first via hole of the first planar layer, and forming a first pixel defining substructure after curing;

[0035] Alternatively, a first pixel defining material is coated in the first via hole of the first planar layer, on the anode layer around the first via hole and / or on the first planar layer, and the first pixel defining substructure is formed after leveling and curing.

[0036] Optionally, a second pixel defining substructure covering at least a portion of the first pixel defining substructure is prepared on a side of the first planar layer away from the substrate, comprising:

[0037] Coating a second pixel defining material on the first pixel defining substructure, and forming the second pixel defining substructure after leveling and curing;

[0038] Alternatively, a second pixel defining substructure is coated on the first pixel defining substructure, and on the anode layer and / or the first planar layer around the first pixel defining substructure, and the second pixel defining substructure is formed after leveling and curing.

[0039] Optionally, a first via hole connected to the driving device layer is prepared on the first flat layer, and an anode layer connected to the via hole is prepared on a side of the first flat layer away from the substrate, including:

[0040] Patterning the first planar layer so that the first planar layer forms a first through hole exposing at least a portion of the conductive structure of the driving device layer;

[0041] Depositing a first metal material layer on a side of the first planar layer away from the substrate, a hole wall of the first through hole, and at least a portion of the exposed conductive structure of the driving device layer;

[0042] The metal material layer is patterned so that the first through hole forms a first via hole, and an anode layer is obtained which is located at a side of the first flat layer away from the base substrate and connected to the via hole.

[0043] The beneficial technical effects brought about by the technical solution provided in the embodiment of the present application include: the display panel adopts a multi-layer pixel defining substructure including a first pixel defining substructure filling the first via hole and a second pixel defining substructure covering at least part of the first pixel defining substructure, and multiple leveling of the multi-layer pixel defining substructure can be achieved during the preparation process, which can effectively fill the step difference caused by the first via hole of the first flat layer, thereby improving the flatness of the pixel defining area in the light-emitting device layer, that is, improving the overall flatness of the reflective surface in the display panel, thereby effectively reducing the probability of irregular reflection in the display panel using COE technology, improving color separation performance, and improving display effect.

[0044] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0046] Figure 1 It is a structural schematic diagram of a display panel in the related art;

[0047] Figure 2 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0048] Figure 3 A structural schematic diagram of a first implementation scheme of a pixel defining structure in a display panel provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of the top view position relationship of a color filter layer, a pixel defining structure and a first via hole in a display panel provided in an embodiment of the present application;

[0050] Figure 5 A structural schematic diagram of a second implementation scheme of a pixel definition structure in a display panel provided in an embodiment of the present application;

[0051] Figure 6 A schematic structural diagram of implementation mode 3 of a display panel provided in an embodiment of the present application;

[0052] Figure 7 A schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application.

[0053] In the figure:

[0054] 100-substrate substrate;

[0055] 200- driver device layer;

[0056] 300 - first flat layer; 310 - first via hole;

[0057] 400-light-emitting device layer;

[0058] 410-light emitting device; 411-anode layer; 412-light emitting layer; 413-cathode layer;

[0059] 420-pixel defining structure; 420a-concave arc surface; 421-first pixel defining substructure; 421a-first flat area; 421b-first inclined area; 422-second pixel defining substructure; 422a-second flat area; 422b-second inclined area;

[0060] 500 - color filter layer; 510 - black matrix; 520 - color filter film. DETAILED DESCRIPTION

[0061] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0062] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or may refer to the connection relationship between the element and the other element established through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0063] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0064] The research and development ideas of this application include: Compared with traditional polarizers, the technical points of COE technology are more complicated, and there are higher process requirements for the underlying structure under the COE structure (such as TFT, anode, packaging, etc.) and the COE structure itself.

[0065] Specifically, COE optical performance has high requirements on the flatness of the reflective surface, but in related technologies, such as Figure 1 As shown, in order to achieve insulation and overlap between the light-emitting device layer 400 and the driving device layer 200 under the COE structure (color filter layer 500), a flat layer with vias can be set, and the light-emitting device layer 400 including the pixel defining structure 420 is directly prepared on the flat layer. However, the large step difference in the vias on the flat layer will cause the pixel defining structure 420 of the light-emitting device layer 400 to form a local concave arc surface 420a (collapse) at the via position. The concave arc surface 420a will not only cause irregular reflection of the incident light and affect color separation, but also affect the development of high PPI (pixel density) products.

[0066] The display panel and its manufacturing method, and the display device provided in the present application are intended to solve the above technical problems in the prior art.

[0067] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0068] The present application provides a display panel. The structure diagram of the display panel is as follows: Figure 2 and Figure 3 As shown, it includes a base substrate 100, a driving device layer 200, a first planar layer 300, a light emitting device layer 400 and a color filter layer 500 which are stacked in sequence.

[0069] The first planar layer 300 has a first via hole 310 exposing the driving device layer 200 .

[0070] The light emitting device layer 400 includes: a light emitting device 410 connected to the driving device layer through a first via hole 310 , and a pixel defining structure 420 surrounding the light emitting device 410 .

[0071] The pixel defining structure 420 includes a first pixel defining substructure 421 filling the first via hole 310 , and a second pixel defining substructure 422 covering at least a portion of the first pixel defining substructure 421 .

[0072] The driving device layer 200 in the display panel provided in this embodiment is used to drive the light emitting device layer 400 to work, and the first flat layer 300 is used to achieve the necessary insulation between the light emitting device layer 400 and the driving device layer 200, and to achieve the overlap required for the driving device layer 200 to drive the light emitting device layer 400 to work.

[0073] The light emitting devices 410 in the light emitting device layer 400 form pixel units in a working state, and the pixel defining structure 420 surrounds the light emitting devices 410 to define the area of ​​the pixel unit.

[0074] Among them, the pixel defining structure 420 adopts a multi-layer pixel defining substructure including a first pixel defining substructure 421 filling the first via hole 310 and a second pixel defining substructure 422 covering at least part of the first pixel defining substructure 421. Multiple leveling of the multi-layer pixel defining substructure can be achieved during the preparation process, and the step difference caused by the via hole of the first flat layer 300 can be effectively filled, thereby improving the flatness of the pixel defining area in the light-emitting device layer 400, that is, improving the overall flatness of the reflective surface in the display panel, thereby effectively reducing the probability of irregular reflection in the display panel using COE technology, improving color separation performance, and improving display effects.

[0075] In some possible implementations, such as Figure 4 As shown, the first pixel defining substructure 421 only fills the first via hole 310 .

[0076] In some possible implementations, the light emitting device 410 includes: an anode layer 411 connected to the driving device layer through the first via hole 310, and a light emitting layer 412 and a cathode layer 413 sequentially located on a side of the anode layer 411 away from the base substrate 100. Figure 5 As shown, the first pixel defining substructure 421 not only fills the first via hole 310 of the first planar layer 300 , but also covers a portion of the anode layer 411 .

[0077] In this embodiment, the first pixel defining substructure 421 not only fills the first via hole 310 of the first planar layer 300, but also extends to the anode layer 411 to a certain extent, which is beneficial to provide sufficient first pixel defining material in the preparation process to ensure that the first pixel defining substructure 421 after curing can fully fill the first via hole 310 of the first planar layer 300.

[0078] The portion of the first pixel defining substructure 421 covering a portion of the anode layer 411 may be formed by leveling a portion of the first pixel defining material overflowing from the first via hole 310 during the preparation process.

[0079] Optionally, the color filter layer 500 includes a plurality of color filter films 520 , and the orthographic projection of the first via hole 310 on the base substrate 100 overlaps with the orthographic projection of the corresponding color filter film 520 on the base substrate 100 .

[0080] In some other possible implementations, the first pixel defining substructure 421 not only fills the first via hole 310 of the first planar layer 300 , but also covers a portion of the first planar layer 300 .

[0081] In this embodiment, the first pixel defining substructure 421 not only fills the first via hole 310 of the first flat layer 300, but also extends to a certain extent toward the surface of the first flat layer 300. This is also beneficial for providing sufficient first pixel defining material in the preparation process to ensure that the first pixel defining substructure 421 after curing can fully fill the first via hole 310 of the first flat layer 300.

[0082] The first pixel defining substructure 421 covering a portion of the surface of the first planar layer 300 may be formed by leveling a portion of the first pixel defining material that overflows the first via hole 310 during the preparation process.

[0083] It is understandable that, in some other possible embodiments, the first pixel defining substructure 421 not only fills the first via hole 310 of the first planar layer 300, but also covers a portion of the anode layer 411 and a portion of the first planar layer 300. This can also help to provide sufficient first pixel defining material in the preparation process to ensure that the first pixel defining substructure 421 after curing can fully fill the first via hole 310 of the first planar layer 300.

[0084] Based on any one of the aforementioned third possible implementations of the first pixel defining substructure 421 , the first pixel defining substructure 421 provided in the embodiment of the present application includes: a first flat region 421 a , and a first slope region 421 b located at the periphery of the first flat region 421 a .

[0085] like Figure 5 As shown, the first flat area 421a has a first surface away from the substrate 100, and the first surface is parallel to the plane where the substrate 100 is located. The first inclined area 421b has a second surface away from the substrate 100, and the second surface intersects with the plane where the substrate 100 is located. The orthographic projection of the first via 310 on the substrate 100 is located within the orthographic projection of the first flat area 421a of the first pixel defining substructure 421 on the substrate 100.

[0086] In this embodiment, the first pixel defining substructure 421 is divided into zones, and the first flat area 421a is flatter than the first bevel area 421b, and the first bevel area 421b is naturally formed during the leveling process of the first pixel defining material. The first pixel defining substructure 421 provided in this embodiment can make the first via hole 310 of the first flat layer 300 covered by the flatter first flat area 421a in the first pixel defining substructure 421, which is conducive to ensuring that the first via hole 310 can be fully filled, and is also conducive to improving the flatness of the first pixel defining substructure 421 located above the first via hole 310.

[0087] In one example, the dimension of the first bevel region 421b of the first pixel defining substructure 421 along the first direction is not less than 0.5 micrometers, and the first direction is parallel to the plane where the base substrate 100 is located. That is, the width of the first bevel region 421b in the first pixel defining substructure 421 is not less than 0.5 micrometers, so as to ensure that the first pixel defining substructure 421 filling the first via hole 310 area is the first flat region 421a, that is, fully leveled.

[0088] In another example, the dimension of the first bevel region 421b of the first pixel defining substructure 421 along the second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the base substrate 100 is located. That is, the thickness of the first bevel region 421b in the first pixel defining substructure 421 is not less than 0.5 micrometers and not more than 2.0 micrometers, which also ensures that the first pixel defining substructure 421 filling the area of ​​the first via hole 310 is the first flat region 421a, that is, ensures that the first pixel defining material is sufficient to be fully leveled.

[0089] Based on any of the possible implementations of the first pixel defining substructure 421 described above, the present application provides the following possible implementations of the second pixel defining substructure 422:

[0090] In some possible implementations, such as Figure 5 As shown, the orthographic projection of the second pixel defining substructure 422 on the substrate 100 is located within the orthographic projection of the first pixel defining substructure 421 on the substrate 100, and the size of the edge of the orthographic projection of the second pixel defining substructure 422 on the substrate 100 and the edge of the orthographic projection of the first pixel defining substructure 421 on the substrate 100 along the first direction is not less than 0.5 microns.

[0091] In this embodiment, the second pixel defining substructure 422 covers the side of the first pixel defining substructure 421 away from the base substrate 100, and does not cover the edge of the first pixel defining substructure 421, so that the edge of the first pixel defining substructure 421 and the edge of the second pixel defining substructure 422 can form a stepped pixel defining boundary. In addition, the edge of the second pixel defining substructure 422 is retracted inward along the first direction relative to the edge of the first pixel defining substructure 421 by not less than 0.5 microns, which is conducive to obtaining a larger opening angle of the pixel defining boundary to meet the light emission requirements.

[0092] In some possible implementations, the light emitting device 410 includes: an anode layer 411 connected to the first via hole 310, and a light emitting layer 412 and a cathode layer 413 sequentially located on a side of the anode layer 411 away from the base substrate 100. Figure 6 As shown, the second pixel defining substructure 422 also covers a portion of the anode layer 411 , and / or the second pixel defining substructure 422 is in direct contact with the anode layer 411 .

[0093] In the present embodiment, the second pixel defining substructure 422 not only covers the side of the first pixel defining substructure 421 away from the base substrate 100, but also covers part of the anode layer 411, that is, it can cover the edge of the first pixel defining substructure 421 close to the anode layer 411. This is conducive to enabling the pixel defining structure 420 including the first pixel defining substructure 421 and the second pixel defining substructure 422 to naturally form a continuous pixel defining boundary with a gradually decreasing cross-section during the leveling process, and the cross-section refers to the cross-section perpendicular to the first direction.

[0094] In some other possible implementations, the second pixel defining substructure 422 further covers a portion of the first planar layer 300 , and / or the second pixel defining substructure 422 is in direct contact with the first planar layer 300 .

[0095] In this embodiment, the second pixel defining substructure 422 not only covers the side of the first pixel defining substructure 421 away from the base substrate 100 , but also covers part of the first planar layer 300 , that is, it can cover the edge of the first pixel defining substructure 421 close to the first planar layer 300 .

[0096] It can be understood that in some other possible embodiments, the second pixel defining substructure 422 not only covers the side of the first pixel defining substructure 421 away from the base substrate 100, but also covers part of the anode layer 411 and part of the first flat layer 300 respectively, that is, it can cover the edge of the first pixel defining substructure 421 close to the anode layer 411 and the edge of the first pixel defining substructure 421 close to the first flat layer 300.

[0097] Based on any of the third possible implementations of the second pixel defining substructure 422, the second pixel defining substructure 422 provided in the embodiment of the present application includes: a second flat region 422a, and a second slope region 422b located at the periphery of the second flat region 422a. Figure 5 or Figure 6 As shown, the orthographic projection of the first via hole 310 on the base substrate 100 is located within the orthographic projection of the second flat area 422 a of the second pixel defining substructure 422 on the base substrate 100 .

[0098] In this embodiment, the second pixel defining substructure 422 is partitioned, and the second flat area 422a is flatter than the second bevel area 422b, and the second bevel area 422b is naturally formed by the second pixel defining material during the leveling process. The second pixel defining substructure 422 provided in this embodiment can make the part of the first pixel defining substructure 421 corresponding to the first via hole 310 covered by the flatter second flat area 422a in the second pixel defining substructure 422, and the secondary leveling of the second pixel defining substructure 422 is used to further compensate for the film layer step difference corresponding to the first via hole 310 area, thereby improving the flatness of the pixel defining area in the light-emitting device layer 400, that is, improving the overall flatness of the reflection surface in the display panel, thereby effectively reducing the probability of irregular reflection in the display panel using COE technology, improving color separation performance, and improving display effect.

[0099] In one example, the dimension of the second bevel region 422b of the second pixel defining substructure 422 along the second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the base substrate 100 is located. That is, the width of the second bevel region 422b in the second pixel defining substructure 422 is not less than 0.5 micrometers, so as to ensure that the second pixel defining substructure 422 corresponding to the first via hole 310 area is the second flat region 422a, that is, fully leveled.

[0100] Based on the same inventive concept, an embodiment of the present application provides a display device, which includes: any one of the display panels provided in the above embodiments.

[0101] In this embodiment, since the display device includes any one of the display panels 100 provided in the aforementioned embodiments, the implementation principles and beneficial effects thereof are similar and will not be described in detail herein.

[0102] Optionally, the display device may include a mobile phone, a tablet computer, a mobile terminal, an e-book, an electronic photo frame, etc.

[0103] Based on the same inventive concept, the present application embodiment provides a method for preparing a display panel, and the flow diagram of the preparation method is as follows: Figure 7 As shown, the following steps S101-S106 are included:

[0104] S101: preparing a driving device layer and a first planarization layer in sequence on one side of the base substrate.

[0105] S102: preparing a first via hole in the first planar layer that exposes the connection of the driver device layer.

[0106] In some possible embodiments, this step S102 can use an etching process to prepare a first through hole connected to the driving device layer 200 in the first flat layer 300, and then deposit a metal material layer on at least the hole wall of the first through hole and at least a portion of the exposed conductive structure of the driving device layer 200, and then pattern the metal material layer so that the first through hole forms a first via 310.

[0107] S103: preparing an anode layer connected to the driving device layer through a first via hole on a side of the first planar layer away from the base substrate.

[0108] In some possible implementations, in step S103, a metal material layer may be deposited on the first planar layer 300, and then the metal material layer may be patterned to obtain an anode layer 411 connected to the driving device layer 200 through the first via hole 310. It is understood that the metal material used in step S103 may be the same as or different from the metal material used in step S102.

[0109] In some possible implementations, the above steps S102 and S103 can be combined to shorten the preparation period and save costs. Specifically, preparing a first via hole connected to the driver device layer on the first flat layer, and preparing an anode layer connected to the via hole on a side of the first flat layer away from the substrate, including the following steps:

[0110] The first planar layer is patterned so that a first through hole is formed in the first planar layer to expose at least a portion of the conductive structure of the driving device layer.

[0111] A first metal material layer is deposited on a side of the first planar layer away from the substrate, a hole wall of the first through hole and at least a portion of the exposed conductive structure of the driving device layer.

[0112] The metal material layer is patterned so that the first through hole forms a first via hole, and an anode layer is obtained which is located at a side of the first flat layer away from the base substrate and connected to the via hole.

[0113] S104: sequentially preparing a first pixel defining substructure filling the first via hole and a second pixel defining substructure covering at least a portion of the first pixel defining substructure on a side of the first planar layer away from the base substrate to form a pixel defining structure.

[0114] In this step S104, the preparation of the first pixel defining substructure 421 can achieve the first compensation for the step difference caused by the via hole of the first flat layer 300 and reduce the step difference. The preparation of the second pixel defining substructure 422 can achieve the second compensation for the step difference caused by the via hole of the first flat layer 300 and reduce the step difference again, so as to improve the overall flatness of the pixel defining structure 420 including the first pixel defining substructure 421 and the second pixel defining substructure 422.

[0115] In some possible implementations, in the above step S104, a first pixel defining substructure filling the first via hole is prepared on a side of the first flat layer away from the base substrate, including: filling the first via hole of the first flat layer with a first pixel defining material, and forming the first pixel defining substructure after curing.

[0116] The first pixel defining substructure 421 prepared in this embodiment can fill the first via hole 310 of the first planar layer 300, effectively fill the step difference caused by the via hole of the first planar layer 300, and is also beneficial to thinning the film layer.

[0117] In one example, the first pixel defining material may be a fully transparent, opaque, or semi-transparent material (for the visible light region). For example, the first pixel defining material may include at least one of polyimide, epoxy acrylic, and silicon-based materials.

[0118] In some possible embodiments, in the above step S104, a first pixel defining substructure filling the first via is prepared on a side of the first flat layer away from the base substrate, including: coating the first pixel defining material in the first via of the first flat layer, on the anode layer around the first via and / or on the first flat layer, and forming the first pixel defining substructure after leveling and curing.

[0119] The first pixel defining substructure 421 prepared in this embodiment can not only fill the first via hole 310 of the first flat layer 300, but also extend to the anode layer 411 or the first flat layer 300 to a certain extent, which is beneficial to provide sufficient first pixel defining material in the preparation process to ensure that the first pixel defining substructure 421 after curing can fully fill the first via hole 310.

[0120] In some possible embodiments, in the above step S104, a second pixel defining substructure covering at least a portion of the first pixel defining substructure is prepared on a side of the first flat layer away from the base substrate, including: coating a second pixel defining substructure on the first pixel defining substructure, and forming the second pixel defining substructure after leveling and curing.

[0121] The second pixel defining substructure 422 prepared in this embodiment can cover the side of the first pixel defining substructure 421 away from the base substrate 100 without covering the edge of the first pixel defining substructure 421 by controlling the coating amount of the second pixel defining material. In this way, the edge of the first pixel defining substructure 421 and the edge of the second pixel defining substructure 422 can form a stepped pixel defining boundary, which is beneficial for the pixel defining boundary to obtain a larger opening angle to meet the light output requirements.

[0122] In one example, the edge of the second pixel defining substructure 422 is retracted inward by no less than 0.5 micrometers along the first direction relative to the edge of the first pixel defining substructure 421, which is beneficial for the pixel defining boundary to obtain a larger opening angle to meet light emission requirements.

[0123] In one example, the second pixel defining material may be a fully transparent, opaque, or semi-transparent material (for the visible light region). For example, the first pixel defining material may include at least one of polyimide, epoxy acrylic, and silicon-based materials.

[0124] It should be noted that the second pixel defining material and the first pixel defining material may be the same or different.

[0125] In some possible embodiments, in the above step S104, a second pixel defining substructure covering at least a portion of the first pixel defining substructure is prepared on a side of the first flat layer away from the base substrate, including: coating a second pixel defining substructure on the first pixel defining substructure, on the anode layer around the first pixel defining substructure and / or on the first flat layer, and forming the second pixel defining substructure after leveling and curing.

[0126] The second pixel defining substructure 422 prepared through the present embodiment can not only target the area where there may be a certain step difference of the first pixel defining substructure 421 corresponding to the first via 310, but can also be extended to the anode layer 411 or the first flat layer 300 to a certain extent, which is conducive to the second pixel defining substructure 422 being able to cover the edge of the first pixel defining substructure 421 close to the anode layer 411 and / or the edge of the first pixel defining substructure 421 close to the first flat layer 300, which is conducive to the pixel defining structure 420 including the first pixel defining substructure 421 and the second pixel defining substructure 422 being able to naturally form a continuous pixel defining boundary with a gradually shrinking cross-section during the leveling process, and the cross-section refers to the cross-section perpendicular to the first direction.

[0127] S105: sequentially preparing a light-emitting layer and a cathode layer on a side of the anode layer away from the substrate to form a light-emitting device; a film layer structure including the light-emitting device and a pixel defining structure surrounding the light-emitting device forms a light-emitting device layer.

[0128] In some possible implementations, in step S105 , the light-emitting layer 412 can be prepared on the anode layer 411 in the hollow area enclosed by the pixel defining structure 420 , and then the cathode layer 413 can be fully prepared on the light-emitting layer 412 and the pixel defining structure 420 .

[0129] S106: preparing a color filter layer on a side of the light-emitting device layer away from the base substrate.

[0130] In some possible implementations, in step S106, a black matrix 510 can be first prepared on the side of the light-emitting device layer 400 away from the base substrate 100, the hollows in the black matrix 510 correspond to the light-emitting devices 410 in the light-emitting device layer 400, and then a color filter film 520 is prepared in the hollows of the black matrix 510 to obtain a color filter layer 500.

[0131] A method for preparing a display panel provided in an embodiment of the present application, after the above steps S101-S106, in the process of preparing the pixel defining structure 420, multiple leveling of a multi-layer pixel defining substructure is adopted, which can effectively fill the step difference caused by the via hole of the first flat layer 300, thereby improving the flatness of the pixel defining area in the light-emitting device layer 400, that is, improving the overall flatness of the reflective surface in the display panel, thereby effectively reducing the probability of irregular reflection in the display panel using COE technology, improving the color separation performance, and improving the display effect.

[0132] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0133] 1. The display panel adopts a multi-layer pixel defining substructure including a first pixel defining substructure 421 filling the first via hole 310 and a second pixel defining substructure 422 covering at least a portion of the first pixel defining substructure 421. Multiple leveling of the multi-layer pixel defining substructure can be achieved during the preparation process, and the step difference caused by the via hole of the first flat layer 300 can be effectively filled, thereby improving the flatness of the pixel defining area in the light-emitting device layer 400, that is, improving the overall flatness of the reflection surface in the display panel, thereby effectively reducing the probability of irregular reflection in the display panel using COE technology, improving color separation performance, and improving display effect.

[0134] 2. The first pixel defining substructure 421 not only fills the first via hole 310 of the first planar layer 300, but also extends to the anode layer 411 to a certain extent, which is conducive to providing sufficient first pixel defining material in the preparation process to ensure that the first pixel defining substructure 421 after curing can fully fill the first via hole 310 of the first planar layer 300.

[0135] 3. The first pixel defining substructure 421 not only fills the first via hole 310 of the first flat layer 300, but also extends to the surface of the first flat layer 300 to a certain extent. This is also beneficial to provide sufficient first pixel defining material in the preparation process to ensure that the first pixel defining substructure 421 after curing can fully fill the first via hole 310 of the first flat layer 300.

[0136] 4. The first pixel defining substructure 421 is divided into zones, and the first flat area 421a is flatter than the first bevel area 421b. The first bevel area 421b is naturally formed during the leveling process of the first pixel defining material. The first pixel defining substructure 421 provided in this embodiment can make the first via hole 310 of the first flat layer 300 covered by the flatter first flat area 421a in the first pixel defining substructure 421, which is conducive to ensuring that the first via hole 310 can be fully filled, and is also conducive to improving the flatness of the first pixel defining substructure 421 located above the first via hole 310.

[0137] 5. The width of the first sloped area 421 b in the first pixel defining substructure 421 is not less than 0.5 micrometers to ensure that the first pixel defining substructure 421 filling the first via hole 310 area is the first flat area 421 a , ie, is fully leveled.

[0138] 6. The thickness of the first slope area 421b in the first pixel defining substructure 421 is not less than 0.5 microns and not more than 2.0 microns, which also ensures that the first pixel defining substructure 421 filling the first via hole 310 area is the first flat area 421a, that is, ensures that the first pixel defining material is sufficient for full leveling.

[0139] 7. The second pixel defining substructure 422 covers the side of the first pixel defining substructure 421 away from the base substrate 100, and does not cover the edge of the first pixel defining substructure 421, so that the edge of the first pixel defining substructure 421 and the edge of the second pixel defining substructure 422 can form a stepped pixel defining boundary. In addition, the edge of the second pixel defining substructure 422 is not less than 0.5 microns inwardly contracted along the first direction relative to the edge of the first pixel defining substructure 421, which is conducive to obtaining a larger opening angle of the pixel defining boundary to meet the light emission requirements.

[0140] 8. The second pixel defining substructure 422 not only covers the side of the first pixel defining substructure 421 away from the base substrate 100, but also covers part of the anode layer 411 and / or the first flat layer 300, that is, it can cover the edge of the first pixel defining substructure 421 close to the anode layer 411 and / or the edge of the first pixel defining substructure 421 close to the first flat layer 300, which is conducive to the pixel defining structure 420 including the first pixel defining substructure 421 and the second pixel defining substructure 422 to naturally form a continuous pixel defining boundary with a gradually shrinking cross-section during the leveling process, and the cross-section refers to the cross-section perpendicular to the first direction.

[0141] 9. The second pixel defining substructure 422 is divided into zones, and the second flat zone 422a is flatter than the second bevel zone 422b. The second bevel zone 422b is naturally formed during the leveling process of the second pixel defining material. The second pixel defining substructure 422 provided in this embodiment can make the portion of the first pixel defining substructure 421 corresponding to the first via hole 310 covered by the flatter second flat zone 422a in the second pixel defining substructure 422, and the secondary leveling of the second pixel defining substructure 422 can be used to further compensate for the step difference of the film layer corresponding to the first via hole 310 area, thereby improving the flatness of the pixel defining area in the light-emitting device layer 400.

[0142] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0143] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0144] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0145] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0146] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0147] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0148] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A display panel, characterized in that: It includes a base substrate, a driving device layer, a first flat layer, a light emitting device layer and a color filter layer which are stacked in sequence; The first planar layer has a first via hole exposing the driving device layer; The light emitting device layer comprises: a light emitting device connected to the driving device layer through the first via hole, and a pixel defining structure enclosed around the light emitting device; The pixel defining structure comprises: a first pixel defining substructure filling the first via hole, and a second pixel defining substructure covering at least a portion of the first pixel defining substructure; The light emitting device comprises: an anode layer connected to the driving device layer through the first via hole, and a light emitting layer and a cathode layer sequentially located on a side of the anode layer away from the base substrate; The first pixel defining substructure also covers a portion of the anode layer; The color filter layer includes a plurality of color filter films, and the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the corresponding color filter film on the base substrate; The first pixel defining substructure includes: a first flat area, and a first inclined area located at the periphery of the first flat area; The first flat area has a first surface away from the substrate, and the first surface is parallel to the plane where the substrate is located; the first inclined area has a second surface away from the substrate, and the second surface intersects with the plane where the substrate is located; The orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the first flat area of ​​the first pixel defining substructure on the base substrate; The dimension of the first slope region of the first pixel defining substructure along a first direction is not less than 0.5 micrometers, and the first direction is parallel to the plane where the substrate is located; And / or, a dimension of the first slope region of the first pixel defining substructure along a second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to a plane where the substrate is located; The orthographic projection of the second pixel defining substructure on the substrate is located within the orthographic projection of the first pixel defining substructure on the substrate, and the size of the edge of the orthographic projection of the second pixel defining substructure on the substrate and the edge of the orthographic projection of the first pixel defining substructure on the substrate along the first direction is not less than 0.5 microns.

2. The display panel according to claim 1, characterized in that: The first pixel defining substructure also covers a portion of the first planar layer.

3. The display panel according to claim 1, characterized in that: The light emitting device comprises: an anode layer connected to the first via hole, and a light emitting layer and a cathode layer sequentially located on a side of the anode layer away from the base substrate; The second pixel defining substructure also covers a portion of the anode layer, and / or the second pixel defining substructure is in direct contact with the anode layer.

4. The display panel according to claim 1, characterized in that: The second pixel defining substructure also covers a portion of the first planar layer, and / or the second pixel defining substructure is in direct contact with the first planar layer.

5. The display panel according to claim 3 or 4, characterized in that: The second pixel defining substructure includes: a second flat area, and a second inclined area located at the periphery of the second flat area; An orthographic projection of the first via hole on the base substrate is located within an orthographic projection of the second flat area of ​​the second pixel defining substructure on the base substrate.

6. The display panel according to claim 5, characterized in that: The dimension of the second slope region of the second pixel defining substructure along a second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the base substrate is located.

7. A display panel, characterized in that: It includes a base substrate, a driving device layer, a first flat layer, a light emitting device layer and a color filter layer which are stacked in sequence; The first planar layer has a first via hole exposing the driving device layer; The light emitting device layer comprises: a light emitting device connected to the driving device layer through the first via hole, and a pixel defining structure enclosed around the light emitting device; The pixel defining structure comprises: a first pixel defining substructure filling the first via hole, and a second pixel defining substructure covering at least a portion of the first pixel defining substructure; The light emitting device comprises: an anode layer connected to the driving device layer through the first via hole, and a light emitting layer and a cathode layer sequentially located on a side of the anode layer away from the base substrate; The first pixel defining substructure also covers a portion of the anode layer; The color filter layer includes a plurality of color filter films, and the orthographic projection of the first via hole on the base substrate overlaps with the orthographic projection of the corresponding color filter film on the base substrate; The second pixel defining substructure also covers a portion of the first planar layer, and / or the second pixel defining substructure is in direct contact with the first planar layer; The second pixel defining substructure includes: a second flat area, and a second inclined area located at the periphery of the second flat area; The orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the second flat area of ​​the second pixel defining substructure on the base substrate; The dimension of the second slope region of the second pixel defining substructure along a second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the base substrate is located.

8. The display panel according to claim 7, characterized in that: The first pixel defining substructure also covers a portion of the first planar layer.

9. The display panel according to any one of claims 7 to 8, characterized in that: The first pixel defining substructure includes: a first flat area, and a first inclined area located at the periphery of the first flat area; The first flat area has a first surface away from the substrate, and the first surface is parallel to the plane where the substrate is located; the first inclined area has a second surface away from the substrate, and the second surface intersects with the plane where the substrate is located; An orthographic projection of the first via hole on the base substrate is located within an orthographic projection of the first flat area of ​​the first pixel defining substructure on the base substrate.

10. The display panel according to claim 9, characterized in that: The dimension of the first slope region of the first pixel defining substructure along a first direction is not less than 0.5 micrometers, and the first direction is parallel to the plane where the substrate is located; And / or, a dimension of the first slope region of the first pixel defining substructure along a second direction is not less than 0.5 micrometers and not more than 2.0 micrometers, and the second direction is perpendicular to the plane where the substrate is located.

11. The display panel according to any one of claims 7 to 8, characterized in that: The orthographic projection of the second pixel defining substructure on the substrate is located within the orthographic projection of the first pixel defining substructure on the substrate, and the size of the edge of the orthographic projection of the second pixel defining substructure on the substrate and the edge of the orthographic projection of the first pixel defining substructure on the substrate along the first direction is not less than 0.5 microns.

12. The display panel according to claim 7, characterized in that: The light emitting device comprises: an anode layer connected to the first via hole, and a light emitting layer and a cathode layer sequentially located on a side of the anode layer away from the base substrate; The second pixel defining substructure also covers a portion of the anode layer, and / or the second pixel defining substructure is in direct contact with the anode layer.

13. A display device, characterized in that: include: A display panel as described in any one of claims 1 to 12 above.

14. A method for preparing a display panel, characterized in that: Used to prepare a display panel as described in any one of claims 1 to 12, comprising: Sequentially preparing a driving device layer and a first planar layer on one side of the substrate; Prepare a first via hole in the first flat layer to expose the driving device layer; Prepare an anode layer connected to the driving device layer through the first via hole on a side of the first flat layer away from the base substrate; Sequentially preparing a first pixel defining substructure filling the first via hole and a second pixel defining substructure covering at least a portion of the first pixel defining substructure on a side of the first planar layer away from the base substrate to form a pixel defining structure; A light-emitting layer and a cathode layer are sequentially prepared on a side of the anode layer away from the substrate to form a light-emitting device; a film layer structure including the light-emitting device and the pixel defining structure enclosed around the light-emitting device forms a light-emitting device layer; A color filter layer is prepared on a side of the light emitting device layer away from the base substrate.

15. The preparation method according to claim 14, characterized in that: A first pixel defining substructure filling the first via hole is prepared on a side of the first planar layer away from the base substrate, comprising: Filling the first via hole of the first planar layer with a first pixel defining material, and forming the first pixel defining substructure after curing; Alternatively, a first pixel defining material is coated in the first via hole of the first planar layer, on the anode layer around the first via hole and / or on the first planar layer, and the first pixel defining substructure is formed after leveling and curing.

16. The preparation method according to claim 14 or 15, characterized in that: A second pixel defining substructure covering at least a portion of the first pixel defining substructure is prepared on a side of the first planar layer away from the base substrate, comprising: Coating a second pixel defining material on the first pixel defining substructure, and forming the second pixel defining substructure after leveling and curing; Alternatively, a second pixel defining substructure is coated on the first pixel defining substructure, on the anode layer around the first pixel defining substructure, and / or on the first planar layer, and the second pixel defining substructure is formed after leveling and curing.

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