Capacitively coupled chopper instrument amplifier and associated methods

Abstract

A capacitively coupled chopper instrument amplifier includes a first chopper, a first gain stage, a capacitive isolation stage electrically coupled between an input of the first gain stage and the first chopper, a second gain stage, a second chopper electrically coupled between an output of the first gain stage and an input of the second gain stage, clamp circuitry electrically coupled between the input of the first gain stage and a reference voltage rail, and a controller. The controller is configured to (a) detect a change in a first common mode voltage beyond a threshold, the first common mode voltage being a common mode voltage at the input of the amplifier, and (b) in response to detecting the change in the first common mode voltage beyond the threshold, cause the clamp circuitry to clamp the input of the first gain stage to the reference voltage rail.

Description

[0001] This application is a divisional application of the application filed on October 25, 2018, with application number 201811252488.1 and entitled "Capacitively Coupled Chopper Instrumentation Amplifier and Related Method".

[0002] Cross-references to related applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 577,261, filed October 26, 2017, and U.S. Provisional Patent Application No. 62 / 577,272, filed October 26, 2017. The entire contents of the above-mentioned U.S. Provisional Applications are incorporated herein by reference. Background Technology

[0004] Instrumentation amplifiers can amplify small differential voltages in the presence of large common-mode voltages. Therefore, instrumentation amplifiers are often used in applications where the signal to be amplified is small and the common-mode voltage is large, such as pressure sensing, temperature sensing, and current sensing applications.

[0005] An ideal instrumentation amplifier operates with infinite input impedance and zero voltage across its input terminals. However, practical instrumentation amplifiers do not achieve these ideal characteristics. For example, a practical instrumentation amplifier will have a non-zero input offset voltage, which is the inherent voltage across the input terminals of the instrumentation amplifier. The input offset voltage degrades the operation of the instrumentation amplifier, and therefore it is desirable for the input offset voltage to be as low as possible.

[0006] Some instrumentation amplifier applications require electrical isolation, for example, to isolate the amplifier's electronic circuitry from large common-mode input voltages. An example of such an application is a high-side current sensing application, where the current-sensing resistor is floating, and the voltage across the resistor has a large common-mode component that may not be suitable for typical low-voltage amplifier circuitry.

[0007] One type of instrumentation amplifier that can achieve low input offset voltage and electrical isolation is the capacitively coupled chopper instrumentation amplifier (CCIA). Figure 1A standard CCIA 100 is shown, including a first chopper 102, a second chopper 104, a capacitive isolation stage 106, a first gain stage 108, a second gain stage 110, reference resistors 112 and 114, and a controller 116. The capacitive isolation stage 106 is electrically coupled between the first chopper 102 and the first gain stage 108. The second chopper 104 is electrically coupled between the first gain stage 108 and the second gain stage 110. The first reference resistor 112 and the second reference resistor 114 are electrically coupled between a reference voltage rail 118 and corresponding inputs 120 and 122 of the first gain stage 108. The first reference resistor 112 and the second reference resistor 114 are necessary to establish a common-mode voltage at inputs 120 and 122 of the first gain stage 108 because the capacitive isolation stage 106 prevents the transmission of the DC component of the input signal to the CCIA 100.

[0008] Controller 116 generates a first clock signal Φ1 and a second clock signal Φ2 to control the first chopper 102 and the second chopper 104, causing the first chopper 102 and the second chopper 104 to alternate between direct signal transmission and inverse signal transmission. This operation of the first chopper 102 and the second chopper 104 shifts the input offset voltage of the first gain stage 108, as well as the noise at the inputs 120 and 122 of the first gain stage 108, to a frequency higher than the frequency of the signal intended to be amplified by CCIA 100. Therefore, CCIA 100 can achieve a lower input offset voltage and lower noise within the frequency range of the signal intended to be amplified by CCIA 100. Summary of the Invention

[0009] In a first aspect, a capacitor-coupled chopper instrumentation amplifier (CCIA) includes: (1) a first chopper, (2) a first gain stage, (3) a capacitor isolation stage electrically coupled between the input of the first gain stage and the first chopper, (4) a second gain stage, (5) a second chopper electrically coupled between the output of the first gain stage and the input of the second gain stage, and (6) a clamping circuit system electrically coupled between the input of the first gain stage and a reference voltage rail.

[0010] In an embodiment of the first aspect, the clamping circuit system may include a plurality of switching devices configured to electrically clamp the input of the first gain stage to the reference voltage rail.

[0011] In another embodiment of the first aspect, the CCIA further includes a first switching circuit system configured to electrically isolate the input of the first gain stage from the input of the CCIA when the clamping circuit system clamps the input of the first gain stage to the reference voltage rail.

[0012] In another embodiment of the first aspect, the CCIA further includes a second switching circuit system configured to electrically isolate the input of the second gain stage from the output of the first gain stage when the clamping circuit system clamps the input of the first gain stage to the reference voltage rail.

[0013] In another embodiment of the first aspect, the CCIA further includes an automatic zeroing circuit system electrically coupled to the output of the first gain stage.

[0014] In another embodiment of the first aspect, the automatic zeroing circuit system is configured to inject current at the output of the first gain stage to compensate for the output ripple caused by the first chopper and the second chopper.

[0015] In another embodiment of the first aspect, the automatic zeroing circuit system includes: (1) a third gain stage, including an output terminal electrically coupled to the output terminal of the first gain stage; (2) a first automatic zeroing capacitor and a second automatic zeroing capacitor, electrically coupled to the input terminal of the third gain stage; and (3) corresponding first automatic zeroing switching devices and second automatic zeroing switching devices, respectively electrically coupled between the first automatic zeroing capacitor and the second automatic zeroing capacitor and the output terminal of the first gain stage.

[0016] In another embodiment of the first aspect, the automatic zeroing circuit system is configured to sample the output of the first gain stage when the clamping circuit system clamps the input of the first gain stage to the reference voltage rail.

[0017] In another embodiment of the first aspect, the CCLA further includes a controller configured to: (1) repeatedly switch each of the first chopper and the second chopper between a first operating state and a second operating state; (2) clamp the input of the first gain stage to the reference voltage rail at least once during each operation of the first chopper and the second chopper in their corresponding first operating state; and (3) clamp the input of the first gain stage to the reference voltage rail at least once during each operation of the first chopper and the second chopper in their corresponding second operating state.

[0018] In another embodiment of the first aspect, the controller is further configured to: (1) cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail at least twice during each operation of the first chopper and the second chopper in their corresponding first operating state; and (2) cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail at least twice during each operation of the first chopper and the second chopper in their corresponding second operating state.

[0019] In another embodiment of the first aspect, the controller is further configured to: (1) cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail at least three times during each operation of the first chopper and the second chopper in their corresponding first operating state; and (2) cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail at least three times during each operation of the first chopper and the second chopper in their corresponding second operating state.

[0020] In another embodiment of the first aspect, the reference voltage rail has a fixed potential.

[0021] In a second aspect, a method for reducing the common-mode settling time of a capacitively coupled chopper instrumentation amplifier (CCIA) includes: (1) clamping the input of a first gain stage of the CCIA to a reference voltage rail at least once during each operation of a first chopper and a second chopper of the CCIA in a corresponding first operating state; and (2) clamping the input of the first gain stage of the CCIA to the reference voltage rail at least once during each operation of the first chopper and the second chopper of the CCIA in a corresponding second operating state.

[0022] In a second aspect embodiment, the method further includes injecting current at the output of the first gain stage to compensate for ripple caused by the first chopper and the second chopper.

[0023] In another embodiment of the second aspect, the method further includes: sampling the output of the first gain stage when the input of the first gain stage is clamped to the reference voltage rail to determine the magnitude of the current to be injected at the output of the first gain stage to compensate for the output ripple caused by the first chopper and the second chopper.

[0024] In another embodiment of the second aspect, the method further includes: when the input terminal of the first gain stage is clamped to the reference voltage rail, electrically isolating the input terminal of the first gain stage from the input terminal of the CCIA.

[0025] In another embodiment of the second aspect, the method further includes: when the input terminal of the first gain stage is clamped to the reference voltage rail, electrically isolating the input terminal of the second gain stage of the CCIA from the output terminal of the first gain stage.

[0026] In another embodiment of the second aspect, each clamping step includes: using a plurality of switching devices to electrically couple the input of the first gain stage to the reference voltage rail.

[0027] In another embodiment of the second aspect, the method further includes: repeatedly switching each of the first chopper and the second chopper between its corresponding first operating state and its corresponding second operating state.

[0028] In another embodiment of the second aspect, the method further includes: (1) clamping the input of the first gain stage of the CCIA to the reference voltage rail at least twice during each operation of the first chopper and the second chopper of the CCIA in a corresponding first operating state; and (2) clamping the input of the first gain stage of the CCIA to the reference voltage rail at least twice during each operation of the first chopper and the second chopper of the CCIA in a corresponding second operating state.

[0029] In another embodiment of the second aspect, the method further includes: (1) clamping the input of the first gain stage of the CCIA to the reference voltage rail at least three times during each operation of the first chopper and the second chopper of the CCIA in a corresponding first operating state; and (2) clamping the input of the first gain stage of the CCIA to the reference voltage rail at least three times during each operation of the first chopper and the second chopper of the CCIA in a corresponding second operating state.

[0030] In another embodiment of the second aspect, the reference voltage rail may have a fixed potential.

[0031] In a third aspect, a capacitively coupled amplifier includes: (1) a capacitive isolation stage, (2) at least one gain stage communicatively coupled to the capacitive isolation stage, and (3) a clamping circuit system configured to repeatedly clamp a common-mode voltage at the capacitive isolation portion of the amplifier to a reference voltage.

[0032] In a third aspect embodiment, the at least one gain stage includes a first gain stage, and the clamping circuit system is electrically coupled between the input of the first gain stage and a reference voltage rail.

[0033] In another embodiment of the third aspect, the clamping circuit system includes a plurality of switching devices configured to electrically clamp the input of the first gain stage to the reference voltage rail.

[0034] In another embodiment of the third aspect, the amplifier further includes a chopper, wherein the clamping circuit system is electrically coupled between the input of the chopper and the reference voltage rail.

[0035] In another embodiment of the third aspect, the amplifier further includes a switching circuit system configured to electrically isolate the at least one gain stage from the input of the amplifier when the clamping circuit system clamps the common-mode voltage to the reference voltage rail.

[0036] In another embodiment of the third aspect, the amplifier further includes a controller configured to cause the clamping circuitry to repeatedly clamp the common-mode voltage to the reference voltage.

[0037] In a fourth aspect, a capacitively coupled chopper instrumentation amplifier (CCIA) includes: (1) a first chopper, (2) a first gain stage, (3) a capacitive isolation stage electrically coupled between the input of the first gain stage and the first chopper, (4) a second gain stage, (5) a second chopper electrically coupled between the output of the first gain stage and the input of the second gain stage, (6) a clamping circuit system electrically coupled between the input of the first gain stage and a reference voltage rail, and (7) a controller configured to: (i) detect a change in a first common-mode voltage exceeding a threshold, the first common-mode voltage being a common-mode voltage at the input of the CCIA; and (ii) in response to detecting that the change in the first common-mode voltage exceeds the threshold, cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail.

[0038] In another embodiment of the fourth aspect, the CCIA further includes a first switching circuit system configured to electrically isolate the input of the first gain stage from the input of the CCIA when the clamping circuit system clamps the input of the first gain stage to the reference voltage rail.

[0039] In another embodiment of the fourth aspect, the controller is further configured to: in response to detecting that a change in the slew rate of the first common-mode voltage exceeds the threshold, cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail.

[0040] In another embodiment of the fourth aspect, the CCIA further includes an automatic zeroing circuit system electrically coupled to the output of the first gain stage.

[0041] In another embodiment of the fourth aspect, the automatic zeroing circuit system is configured to inject current at the output of the first gain stage to compensate for ripple caused by the first chopper and the second chopper.

[0042] In another embodiment of the fourth aspect, the automatic zeroing circuit system includes: (1) a third gain stage, including an output terminal electrically coupled to the output terminal of the first gain stage; (2) a first automatic zeroing capacitor and a second automatic zeroing capacitor electrically coupled to the input terminal of the third gain stage; and (3) corresponding first automatic zeroing switching devices and second automatic zeroing switching devices electrically coupled between the first automatic zeroing capacitor and the second automatic zeroing capacitor and the output terminal of the first gain stage.

[0043] In another embodiment of the fourth aspect, the controller is further configured to: cause the automatic zeroing circuit system to sample the output of the first gain stage when the clamping circuit system clamps the input of the first gain stage to the reference voltage rail.

[0044] In another embodiment of the fourth aspect, the clamping circuit system includes a plurality of switching devices configured to electrically clamp the input of the first gain stage to the reference voltage rail.

[0045] In another embodiment of the fourth aspect, the CCIA further includes a second switching circuit system configured to electrically isolate the input of the second gain stage from the output of the first gain stage when the clamping circuit system clamps the input of the first gain stage to the reference voltage rail.

[0046] In another embodiment of the fourth aspect, the CCIA further includes a controller configured to repeatedly switch each of the first chopper and the second chopper between a corresponding first operating state and a corresponding second operating state.

[0047] In another embodiment of the fourth aspect, the reference voltage rail may be at a fixed potential.

[0048] In a fifth aspect, a method for reducing the common-mode settling time of a capacitively coupled chopper instrumentation amplifier (CCIA) includes: (1) detecting a change in a first common-mode voltage exceeding a threshold, the first common-mode voltage being a common-mode voltage at an input of the CCIA; and (2) in response to detecting that the change in the first common-mode voltage exceeds the threshold, electrically isolating an input of a first gain stage of the CCIA from the input of the CCIA.

[0049] In a fifth aspect embodiment, the method further includes: clamping the input of the first gain stage to a reference voltage rail in response to detecting that the change in the first common-mode voltage exceeds the threshold.

[0050] In another embodiment of the fifth aspect, the step of detecting that the change in the first common-mode voltage exceeds the threshold includes: detecting that the change in the conversion rate of the first common-mode voltage exceeds the threshold.

[0051] In another embodiment of the fifth aspect, the method further includes injecting current at the output of the first gain stage to compensate for ripple caused by the first and second choppers of the CCIA.

[0052] In another embodiment of the fifth aspect, the method further includes: sampling the output of the first gain stage when the input of the first gain stage is clamped to the reference voltage rail to determine the magnitude of the current to be injected at the output of the first gain stage to compensate for the ripple caused by the first chopper and the second chopper of the CCIA.

[0053] In another embodiment of the fifth aspect, the method further includes: when the input terminal of the first gain stage is clamped to the reference voltage rail, electrically isolating the input terminal of the second gain stage of the CCIA from the output terminal of the first gain stage.

[0054] In another embodiment of the fifth aspect, each clamping step may include: using a plurality of switching devices to electrically couple the input of the first gain stage to the reference voltage rail.

[0055] In another embodiment of the fifth aspect, the method further includes: causing each of the first chopper and the second chopper of the CCIA to repeatedly switch between a corresponding first operating state and a corresponding second operating state.

[0056] In another embodiment of the fifth aspect, the reference voltage rail may be at a fixed potential.

[0057] In a sixth aspect, a capacitively coupled amplifier includes: (1) a capacitive isolation stage, (2) a gain stage communicatively coupled to the capacitive isolation stage, (3) a switching circuit system configured to electrically isolate the gain stage from the input of the amplifier, and (4) a controller configured to: (i) detect a change in a first common-mode voltage exceeding a threshold, the first common-mode voltage being a common-mode voltage at the input of the amplifier; and (ii) in response to detecting that the change in the first common-mode voltage exceeds the threshold, cause the switching circuit system to electrically isolate the gain stage from the input of the amplifier.

[0058] In a sixth aspect embodiment, the amplifier further includes a clamping circuit system electrically coupled between the input of the gain stage and a reference voltage rail, wherein the controller is further configured to: in response to detecting that the change in the first common-mode voltage exceeds the threshold, cause the clamping circuit system to clamp the input of the first gain stage to the reference voltage rail.

[0059] In another embodiment of the sixth aspect, the clamping circuit system includes a plurality of switching devices configured to electrically clamp the input of the gain stage to the reference voltage rail.

[0060] In another embodiment of the sixth aspect, the amplifier further includes: (1) a chopper, and (2) a clamping circuit system electrically coupled between the input of the chopper and a reference voltage rail, wherein the controller is further configured to: in response to detecting that the change in the first common-mode voltage exceeds the threshold, cause the clamping circuit system to clamp the input of the chopper to the reference voltage rail.

[0061] In another embodiment of the sixth aspect, the reference voltage rail has a fixed potential.

[0062] In another embodiment of the sixth aspect, the controller is further configured to: in response to detecting that a change in the slew rate of the first common-mode voltage exceeds the threshold, cause the switching circuit system to electrically isolate the gain stage from the input of the amplifier. Attached Figure Description

[0063] Figure 1 The standard CCIA was demonstrated.

[0064] Figure 2 It is a line graph, showing Figure 1 Example waveform of CCIA responding to rapid changes in the common-mode component of the input signal.

[0065] Figure 3An embodiment illustrates a CCIA configured to repeatedly clamp a common-mode voltage to a reference voltage.

[0066] Figure 4 It's a line graph, showing... Figure 3 Signals in one embodiment of CCIA.

[0067] Figure 5 It's a line graph, showing... Figure 3 The signal in another embodiment of CCIA.

[0068] Figure 6 yes Figure 3 The graphs show the analog output voltages of several CCIA implementations.

[0069] Figure 7 The embodiments illustrate, as shown below. Figure 3 It has a CCIA, but the automatic zeroing circuit system is omitted.

[0070] Figure 8 The embodiments illustrate a method for reducing the common-mode settling time of CCIA.

[0071] Figure 9 An embodiment illustrates a capacitively coupled linear amplifier configured to repeatedly clamp a common-mode voltage to a reference voltage.

[0072] Figure 10 It's a line graph, showing... Figure 9 The clock signal in one embodiment of the amplifier.

[0073] Figure 11 An embodiment illustrates a chopper-stabilized instrumentation amplifier configured to repeatedly clamp a common-mode voltage to a reference voltage.

[0074] Figure 12 Showing Figure 11 The chopper stabilization circuit system of the instrumentation amplifier.

[0075] Figure 13 An embodiment illustrates a CCIA configured to: (a) isolate the gain stage from the amplifier input; and (b) clamp the common-mode voltage at the capacitive isolation portion of the CCIA to a reference voltage in response to a change in the common-mode voltage.

[0076] Figure 14 The common-mode response subsystem is illustrated in the embodiment.

[0077] Figure 15 It's a line graph, showing... Figure 13 An example of the operation of a CCIA implementation in response to changes in common-mode voltage.

[0078] Figure 16 It's a line graph, showing... Figure 13 Another example of the operation of an embodiment of CCIA.

[0079] Figure 17 yes Figure 13 A graph of the analog output voltage in response to changes in the common-mode input voltage of a CCIA embodiment.

[0080] Figure 18 yes Figure 13 A graph showing the analog output voltage of a CCIA embodiment in response to changes in common-mode voltage and differential AC voltage.

[0081] Figure 19 The embodiments illustrate, as shown below. Figure 13 It has a CCIA, but the automatic zeroing circuit system is omitted.

[0082] Figure 20 The embodiments illustrate a method for reducing the common-mode settling time of CCIA.

[0083] Figure 21 An embodiment illustrates a capacitively coupled linear amplifier configured to: (a) clamp a common-mode voltage at a capacitively isolated portion of the amplifier to a reference voltage; and (b) isolate a gain stage from the amplifier input in response to a change in the common-mode voltage.

[0084] Figure 22 It's a line graph, showing... Figure 21 The clock signal in one embodiment of the amplifier.

[0085] Figure 23 According to an embodiment, a chopper-stabilized instrumentation amplifier is shown, which is configured to: (a) clamp the common-mode voltage at the capacitor isolation portion of the instrumentation amplifier to a reference voltage; and (b) isolate the gain stage from the amplifier input in response to a change in the common-mode voltage.

[0086] Figure 24 Showing Figure 23 The chopper stabilization circuit system of the instrumentation amplifier. Detailed Implementation

[0087] Conventional CCIAs do not perform well in handling rapid changes in the common-mode components of their input signals. For example, Figure 2Figure 200 shows an example waveform of the CCIA 100 responding to a rapid change in the common-mode voltage at inputs 124 and 126 of the CCIA 100. Curve 202 represents the voltage at CCIA input 124, curve 204 represents the voltage at CCIA input 126, curve 206 represents the voltage at the first gain stage input 120, curve 208 represents the voltage at the first gain stage input 122, and curve 210 represents the output voltage V of the CCIA 100. 输出 .

[0088] At time t1, the voltage magnitude at each of CCIA inputs 124 and 126 changes rapidly from V1 to V2, causing the common-mode voltage magnitude at the CCIA 100 input to change rapidly from V1 to V2. The first reference resistor 112 and the second reference resistor 114 must have large resistance values ​​to prevent excessive signal loss and noise, and the reference voltage rail 118 therefore acts as a high-impedance voltage source relative to the first gain stage inputs 120 and 122. Therefore, the reference voltage rail 118 cannot maintain the common-mode voltage at the first gain stage inputs 120 and 122 during the transient event, and a significant amount of time is required to establish the common-mode voltage at inputs 120 and 122 after the transient event. Thus, the rapid change in the common-mode input voltage at time t1 causes glitches 212 and 214, respectively, to appear at each of the first gain stage inputs 120 and 122, and these glitches are amplified by the first gain stage 108 and the second gain stage 110, resulting in a change in the input voltage V. 输出 The corresponding glitches 216. Therefore, the rapid change of the common-mode input voltage at time t1 causes the output voltage V to... 输出 Distortion.

[0089] The applicant has developed new CCIAs and associated methods that at least partially overcome one or more of the disadvantages of conventional CCIAs discussed above. Certain embodiments of these new CCIAs are configured to repeatedly clamp the common-mode voltage at the capacitive isolation portion of the CCIA (e.g., at the input of the gain stage after the capacitive isolation stage) to a reference voltage rail, thereby helping to minimize the common-mode voltage settling time after a transient event. Some embodiments are configured to detect changes in the common-mode voltage and, in response to the detected change, (a) isolate the gain stage from the amplifier input and (b) clamp the common-mode voltage at the capacitive isolation portion of the CCIA to the reference voltage, thereby helping to minimize the common-mode voltage settling time after a transient event.

[0090] Figure 3A CCIA 300 is shown, which is an embodiment of a new CCIA configured to repeatedly clamp the common-mode voltage at the capacitive isolation section of the CCIA to a reference voltage of a reference voltage rail. The CCIA 300 includes a first chopper 302, a second chopper 304, a first gain stage 306, a second gain stage 308, a capacitive isolation stage 310, a clamping circuit system 312, an automatic zeroing circuit system 314, a first switching circuit system 316, a second switching circuit system 318, and a controller 320.

[0091] The first chopper 302 is electrically coupled to (a) the CCIA input terminal V. i_p and V i_n Between (b) capacitor isolation stage 310. The first chopper 302 is controlled by clock signals Φ1 and Φ2, and includes at least a first operating state and a second operating state. When clock signal Φ1 is asserted, the first chopper 302 operates in its first operating state; and when clock signal Φ2 is asserted, the first chopper 302 operates in its second operating state. The first operating state is characterized by direct signal transmission, that is, the first chopper 302 transmits the CCIA input V... i_p Electrically coupled to the positive input path 322, and the first chopper 302 converts the CCIA input terminal V... i_n Electrically coupled to the negative input path 324. The second operating state is characterized by the reverse signal transmission, that is, the first chopper 302 converts the CCIA input V... i_p Electrically coupled to the negative input path 324, and the first chopper 302 converts the CCIA input V... i_n Electrically coupled to positive input path 322. Positive input path 322 feeds into input terminal 326 of first gain stage 306, and negative input path 324 feeds into input terminal 328 of first gain stage 306. In some embodiments, first chopper 302 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first operating state and the second operating state.

[0092] A capacitive isolation stage 310 is electrically coupled between the first chopper 302 and the first gain stage inputs 326 and 328, such that the first gain stage 306 is communicatively coupled to the capacitive isolation stage 310. The capacitive isolation stage 310 electrically couples the alternating current (AC) signal between the first chopper 302 and the first gain stage 306 while blocking the transmission of DC signals. In some embodiments, as shown, the capacitive isolation stage 310 includes a first capacitor 330 and a second capacitor 332. In these embodiments, the first capacitor 330 is electrically coupled in series with the positive input path 322, and the second capacitor 332 is electrically coupled in series with the negative input path 324. Without departing from the scope of this document, the capacitive isolation stage 310 may include additional capacitors. Furthermore, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitive isolation stage 310.

[0093] Clamping circuitry 312 is electrically coupled between first gain stage inputs 326 and 328 and a reference voltage rail 334. In some embodiments, the reference voltage rail 334 has a fixed potential set to achieve the desired common-mode voltage at the first gain stage inputs 326 and 328. Clamping circuitry 312 is configured to clamp the first gain stage inputs 326 and 328 to the reference voltage rail 334 when a clock signal Φ3 is asserted, thereby clamping the common-mode voltage at the first gain stage inputs 326 and 328 to a reference voltage of the reference voltage rail 334. As discussed below, clamping circuitry 312 repeatedly clamps the first gain stage inputs 326 and 328 to the reference voltage rail 334 to help minimize the common-mode voltage settling time after transient events. In some embodiments, as shown, clamping circuitry 312 includes switching devices 336 and 338, respectively, electrically coupled between the reference voltage rail 334 and the first gain stage inputs 326 and 328. When clock signal Φ3 is asserted, switching devices 336 and 338 are turned off to clamp the first gain stage inputs 326 and 328 to the reference voltage rail 334, respectively. When clock signal Φ3 is deasserted, switching devices 336 and 338 are turned on. For example, each of switching devices 336 and 338 includes one or more transistors. Without departing from the scope of this document, the configuration of the clamping circuit system 312 can be changed, for example, to include additional switching devices.

[0094] The first switching circuit system 316 is configured to: when the clamping circuit system 312 clamps the first gain stage inputs 326 and 328 to the reference voltage rail 334, that is, when the clock signal Φ3 is asserted, cause the first gain stage inputs 326 and 328 to be connected to the CCIA input V i_p and V i_nElectrical isolation. In some embodiments, as shown, the first switching circuit system 316 includes corresponding switching devices 340 and 342 electrically coupled in series with the positive input path 322 and the negative input path 324. Switching devices 340 and 342 are turned off when the clock signal Φ3 is deasserted; and switching devices 340 and 342 are turned on when the clock signal Φ3 is asserted. For example, each of switching devices 340 and 342 includes one or more transistors. Although the first switching circuit system 316 is shown as electrically coupled between the capacitive isolation stage 310 and the first gain stage 306, the first switching circuit system 316 may alternatively be electrically coupled between the first chopper 302 and the capacitive isolation stage 310.

[0095] In a specific embodiment, the first gain stage 306 performs a transconductance function, that is, it generates a differential output current signal in response to a difference in the input voltage signal. However, the configuration of the first gain stage 306 can be varied without departing from the scope of this document. Although the first gain stage 306 is shown as a single element for the sake of simplicity, it may include multiple elements.

[0096] The second chopper 304 is electrically coupled between the outputs 344 and 346 of the first gain stage 306 and the inputs 348 and 350 of the second gain stage 308. The second chopper 304 is controlled by clock signals Φ1 and Φ2 in the same manner as the first chopper 302. Specifically, when clock signal Φ1 is asserted, the second chopper 304 operates in its first operating state; and when clock signal Φ2 is asserted, the second chopper 304 operates in its second operating state. The first operating state is characterized by direct signal transmission, i.e., the second chopper 304 electrically couples the output 344 of the first gain stage to the positive output path 352, and the second chopper 304 electrically couples the output 346 of the first gain stage to the negative output path 354. The second operating state is characterized by reverse signal transmission, i.e., the second chopper 304 electrically couples the first gain stage output 344 to the negative output path 354, and the second chopper 304 electrically couples the first gain stage output 346 to the positive output path 352. The positive output path 352 is fed into the second gain stage input 348, and the negative output path 354 is fed into the second gain stage input 350. In some embodiments, the second chopper 304 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first and second operating states.

[0097] The second switching circuit system 318 is configured to electrically isolate the second gain stage inputs 348 and 350 from the first gain stage outputs 344 and 346 when the clamping circuit system 312 clamps the first gain stage inputs 326 and 328 to the reference voltage rail 334, i.e., when the clock signal Φ3 is asserted. In some embodiments, as shown, the second switching circuit system 318 includes corresponding switching devices 356 and 358 electrically coupled in series with the positive output path 352 and the negative output path 354. Switching devices 356 and 358 are turned off when the clock signal Φ3 is deasserted; and are turned on when the clock signal Φ3 is asserted. For example, each of the switching devices 356 and 358 includes one or more transistors. Although the second switching circuit system 318 is shown as electrically coupled between the second chopper 304 and the second gain stage 308, the second switching circuit system 318 can be electrically coupled between the first gain stage 306 and the second chopper 304 instead.

[0098] In a specific embodiment, as shown, the second gain stage 308 performs a transconductance function, and the CCIA 300 further includes feedback capacitors 360 and 362. Feedback capacitor 360 is electrically coupled between the input terminal 348 of the second gain stage and the output terminal 366 of the second gain stage 308. Feedback capacitor 362 is electrically coupled between the input terminal 350 of the second gain stage and the output terminal 368 of the second gain stage 308. Therefore, the second gain stage 308 is Miller-compensated. However, the configuration of the second gain stage 308 can be varied without departing from the scope of this document. Although the second gain stage 308 is shown as a single element for the sake of simplicity, it can include multiple elements without departing from the scope of this document.

[0099] The automatic zeroing circuit system 314 is electrically coupled to the output terminals 344 and 346 of the first gain stage. The automatic zeroing circuit system 314 includes a third gain stage 370, automatic zeroing capacitors 372 and 374, and automatic zeroing switching devices 376 and 378. Automatic zeroing capacitors 372 and 374 are electrically coupled to the output terminals 344 and 346 of the first gain stage via automatic zeroing switching devices 376 and 378, respectively. Automatic zeroing capacitors 372 and 374 are also electrically coupled to the input terminals 380 and 382 of the third gain stage, respectively. The output terminals 384 and 386 of the third gain stage 370 are electrically coupled to the output terminals 344 and 346 of the first gain stage, respectively. Automatic zeroing switching devices 376 and 378 are controlled by a clock signal Φ3; that is, when the clock signal Φ3 is asserted, automatic zeroing switching devices 376 and 378 are turned off, and when the clock signal Φ3 is deasserted, automatic zeroing switching devices 376 and 378 are turned on. For example, each of the automatic zero-adjustment switching devices 376 and 378 includes one or more transistors. As discussed below, the automatic zero-adjustment circuit system 314 injects current at the outputs of the first gain stage 344 and 346 to compensate for the output ripple caused by the first chopper 302 and the second chopper 304.

[0100] Controller 320 generates a first clock signal Φ1, a second clock signal Φ2, and a third clock signal Φ3. Controller 320 is formed from, for example, analog electrical circuitry, digital electrical circuitry, or a combination of analog and digital electrical circuitry. For example, in one embodiment, controller 320 is formed from a processor and an interface circuitry, wherein the interface circuitry electrically couples the processor to a chopper and switching device of the CCIA 300. In this embodiment, the processor executes instructions in the form of software or firmware to generate the first clock signal Φ1, the second clock signal Φ2, and the third clock signal Φ3. Although controller 320 is symbolically shown as a single element, controller 320 can be formed from multiple elements such as multiple integrated circuits and / or multiple discrete components.

[0101] In some embodiments, controller 320 generates a first clock signal Φ1 and a second clock signal Φ2, such that the first clock signal Φ1 and the second clock signal Φ2 are asserted in a complementary manner; that is, when the second clock signal Φ2 is deasserted, the first clock signal Φ1 is asserted, and vice versa. Therefore, in these embodiments, the first chopper 302 and the second chopper 304 consistently and repeatedly switch between their corresponding first operating states and second operating states. During each assertion of the first clock signal Φ1, controller 320 asserts the third clock signal Φ3 at least once, and during each assertion of the second clock signal Φ2, controller 320 also asserts the third clock signal Φ3 at least once, such that the third clock signal Φ3 is asserted at least once during each chopping cycle. Therefore, during each operation of the first chopper 302 and the second chopper 304 in their respective first operating states, the clamping circuit system 312 clamps the first gain stage inputs 326 and 328 to the reference voltage rail 334 at least once; and during each operation of the first chopper 302 and the second chopper 304 in their respective second operating states, the clamping circuit system 312 clamps the first gain stage inputs 326 and 328 to the reference voltage rail 334 at least once.

[0102] Figure 4 Graph 400 illustrates a first clock signal Φ1, a second clock signal Φ2, and a third clock signal Φ3 generated by controller 320 in one embodiment of CCIA 300. The vertical axis of graph 400 represents signal amplitude, and the horizontal axis represents time. In this specific embodiment, the clock signals are asserted when they are logic high. However, without departing from the scope of this document, CCIA 300 can be configured such that one or more of the first clock signal Φ1, the second clock signal Φ2, and the third clock signal Φ3 are asserted when they are logic low.

[0103] exist Figure 4In this embodiment, the first clock signal Φ1 and the second clock signal Φ2 are asserted in a complementary manner. Therefore, the input offset voltage of the first gain stage 306 and the noise at the first gain stage inputs 326 and 328 are shifted to a higher frequency. Additionally, a third clock signal Φ3 is asserted once during each assertion of the first clock signal Φ1; and a third clock signal Φ3 is also asserted once during each assertion of the second clock signal Φ2. Therefore, the clamping circuit system 312 repeatedly clamps the common-mode voltage at the capacitive isolation portion of the CCIA 300 (i.e., at the first gain stage inputs 326 and 328) to the reference voltage of the reference voltage rail 334 to repeatedly “reset” the common-mode voltage. Therefore, the first gain stage inputs 326 and 328 are significantly less susceptible to glitches due to transient events than conventional CCIAs because the common-mode voltage at the first gain stage inputs 326 and 328 is frequently reset. Therefore, CCIA 300 is significantly less prone to glitch generation due to common-mode transient events than conventional CCIA.

[0104] Furthermore, the automatic zeroing circuit system 314 utilizes the clamping circuit system 312 to help minimize the output ripple associated with the operation of the first chopper 302 and the second chopper 304. Specifically, when the third clock signal Φ3 is asserted, the clamping circuit system 312 shorts the first gain stage inputs 326 and 328 together, and therefore the first gain stage outputs 344 and 346 ideally have a common value when the third clock signal Φ3 is asserted. When the third clock signal Φ3 is asserted, i.e., when the clamping circuit system 312 clamps the first gain stage inputs 326 and 328 to the reference voltage rail 334, the automatic zeroing circuit system 314 uses the shorted first gain stage inputs 326 and 328 by sampling the first gain stage outputs 344 and 346 to determine the presence of ripple associated with the operation of the first chopper 302 and the second chopper 304. Specifically, when the third clock signal Φ3 is asserted, the automatic zeroing switching devices 376 and 378 are turned off, and the automatic zeroing capacitors 372 and 374 are charged to the corresponding voltages at the output terminals 344 and 346 of the first gain stage. The third gain stage 370 amplifies the voltage difference between the automatic zeroing capacitors 372 and 374 to generate compensation currents I. c_p and I c_n A compensation current I is injected at the output terminals 344 and 346 of the first gain stage. c_p and I c_n This compensates for the output ripple associated with the operation of the first chopper 302 and the second chopper 304. Therefore, the combination of the automatic zeroing circuitry 314 and the clamping circuitry 312 enables certain embodiments of the CCIA 300 to achieve lower output ripple than conventional CCIAs.

[0105] Increasing the frequency of assertions for the third clock signal Φ3 increases the AC common-mode rejection ratio (CMRR) of the CCIA 300. Therefore, in some embodiments, the controller 320 generates the third clock signal Φ3 such that it is asserted at least twice during each assertion of the first clock signal Φ1, and at least twice during each assertion of the second clock signal Φ2. In other words, the third clock signal Φ3 is asserted at least twice during each chopping cycle. For example, Figure 5 Is with Figure 4 The graph is similar to graph 500, but illustrates the clock signals of an alternative embodiment of the CCIA 300, wherein the third clock signal Φ3 is asserted twice during each assertion of the first clock signal Φ1, and twice during each assertion of the second clock signal Φ2. The controller 320 can be modified to add an extra number of assertions to the third clock signal Φ3 in each chopping cycle to further increase the CMRR of the CCIA 300.

[0106] Figure 6 Several embodiments of the CCIA 300 provide an analog output voltage V that responds to a 50-volt variation in the common-mode input voltage. 输出 The curve in graph 600. The vertical axis of graph 600 represents the output voltage V. 输出 Furthermore, the horizontal axis of curve 600 represents time. Curve 602 and... Figure 4 This corresponds to the CCIA 300 embodiment that generates clock signals in a manner similar to that used in [the example], and curve 604 is related to [the example]... Figure 5 This corresponds to an embodiment of the CCIA 300 that generates clock signals in a manner that... Furthermore, curve 606 corresponds to the clamping circuitry system 312, which is omitted from the CCIA 300. (As from...) Figure 6 It is evident that the clamping circuitry system 312 included in the CCIA 300 significantly reduces output voltage distortion in response to transient events of the common-mode input, and the increased frequency of the third clock signal Φ3 assertion further reduces output voltage distortion.

[0107] The automatic zeroing circuitry 314 can be omitted from the CCIA 300 to reduce cost and complexity, but this also has the disadvantage of increasing output ripple. For example, Figure 7 The CCIA 700, such as the CCIA 300, is shown, but the automatic zeroing circuit system 314 is omitted.

[0108] One possible application of the instrumentation amplifier disclosed herein is for current sensing applications, such as sensing current flowing through inductive loads, such as motors or solenoids driven by pulse-width modulation (PWM) or pulse-frequency modulation (PFM) voltages. Current sensing measurements in these applications typically need to be very accurate to ensure proper control of the inductive load. However, accurate current sensing in these applications is challenging because the current sensing amplifier must be able to sense small differential voltages (e.g., in the millivolt range) superimposed on large PWM or PFM common-mode voltages (e.g., in the tens of volts range). Furthermore, as discussed above, PWM or PFM common-mode voltages can have edge slew rates as high as 500 volts per microsecond, which can distort the output of conventional instrumentation amplifiers. However, the clamping circuitry system 312 in some embodiments of the CCIA 300 gives the CCIA 300 a large CMRR, thereby enabling the CCIA 300 to substantially suppress PWM and PFM common-mode voltages in current sensing applications. Therefore, certain embodiments of the CCIA 300 enable accurate current sensing in applications where inductive loads are driven by PWM or PFM voltages.

[0109] Figure 8 A method 800 for reducing the common-mode settling time of a CCIA is illustrated. In step 802, during each operation of the first and second choppers of the CCIA in their respective first operating states, the inputs of the first gain stage of the CCIA are clamped to a reference voltage rail at least once. In one example of step 802, during each operation of the first chopper 302 and the second chopper 304 in their respective first operating states, a clamping circuit system 312 clamps the inputs 326 and 328 of the first gain stage to the reference voltage rail 334 at least once. In step 804, during each operation of the first and second choppers of the CCIA in their respective second operating states, the inputs of the first gain stage of the CCIA are clamped to the reference voltage rail at least once. In one example of step 804, during each operation of the first chopper 302 and the second chopper 304 in their respective second operating states, the clamping circuit system 312 clamps the inputs 326 and 328 of the first gain stage to the reference voltage rail 334 at least once.

[0110] Method 800 may optionally further include step 806, wherein a current is injected at the output of the first gain stage to compensate for the output ripple caused by the first and second choppers. Step 806 is performed, for example, in parallel with steps 802 and 804. In one example of step 806, a compensation current I is injected into the third gain stage 370 at the outputs 344 and 346 of the first gain stage. c_p and I c_nTo compensate for the output ripple caused by the first chopper 302 and the second chopper 304. The outputs 344 and 346 of the first gain stage 306 are sampled when the inputs 326 and 328 of the first gain stage are clamped to the reference voltage rail 334, for example, to determine the compensation current I. c_p and I c_n The amplitude.

[0111] The applicant has further determined that the principle of repeatedly clamping the common-mode voltage in a capacitively coupled amplifier to a reference voltage to help minimize the common-mode voltage settling time after a transient event is not limited to CCIA. Rather, the principle can be applied to many other capacitively coupled amplifiers. See below for reference. Figures 9 to 12 Several examples of how the principle of repeatedly clamping the common-mode voltage to a reference voltage can be applied to amplifiers other than those in a CCIA are discussed. However, it should be understood that this principle is not limited to the specific topology discussed herein, but can be applied to many other capacitively coupled amplifiers.

[0112] Figure 9 A capacitively coupled linear amplifier 900 is shown, configured to repeatedly clamp the common-mode voltage at the capacitive isolation section of the amplifier to a reference voltage. The amplifier 900 includes a capacitive isolation stage 902, a gain stage 904, a switching circuit system 906, a clamping circuit system 908, and a controller 910. The capacitive isolation stage 902 includes a first capacitor 912 and a second capacitor 914. The first capacitor 912 is electrically coupled to the amplifier input V. i_p Between the input terminal 916 of the gain stage 904 and the second capacitor 914, which is electrically coupled to the amplifier input terminal V... i_n Between the input terminal 918 of the gain stage 904 and the input terminal 918, the gain stage 904 is communicatively coupled to the capacitor isolation stage 902. The capacitor isolation stage 902 is electrically coupled to the amplifier input terminal V. i_p and V i_n The AC signal between the inputs 916 and 918 of the gain stage is blocked, while the transmission of the DC signal is also blocked. Without departing from the scope of this document, the capacitive isolation stage 902 may include an additional capacitor. Alternatively, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitive isolation stage 902.

[0113] Clamping circuitry 908 is electrically coupled between gain stage inputs 916 and 918 and a reference voltage rail 920. In some embodiments, the reference voltage rail 920 has a fixed potential set to achieve the desired common-mode voltage at gain stage inputs 916 and 918. Clamping circuitry 908 is configured to clamp gain stage inputs 916 and 918 to the reference voltage rail 920 when a clock signal Φ is asserted, thereby clamping the common-mode voltage to a reference voltage of the reference voltage rail 920. As discussed below, controller 910 repeatedly asserts the clock signal Φ to help minimize the common-mode voltage settling time following transient events. In some embodiments, as shown, clamping circuitry 908 includes switching devices 922 and 924, respectively, electrically coupled between the reference voltage rail 920 and gain stage inputs 916 and 918. When the clock signal Φ is asserted, switching devices 922 and 924 are turned off to clamp the gain stage inputs 916 and 918 to the reference voltage rail 920, respectively. When the clock signal Φ is deasserted, switching devices 922 and 924 are turned on. For example, each of switching devices 922 and 924 includes one or more transistors. Without departing from the scope of this document, the configuration of the clamping circuit system 908 can be changed, for example, to include additional switching devices.

[0114] The switching circuit system 906 is configured to: when the clamping circuit system 908 clamps the common-mode voltage to the voltage of the reference voltage rail 920, i.e., when the clock signal Φ is asserted, cause the gain stage 904 to switch with the amplifier input V. i_p and V i_n Electrical isolation. In some embodiments, as shown, the switching circuit system 906 includes corresponding switching devices 926 and 928 electrically coupled in series to the gain stage inputs 916 and 918. Switching devices 926 and 928 are turned off when the clock signal Φ is deasserted; and are turned on when the clock signal Φ is asserted. For example, each of switching devices 926 and 928 includes one or more transistors.

[0115] Gain stage 904 can have virtually any configuration, as long as it generates a signal at gain stage output 930 in response to the signal difference at gain stage inputs 916 and 918. For example, in some embodiments, gain stage 904 is configured as an instrumentation amplifier. Although gain stage 904 is shown as a single element for the sake of simplicity, gain stage 904 may include multiple elements. Depending on the configuration of gain stage 904, the signal at gain stage output 930 can be a voltage signal or a current signal. In some embodiments of amplifier 900, the signal at gain stage output 930 is a differential signal.

[0116] Controller 910 generates a clock signal Φ, which is repeatedly asserted. Therefore, clamping circuitry 908 repeatedly clamps the gain stage inputs 916 and 918 to the reference voltage rail 920. Consequently, the gain stage inputs 916 and 918 are significantly less susceptible to glitches due to transient events than in a conventional CCIA, because the common-mode voltages at the gain stage inputs 916 and 918 are frequently reset to the reference voltage of the reference voltage rail 920. Therefore, for similar reasons as discussed above with respect to CCIA 300, amplifier 900 is advantageously significantly less susceptible to glitches due to common-mode transient events than a conventional capacitively coupled differential amplifier.

[0117] Figure 10 Graph 1000 illustrates a clock signal Φ generated by controller 910 as in one embodiment of amplifier 900. The vertical axis of graph 1000 represents the signal amplitude, and the horizontal axis represents time. In this specific embodiment, the clock signal Φ is asserted when it is logic high. However, without departing from the scope of this document, amplifier 1000 may be configured such that the clock signal Φ is asserted when it is logic low. Figure 10 In the embodiment, controller 910 asserts the clock signal Φ at a frequency f. However, without departing from the scope of this document, controller 910 can be modified to assert the clock signal Φ at different frequencies, or even in a non-periodic manner. The CMRR of amplifier 900 typically increases with increasing frequency f, and therefore, it is desirable to configure amplifier 910 such that frequency f is as large as possible.

[0118] Figure 11 A chopper-stabilized instrumentation amplifier 1100 is shown, comprising a first chopper 1102, a second chopper 1104, a first gain stage 1106, a second gain stage 1108, a capacitor isolation stage 1110, a clamping circuit system 1112, a chopper-stabilized circuit system 1114, a first switching circuit system 1116, a second switching circuit system 1118, and a controller 1120. The first chopper 1102 is electrically coupled to (a) the amplifier input terminal V. i_p and V i_n Between (b) capacitor isolation stage 1110. The first chopper 1102 is controlled by clock signals Φ1 and Φ2, and includes at least the following components: Figure 3The first chopper 302 has a first operating state and a second operating state similar to the first operating state. When clock signal Φ1 is asserted, the first chopper 1102 operates in its first operating state; and when clock signal Φ2 is asserted, the first chopper 1102 operates in its second operating state. In some embodiments, the first chopper 1102 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first operating state and the second operating state.

[0119] A capacitive isolation stage 1110 is electrically coupled between the input terminals 1122 and 1124 of the first chopper 1102 and the second chopper 1104. The capacitive isolation stage 1110 electrically couples the alternating current (AC) signal between the first chopper 1102 and the second chopper 1104 while blocking the transmission of DC signals. In some embodiments, as shown, the capacitive isolation stage 1110 includes a first capacitor 1130 and a second capacitor 1132. In these embodiments, the first capacitor 1130 is electrically coupled in series with the input terminal 1122 of the second chopper, and the second capacitor 1132 is electrically coupled in series with the input terminal 1124 of the second chopper. Without departing from the scope of this document, the capacitive isolation stage 1110 may include additional capacitors. Furthermore, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitive isolation stage 1110.

[0120] Clamping circuitry 1112 is electrically coupled between the second chopper inputs 1122 and 1124 and a reference voltage rail 1134. In some embodiments, the reference voltage rail 1134 has a fixed potential set to achieve the desired common-mode voltage at the second chopper inputs 1122 and 1124. Clamping circuitry 1112 is configured to clamp the second chopper inputs 1122 and 1124 to the reference voltage rail 1134 when the clock signal Φ3 is asserted. Clamping circuitry 1112 repeatedly clamps the second chopper inputs 1122 and 1124 to the reference voltage rail 1134, thereby repeatedly resetting the common-mode voltage in the instrumentation amplifier 1100 to help minimize the common-mode voltage settling time after transient events. In some embodiments, as shown, the clamping circuit system 1112 includes switching devices 1136 and 1138, respectively electrically coupled between a reference voltage rail 1134 and second chopper inputs 1122 and 1124. When a clock signal Φ3 is asserted, switching devices 1136 and 1138 are turned off to clamp the second chopper inputs 1122 and 1124 to the reference voltage rail 1134, respectively. When the clock signal Φ3 is deasserted, switching devices 1136 and 1138 are turned on. For example, each of switching devices 1136 and 1138 includes one or more transistors. The configuration of the clamping circuit system 1112 can be changed, for example, to include additional switching devices, without departing from the scope of this document.

[0121] The first switching circuit system 1116 is configured to: when the clamping circuit system 1112 clamps the second chopper inputs 1122 and 1124 to the reference voltage rail 1134, that is, when the clock signal Φ3 is asserted, cause the second chopper inputs 1122 and 1124 to be connected to the CCIA input V i_p and V i_n Electrical isolation. In some embodiments, as shown, the first switching circuit system 1116 includes corresponding switching devices 1140 and 1142 electrically coupled in series with the inputs of the second chopper 1122 and 1124. Switching devices 1140 and 1142 are turned off when the clock signal Φ3 is deasserted; and switching devices 1140 and 1142 are turned on when the clock signal Φ3 is asserted. For example, each of switching devices 1140 and 1142 includes one or more transistors. Although the first switching circuit system 1116 is shown as electrically coupled between the capacitive isolation stage 1110 and the second chopper 1104, the first switching circuit system 1116 may alternatively be electrically coupled between the first chopper 1102 and the capacitive isolation stage 1110.

[0122] The second chopper 1104 is electrically coupled between the capacitive isolation stage 1110 and the first gain stage 1106. The second chopper 1104 is controlled by clock signals Φ1 and Φ2 in a manner similar to the first chopper 1102. Specifically, when clock signal Φ1 is asserted, the second chopper 1104 operates in its first operating state; and when clock signal Φ2 is asserted, the second chopper 1104 operates in its second operating state. In some embodiments, the second chopper 1104 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first and second operating states.

[0123] The first gain stage 1106 is communicatively coupled to the capacitive isolation stage 1110 via the second chopper 1140. In a specific embodiment, the first gain stage 1106 performs a transconductance function, i.e., it generates a differential output current signal in response to a difference in the input voltage signal. However, the configuration of the first gain stage 1106 can be varied without departing from the scope of this document. Although the first gain stage 1106 is shown as a single element for the sake of simplicity, it may include multiple elements.

[0124] The second switching circuit system 1118 is configured to electrically isolate the second gain stage 1108 from the first gain stage 1106 when the clamping circuit system 1112 clamps the second chopper inputs 1122 and 1124 to the reference voltage rail 1134, i.e., when the clock signal Φ3 is asserted. In some embodiments, as shown, the second switching circuit system 1118 includes corresponding switching devices 1144 and 1146 electrically coupled in series with the inputs 1148 and 1150 of the second gain stage 1108. Switching devices 1144 and 1146 are turned off when the clock signal Φ3 is deasserted; and are turned on when the clock signal Φ3 is asserted. For example, each of the switching devices 1144 and 1146 includes one or more transistors.

[0125] In a specific embodiment, as shown, the second gain stage 1108 performs a transconductance function, and the amplifier 1100 further includes feedback capacitors 1152 and 1154. Feedback capacitor 1152 is electrically coupled between the input terminal 1148 of the second gain stage and the output terminal 1156 of the second gain stage 1108. Feedback capacitor 1154 is electrically coupled between the input terminal 1150 of the second gain stage and the output terminal 1158 of the second gain stage 1108. Therefore, the second gain stage 1108 is Miller-compensated. However, the configuration of the second gain stage 1108 can be varied without departing from the scope of this document. Although the second gain stage 1108 is shown as a single element for the sake of brevity, it can include multiple elements without departing from the scope of this document.

[0126] Figure 12 A chopper stabilization circuit system 1114 is shown, comprising a third chopper 1202, a fourth chopper 1204, a third gain stage 1206, a fourth gain stage 1208, a fifth gain stage 1210, feedback capacitors 1214 and 1216, feedback capacitors 1218 and 1220, and resistors 1222 and 1224. Resistors 1222 and 1224 together form a voltage divider across the output of the second gain stage 1108, and the third chopper 1202 is electrically coupled between resistor 1222 and the second capacitor isolation stage 1212. The third chopper 1202 is controlled by clock signals Φ1 and Φ2 in a manner similar to the first chopper 1102. Specifically, when clock signal Φ1 is asserted, the third chopper 1202 operates in its first operating state; and when clock signal Φ2 is asserted, the third chopper 1202 operates in its second operating state. In some embodiments, the third chopper 1202 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first operating state and the second operating state.

[0127] A second capacitor isolation stage 1212 is electrically coupled between the inputs 1226 and 1228 of the third chopper 1202 and the third gain stage 1206. The capacitor isolation stage 1212 electrically couples the alternating current (AC) signal between the third chopper 1202 and the third gain stage 1206 while blocking the transmission of DC signals. In some embodiments, as shown, the capacitor isolation stage 1212 includes a third capacitor 1230 and a fourth capacitor 1232. In these embodiments, the third capacitor 1230 is electrically coupled in series with the input 1226 of the third gain stage, and the fourth capacitor 1232 is electrically coupled in series with the input 1228 of the third gain stage. Without departing from the scope of this document, the capacitor isolation stage 1212 may include additional capacitors. Furthermore, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitor isolation stage 1212.

[0128] The third gain stage 1206 is communicatively coupled between the second capacitor isolation stage 1212 and the fourth chopper 1204. In a specific embodiment, the third gain stage 1206 performs a transconductance function, i.e., it generates a differential output current signal in response to a difference in the input voltage signal. However, the configuration of the third gain stage 1206 can be varied without departing from the scope of this document. Although the third gain stage 1206 is shown as a single element for the sake of simplicity, it may include multiple elements.

[0129] The fourth chopper 1204 is electrically coupled between the third gain stage 1206 and the fourth gain stage 1208. The fourth chopper 1204 is controlled by clock signals Φ1 and Φ2 in a manner similar to the first chopper 1102. Specifically, when clock signal Φ1 is asserted, the fourth chopper 1204 operates in its first operating state; and when clock signal Φ2 is asserted, the fourth chopper 1204 operates in its second operating state. In some embodiments, the fourth chopper 1204 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first and second operating states.

[0130] The fourth gain stage 1208 is electrically coupled between the fourth chopper 1204 and the fifth gain stage 1210. In a specific embodiment, the fourth gain stage 1208 performs a transconductance function. Feedback capacitors 1214 and 1216 are electrically coupled between the corresponding input and output terminals of the fourth gain stage 1208. The configuration of the fourth gain stage 1208 can be varied without departing from the scope of this document. Although the fourth gain stage 1208 is shown as a single element for the sake of simplicity, it can include multiple elements without departing from the scope of this document. Feedback capacitors 1218 and 1220 are electrically coupled between the corresponding output terminals of the second gain stage 1108 and the corresponding input terminals of the fourth gain stage 1208.

[0131] The fifth gain stage 1210 is electrically coupled between the fourth gain stage 1208 and the inputs 1148 and 1150 of the second gain stage. In a specific embodiment, the fifth gain stage 1210 performs a transconductance function, but the configuration of the fifth gain stage 1210 can be varied without departing from the scope of this document. Although the fifth gain stage 1210 is shown as a single element for the sake of simplicity, it can include multiple elements without departing from the scope of this document.

[0132] Controller 1120 ( Figure 11 The controller 1120 generates a first clock signal Φ1, a second clock signal Φ2, and a third clock signal Φ3. The controller 1120 is formed from, for example, an analog electrical circuit system, a digital electrical circuit system, or a combination of analog and digital electrical circuit systems. Although the controller 1120 is symbolically shown as a single element, it can be formed from multiple elements such as multiple integrated circuits and / or multiple discrete components.

[0133] In some embodiments, controller 1120 generates a first clock signal Φ1 and a second clock signal Φ2 such that the first clock signal Φ1 and the second clock signal Φ2 are asserted in a complementary manner, i.e., the first clock signal Φ1 is asserted when the second clock signal Φ2 is deasserted, and vice versa. Therefore, in these embodiments, the first chopper 1102, the second chopper 1104, the third chopper 1202, and the fourth chopper 1204 consistently and repeatedly switch between their corresponding first and second operating states. The first gain stage 1106 forms part of a high-frequency, low-gain first path, and the third gain stage 1206 forms part of a low-offset, low-frequency, and low-gain second path. Chopper stabilization circuitry 1114 corrects the input offset voltage of the first gain stage 1106 to a degree that the second path has a higher gain than the first path.

[0134] During each assertion of the first clock signal Φ1, the controller 1120 asserts the third clock signal Φ3 at least once, and during each assertion of the second clock signal Φ2, the controller 1120 also asserts the third clock signal Φ3 at least once, such that the third clock signal Φ3 is asserted at least once during each chopping cycle. Therefore, during each operation of the first chopper 1102, the second chopper 1104, the third chopper 1202, and the fourth chopper 1204 in their respective first operating states, the clamping circuit system 1112 clamps the second chopper inputs 1122 and 1124 to the reference voltage rail 1134 at least once; and during each operation of the first chopper 1102, the second chopper 1104, the third chopper 1202, and the fourth chopper 1204 in their respective second operating states, the clamping circuit system 1112 clamps the second chopper inputs 1122 and 1124 to the reference voltage rail 1134 at least once. Therefore, the clamping circuit system 1112 repeatedly clamps the common-mode voltage at the second chopper inputs 1122 and 1124 to the reference voltage of the reference voltage rail 1134, thereby repeatedly “resetting” the common-mode voltage. Thus, the amplifier 1100 is advantageously significantly less susceptible to glitches due to common-mode transient events than a conventional amplifier without the clamping circuit system 1112.

[0135] Figure 13An embodiment of the new CCIA, CCIA 1300, is shown. CCIA 1300 is configured to: (a) isolate a gain stage from an amplifier input; and (b) clamp the common-mode voltage at the capacitive isolation portion of the CCIA to a reference voltage in response to a detected change in common-mode voltage. CCIA 1300 includes a first chopper 1302, a second chopper 1304, a first gain stage 1306, a second gain stage 1308, a capacitive isolation stage 1310, a clamping circuit system 1312, an automatic zeroing circuit system 1314, a first switching circuit system 1316, a second switching circuit system 1318, and a controller 1320.

[0136] The first chopper 1302 is electrically coupled to (a) the CCIA input terminal V. i_p and V i_n Between (b) capacitor isolation stage 1310. The first chopper 1302 is controlled by clock signals Φ1 and Φ2, and includes at least a first operating state and a second operating state. When clock signal Φ1 is asserted, the first chopper 1302 operates in its first operating state; and when clock signal Φ2 is asserted, the first chopper 1302 operates in its second operating state. The first operating state is characterized by direct signal transmission, that is, the first chopper 1302 transmits the CCIA input V... i_p Electrically coupled to the positive input path 1322, and the first chopper 1302 converts the CCIA input terminal V... i_n Electrically coupled to the negative input path 1324. The second operating state is characterized by the reverse signal transmission, that is, the first chopper 1302 converts the CCIA input V... i_p Electrically coupled to the negative input path 1324, and the first chopper 1302 converts the CCIA input terminal V... i_n Electrically coupled to the positive input path 1322. The positive input path 1322 feeds into the input terminal 1326 of the first gain stage 1306, and the negative input path 1324 feeds into the input terminal 1328 of the first gain stage 1306. In some embodiments, the first chopper 1302 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first operating state and the second operating state.

[0137] A capacitive isolation stage 1310 is electrically coupled between the first chopper 1302 and the first gain stage inputs 1326 and 1328, such that the first gain stage 1306 is communicatively coupled to the capacitive isolation stage 1310. The capacitive isolation stage 1310 electrically couples the alternating current (AC) signal between the first chopper 1302 and the first gain stage 1306 while blocking the transmission of DC signals. In some embodiments, as shown, the capacitive isolation stage 1310 includes a first capacitor 1330 and a second capacitor 1332. In these embodiments, the first capacitor 1330 is electrically coupled in series with the positive input path 1322, and the second capacitor 1332 is electrically coupled in series with the negative input path 1324. Without departing from the scope of this document, the capacitive isolation stage 1310 may include additional capacitors. Furthermore, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitive isolation stage 1310.

[0138] Clamping circuitry 1312 is electrically coupled between the first gain stage inputs 1326 and 1328 and a reference voltage rail 1334. In some embodiments, the reference voltage rail 1334 has a fixed potential set to achieve the desired common-mode voltage at the first gain stage inputs 1326 and 1328. Clamping circuitry 1312 is configured to clamp the first gain stage inputs 1326 and 1328 to the reference voltage rail 1334 when the clock signal Φ3 is asserted, thereby clamping the common-mode voltage at the first gain stage inputs 1326 and 1328 to the reference voltage of the reference voltage rail 1334. As discussed below, in response to the CCIA input V... i_p and V i_n When the common-mode voltage changes at a point, clock signal Φ3 is asserted to help minimize the common-mode voltage settling time following a transient event. In some embodiments, as shown, clamping circuitry 1312 includes switching devices 1336 and 1338, respectively electrically coupled between a reference voltage rail 1334 and first gain stage inputs 1326 and 1328. When clock signal Φ3 is asserted, switching devices 1336 and 1338 are turned off to clamp the first gain stage inputs 1326 and 1328 to the reference voltage rail 1334, respectively. When clock signal Φ3 is deasserted, switching devices 1336 and 1338 are turned on. For example, each of switching devices 1336 and 1338 includes one or more transistors. The configuration of clamping circuitry 1312 can be changed, for example, to include additional switching devices, without departing from the scope of this document.

[0139] The first switching circuit system 1316 is configured to: when the clamping circuit system 1312 clamps the first gain stage inputs 1326 and 1328 to the reference voltage rail 1334, that is, when the clock signal Φ3 is asserted, cause the first gain stage inputs 1326 and 1328 to be connected to the CCIA input Vi_p and V i_n Electrical isolation. In some embodiments, as shown, the first switching circuit system 1316 includes corresponding switching devices 1340 and 1342 electrically coupled in series with the positive input path 1322 and the negative input path 1324. Switching devices 1340 and 1342 are turned off when the clock signal Φ3 is deasserted; and switching devices 1340 and 1342 are turned on when the clock signal Φ3 is asserted. For example, each of switching devices 1340 and 1342 includes one or more transistors. Although the first switching circuit system 1316 is shown as electrically coupled between the capacitive isolation stage 1310 and the first gain stage 1306, the first switching circuit system 1316 may alternatively be electrically coupled between the first chopper 1302 and the capacitive isolation stage 1310.

[0140] The first gain stage 1306 is communicatively coupled to the capacitive isolation stage 1310 via a first switching circuit system 1316. In a specific embodiment, the first gain stage 1306 performs a transconductance function, i.e., it generates a differential output current signal in response to a difference in the input voltage signal. However, the configuration of the first gain stage 1306 can be varied without departing from the scope of this document. Although the first gain stage 1306 is shown as a single element for the sake of simplicity, it may include multiple components.

[0141] The second chopper 1304 is electrically coupled between the outputs 1344 and 1346 of the first gain stage 1306 and the inputs 1348 and 1350 of the second gain stage 1308. The second chopper 1304 is controlled by clock signals Φ1 and Φ2 in the same manner as the first chopper 1302. Specifically, when clock signal Φ1 is asserted, the second chopper 1304 operates in its first operating state; and when clock signal Φ2 is asserted, the second chopper 1304 operates in its second operating state. The first operating state is characterized by direct signal transmission, i.e., the second chopper 1304 electrically couples the output 1344 of the first gain stage to the positive output path 1352, and the second chopper 1304 electrically couples the output 1346 of the first gain stage to the negative output path 1354. The second operating state is characterized by reverse signal transmission, i.e., the second chopper 1304 electrically couples the first gain stage output 1344 to the negative output path 1354, and the second chopper 1304 electrically couples the first gain stage output 1346 to the positive output path 1352. The positive output path 1352 is fed into the second gain stage input 1348, and the negative output path 1354 is fed into the second gain stage input 1350. In some embodiments, the second chopper 1304 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first and second operating states.

[0142] The second switching circuit system 1318 is configured to electrically isolate the second gain stage inputs 1348 and 1350 from the first gain stage outputs 1344 and 1346 when the clamping circuit system 1312 clamps the first gain stage inputs 1326 and 1328 to the reference voltage rail 1334, i.e., when the clock signal Φ3 is asserted. In some embodiments, as shown, the second switching circuit system 1318 includes corresponding switching devices 1356 and 1358 electrically coupled in series with the positive output path 1352 and the negative output path 1354. Switching devices 1356 and 1358 are turned off when the clock signal Φ3 is deasserted; and are turned on when the clock signal Φ3 is asserted. For example, each of the switching devices 1356 and 1358 includes one or more transistors. Although the second switching circuit system 1318 is shown as electrically coupled between the second chopper 1304 and the second gain stage 1308, the second switching circuit system 1318 can be electrically coupled between the first gain stage 1306 and the second chopper 1304 instead.

[0143] In a specific embodiment, as shown, the second gain stage 1308 performs a transconductance function, and the CCIA 1300 further includes feedback capacitors 1360 and 1362. Feedback capacitor 1360 is electrically coupled between the input terminal 1348 of the second gain stage and the output terminal 1366 of the second gain stage 1308. Feedback capacitor 1362 is electrically coupled between the input terminal 1350 of the second gain stage and the output terminal 1368 of the second gain stage 1308. Therefore, the second gain stage 1308 is Miller-compensated. However, the configuration of the second gain stage 1308 can be varied without departing from the scope of this document. Although the second gain stage 1308 is shown as a single element for the sake of simplicity, it can include multiple components without departing from the scope of this document.

[0144] The automatic zeroing circuit system 1314 is electrically coupled to the output terminals 1344 and 1346 of the first gain stage. The automatic zeroing circuit system 1314 includes a third gain stage 1370, automatic zeroing capacitors 1372 and 1374, and automatic zeroing switching devices 1376 and 1378. Automatic zeroing capacitors 1372 and 1374 are electrically coupled to the output terminals 1344 and 1346 of the first gain stage via automatic zeroing switching devices 1376 and 1378, respectively. Automatic zeroing capacitors 1372 and 1374 are also electrically coupled to the input terminals 1380 and 1382 of the third gain stage, respectively. The output terminals 1384 and 1386 of the third gain stage 1370 are electrically coupled to the output terminals 1344 and 1346 of the first gain stage, respectively. Automatic zeroing switching devices 1376 and 1378 are controlled by clock signal Φ3; that is, automatic zeroing switching devices 1376 and 1378 are turned off when clock signal Φ3 is asserted, and are turned on when clock signal Φ3 is deasserted. For example, each of automatic zeroing switching devices 1376 and 1378 includes one or more transistors. As discussed below, the automatic zeroing circuit system 1314 injects current at the outputs of the first gain stage 1344 and 1346 to compensate for the output ripple caused by the first chopper 1302 and the second chopper 1304.

[0145] Controller 1320 includes a timing subsystem 1388 and a common-mode response subsystem 1390. As discussed below, timing subsystem 1388 is configured to generate a first clock signal Φ1 and a second clock signal Φ2, and common-mode response subsystem 1390 is configured to generate a third clock signal Φ3. Controller 1320 is formed from, for example, analog electrical circuitry, digital electrical circuitry, or a combination of analog and digital electrical circuitry. For example, in one embodiment, controller 1320 is formed from a processor and an interface circuitry, wherein the interface circuitry electrically couples the processor to a chopper and switching device of CCIA 1300. In this embodiment, the processor executes instructions in the form of software or firmware to generate the first clock signal Φ1, the second clock signal Φ2, and the third clock signal Φ3. Although controller 1320 is symbolically shown as a single element, controller 1320 may be formed from multiple elements such as multiple integrated circuits and / or multiple discrete components. Furthermore, although the timing subsystem 1388 and the common-mode response subsystem 1390 are shown as separate elements, these two subsystems may share common components or even be part of a common subsystem.

[0146] In some embodiments, the timing subsystem 1388 generates a first clock signal Φ1 and a second clock signal Φ2 such that the first clock signal Φ1 and the second clock signal Φ2 are asserted in a complementary manner; that is, the first clock signal Φ1 is asserted when the second clock signal Φ2 is deasserted, and vice versa. Therefore, in these embodiments, the first chopper 1302 and the second chopper 1304 consistently and repeatedly switch between their corresponding first and second operating states.

[0147] The common-mode response subsystem 1390 is configured to respond to CCIA input V. i_p and V i_n The change in the common-mode voltage at the location is used to assert the third clock signal Φ3. In some embodiments, the common-mode response subsystem 1390 responds to the CCIA input V. i_p and V i_n The rate of change of the common-mode voltage at the point exceeds a predetermined threshold, or in other words, in response to the CCIA input V. i_p and V i_n The common-mode voltage slew rate at a given threshold is used to assert the third clock signal Φ3. In some embodiments, the common-mode acknowledgment subsystem 1390 asserts the third clock signal Φ3 at least continuously with respect to the CCIA input V. i_p and V i_n The common-mode voltage slew rate exceeds a predetermined threshold for a period of time; in some other embodiments, after detecting that the common-mode voltage slew rate exceeds the predetermined threshold, the common-mode acknowledgment subsystem 1390 causes a third clock signal Φ3 to assert for a predetermined duration. The predetermined duration is selected, for example, to be greater than the expected duration of common-mode voltage changes under expected operating conditions. Alternatively or additionally, in some embodiments, the common-mode acknowledgment subsystem 1390 responds to the CCIA input V i_p and V i_n The change in the common-mode voltage amplitude at a given point exceeds a predetermined threshold to assert the third clock signal Φ3.

[0148] Figure 14 A common-mode response subsystem 1400 is illustrated, which is a possible embodiment of the common-mode response subsystem 1390. The common-mode response subsystem 1400 includes a conversion detector 1402 and a comparator circuit system 1404. The detector 1402 generates a response indicating the CCIA input V. i_p and V i_nThe conversion signal 1406 represents the rate of change of the common-mode voltage at a given location. The comparator circuitry 1404 compares the conversion signal 1406 with a predetermined threshold 1408, and asserts a third clock signal Φ3 in response to the conversion signal 1406 exceeding the predetermined threshold 1408. In some embodiments, the comparator circuitry 1404 implements a hysteresis to prevent the third clock signal Φ3 from oscillating between an assertion state and a deassertion state.

[0149] Figure 15 Graph 1500 shows an example of how an embodiment of the CCIA 1300 responds to changes in common-mode voltage. Figure 15 Including the CCIA input terminal V i_p and V i_n The common-mode voltage curve 1502 is shown, along with corresponding curves representing the first clock signal Φ1, the second clock signal Φ2, and the third clock signal Φ3. The vertical axis of curve 1500 represents the signal amplitude, and the horizontal axis of curve 1500 represents time. In this specific embodiment, the clock signal is asserted when it is logic high. However, without departing from the scope of this document, the CCIA 1300 can be configured such that one or more of the first clock signal Φ1, the second clock signal Φ2, and the third clock signal Φ3 are asserted when they are logic low.

[0150] exist Figure 15 In the example, the timing subsystem 1388 generates a first clock signal Φ1 and a second clock signal Φ2 and asserts them in a complementary manner. Therefore, the input offset voltage of the first gain stage 1306 and the noise at the inputs 1326 and 1328 of the first gain stage are shifted to a higher frequency. At time t1, the CCIA input V... i_p and V i_n The magnitude of the common-mode voltage at point t1 changes at a high slew rate ΔV1, and the common-mode response subsystem 1390 detects this change in the common-mode voltage and responds accordingly to assert the third clock signal Φ3. At time t2, the CCIA input V... i_p and V i_n The amplitude of the common-mode voltage at the location changes at a higher slew rate ΔV2, and the common-mode response subsystem 1390 detects this change in the common-mode voltage amplitude and, in response, asserts the third clock signal Φ3.

[0151] Therefore, when the third clock signal Φ3 is asserted, the first switching circuit system 1316 causes the first gain stage 1306 to switch with the CCIA input V. i_p and V i_nThe common-mode voltage variation is isolated, thus preventing the common-mode voltage variation from reaching the first gain stage 1306. Therefore, the inputs 1326 and 1328 of the first gain stage are significantly less susceptible to glitches due to transient events than conventional CCIAs. Furthermore, the clamping circuit system 1312 responds to the CCIA input V... i_p and V i_n The common-mode voltage change at the point clamps the first gain stage inputs 1326 and 1328 to the reference voltage of the reference voltage rail 1334, thereby "resetting" the common-mode voltage to the reference voltage of the reference voltage rail 1334. Therefore, the CCIA 1300 is advantageously significantly less susceptible to glitches due to common-mode transient events than a conventional CCIA.

[0152] Furthermore, in some embodiments, during each chopping cycle, the common-mode response subsystem 1390 asserts the third clock signal Φ3 at least once, regardless of changes in the common-mode voltage. For example, Figure 16 Graph 1600 illustrates another example of the operation of an embodiment of the CCIA 1300. In this embodiment, the common-mode response subsystem 1390 is configured to assert the third clock signal Φ3 at least once during each chopping cycle, and in response to the CCIA input V i_p and V i_n The third clock signal Φ3 is asserted when the slew rate and / or amplitude variation of the common-mode voltage exceeds a predetermined threshold. This repeated assertion of the third clock signal Φ3 increases the AC common-mode rejection ratio (CMRR) of the CCIA 1300.

[0153] Figure 17 This is graph 1700, showing the analog output voltage of a CCIA 1300 embodiment in response to a 50-volt change in the common-mode input voltage. The vertical axis of graph 1700 represents the voltage magnitude, and the horizontal axis represents time. Curve 1702 represents the voltage at the CCIA input V. i_p and V i_n The common-mode voltage at the location, and curve 1704 represents the output voltage V of the CCIA 1300. 输出 Furthermore, curve 1706 indicates that the output voltage V of the clamping circuit system 1312 was omitted from the CCIA 1300. 输出 For example from Figure 17 It is evident that the clamping circuitry system 1312 included in the CCIA 1300 significantly reduces output voltage distortion in response to transient events at the common-mode input.

[0154] In addition, the applicant has determined that the response to CCIA input V i_p and V i_n The change in common-mode voltage at the point of reference is used to assert that the third clock signal Φ3 will not impede the input of CCIA to V.i_p and V i_n Amplification of the differential AC signal at that location. For example, Figure 18 The CCIA 1300 embodiment responds to (a) repetitive changes in the common-mode input voltage and (b) changes in the CCIA input V. i_p and V i_n The analog voltage curve at the differential AC voltage point is shown in Figure 1800. Curve 1802 represents the analog voltage curve at the CCIA input V. i_p and V i_n The common-mode voltage at the location, and curve 1804 represents the CCIA output voltage V. 输出 Starting from time t1, the CCIA input V... i_p and V i_n There is also a relatively low-frequency AC differential signal (not shown). As is evident from curve 1804, the CCIA 1300 suppresses the common-mode signal, but the CCIA 1300 amplifies the differential signal.

[0155] Furthermore, the automatic zeroing circuit system 1314 utilizes the clamping circuit system 1312 to help minimize the output ripple associated with the operation of the first chopper 1302 and the second chopper 1304. Specifically, when the third clock signal Φ3 is asserted, the clamping circuit system 1312 shorts the first gain stage inputs 1326 and 1328 together, and therefore the first gain stage outputs 1344 and 1346 ideally have a common value when the third clock signal Φ3 is asserted. When the third clock signal Φ3 is asserted, i.e., when the clamping circuit system 1312 clamps the first gain stage inputs 1326 and 1328 to the reference voltage rail 1334, the automatic zeroing circuit system 1314 uses the shorted first gain stage inputs 1326 and 1328 by sampling the first gain stage outputs 1344 and 1346 to determine the presence of ripple associated with the operation of the first chopper 1302 and the second chopper 1304. Specifically, when the third clock signal Φ3 is asserted, the automatic zeroing switching devices 1376 and 1378 are turned off, and the automatic zeroing capacitors 1372 and 1374 are charged to the corresponding voltages at the output terminals 1344 and 1346 of the first gain stage. The third gain stage 1370 amplifies the voltage difference between the automatic zeroing capacitors 1372 and 1374 to generate a compensation current I. c_p and I c_n A compensation current I is injected at the output terminals 1344 and 1346 of the first gain stage. c_p and I c_nThis is to compensate for the output ripple associated with the operation of the first chopper 1302 and the second chopper 1304. Therefore, the combination of the automatic zeroing circuit system 1314 and the clamping circuit system 1312 enables certain embodiments of the CCIA 1300 to achieve lower output ripple than conventional CCIAs.

[0156] The auto-zeroing circuitry system 1314 can be omitted from the CCIA 1300 to reduce cost and complexity, but this also has the disadvantage of increasing output ripple. For example, Figure 19 The CCIA 1900, such as the CCIA 1300, is shown, but the automatic zeroing circuitry system 1314 is omitted.

[0157] As discussed above, one possible application of the instrumentation amplifiers disclosed herein is for current sensing applications, such as sensing current flowing through inductive loads like motors or solenoids driven by PWM or PFM voltages. Current sensing measurements in these applications typically need to be very accurate to ensure proper control of the inductive load. The clamping circuitry 1312 in some embodiments of the CCIA 1300 gives the CCIA 1300 a large CMRR, enabling it to substantially suppress PWM and PFM common-mode voltages in current sensing applications. Therefore, some embodiments of the CCIA 1300 can enable accurate current sensing in applications where inductive loads are driven by PWM or PFM voltages.

[0158] Figure 20 A method 2000 for reducing the common-mode settling time of a CCIA is illustrated. In step 2002, a change in a first common-mode voltage exceeding a threshold is detected, wherein the first common-mode voltage is the common-mode voltage at the input of the CCIA. In an example of step 2002, the common-mode response subsystem 1390 detects a change in the CCIA input V. i_p and V i_n The change in the slew rate of the common-mode voltage exceeds a threshold. In step 2004, in response to detecting that the change in the first common-mode voltage exceeds the threshold, the input of the first gain stage of the CCIA is electrically isolated from the CCIA input. In one example of step 2004, in response to the CCIA input V i_p and V i_n When the common-mode voltage slew rate exceeds a threshold, the first switching circuit system 1316 connects the first gain stage inputs 1326 and 1328 to the CCIA input V. i_p and V i_n Electrical isolation. In step 2006, in response to detecting a change in the first common-mode voltage exceeding a threshold, the input of the first gain stage of the CCIA is clamped to a reference voltage. In one example of step 2006, in response to detecting a change in the CCIA input V...i_p and V i_n When the change in the common-mode voltage slew rate exceeds a threshold, the clamping circuit system 1312 clamps the first gain stage inputs 1326 and 1328 to the reference voltage of the reference voltage rail 1334.

[0159] Method 2000 may optionally further include step 2008, wherein a current is injected at the output of the first gain stage to compensate for the output ripple caused by the first and second choppers. Step 2008 is performed, for example, in parallel with steps 2002, 2004, and 2006. In one example of step 2008, a compensation current I is injected into the third gain stage 1370 at the outputs 1344 and 1346 of the first gain stage. c_p and I c_n This is to compensate for the output ripple caused by the first chopper 1302 and the second chopper 1304. The outputs 1344 and 1346 of the first gain stage 1306 are sampled when the inputs 1326 and 1328 of the first gain stage are clamped to the reference voltage rail 1334, for example, to determine the compensation current I. c_p and I c_n The amplitude.

[0160] The applicant has further determined that the principles of detecting changes in common-mode voltage and, in response to the detected changes, (a) isolating the gain stage from the amplifier input and (b) clamping the common-mode voltage at the capacitor isolation section of the CCIA to a reference voltage are not limited to CCIAs. Instead, these principles can be applied to many other capacitively coupled amplifiers. See below for reference. Figures 21 to 24 Several examples of how the described principles can be applied to amplifiers other than those in the CCIA are discussed. However, it should be understood that the principles are not limited to the specific topologies discussed herein, but can be applied to many other capacitively coupled amplifiers.

[0161] For example, Figure 21 A capacitively coupled linear amplifier 2100 is illustrated, configured to detect changes in the common-mode voltage at the amplifier input and, in response to the detected change, (a) isolate a gain stage from the amplifier input and (b) clamp the common-mode voltage at the capacitively isolated portion of the amplifier to a reference voltage, thereby helping to minimize the common-mode voltage settling time following a transient event. The amplifier 2100 includes a capacitively coupled isolation stage 2102, a gain stage 2104, a switching circuit system 2106, a clamping circuit system 2108, and a controller 2110.

[0162] Capacitive isolation stage 2102 includes a first capacitor 2112 and a second capacitor 2114. The first capacitor 2112 is electrically coupled to the amplifier input terminal V. i_pBetween the input terminal 2116 of the gain stage 2104 and the second capacitor 2114, and electrically coupled to the amplifier input terminal V. i_n Between the input terminal 2118 of the gain stage 2104 and the input terminal V of the electrocoupled amplifier of the capacitor isolation stage 2102. i_p and V i_n The AC signal between the inputs 2116 and 2118 of the gain stage is blocked, while the transmission of the DC signal is also blocked. Without departing from the scope of this document, the capacitive isolation stage 2102 may include an additional capacitor. Alternatively, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitive isolation stage 2102.

[0163] Clamping circuitry 2108 is electrically coupled between the gain stage inputs 2116 and 2118 and a reference voltage rail 2120. In some embodiments, the reference voltage rail 2120 has a fixed potential set to achieve the desired common-mode voltage at the gain stage inputs 2116 and 2118. Clamping circuitry 2108 is configured to clamp the gain stage inputs 2116 and 2118 to the reference voltage rail 2120 when a clock signal Φ is asserted. As discussed below, in response to the amplifier input V... i_p and V i_n When the common-mode voltage changes, controller 2110 asserts clock signal Φ to help minimize the common-mode voltage settling time following a transient event. In some embodiments, as shown, clamping circuitry 2108 includes switching devices 2122 and 2124, respectively electrically coupled between reference voltage rail 2120 and gain stage inputs 2116 and 2118. When clock signal Φ is asserted, switching devices 2122 and 2124 are turned off to clamp gain stage inputs 2116 and 2118 to reference voltage rail 2120, respectively. When clock signal Φ is deasserted, switching devices 2122 and 2124 are turned on. For example, each of switching devices 2122 and 2124 includes one or more transistors. The configuration of clamping circuitry 2108 can be changed, for example, to include additional switching devices, without departing from the scope of this document.

[0164] The switching circuit system 2106 is configured to: when in response to detecting amplifier input V i_p and V i_p When the clock signal Φ asserts due to the change in the common-mode voltage at the point, the input terminals 2116 and 2118 of the gain stage are connected to the amplifier input terminal V. i_p and V i_nElectrical isolation. In some embodiments, as shown, the switching circuit system 2106 includes corresponding switching devices 2126 and 2128 electrically coupled in series with the first capacitor 2112 and the second capacitor 2114. Switching devices 2126 and 2128 are turned off when the clock signal Φ is deasserted; and are turned on when the clock signal Φ is asserted. For example, each of switching devices 2126 and 2128 includes one or more transistors.

[0165] Gain stage 2104 can have virtually any configuration, as long as it generates a signal at gain stage output 2130 in response to a signal difference between gain stage inputs 2116 and 2118. For example, in some embodiments, gain stage 2104 is configured as an instrumentation amplifier. Although gain stage 2104 is shown as a single element for the sake of simplicity, gain stage 2104 may include multiple elements. Depending on the configuration of gain stage 2104, the signal at gain stage output 2130 can be a voltage signal or a current signal. In some embodiments of amplifier 2100, the signal at gain stage output 2130 is a differential signal.

[0166] The controller 2110 generates a clock signal Φ, and the controller 2110 is configured to respond to the amplifier input V. i_p and V i_n The clock signal Φ is asserted by the change in the slew rate and / or amplitude of the common-mode voltage at the input. In some embodiments, the controller 2110 detects the amplifier input V. i_p and V i_n If the change in the slew rate or amplitude of the common-mode voltage exceeds a predetermined first threshold, and in response to detecting that the change in the common-mode voltage exceeds the first threshold, the controller 2110 asserts the clock signal Φ. In a specific embodiment, the controller 2110 includes a... Figure 14 The circuitry is similar to that of the common-mode response subsystem. In some embodiments, the controller 2110 asserts the clock signal Φ until the change in the common-mode voltage at the inputs 2116 and 2118 of the gain stage drops below a second threshold, wherein the first threshold may optionally be greater than the second threshold to achieve hysteresis. In some other embodiments, after detecting a change in the common-mode voltage, the controller 2110 asserts the clock signal Φ for a predetermined duration.

[0167] Figure 22 Graph 2200 illustrates a clock signal Φ generated by controller 2110 as in one embodiment of amplifier 2100. The vertical axis of graph 2200 represents the signal amplitude, and the horizontal axis represents time. Graph 2200 includes representations of the amplifier input V. i_p and V i_nThe common-mode voltage curve 2202 and the curve representing the clock signal Φ are shown. In this specific embodiment, the clock signal Φ is asserted when it is logic high. However, without departing from the scope of this document, amplifier 2100 can be configured such that the clock signal Φ is asserted when it is logic low. Amplifier input V i_p and V i_n The magnitude of the common-mode voltage changes at a higher slew rate at times t1 and t2, causing the controller 2110 to assert the clock signal Φ in response.

[0168] Figure 23 A chopper-stabilized instrumentation amplifier 2300 is shown, comprising a first chopper 2302, a second chopper 2304, a first gain stage 2306, a second gain stage 2308, a capacitor isolation stage 2310, a clamping circuit system 2312, a chopper-stabilized circuit system 2314, a first switching circuit system 2316, a second switching circuit system 2318, and a controller 2320. The first chopper 2302 is electrically coupled to (a) the amplifier input terminal V. i_p and V i_n Between (b) capacitor isolation stage 2310. The first chopper 2302 is controlled by clock signals Φ1 and Φ2, and includes at least the following components: Figure 13 The first chopper 2302 has a first operating state and a second operating state similar to the first operating state. When clock signal Φ1 is asserted, the first chopper 2302 operates in its first operating state; and when clock signal Φ2 is asserted, the first chopper 2302 operates in its second operating state. In some embodiments, the first chopper 2302 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first operating state and the second operating state.

[0169] A capacitive isolation stage 2310 is electrically coupled between input terminals 2322 and 2324 of the first chopper 2302 and the second chopper 2304. The capacitive isolation stage 2310 electrically couples the alternating current (AC) signal between the first chopper 2302 and the second chopper 2304 while blocking the transmission of DC signals. In some embodiments, as shown, the capacitive isolation stage 2310 includes a first capacitor 2330 and a second capacitor 2332. In these embodiments, the first capacitor 2330 is electrically coupled in series with the second chopper input terminal 2322, and the second capacitor 2332 is electrically coupled in series with the second chopper input terminal 2324. Without departing from the scope of this document, the capacitive isolation stage 2310 may include additional capacitors. Furthermore, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitive isolation stage 2310.

[0170] Clamping circuitry 2312 is electrically coupled between the second chopper inputs 2322 and 2324 and a reference voltage rail 2334. In some embodiments, the reference voltage rail 2334 has a fixed potential set to achieve the desired common-mode voltage at the second chopper inputs 2322 and 2324. Clamping circuitry 2312 is configured to clamp the second chopper inputs 2322 and 2324 to the reference voltage rail 2334 when the clock signal Φ3 is asserted, thereby clamping the common-mode voltage at the second chopper inputs 2322 and 2324 to the reference voltage of the reference voltage rail 2334. This is in response to the amplifier input V... i_p and V i_n As the common-mode voltage changes, clamping circuitry 2312 repeatedly clamps the second chopper inputs 2322 and 2324 to the reference voltage rail 2334, thereby repeatedly resetting the common-mode voltage in instrumentation amplifier 2300 to help minimize the common-mode voltage settling time after a transient event. In some embodiments, as shown, clamping circuitry 2312 includes switching devices 2336 and 2338, respectively, electrically coupled between the reference voltage rail 2334 and the second chopper inputs 2322 and 2324. Switching devices 2336 and 2338 are turned off when clock signal Φ3 is asserted to clamp the second chopper inputs 2322 and 2324 to the reference voltage rail 2334. Switching devices 2336 and 2338 are turned on when clock signal Φ3 is deasserted. For example, each of switching devices 2336 and 2338 includes one or more transistors. Without departing from the scope of this document, the configuration of the clamping circuit system 2312 may be changed, for example, to include additional switching devices.

[0171] The first switching circuit system 2316 is configured to: when the clock signal Φ3 is asserted, i.e., in response to the detected amplifier input V i_p and V i_n The change in common-mode voltage at the input of the second chopper 2322 and 2324 causes the common-mode voltage at the amplifier input V to change. i_p and V i_nElectrical isolation. In some embodiments, as shown, the first switching circuit system 2316 includes corresponding switching devices 2340 and 2342 electrically coupled in series with the inputs 2322 and 2324 of the second chopper. Switching devices 2340 and 2342 are turned off when the clock signal Φ3 is deasserted; and switching devices 2340 and 2342 are turned on when the clock signal Φ3 is asserted. For example, each of switching devices 2340 and 2342 includes one or more transistors. Although the first switching circuit system 2316 is shown as electrically coupled between the capacitive isolation stage 2310 and the second chopper 2304, the first switching circuit system 2316 may alternatively be electrically coupled between the first chopper 2302 and the capacitive isolation stage 2310.

[0172] The second chopper 2304 is electrically coupled between the capacitive isolation stage 2310 and the first gain stage 2306. The second chopper 2304 is controlled by clock signals Φ1 and Φ2 in a manner similar to the first chopper 2302. Specifically, when clock signal Φ1 is asserted, the second chopper 2304 operates in its first operating state; and when clock signal Φ2 is asserted, the second chopper 2304 operates in its second operating state. In some embodiments, the second chopper 2304 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first and second operating states.

[0173] The first gain stage 2306 is communicatively coupled to the capacitive isolation stage 2310 via the second chopper 2304. In a specific embodiment, the first gain stage 2306 performs a transconductance function, i.e., it generates a differential output current signal in response to a difference in the input voltage signal. However, the configuration of the first gain stage 2306 can be varied without departing from the scope of this document. Although the first gain stage 2306 is shown as a single element for the sake of simplicity, it may include multiple elements.

[0174] The second switching circuit system 2318 is configured to electrically isolate the second gain stage 2308 from the first gain stage 2306 when the clock signal Φ3 is asserted. In some embodiments, as shown, the second switching circuit system 2318 includes corresponding switching devices 2344 and 2346 electrically coupled in series to inputs 2348 and 2350 of the second gain stage 2308. When the clock signal Φ3 is deasserted, switching devices 2344 and 2346 are turned off; and when the clock signal Φ3 is asserted, switching devices 2344 and 2346 are turned on. For example, each of the switching devices 2344 and 2346 includes one or more transistors.

[0175] In a specific embodiment, as shown, the second gain stage 2308 performs a transconductance function, and the instrumentation amplifier 2300 further includes feedback capacitors 2352 and 2354. Feedback capacitor 2352 is electrically coupled between the input terminal 2348 of the second gain stage and the output terminal 2356 of the second gain stage 2308. Feedback capacitor 2354 is electrically coupled between the input terminal 2350 of the second gain stage and the output terminal 2358 of the second gain stage 2308. Therefore, the second gain stage 2308 is Miller-compensated. However, the configuration of the second gain stage 2308 can be varied without departing from the scope of this document. Although the second gain stage 2308 is shown as a single element for the sake of simplicity, it can include multiple elements without departing from the scope of this document.

[0176] Figure 24 A chopper stabilization circuit system 2314 is shown, comprising a third chopper 2402, a fourth chopper 2404, a third gain stage 2406, a fourth gain stage 2408, a fifth gain stage 2410, feedback capacitors 2414 and 2416, feedback capacitors 2418 and 2420, and resistors 2422 and 2424. Resistors 2422 and 2424 together form a voltage divider across the output of the second gain stage 2308, and the third chopper 2402 is electrically coupled between resistor 2422 and the second capacitor isolation stage 2412. The third chopper 2402 is controlled by clock signals Φ1 and Φ2 in a manner similar to the first chopper 2302. Specifically, when clock signal Φ1 is asserted, the third chopper 2402 operates in its first operating state; and when clock signal Φ2 is asserted, the third chopper 2402 operates in its second operating state. In some embodiments, the third chopper 2402 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first operating state and the second operating state.

[0177] A second capacitor isolation stage 2412 is electrically coupled between the inputs 2426 and 2428 of the third chopper 2402 and the third gain stage 2406. The capacitor isolation stage 2412 electrically couples the alternating current (AC) signal between the third chopper 2402 and the third gain stage 2406 while blocking the transmission of DC signals. In some embodiments, as shown, the capacitor isolation stage 2412 includes a third capacitor 2430 and a fourth capacitor 2432. In these embodiments, the third capacitor 2430 is electrically coupled in series with the input 2426 of the third gain stage, and the fourth capacitor 2432 is electrically coupled in series with the input 2428 of the third gain stage. Without departing from the scope of this document, the capacitor isolation stage 2412 may include additional capacitors. Furthermore, another device that only transmits AC signals, such as an optocoupler, may be used instead of the capacitor isolation stage 2412.

[0178] The third gain stage 2406 is communicatively coupled between the second capacitor isolation stage 2412 and the fourth chopper 2404. In a specific embodiment, the third gain stage 2406 performs a transconductance function, i.e., it generates a differential output current signal in response to a difference in the input voltage signal. However, the configuration of the third gain stage 2406 can be varied without departing from the scope of this document. Although the third gain stage 2406 is shown as a single element for the sake of simplicity, it may include multiple elements.

[0179] The fourth chopper 2404 is electrically coupled between the third gain stage 2406 and the fourth gain stage 2408. The fourth chopper 2404 is controlled by clock signals Φ1 and Φ2 in a manner similar to the first chopper 2302. Specifically, when clock signal Φ1 is asserted, the fourth chopper 2404 operates in its first operating state; and when clock signal Φ2 is asserted, the fourth chopper 2404 operates in its second operating state. In some embodiments, the fourth chopper 2404 includes a plurality of transistors (not shown) controlled by clock signals Φ1 and Φ2 to implement the first and second operating states.

[0180] The fourth gain stage 2408 is electrically coupled between the fourth chopper 2404 and the fifth gain stage 2410. In a specific embodiment, the fourth gain stage 2408 performs a transconductance function. Feedback capacitors 2414 and 2416 are electrically coupled between the corresponding inputs and outputs of the fourth gain stage 2408. The configuration of the fourth gain stage 2408 can be varied without departing from the scope of this document. Although the fourth gain stage 2408 is shown as a single element for the sake of simplicity, it may include multiple elements without departing from the scope of this document. Feedback capacitors 2418 and 2420 are electrically coupled between the corresponding outputs of the second gain stage 2308 and the corresponding inputs of the fourth gain stage 2408.

[0181] The fifth gain stage 2410 is electrically coupled between the fourth gain stage 2408 and the inputs 2348 and 2350 of the second gain stage. In a specific embodiment, the fifth gain stage 2410 performs a transconductance function, but the configuration of the fifth gain stage 2410 can be varied without departing from the scope of this document. Although the fifth gain stage 2410 is shown as a single element for the sake of simplicity, it can include multiple elements without departing from the scope of this document.

[0182] Controller 2320 ( Figure 23The controller 2320 generates a first clock signal Φ1, a second clock signal Φ2, and a third clock signal Φ3. The controller 2320 is formed from, for example, an analog electrical circuit system, a digital electrical circuit system, or a combination of analog and digital electrical circuit systems. Although the controller 2320 is symbolically shown as a single element, it can be formed from multiple elements such as multiple integrated circuits and / or multiple discrete components.

[0183] In some embodiments, controller 2320 generates a first clock signal Φ1 and a second clock signal Φ2 such that the first clock signal Φ1 and the second clock signal Φ2 are asserted in a complementary manner, i.e., the first clock signal Φ1 is asserted when the second clock signal Φ2 is deasserted, and vice versa. Therefore, in these embodiments, the first chopper 2302, the second chopper 2304, the third chopper 2402, and the fourth chopper 2404 consistently and repeatedly switch between their corresponding first and second operating states. The first gain stage 2306 forms part of a high-frequency, low-gain first path, and the third gain stage 2406 forms part of a low-offset, low-frequency, and low-gain second path. Chopper stabilization circuitry 2314 corrects the input offset voltage of the first gain stage 2306 to a degree that the second path has a higher gain than the first path.

[0184] The controller 2320 responds at least to the amplifier input V. i_p and V i_n The third clock signal Φ3 is asserted by the change in the slew rate and / or amplitude of the common-mode voltage at the input. In some embodiments, the controller 2320 detects the amplifier input V. i_p and V i_n If the change in the slew rate or amplitude of the common-mode voltage exceeds a predetermined first threshold, and in response to detecting that the change in the common-mode voltage exceeds the first threshold, the controller 2320 asserts the clock signal Φ3. In a specific embodiment, the controller 2320 includes... Figure 14 The circuit system is similar to the common-mode response subsystem.

[0185] Modifications to the amplifier and method described above may be made without departing from the scope of this document. For example, an alternative auto-zeroing circuit system 314 may be used in conjunction with clamping circuit system 312. Therefore, it should be noted that the contents contained in the above description and shown in the accompanying drawings should be interpreted illustratively rather than restrictively. The following claims are intended to cover the general and specific features described herein, and all statements regarding the scope of this method and system may be said to fall within them.

Claims

1. A capacitively coupled amplifier, comprising: The capacitor isolation stage is located at the input of the capacitively coupled amplifier; The gain stage is communication-coupled to the capacitive isolation stage; A first switching circuit system is configured to electrically isolate the gain stage from the capacitor isolation stage; The controller is configured to assert a control signal to cause the first switching circuit system to electrically isolate the gain stage from the capacitor isolation stage; A second switching circuit system, electrically coupled to the gain stage between the gain stage and the first switching circuit system, is configured to clamp the input of the gain stage to a reference voltage when the controller asserts the control signal to electrically isolate the gain stage from the capacitor isolation stage.

2. The capacitively coupled amplifier as described in claim 1, wherein, The capacitively coupled amplifier is a differential amplifier.

3. The capacitively coupled amplifier as described in claim 1, wherein, The controller is further configured to assert the control signal in response to sensing that the common-mode voltage exceeds a first threshold.

4. The capacitively coupled amplifier as described in claim 3, wherein, The controller is further configured to de-assert the control signal in response to sensing that the common-mode voltage has dropped below a second threshold.

5. The capacitively coupled amplifier as described in claim 1, wherein, The controller is further configured to sense that the common-mode voltage conversion rate exceeds a threshold.

6. A method for reducing the common-mode settling time of a capacitively coupled amplifier, the method comprising: Detect changes in the common-mode voltage, where the common-mode voltage exceeds a threshold. In response to the common-mode voltage exceeding the threshold, the input terminal of the gain stage is electrically isolated from the input terminal of the amplifier; as well as The input terminal of the gain stage is clamped to the reference voltage.

7. The method of claim 6, further comprising: Current is injected at the output of the capacitively coupled amplifier based on the output ripple.

8. A method for reducing the common-mode settling time of a capacitively coupled amplifier, the method comprising: The change in the slew rate of the common-mode voltage is detected, and the slew rate exceeds a threshold. In response to the slew rate exceeding the threshold, the input of the gain stage is electrically isolated from the input of the amplifier. as well as In response to the conversion rate exceeding the threshold, the input of the gain stage is clamped to the reference voltage.

9. The method of claim 8, further comprising: Current is injected at the output of the capacitively coupled amplifier based on the output ripple.

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