Microphone sensor chip test board

Abstract

This invention discloses a microphone sensor chip test board, including a circuit board with a chip pin mounting position group and a peripheral device mounting position group. The chip pin mounting position group includes multiple chip pin mounting positions, each used to connect to a pin on the chip under test; the chip pin mounting positions include input pin mounting positions and output pin mounting positions. The peripheral device mounting position group includes a first device mounting position and a second device mounting position. The first device mounting position is electrically connected to the input pin mounting position, and the second device mounting position is electrically connected to the output pin mounting position. This invention improves the efficiency of microphone sensor chip testing.

Description

Technical Field

[0001] This invention relates to the field of microphone sensor chip testing, and in particular to a microphone sensor chip test board. Background Technology

[0002] In the testing of each microphone sensor chip, AC Couple open-loop testing, AC Couple closed-loop testing, and DC Couple open-loop testing are often required. However, different tests require different levels of encapsulation of the corresponding pins of the chip. For example, in AC Couple open-loop testing, a capacitor needs to be connected to the INN pin of the chip under test so that the input test voltage signal passes through the capacitor to the INN pin of the chip under test; in AC Couple closed-loop testing, the INN pin of the chip under test needs to be connected to its MIC / VMIC pin through a capacitor; and in DC Couple open-loop testing, the test voltage signal needs to be directly connected through the INN pin of the chip under test. These three tests require three different encapsulations of the chip, which is very cumbersome and requires repeated soldering by testers, reducing the efficiency of microphone sensor chip testing. Summary of the Invention

[0003] The main objective of this invention is to provide a microphone sensor chip test board, which aims to improve the efficiency of microphone sensor chip testing.

[0004] To achieve the above objectives, the present invention proposes a microphone sensor chip test board, the microphone sensor chip test board comprising:

[0005] A circuit board, wherein chip pin mounting positions and peripheral device mounting positions are provided on the circuit board;

[0006] The chip pin mounting position group includes multiple chip pin mounting positions, which are used to connect to pins on the chip under test one by one; the chip pin mounting positions include input pin mounting positions and output pin mounting positions, whereby the input pin mounting positions are used to connect to input pins on the chip under test; and the output pin mounting positions are used to connect to output pins on the chip under test.

[0007] The peripheral device mounting position group includes a first device mounting position and a second device mounting position. The first device mounting position is electrically connected to the input pin mounting position, and the second device mounting position is electrically connected to the output pin mounting position. The first device mounting position and the second device mounting position are used to connect a peripheral device.

[0008] Optionally, the circuit board has M wiring layers, and the chip pin mounting bit group and the peripheral device mounting bit group are disposed on the top wiring layer;

[0009] The first device mounting position and its corresponding input pin mounting position are arranged in close proximity; the second device mounting position and its corresponding input pin mounting position are arranged in close proximity.

[0010] Optionally, there are multiple input pin mounting positions, output pin mounting positions, first device mounting positions, and second device mounting positions, and each first device mounting position is disposed in close contact with at least one second device mounting position in at least one direction.

[0011] Optionally, the input pin mounting positions include INN pin mounting positions and INP pin mounting positions; the output pin mounting positions include MIC pin mounting positions and VMIC pin mounting positions.

[0012] Optionally, the top wiring layer of the circuit board is further provided with a redundant pin mounting bit group, which includes redundant pin mounting bits electrically connected to the chip pin mounting bits.

[0013] The chip pin mounting positions and redundant pin mounting positions used for connecting to the same pin of the chip under test are arranged side by side and spaced apart from the chip pin mounting positions and / or redundant pin mounting positions used for connecting other pins of the chip under test.

[0014] Optionally, a portion of the plurality of chip pin mounting positions and the plurality of redundant pin mounting positions are arranged along a first direction on the top wiring layer of the circuit board, and another portion of the plurality of chip pin mounting positions and the plurality of redundant pin mounting positions are arranged along a second direction on the top wiring layer of the circuit board, the second direction being different from the first direction.

[0015] Optionally, when the chip pin mounting position electrically connected to at least one of the redundant pin mounting positions is an input pin mounting position or an output pin mounting position, at least one of the redundant pin mounting positions is electrically connected to the corresponding chip pin mounting position through a via and a first signal line;

[0016] Among them, at least one of the first signal lines is disposed on the Nth wiring layer (1 < N < M);

[0017] A ground plane is provided on the N-1 wiring layer at the position corresponding to any of the first signal lines on the Nth wiring layer;

[0018] A ground plane is provided on the N+1 wiring layer at the position corresponding to any of the first signal lines on the Nth wiring layer.

[0019] Optionally, there may be multiple first signal lines, which may be disposed on different wiring layers.

[0020] Optionally, the circuit board is also provided with a test terminal mounting position group;

[0021] The test terminal mounting position group includes multiple test mounting positions, the number of which is the same as the number of chip pin mounting positions. The multiple test mounting positions and the multiple chip pin mounting positions are electrically connected in a one-to-one correspondence, and the multiple test mounting positions are used to connect to the test terminal.

[0022] Optionally, multiple test mounting positions are disposed on the bottom wiring layer of the circuit board, and the test mounting positions are electrically connected to the corresponding chip pin mounting positions through holes.

[0023] The microphone sensor chip test board of the present invention includes a circuit board, on which are provided a chip pin mounting position group and a peripheral device mounting position group. The chip pin mounting position group includes multiple chip pin mounting positions, each used to connect to a pin on the chip under test (DUT). The chip pin mounting positions include input pin mounting positions and output pin mounting positions. The input pin mounting positions are used to connect to input pins on the DUT, and the output pin mounting positions are used to connect to output pins on the DUT. The peripheral device mounting position group includes a first device mounting position and a second device mounting position. The first device mounting position is electrically connected to the input pin mounting position, and the second device mounting position is electrically connected to the output pin mounting position. The first and second device mounting positions are used to connect a peripheral device. Thus, in practical applications, when testers need to perform AC Couple open-loop testing, AC Couple closed-loop testing, and DC Couple open-loop testing on the microphone sensor chip under test, they only need to connect the INN pin on the chip under test to the corresponding INN input pin mounting position on the circuit board via wire bonding, and connect the MIC pin on the chip under test to the corresponding MIC output pin mounting position on the circuit board via wire bonding. Capacitors are then placed on the first device mounting position connected to the INN input pin mounting position and the second device mounting position connected to the MIC output pin mounting position. This completes all three tests without requiring repackaging and testing of the chip under test, effectively improving the efficiency of microphone sensor chip testing. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of an embodiment of the microphone sensor chip test board of the present invention;

[0026] Figure 2 This is a schematic diagram of the top wiring layer structure of a circuit board according to an embodiment of the microphone sensor chip test board of the present invention;

[0027] Figure 3 This is a schematic diagram of the second wiring layer structure of a circuit board according to an embodiment of the microphone sensor chip test board of the present invention;

[0028] Figure 4 This is a schematic diagram of the third wiring layer structure of a circuit board according to an embodiment of the microphone sensor chip test board of the present invention;

[0029] Figure 5 This is a schematic diagram of the bottom wiring layer structure of a circuit board according to an embodiment of the microphone sensor chip test board of the present invention;

[0030] Figure 6 A is a partial pin location diagram of a package of the microphone sensor chip under test;

[0031] Figure 6 B is a partial pin location diagram of another package of the microphone sensor chip under test;

[0032] Figure 6 C is a partial pin location diagram of another package of the microphone sensor chip under test;

[0033] Figure 6 D is a partial pin location diagram of the microphone sensor chip under test in its package.

[0034] Explanation of icon numbers:

[0035] 10 Chip pin mounting points 11 Input pin mounting position 12 Output pin mounting position 21 First device mounting position 22 Second device mounting position 00 circuit board 01 Top wiring layer 02 Second wiring layer 03 Third wiring layer 04 Bottom wiring layer 30 Redundant pin mounting points 40 Test installation location

[0036] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0038] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0039] It's important to understand that testing each microphone sensor chip typically involves AC Couple open-loop, AC Couple closed-loop, and DC Couple open-loop tests. However, different tests require varying degrees of encapsulation for the chip's pins. For example, in AC Couple open-loop testing, a capacitor is connected to the INN pin of the chip under test (DUT) so that the test voltage signal passes through the capacitor to the INN pin. In AC Couple closed-loop testing, the INN pin of the DUT is connected to its MIC / VMIC pin via a capacitor. Furthermore, in DC Couple open-loop testing, the test voltage signal is directly connected to the INN pin of the DUT. These three tests require three different encapsulations, making the testing process cumbersome and requiring repeated soldering by the testers, thus reducing the efficiency of microphone sensor chip testing.

[0040] Therefore, the present invention proposes a microphone sensor chip test board. In one embodiment of the present invention, referring to... Figure 1 The microphone sensor chip test board includes:

[0041] Circuit board 00, which has 10 sets of chip pin mounting positions and 10 sets of peripheral device mounting positions;

[0042] The chip pin mounting position 10 group includes multiple chip pin mounting positions 10, which are used to connect to the pins on the chip under test one by one; the chip pin mounting position 10 includes an input pin mounting position 11 and an output pin mounting position 12, where the input pin mounting position 11 is used to connect to the input pins on the chip under test; and the output pin mounting position 12 is used to connect to the output pins on the chip under test.

[0043] The peripheral device mounting position group includes a first device mounting position and a second device mounting position. The first device mounting position is electrically connected to the input pin mounting position 11, and the second device mounting position is electrically connected to the output pin mounting position 12. The first device mounting position and the second device mounting position are used to connect a peripheral device.

[0044] In this embodiment, the circuit board 00 can be implemented using fiberglass board, ceramic circuit board 00, aluminum nitride ceramic circuit board 00, alumina ceramic circuit board 00, etc. The chip pin mounting positions 10, the first device mounting position, and the second device mounting position can all be implemented using pads on the circuit board 00. The pads can be smooth pads or pads with solder holes. At the start of the test, the tester can solder the pins of the chip under test (referring to the microphone sensor chip under test, hereinafter the same) to the corresponding chip pin mounting positions 10 on the circuit board 00 by wire bonding. Optionally, in one embodiment, the tester can also connect each chip pin mounting position 10 to a test terminal simultaneously by wire bonding, and operate the test terminal to output corresponding test signals through the corresponding chip pin mounting positions 10 to the corresponding pins of the chip under test, and receive signals output by the pins of the chip under test through the corresponding chip pin mounting positions 10, thereby completing the test of the chip under test. Optionally, in another embodiment, the circuit board 00 may also be directly provided with test mounting positions 40 that correspond one-to-one with multiple chip pin mounting positions 10, so as to be connected to the test terminal by means of soldering, pin headers, etc., so that the test terminal is connected to multiple pins on the chip under test through multiple test mounting positions 40 and multiple chip pin mounting positions 10, so that the tester can complete the test according to the above operation.

[0045] It is understood that there can be multiple input pin mounting bits 11 and multiple output pin mounting bits 12. Similarly, there can also be multiple first device mounting bits and multiple second device mounting bits corresponding to input pin mounting bits 11 and multiple output pin mounting bits 12, respectively. Optionally, each input pin mounting bit 11 / output pin mounting bit 12 can be electrically connected to at least one first device mounting bit / at least one second device mounting bit.

[0046] In this embodiment, before the test begins, appropriate first and second device mounting positions can be selected to mount peripheral devices, such as capacitors and resistors, according to specific test requirements. The number of first and second device mounting positions and their connected objects can be set according to the actual needs of the R&D personnel.

[0047] Specifically, refer to Figure 2In one embodiment of the present invention, the chip pin mounting position 10 group includes a SUB pin mounting position, a MIC pin mounting position, an INN pin mounting position, an INP pin mounting position, a VMIC pin mounting position, a GND pin mounting position, an L / R pin mounting position, a DATA pin mounting position, a CLK pin mounting position, and a VDD pin mounting position. The peripheral device mounting position group includes one first device mounting position MPAD2 and two second device mounting positions (second device mounting position MPAD1 and second device mounting position MPAD3). The following description uses the INN pin mounting position as the input pin mounting position 11 and the MIC and VMIC pin mounting positions as the output pin mounting positions 12 as an example. The first device mounting position MPAD2 is connected to the INN pin mounting position, the second device mounting position MPAD1 is connected to the MIC pin mounting position, and the second device mounting position MPAD3 is connected to the VMIC pin mounting position.

[0048] Before starting the AC Couple open-loop test, AC Couple closed-loop test, and DC Couple open-loop test, the tester will connect the pins on the chip under test (DUT) to the corresponding chip pin mounting positions 10 on the circuit board 00 via wire bonding. It is important to understand that the types and numbers of pins on different packages and models of DUTs vary, but the chip pin mounting positions 10 on the circuit board 00 will include all pin types of DUTs of different packages and models. Furthermore, it is understood that for DUTs with different packages, multiple chip pin mounting positions 10 can be provided for connecting to the same pin on the DUT, such as the MIC pin and VMIC pin in the above embodiment. The MIC pin can be used to connect to the MIC pin of a digital microphone sensor chip to detect its voltage bias, and the VMIC pin can be used to connect to the MIC pin of an analog microphone sensor chip to detect its voltage bias, thereby facilitating differentiation during testing.

[0049] After the tester establishes an electrical connection between each pin on the chip under test and the corresponding chip pin mounting position 10 on the circuit board 00 using wire bonding, the tester will install a capacitor on the second device mounting position MPAD1 and the first device mounting position MPAD2 (one end of the capacitor is soldered to the second device mounting position MPAD1, and the other end is soldered to the first device mounting position MPAD2).

[0050] Subsequently, the tester will connect the multiple chip pin mounting positions 10 one by one to the test terminal or connect the multiple test mounting positions 40 on the circuit board 00 to the test terminal so that the test terminal and each chip pin mounting position 10 are electrically connected, thereby electrically connecting each pin on the chip under test.

[0051] When performing DC Couple open-loop testing, the tester can control the test terminal to start working in DC Couple open-loop test mode, so as to directly output the test voltage signal from the INN pin mounting position to the INN pin of the chip under test, and similarly output / receive the corresponding signals output by the chip under test from other chip pin mounting positions 10, so as to realize the Couple open-loop test of the chip under test.

[0052] During AC Couple open-loop testing, since the chip's MIC pin is an output pin and does not require testing during the AC Couple open-loop test, the tester can control the test terminal to start operating in AC Couple open-loop test mode to output a test voltage signal from the MIC pin mounting position. Because the chip's MIC pin is an output pin, the MIC pin of the chip under test (DUT) will not be affected by this test voltage signal. Simultaneously, the test voltage signal will be transmitted from the MIC pin mounting position and the second device mounting position MPAD2 to one end of a capacitor, then through the capacitor, and then from the other end of the capacitor through the first device mounting position MPAD1 and the INN pin mounting position to the INN pin of the DUT. This fulfills the test requirement of AC Couple open-loop testing, which involves inputting the test voltage signal through a capacitor into the INN pin of the DUT. Similarly, the test terminal can also output / receive corresponding signals from other chip pin mounting positions 10 to perform AC Couple open-loop testing on the DUT.

[0053] During AC Couple closed-loop testing, the tester can similarly control the test terminal to start operating in AC Couple closed-loop test mode. At this time, the test terminal will not output / receive any signals to the INN and MIC pins. The capacitors located on the second device mounting position MPAD1 and the first device mounting position MPAD2 are effectively connected to the INN and MIC pins of the chip under test, fulfilling the requirements of AC Couple closed-loop testing. Similarly, the test terminal will also output / receive the corresponding signals from the chip under test from other chip mounting positions 10 according to AC Couple closed-loop test mode to achieve AC Couple closed-loop testing of the chip under test. Thus, in practical applications, when testers need to perform AC Couple open-loop testing, AC Couple closed-loop testing, and DC Couple open-loop testing on the microphone sensor chip under test, they only need to connect the INN pin on the chip under test to the corresponding INN input pin mounting position 11 on the circuit board 00 via wire bonding, and connect the MIC pin on the chip under test to the corresponding MIC output pin mounting position 12 on the circuit board 00 via wire bonding. Capacitors are then placed on the first device mounting position 21 connected to the INN input pin mounting position 11 and the second device mounting position 22 connected to the MIC output pin mounting position 12. This allows the three tests to be completed through the test terminal without requiring re-testing and repackaging of the chip under test for each test, effectively improving the efficiency of microphone sensor chip testing.

[0054] The microphone sensor chip test board of the present invention includes a circuit board 00, on which are provided a chip pin mounting position 10 group and a peripheral device mounting position group. The chip pin mounting position 10 group includes multiple chip pin mounting positions 10, each used to connect to a pin on the chip under test. Each chip pin mounting position 10 includes an input pin mounting position 11 and an output pin mounting position 12. The input pin mounting position 11 is used to connect to an input pin on the chip under test, and the output pin mounting position 12 is used to connect to an output pin on the chip under test. The peripheral device mounting position group includes a first device mounting position 21 and a second device mounting position 22. The first device mounting position 21 is electrically connected to the input pin mounting position 11, and the second device mounting position 22 is electrically connected to the output pin mounting position 12. The first device mounting position 21 and the second device mounting position 22 are used to connect to a peripheral device. Thus, in practical applications, when testers need to perform AC Couple open-loop testing, AC Couple closed-loop testing, and DC Couple open-loop testing on the microphone sensor chip under test, they only need to connect the INN pin on the chip under test to the corresponding INN input pin mounting position 11 on the circuit board 00 via wire bonding, and connect the MIC pin on the chip under test to the corresponding MIC output pin mounting position 12 on the circuit board 00 via wire bonding. Capacitors are then placed on the first device mounting position 21 connected to the INN input pin mounting position 11 and the second device mounting position 22 connected to the MIC output pin mounting position 12. This completes the three tests without requiring re-testing and repackaging of the chip under test, effectively improving the efficiency of microphone sensor chip testing.

[0055] It is important to understand that in actual testing, the input signals transmitted on circuit board 00, such as the signal output from the test terminal to the INN pin of the chip under test (DUT) via the INN pin mounting bit, and the output signals, such as the signal input from the test terminal via the MIC pin mounting bit, are subject to interference from various factors during transmission. These factors include the transmission distance of the input and output signals on circuit board 00, other signals transmitted on circuit board 00, and external influences. This can lead to deviations in the test results.

[0056] Therefore, refer to Figure 1-5 In one embodiment of the present invention, the circuit board 00 has M wiring layers, and the chip pin mounting positions 10 groups and the peripheral device mounting positions 10 groups are disposed on the top wiring layer 01.

[0057] The first device mounting position 21 and its corresponding input pin mounting position 11 are arranged in close proximity; the second device mounting position 22 and its corresponding input pin mounting position 11 are arranged in close proximity.

[0058] It is understandable that the circuit board 00 can have multiple wiring layers, each of which can have copper traces, and different wiring layers can be connected by vias to establish electrical connections.

[0059] In this embodiment, to facilitate the wire bonding and device placement operations performed by testers, all chip pin mounting positions 10 in the chip pin mounting position 10 group and the first device mounting position 21 and the second device mounting position 22 in the peripheral device mounting position group can be located on the top wiring layer 01. Furthermore, during testing, especially when performing ACCouple open-loop testing, as can be seen from the above, referring to... Figure 2 The test terminal outputs a test voltage signal to the MIC chip pin mounting position 10. This test voltage signal needs to be transmitted through lines on the circuit board 00 to the second device mounting position MPAD1, then through a capacitor to the first intermediate mounting position MPAD2, and finally through lines on the circuit board 00 to the INN pin mounting position. Therefore, placing the first device mounting position 21 and its corresponding input pin mounting position 11 close together, and placing the second device mounting position 22 and its corresponding input pin mounting position 11 close together, can effectively shorten the transmission distance of the input signal flowing into the input pin of the chip under test and the output signal output from the output pin of the chip under test on the circuit board 00, thereby improving the signal quality of the input and output signals and reducing interference.

[0060] Furthermore, in one embodiment of the present invention, reference is made to... Figure 2 Each first device mounting position 21 is disposed in close contact with at least one second device mounting position 22 in at least one direction.

[0061] It is important to understand that, as mentioned above, the types and numbers of pins on microphone sensor chips with different packages are not the same. For example, microphone sensor chip A has an input pin INP and an output pin MIC, while microphone sensor chip B has an input pin INN and an output pin MIC, and so on.

[0062] In this embodiment, each first device mounting position 21 is disposed in close proximity to at least one second device mounting position 22 in at least one direction. Since the output pin mounting positions 12 and input pin mounting positions 11 on the circuit board 00 include all input and / or output pins under all packages of the chip under test, at least one second device mounting position 22 electrically connected to other output pins is disposed in close proximity around the first device mounting position 21 to which any input pin or output pin is connected. Thus, in practical applications, for chips under test with different package forms, it is possible to find the first device mounting position 21 and the second device mounting position 22 on the circuit board 00 that correspond to its input and output pins (with the same pin attributes, such as INN input pin and MIC output pin) and have the shortest distance between them. This further shortens the distance the input / output signals travel on the circuit board 00, thereby reducing interference to the signal during transmission.

[0063] Specifically, refer to Figure 2 The first device mounting position MPAD2 is connected to the INN pin mounting position; the second device mounting position MPAD1 is connected to the MIC pin mounting position; the second device mounting position MPAD3 is connected to the VMIC pin mounting position; and the first device mounting position MPAD4 is electrically connected to the INP pin mounting position. (Connections are made via vias and wires, not shown in the diagram.)

[0064] As described in the above embodiments, the MIC pin mounting position and the VMIC pin mounting position are mounting positions used to connect different chips under test (DUTs) to the same pin. Therefore, first device mounting positions MPAD4 and MPAD2 are respectively disposed close to both sides of the second device mounting position MPAD3, which is electrically connected to the VMIC pin mounting position. In this way, regardless of whether the chip under test has an INN pin or an INP pin, the tester can find a corresponding set of closely disposed first device mounting positions 21 and second device mounting positions 22 to place a capacitor, thereby further shortening the distance of input / output signal transmission on the circuit board 00 and reducing interference to the signal during transmission.

[0065] It's important to understand that in actual testing, testers typically use wire bonding to solder the pins on the chip to the corresponding pin mounting positions 10 on the circuit board 00, establishing an electrical connection between the pins of the chip under test (DUT) and the corresponding pin mounting positions 10 on the circuit board 00. However, the wires used for wire bonding are not insulated and made of metal, such as silver alloy bonding wire. Since the positions of the pin mounting positions 10 on the circuit board 00 are fixed, when testing DUTs with different package types, due to the different pin arrangements, at least two wires will inevitably cross during wire bonding. If these crossing wires collide, a short circuit will occur, causing the test to fail.

[0066] Therefore, refer to Figure 2 In one embodiment of the present invention, a redundant pin mounting position 30 group is further provided on the top wiring layer 01 of the circuit board 00. The redundant pin mounting position 30 group includes a redundant pin mounting position 30 that is electrically connected to the chip pin mounting position 10.

[0067] Among them, the chip pin mounting position 10 and the redundant pin mounting position 30 used to connect to the same pin of the chip under test are arranged side by side and spaced apart from the chip pin mounting positions 10 and / or redundant pin mounting positions 30 used to connect to other pins of the chip under test.

[0068] In this embodiment, the redundant pin mounting position 30 is also used to connect to pins on the chip under test (DUT), and it is the same pin connected to the chip pin mounting position 10 that is electrically connected to it. There can be multiple redundant pin mounting positions 30, all of which are located on the top wiring layer 01 of the circuit board 00. When designing, researchers can design a corresponding number and pin type of redundant pin mounting positions 30 on the circuit board 00 according to the different package types of the actual DUT. It is understood that multiple redundant pin mounting positions 30, all electrically connected to the same chip pin mounting position 10, can also be provided.

[0069] In this embodiment, the chip pin mounting position 10 and redundant pin mounting position 30 connected to the same pin of the chip under test cannot be set adjacent to each other on the circuit board 00. They need to be set side by side and spaced apart from the chip pin mounting positions 10 and / or redundant pin mounting positions 30 connected to other pins of the chip under test, so as to be able to adapt to test chips under test with different package types.

[0070] Specifically, refer to Figure 6 A, Figure 6 B and Figure 2The redundant pin mounting positions 30 include DATA1 redundant pin mounting position 30, INP1 redundant pin mounting position 30, INN1 redundant pin mounting position 30, and MIC1 redundant pin mounting position 30. Among them, the DATA1 redundant pin mounting position 30 is electrically connected to the DATA pin mounting position, and the DATA1 redundant pin mounting position 30, the CLK pin mounting position, and the DATA pin mounting position are arranged side by side from top to bottom along the first direction.

[0071] refer to Figure 6 A and Figure 6 B, Figure 6 In circuit A, the DATA and CLK pins of the chip under test (DUT) are arranged from top to bottom along the first direction. At the start of the test, the tester can connect the DATA pin of the DUT to the DATA1 redundant pin mounting position 30 on circuit board 00 by wiring, and connect the CLK pin of the DUT to the CLK pin mounting position on circuit board 00. This ensures that the two connecting wires do not cross, thus preventing accidental short circuits caused by crossover.

[0072] At the same time, refer to Figure 6 B, Figure 6 In section B, the CLK and DATA pins of the chip under test (DUT) are positioned from top to bottom along the first direction. At the start of the test, the tester can connect the DUT's DATA pin to the DATA pin mounting position 10 on circuit board 00 and the DUT's CLK pin to the CLK pin mounting position on circuit board 00 using a wire bonding method. This prevents the two wires from crossing, thus avoiding accidental short circuits caused by crossover.

[0073] refer to Figure 2 In another embodiment of the present invention, a portion of the plurality of chip pin mounting positions 10 and the plurality of redundant pin mounting positions 30 are arranged along a first direction on the top wiring layer 01 of the circuit board 00, and another portion of the plurality of chip pin mounting positions 10 and the plurality of redundant pin mounting positions 30 are arranged along a second direction on the top wiring layer 01 of the circuit board 00, the second direction being different from the first direction.

[0074] It is important to understand that, as mentioned above, the chip under test (DUT) has different pin arrangements and different package configurations. Therefore, the pin pads on the DUT may not only be located on one side of the bottom edge, but may be located on multiple edges. If all the chip pin mounting positions 10 and redundant pin mounting positions 30 on the circuit board 00 are arranged side by side in the same position and in the same direction, then during the actual wire bonding process, the multiple connecting wires from the pins arranged side by side in different directions on the DUT may accidentally touch each other due to crossing, causing the aforementioned pin short circuit.

[0075] In this embodiment, a portion of the multiple chip pin mounting positions 10 and multiple redundant pin mounting positions 30 are grouped into a set of mounting positions. This set of mounting positions can be arranged from top to bottom along a first direction, or from left to right along a second direction. Furthermore, multiple sets of mounting positions can be provided in the same direction; for example, one set of mounting positions can be arranged from top to bottom along the first direction on the left side of the circuit board 00, and another set of mounting positions can be arranged from top to bottom along the first direction on the right side of the circuit board 00. The specific arrangement can be designed by the R&D personnel during the design of the circuit board 00 based on the actual package and pin arrangement of the chip under test.

[0076] Specifically, refer to Figure 2 In this embodiment, the VDD pin mounting position, DATA1 redundant pin mounting position 30, CLK pin mounting position, DATA pin mounting position, L / R pin mounting position, and GND pin mounting position are arranged from top to bottom along the first direction, and this group of pin mounting positions is placed on the circuit board 00 near the left side. The SUB pin mounting position, MIC pin mounting position, INN pin mounting position, and INP pin mounting position are arranged from top to bottom along the first direction, and this group of pin mounting positions is placed on the circuit board 00 near the right side. The MIC1 redundant pin mounting position 30, INN1 redundant pin mounting position 30, INP1 redundant pin mounting position 30, and VMIC pin mounting position are arranged from left to right along the second direction, and this group of pin mounting positions is placed on the circuit board 00 near the lower side. Specifically, the MIC1 redundant pin mounting position 30 is electrically connected to the MIC pin mounting position, the INN redundant pin mounting position 30 is electrically connected to the INN1 redundant pin mounting position 30, and the INP redundant pin mounting position 30 is electrically connected to the INP1 redundant pin mounting position 30.

[0077] refer to Figure 6 C and Figure 6 D, Figure 6In circuit C, the DATA and CLK pins of the chip under test (DUT) are positioned on the left side of the DUT along the first direction from top to bottom, while the MIC, INN, and INP pins are positioned on the right side of the DUT along the first direction from top to bottom. At the start of testing, the tester can use wire bonding to connect the DUT's DATA pin to the DATA1 redundant pin mounting position 30 on circuit board 00, the CLK pin to the CLK pin mounting position on circuit board 00, the MIC pin to the MIC pin mounting position on circuit board 00, the INN pin to the INN pin mounting position on circuit board 00, and the INP pin to the INP pin mounting position on circuit board 00. This ensures that the wires connecting the pins on the left and right sides of the DUT will not cross, thus preventing accidental short circuits caused by crossover wires.

[0078] at the same time, Figure 6 In circuit D, the DATA and CLK pins of the chip under test (DUT) are positioned on the left side of the DUT along the first direction from top to bottom, while the MIC, INN, and INP pins are positioned on the lower side of the DUT along the second direction from left to right. At the start of testing, the tester can use wire bonding to connect the DATA pin of the DUT to the DATA1 redundant pin mounting position 30 on circuit board 00, the CLK pin to the CLK pin mounting position on circuit board 00, the MIC pin to the MIC1 redundant pin mounting position 30 on circuit board 00, the INN pin to the INN1 redundant pin mounting position 30 on circuit board 00, and the INP pin to the INP1 redundant pin mounting position 30 on circuit board 00. This ensures that the wires connecting the pins on the lower left side of the DUT do not cross, preventing accidental short circuits caused by crossover wires.

[0079] Thus, in practical applications, when testers wire-connect the pins of chips under test with different packages and pin arrangements to the corresponding chip pin mounting positions 10 on the circuit board 00, the two connecting wires will not cross each other, effectively preventing short circuits caused by collisions between the crossed connecting wires, thereby further improving the accuracy of chip test results.

[0080] It is important to understand that, as described above, multiple mounting positions are set in different locations and along different directions. In this case, redundant pin mounting positions 30 and chip pin mounting positions 10, located in different positions but connected to the same chip under test, need to be electrically connected by laying signal lines on the top wiring layer 01 / bottom wiring layer 04 of the circuit board 00. However, if the chip pin mounting position 10 is an input pin mounting position 11 or an output pin mounting position 12, the signal lines used to transmit the input or output signals in the above embodiments will be easily affected by external factors due to their location on the top wiring layer 01 and bottom wiring layer 04, causing interference to the input or output signals and leading to deviations in test results. Simultaneously, since there are other signal lines transmitting signals on the same surface, multiple signal lines are often placed close together. In this case, signals transmitted on other signal lines, such as power signals, will also interfere with the input or output signals.

[0081] Therefore, refer to Figure 1-5 In one embodiment of the present invention, when the chip pin mounting position 10 electrically connected to at least one redundant pin mounting position 30 is an input pin mounting position 11 or an output pin mounting position 12, at least one redundant pin mounting position 30 is electrically connected to the corresponding chip pin mounting position 10 through a via and a first signal line.

[0082] Among them, at least one first signal line is disposed on the Nth wiring layer (1 < N < M);

[0083] A ground plane is provided on the N-1 wiring layer at the position of any first signal line on the Nth wiring layer;

[0084] A ground plane is provided at the position of any first signal line on the Nth wiring layer on the N+1 wiring layer.

[0085] In this embodiment, the via can be a fully through-hole or a blind via that only penetrates a portion of the layers (i.e., it will only connect a few wiring layers and will not electrically connect from the top wiring layer 01 to the bottom wiring layer 04).

[0086] In this embodiment, a grounding routing surface can be provided in the blank area of ​​each routing layer, such as by laying grounding copper, thereby isolating the first signal line on the routing layer between boards. This prevents it from being affected by external factors, which could affect the transmitted input or output signals.

[0087] It is understood that in this embodiment, there are multiple first signal lines, each disposed on a different wiring layer. Thus, in this embodiment, the multiple first signal lines will not all be disposed on the same wiring layer, but rather on different wiring layers; for example, two lines are on the second wiring layer 02, and one is on the third wiring layer. This prevents signal interference between the multiple first signal lines in practical applications. Simultaneously, because they are disposed on different wiring layers, the length of the first signal line between the chip pin mounting position 10 and the redundant pin mounting position 30 can be minimized (because they are not on the same wiring layer, there is more space for wiring, allowing for shorter trace lengths), thereby ensuring that the signal quality of the input / output signals is not degraded due to excessively long first signal lines.

[0088] Specifically, referring to the above embodiments and related information... Figures 2-5 The circuit board 00 has four wiring layers. The blank areas on the four wiring layers are covered with ground copper. The ground copper between the four wiring layers is electrically connected to each other through vias H12, H13, H14 and H15.

[0089] The MIC pin mounting position is electrically connected to the MIC1 redundant pin mounting position 30 via a blind via H11 connecting the top routing layer 01 and the third routing layer 03, a blind via H20 connecting the bottom routing layer 04 and the third routing layer 03, a blind via H5 connecting the top routing layer 01 and the third routing layer 03, and a first signal line placed on the third routing layer 03.

[0090] The INN pin mounting bits are electrically connected to the INN1 redundant pin mounting bit 30 via a blind via H10 connecting the top routing layer 01 and the second routing layer 02, a blind via H17 connecting the second routing layer 02 and the bottom routing layer 04, a blind via H6 connecting the top routing layer 01 and the second routing layer 02, and a first signal line placed on the second routing layer 02.

[0091] The INP pin mounting position is electrically connected to the INP1 redundant pin mounting position 30 via via H9, blind via H7 connecting the top routing layer 01 and the third routing layer 03, and the first signal line placed on the third routing layer 03.

[0092] Thus, through the above settings, not only can the first signal line transmitting input and output signals be prevented from being interfered with by the external environment, but its routing distance can also be kept short enough and not close to other first signal lines, effectively improving the signal quality of input and output signals when transmitted on the circuit board 00, thereby improving the accuracy of test results.

[0093] In one embodiment of the present invention, reference is made to... Figure 1-5The circuit board 00 also has a test terminal mounting position group;

[0094] The test terminal mounting position group includes multiple test mounting positions 40. The number of test mounting positions 40 is the same as the number of chip pin mounting positions 10. The multiple test mounting positions 40 and the multiple chip pin mounting positions 10 are electrically connected in a one-to-one correspondence. The multiple test mounting positions 40 are used to connect to the test terminal.

[0095] In this embodiment, the test mounting positions 40 can also be implemented using the pads described in the previous embodiment. Multiple test mounting positions 40 are disposed on the bottom wiring layer 04 of the circuit board 00, and the test mounting positions 40 are electrically connected to the corresponding chip pin mounting positions 10 via holes. This facilitates the electrical connection between the circuit board 00 and the test terminal during testing. Furthermore, compared to placing multiple test mounting positions 40 and chip pin mounting positions 10 on the same wiring layer, the routing distance of the first signal line connecting the test mounting positions 40 and the corresponding chip mounting positions can be effectively shortened, thereby improving the quality of the signal transmitted on the first signal line and further enhancing the accuracy of the measurement results.

[0096] Specifically, refer to Figures 1-5 Based on the above embodiments, the test mounting positions 40 group includes VDD test mounting position 40, DATA test mounting position 40, CLK test mounting position 40, L / R test mounting position 40, GND test mounting position 40, SUB test mounting position 40, MIC test mounting position 40, INN test mounting position 40, INP test mounting position 40, and VMIC test mounting position 40. The VDD test mounting position 40 is electrically connected to the VDD pin mounting position via via H1. The DATA test mounting position 40 is electrically connected to the DATA pin mounting position via via H2. The CLK test mounting position 40 is electrically connected to the CLK pin mounting position via via H3. The SUB test mounting position 40 is electrically connected to the SUB pin mounting position via via H16. The MIC test mounting position 40 is connected to the MIC pin mounting position via blind via H20 (connecting the third routing layer 03 and the bottom routing layer 04) and blind via H11 (connecting the top routing layer 01 and the third routing layer 03). The C pin mounting position is electrically connected. The INN test mounting position 40 is connected to the INN pin mounting position through a blind via H17 connecting the second routing layer 02 and the bottom routing layer 04, and a blind via H10 connecting the top routing layer 01 and the second routing layer 02. The INP test mounting position 40 is connected to the INP pin mounting position through a via H9. The VMIC test mounting position 40 is connected to the VMIC pin mounting position through a blind via H19 connecting the bottom routing layer 04 and the second routing layer 02, and a blind via H8 connecting the top routing layer 01 and the second routing layer 02.

[0097] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural transformations made using the contents of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of the present invention.

Claims

1. A microphone sensor chip test board, characterized in that, The microphone sensor chip test board includes: A circuit board, wherein chip pin mounting positions and peripheral device mounting positions are provided on the circuit board; The chip pin mounting position group includes multiple chip pin mounting positions, which are used to connect to pins on the chip under test one by one; the chip pin mounting positions include input pin mounting positions and output pin mounting positions, whereby the input pin mounting positions are used to connect to input pins on the chip under test; and the output pin mounting positions are used to connect to output pins on the chip under test. The peripheral device mounting position group includes a first device mounting position and a second device mounting position. The first device mounting position is electrically connected to the input pin mounting position, and the second device mounting position is electrically connected to the output pin mounting position. A capacitor is connected between the first device mounting position and the second device mounting position. One end of the capacitor is soldered to the first device mounting position, and the other end of the capacitor is soldered to the second device mounting position to simultaneously support AC Couple open-loop testing, AC Couple closed-loop testing, and DC Couple open-loop testing. Wherein, the first device mounting position and its corresponding input pin mounting position are closely attached to each other; the second device mounting position and its corresponding input pin mounting position are closely attached to each other; each of the first device mounting positions is closely attached to at least one of the second device mounting positions in at least one direction.

2. The microphone sensor chip test board as described in claim 1, characterized in that, The circuit board has M wiring layers, and the chip pin mounting group and the peripheral device mounting group are located on the top wiring layer.

3. The microphone sensor chip test board as described in claim 1, characterized in that, The number of input pin mounting bits, output pin mounting bits, first device mounting bits, and second device mounting bits are all multiple.

4. The microphone sensor chip test board as described in claim 3, characterized in that, The input pin mounting positions include the INN pin mounting position and the INP pin mounting position; the output pin mounting positions include the MIC pin mounting position and the VMIC pin mounting position.

5. The microphone sensor chip test board as described in claim 2, characterized in that, The top wiring layer of the circuit board is also provided with a redundant pin mounting position group, which includes redundant pin mounting positions that are electrically connected to the chip pin mounting positions. The chip pin mounting positions and redundant pin mounting positions used for connecting to the same pin of the chip under test are arranged side by side and spaced apart from the chip pin mounting positions and / or redundant pin mounting positions used for connecting other pins of the chip under test.

6. The microphone sensor chip test board as described in claim 5, characterized in that, A portion of the plurality of chip pin mounting positions and a portion of the plurality of redundant pin mounting positions are arranged along a first direction on the top wiring layer of the circuit board, and another portion of the plurality of chip pin mounting positions and the plurality of redundant pin mounting positions are arranged along a second direction on the top wiring layer of the circuit board, the second direction being different from the first direction.

7. The microphone sensor chip test board as described in claim 6, characterized in that, When at least one of the redundant pin mounting positions is electrically connected to a chip pin mounting position that is either an input pin mounting position or an output pin mounting position, at least one of the redundant pin mounting positions is electrically connected to the corresponding chip pin mounting position through a via and a first signal line. Among them, at least one of the first signal lines is disposed on the Nth wiring layer, where 1 < N < M; A ground plane is provided on the N-1 wiring layer at the position corresponding to any of the first signal lines on the Nth wiring layer; A ground plane is provided on the N+1 wiring layer at the position corresponding to any of the first signal lines on the Nth wiring layer.

8. The microphone sensor chip test board as described in claim 7, characterized in that, The number of the first signal lines is multiple, and the multiple first signal lines are respectively disposed on different wiring layers.

9. The microphone sensor chip test board as described in claim 2, characterized in that, The circuit board is also equipped with a test terminal mounting position group; The test terminal mounting position group includes multiple test mounting positions, the number of which is the same as the number of chip pin mounting positions. The multiple test mounting positions and the multiple chip pin mounting positions are electrically connected in a one-to-one correspondence, and the multiple test mounting positions are used to connect to the test terminal.

10. The microphone sensor chip test board as described in claim 9, characterized in that, Multiple test mounting positions are disposed on the bottom wiring layer of the circuit board, and the test mounting positions are electrically connected to the corresponding chip pin mounting positions through holes.

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