Peak holding circuit, pulse collection circuit and laser radar

Abstract

The application discloses a peak holding circuit, a pulse collection circuit and a laser radar, and the peak holding circuit comprises an amplifier, a negative input end of the amplifier is connected with an input signal, and a positive input end of the amplifier is connected with an output signal of the peak holding circuit; a level shifter, an input end of the level shifter is connected with an output end of the amplifier, and the level shifter is used for generating a voltage difference, so that the amplifier is always in a linear working state; and a current follower, an input end of the current follower is connected with an output end of the amplifier and an output end of the level shifter, and an output end of the current follower generates the output signal. The technical scheme can improve the precision and stability of the peak holding circuit.

Description

Technical Field

[0001] This invention relates to the field of lidar, and more particularly to a peak hold circuit, a pulse acquisition circuit, and a lidar. Background Technology

[0002] In lidar, the echo signal is typically a narrow pulse signal with a pulse width of only a few nanoseconds. The peak information of the pulse can usually characterize the signal strength and is crucial to improving the performance of lidar. To obtain the peak information of the narrow pulse signal, the common practice is to use a high-speed analog-to-digital converter (ADC) with a sampling rate of 1 GHz or higher to sample it. However, high-speed ADCs are not only complex to design and consume a lot of power, but they are also difficult to accurately sample the peak value, so they are not an ideal solution.

[0003] The pulse signals detected by lidar are typically a few nanoseconds long. In existing technologies, current mirrors (Rectifier Current Mirrors, RCMs) are usually used to achieve unidirectional conduction. Figure 1 The diagram illustrates the structure of a peak hold circuit in the prior art. The circuit's operation is divided into three stages: reset, sampling, and holding. In the reset stage, the reset signal RST is high, the reset transistor Mrst is turned on, and the output voltage Vo is reset to zero. In the sampling stage, the reset signal RST is low, the reset transistor Mrst is turned off, and when the input signal Vi's voltage value is greater than the output signal Vo's voltage value, the amplifier OTA controls the current mirror RCM to supply power to the capacitor C. H During charging, the current mirror RCM conducts unidirectionally, only affecting capacitor C. H During charging, the output signal Vo gradually increases. When the voltage value of the output signal Vo is greater than or equal to the voltage value of the input signal Vi, the output voltage of the amplifier OTA approaches the power supply voltage VDD, and the charging current drops to 0. During the sampling phase, capacitor C... H Once the peak pulse is sampled, the signal enters a hold state, and the output signal Vo will not change with the input signal Vi.

[0004] However, the OTA amplifier is a non-ideal amplifier, and it only provides gain when operating in a linear state. Specifically, when the output voltage of the OTA amplifier approaches the supply voltage VDD, the OTA amplifier operates in a non-linear state, its gain decreases, the current mirror cannot be turned off in time, and the voltage value of the output signal Vo will continue to rise, resulting in a pedal voltage error. When the input signal is a pulse signal, the output overshoot will also occur because the current mirror RCM cannot be turned off in time. Pedestal voltage error and overshoot will greatly affect the accuracy and stability of the peak hold circuit. Summary of the Invention

[0005] The technical problem solved by this invention is to improve the accuracy and stability of peak hold circuits.

[0006] To address the aforementioned technical problems, this invention provides a peak hold circuit, comprising: an amplifier, wherein an input signal is connected to the negative input terminal of the amplifier, and an output signal of the peak hold circuit is connected to the positive input terminal of the amplifier; a level shifter, wherein the input terminal of the level shifter is coupled to the output terminal of the amplifier, and the level shifter is used to generate a voltage difference to ensure that the amplifier is always in a linear operating state; and a current follower, wherein the input terminal of the current follower is coupled to the output terminal of the amplifier and the output terminal of the level shifter, and the output terminal of the current follower generates the output signal.

[0007] Optionally, the level shifter includes a first current source structure, an impedance unit, and a second current source structure. The output terminal of the first current source structure is coupled to a first terminal of the impedance unit, and the second terminal of the impedance unit is coupled to the input terminal of the second current source structure. The input terminal of the first current source structure is connected to a power supply voltage, and the output terminal of the second current source structure is grounded.

[0008] Optionally, both the first current source structure and the second current source structure are constant current sources.

[0009] Optionally, the first current source structure includes: a constant current source; a first current mirror including a third MOS transistor and a fourth MOS transistor, wherein the gate of the third MOS transistor is coupled to the gate of the fourth MOS transistor, the source of the third MOS transistor is coupled to the source of the fourth MOS transistor, the drain of the third MOS transistor is coupled to the first terminal of the constant current source, and the drain of the fourth MOS transistor is coupled to the first terminal of the impedance unit.

[0010] Optionally, the second current source structure includes: a second current mirror, comprising a fifth MOS transistor and a sixth MOS transistor, wherein the gate of the fifth MOS transistor is coupled to the gate of the sixth MOS transistor, the source of the fifth MOS transistor is coupled to the source of the sixth MOS transistor, the drain of the fifth MOS transistor is coupled to the second terminal of the constant current source, and the drain of the sixth MOS transistor is coupled to the second terminal of the impedance unit.

[0011] Optionally, the impedance unit includes: a first resistor, a first end of which is coupled to the output terminal of the first current source structure, and a second end of which is coupled to the input terminal of the second current source structure.

[0012] Optionally, the impedance unit includes: a second resistor, the first end of which is coupled to the output terminal of the first current source structure, and the second end of which is coupled to the input terminal of the second current source structure; and a compensation capacitor, which is connected in parallel with the second resistor.

[0013] Optionally, the current follower is a current mirror, which includes a first MOSFET and a second MOSFET. The gate of the first MOSFET is coupled to a first terminal of the impedance unit, the drain of the first MOSFET is coupled to a second terminal of the impedance unit, the gate of the second MOSFET is coupled to a first terminal of the impedance unit, and the drain of the second MOSFET is the output terminal of the current follower, generating the output signal.

[0014] Optionally, the voltage value of the input signal is less than the reference voltage value of the input pulse, the first MOS transistor and the second MOS transistor are both NMOS transistors, and the source of the first MOS transistor and the source of the second MOS transistor are both grounded; the first end of the impedance unit is coupled to the output end of the amplifier and the drain of the first MOS transistor respectively.

[0015] Optionally, the voltage value of the input signal is greater than the reference voltage value of the input pulse, the first MOS transistor and the second MOS transistor are both PMOS transistors, and the source of the first MOS transistor and the source of the second MOS transistor are both connected to the power supply voltage; the second terminal of the impedance unit is coupled to the output terminal of the amplifier and the drain of the first MOS transistor respectively.

[0016] Optionally, the current output by the first current source structure is equal to the current output by the second current source structure.

[0017] Optionally, the peak hold circuit further includes: an energy storage unit for storing charge, a first terminal of the energy storage unit being coupled to the output terminal of the current follower, a second terminal of the energy storage unit being grounded or connected to a power supply voltage, and the current follower being used to charge or discharge the energy storage unit according to the output signal of the amplifier.

[0018] Optionally, the energy storage unit includes a capacitor, the first end of which is coupled to the output of the current follower, and the second end of which is grounded or connected to a power supply voltage.

[0019] Optionally, the peak hold circuit further includes a reset unit for resetting the output signal of the peak hold circuit. The input terminal of the reset unit is coupled to the positive input terminal of the amplifier, and the output terminal of the reset unit is grounded or connected to a baseline voltage, which is a reference voltage of the input pulse.

[0020] Optionally, the reset unit includes a MOS transistor, the gate of which is connected to a reset signal, the drain of which is coupled to the positive input terminal of the amplifier, and the source of which is grounded or connected to the baseline voltage.

[0021] To address the aforementioned technical problems, this invention also discloses a pulse acquisition circuit, comprising: a pulse amplifier; a peak hold circuit, the input terminal of which is coupled to the output terminal of the pulse amplifier; and an analog-to-digital converter, the input terminal of which is coupled to the output terminal of the peak hold circuit.

[0022] This invention also discloses a lidar, which includes the peak hold circuit.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0024] In this invention, the peak hold circuit includes an amplifier, a level shifter, and a current follower. The level shifter generates a voltage difference, ensuring the amplifier remains in a linear operating state. In other words, by incorporating a level shifter into the peak hold circuit, the voltage difference generated by the level shifter keeps the amplifier in a linear operating state, thereby reducing base voltage errors and output overshoot when the input signal pulse peak arrives, and improving the accuracy and stability of the peak hold circuit.

[0025] Furthermore, the level shifter includes a first current source structure, an impedance unit, and a second current source structure. The output terminal of the first current source structure is coupled to a first terminal of the impedance unit, and the second terminal of the impedance unit is coupled to the input terminal of the second current source structure. The input terminal of the first current source structure is connected to a power supply voltage, and the output terminal of the second current source structure is grounded. In this invention, by incorporating an impedance unit into the level shifter, the bandwidth of the feedback loop can be increased.

[0026] Furthermore, in the technical solution of the present invention, the impedance unit may include a second resistor and a compensation capacitor connected in parallel. The compensation capacitor is connected in parallel with the second resistor, thereby enabling the compensation capacitor to form a fast AC signal transmission path with the parasitic capacitance of the current follower, increasing the feedback loop bandwidth, and thus enabling the peak holding circuit to maintain the peak value of a narrower pulse width pulse signal.

[0027] Furthermore, the peak hold circuit in the present invention includes a reset unit, the output of which can be connected to a baseline voltage, which is the reference voltage of the input pulse. By connecting the output of the reset unit to the baseline voltage, the output voltage can be reset to the reference voltage of the input pulse, thereby reducing the range of output voltage variation and thus reducing the error of the peak hold circuit. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a pulse peak acquisition circuit in the prior art;

[0029] Figure 2 This is a schematic diagram of a peak hold circuit according to an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of the specific structure of a peak holding circuit when the input signal is a positive pulse, according to an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the peak hold circuit in another embodiment of the present invention when the input signal is a positive pulse;

[0032] Figure 5 This is a schematic diagram of the peak hold circuit when the input signal is a positive pulse, according to another embodiment of the present invention.

[0033] Figure 6 This is a schematic diagram of a peak hold circuit when the input signal is a negative pulse, according to an embodiment of the present invention.

[0034] Figure 7 This is a schematic diagram of a positive pulse and a negative pulse according to an embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the peak hold circuit in another embodiment of the present invention when the input signal is a negative pulse;

[0036] Figure 9 This is a schematic diagram of a pulse acquisition circuit according to an embodiment of the present invention;

[0037] Figure 10 This is a schematic diagram of the structure of a lidar according to an embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, the amplifier OTA is a non-ideal amplifier, and it only provides gain when operating in a linear state. Specifically, when the output voltage of the amplifier OTA approaches the supply voltage VDD, the amplifier OTA operates in a non-linear state, its gain decreases, the current mirror cannot be turned off in time, and the output voltage Vo will continue to rise, resulting in a pedal voltage error. When the input signal is a pulse signal, the output overshoot will also occur because the current mirror RCM cannot be turned off in time. Pedestal voltage error and overshoot will significantly affect the accuracy and stability of the peak hold circuit.

[0039] In this invention, the peak hold circuit includes an amplifier, a level shifter, and a current follower. The level shifter generates a voltage difference, ensuring the amplifier remains in a linear operating state. In other words, by incorporating a level shifter into the peak hold circuit, the voltage difference generated by the level shifter keeps the amplifier in a linear operating state, thereby preventing base voltage errors and output overshoot when the input signal pulse peak arrives, thus improving the accuracy and stability of the peak hold circuit.

[0040] Furthermore, by setting an impedance unit in the level shifter, the bandwidth of the feedback loop can be improved in the technical solution of the present invention.

[0041] Furthermore, in the technical solution of the present invention, the impedance unit may include a second resistor and a compensation capacitor connected in parallel. The compensation capacitor is connected in parallel with the second resistor, thereby enabling the compensation capacitor to form a fast AC signal transmission path with the parasitic capacitance of the current follower, increasing the feedback loop bandwidth, and thus enabling the peak holding circuit to maintain the peak value of a narrower pulse width pulse signal.

[0042] Furthermore, the peak hold circuit in the present invention includes a reset unit, the output of which can be connected to a baseline voltage, which is the reference voltage of the input pulse. By connecting the output of the reset unit to the baseline voltage, the output voltage can be reset to the reference voltage of the input pulse, thereby reducing the range of output voltage variation and thus reducing the error of the peak hold circuit.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figure 2 This is a schematic diagram of a peak hold circuit according to an embodiment of the present invention.

[0045] The peak hold circuit mentioned in the embodiments of the present invention can be used to hold the peak value of a pulse signal, for example, to hold the peak value of the echo signal measured by a lidar.

[0046] Please refer to Figure 2 The peak hold circuit includes an amplifier, a level shifter 201, and a current follower 202.

[0047] The amplifier can be an operational transconductance amplifier (OTA), which converts the input differential voltage into an output current. The negative input terminal of the amplifier is connected to the input signal V. i The positive input terminal of the amplifier is connected to the output signal V of the peak hold circuit. o .

[0048] The input of level shifter 201 is coupled to the output of the amplifier. Level shifter 201 generates a voltage difference to ensure the amplifier always operates linearly. The input of current follower 202 is coupled to both the output of the amplifier and the output of level shifter 201. The output of current follower 202 generates the output signal V. o .

[0049] In specific implementation, the input signal V i The voltage value is greater than the output signal V o At the specified voltage value, the amplifier outputs current, and the current follower 202 outputs the current at a specific multiple, such as 1:1, generating an output signal Vo. When the voltage value of the input signal Vi reaches its peak, the voltage value of the input signal Vi equals the voltage value of the output signal Vo, and the amplifier's output current is 0. The output signal Vo remains at the peak value of the input pulse signal.

[0050] The embodiments of the present invention use the voltage difference generated by the level shifter to keep the amplifier in a linear operating state, thereby avoiding base voltage error and output overshoot when the pulse peak of the input signal arrives, and improving the accuracy and stability of the peak hold circuit.

[0051] Figure 3 A peak hold circuit for a specific application scenario is illustrated. In this embodiment, the input signal V i It is a positive pulse, that is, the input signal V i The voltage value is always greater than the baseline voltage V. i,Dc .

[0052] In this embodiment of the invention, the level shifter 201 may include a first current source structure, an impedance unit, and a second current source structure. The output terminal of the first current source structure is coupled to the first terminal of the impedance unit, and the second terminal of the impedance unit is coupled to the input terminal of the second current source structure. The input terminal of the first current source structure is connected to the power supply voltage VDD, and the output terminal of the second current source structure is grounded.

[0053] In specific implementation, the first current source structure is a constant current source Ib1, and the second current source structure is a constant current source Ib2. The impedance unit includes a first resistor R1, the first end of which is coupled to the output terminal of the first current source structure Ib1, and the second end of which is coupled to the input terminal of the second current source structure Ib2.

[0054] In this embodiment, the current follower 203 is a current mirror, which includes a first MOSFET M1 and a second MOSFET M2. The gate of the first MOSFET M1 is coupled to the first terminal of a first resistor R1, and the drain of the first MOSFET M1 is coupled to the second terminal of the first resistor R1. The gate of the second MOSFET M2 is coupled to the first terminal of the first resistor R1, and the drain of the second MOSFET M2 serves as the output terminal of the current mirror, that is, the output terminal of the current follower 203, generating the output signal V. o Among them, the first MOS transistor M1 and the second MOS transistor M2 are both PMOS transistors.

[0055] In this embodiment, the peak hold circuit may further include an energy storage unit for storing charge. The first terminal of the energy storage unit is coupled to the output terminal of the current follower 203, and the second terminal of the energy storage unit is grounded or connected to the power supply voltage VDD. The current follower 203 is used to charge the energy storage unit according to the output signal of the amplifier. Specifically, the energy storage unit is a capacitor C. H Capacitor C H The first terminal is coupled to the drain of the second MOS transistor M2, and the capacitor C H The second end is grounded.

[0056] In this embodiment, the peak hold circuit may further include a reset unit for resetting the output signal of the peak hold circuit. The input terminal of the reset unit is coupled to the positive input terminal of the amplifier, and the output terminal of the reset unit is grounded or connected to a baseline voltage, which is the reference voltage of the input pulse. In a specific implementation, the reset unit includes a MOSFET M rst The MOS transistor M rst The gate of the MOS transistor is connected to the reset signal RST. rst The drain of the MOSFET is coupled to the positive input terminal of the amplifier, and the source of the MOSFET is grounded or connected to the baseline voltage V.i,Dc The reset unit acts as a reset switch, capable of resetting the output signal V. o The voltage value is reset to the ground voltage or baseline voltage V. i,Dc .

[0057] In practice, during the reset phase, when the reset signal RST is high, the voltage value of the output signal Vo is reset to the ground voltage or the baseline voltage (also known as the DC level) Vi,dc of the input signal Vi. By resetting to the baseline voltage Vi,dc, the voltage value of the output signal Vo changes less, thereby reducing errors.

[0058] In practice, the transconductance amplifier converts the voltage input into a current output and superimposes it onto the current of the first MOSFET M1. The current mirror accurately mirrors the current, converting the current of the first MOSFET M1 into the current of the second MOSFET M2 at a specific multiple (e.g., 1:1), and then directing it to capacitor C. H A unidirectional current is provided to charge it until the pulse peak. When capacitor C H When the voltage reaches the peak pulse, the output current of the transconductance amplifier is close to 0, so there is basically no overshoot.

[0059] In practical implementation, current sources Ib1 and Ib2 are constant current sources, and their outputs are in a high-impedance state, meaning the generated current is independent of the applied voltage. Furthermore, the output currents of current sources Ib1 and Ib2 are equal. Therefore, when the input signal Vi reaches its peak value, the input signal Vi's voltage value is equal to the output signal Vo's voltage value, and the transconductance amplifier does not need to provide additional output current. Current sources Ib1 and Ib2, along with the first resistor R1, keep the voltage Vdg between the gate and drain of the first MOS transistor M1 stable, i.e., Vdg = Ib × R, where Ib is the current output by current sources Ib1 and Ib2, and R is the resistance value of the first resistor. When capacitor C... H When the voltage reaches the pulse peak, the current in the first MOSFET M1 and the second MOSFET M2 is 0. Because the current sources Ib1 and Ib2 and the resistor R keep the transconductance amplifier in a linear operating state, it can still function normally, avoiding errors caused by the decrease in OTA gain and improving loop stability. Furthermore, the resistance value of the first resistor R1 is typically several hundred ohms, and the output of the transconductance amplifier is coupled to R1. Compared to the output of the transconductance amplifier being directly coupled to the gate of the MOSFET (which has extremely high gate impedance, typically several hundred megohms), this significantly reduces the output impedance of the transconductance amplifier, increasing the bandwidth of the feedback loop and enabling the circuit to maintain the pulse peak of narrow pulse widths (e.g., 2 nanoseconds).

[0060] In this embodiment of the invention, the current mirror has a large output impedance, which is high when there is no current and low when there is current. Therefore, using a current mirror will make the feedback loop more stable.

[0061] The current mirror in this embodiment of the invention can achieve a current follower ratio of 1:1. Compared with other ratios such as 1:2, 1:3, etc., the impedance of the current follower is smaller.

[0062] It should be noted that in practical applications, other ratios of the current mirror structure can be set according to different application requirements, such as 1:2, 1:3, etc., and the embodiments of the present invention do not limit this.

[0063] Please refer to Figure 4 ,and Figure 3 Unlike the peak hold circuit shown, in Figure 4 In the peak hold circuit shown, the impedance unit includes a second resistor R2 and a compensation capacitor Cc. The first end of the second resistor R2 is coupled to the output terminal of the first current source structure Ib1, and the second end of the second resistor R2 is coupled to the input terminal of the second current source structure Ib2. The compensation capacitor Cc is connected in parallel with the second resistor R2. That is, the first end of the compensation capacitor Cc is coupled to the output terminal of the first current source structure Ib1, and the second end of the compensation capacitor Cc is coupled to the input terminal of the second current source structure Ib2.

[0064] exist Figure 3 In the circuit structure shown, the output current of the transconductance amplifier passes through the RC circuit formed by the parasitic capacitance of the first resistor R1 and the first MOS transistor M1. The parasitic capacitance needs to be charged, and the current signal is fed back to the output signal Vo relatively slowly.

[0065] In this embodiment, frequency compensation can be achieved by connecting a second resistor R2 and a compensation capacitor Cc in parallel. The compensation capacitor Cc has the characteristics of passing AC and having low impedance at high frequencies. By connecting it in parallel with the second resistor R2, it can be short-circuited. Thus, the compensation capacitor Cc can form a fast AC signal transmission path with the parasitic capacitances of the first MOSFET M1 and the second MOSFET M2, increasing the feedback loop bandwidth, thereby enabling the circuit to maintain the pulse peak value of narrow pulse width pulses.

[0066] Please refer to Figure 5 ,and Figure 3 The first current source structure is a constant current source Ib1, and the second current source structure is a constant current source Ib2. The difference is that in this embodiment, the first current source structure and the second current source structure are formed by a single current source through two current mirrors.

[0067] In this embodiment, the first current source structure includes a constant current source I and a first current mirror. The first current mirror includes a third MOSFET M3 and a fourth MOSFET M4. The gate of the third MOSFET M3 is coupled to the gate of the fourth MOSFET M4, the source of the third MOSFET M3 is coupled to the source of the fourth MOSFET M4, the drain of the third MOSFET M3 is coupled to the first terminal of the constant current source, and the drain of the fourth MOSFET M4 is coupled to the first terminal of the impedance unit. Both the third MOSFET M3 and the fourth MOSFET M4 are PMOS transistors.

[0068] The second current source structure includes a second current mirror. The second current mirror includes a fifth MOSFET M5 and a sixth MOSFET M6. The gate of the fifth MOSFET M5 is coupled to the gate of the sixth MOSFET M6, the source of the fifth MOSFET M5 is coupled to the source of the sixth MOSFET M6, the drain of the fifth MOSFET M5 is coupled to the second terminal of the constant current source, and the drain of the sixth MOSFET M6 is coupled to the second terminal of the impedance unit. Both the fifth MOSFET M5 and the sixth MOSFET M6 are NMOS transistors.

[0069] It should be noted that, Figure 5 The impedance unit shown is a parallel structure of the second resistor R2 and the compensation capacitor Cc, which can also be... Figure 3 The first resistor R1 shown is not limited in this embodiment of the invention.

[0070] Figure 3 , Figure 4 and Figure 5 The circuit structure shown can be applied to input signal V i This is a scenario with a positive pulse.

[0071] Please refer to Figure 6 , Figure 6 A peak hold circuit for a specific application scenario is illustrated. In this embodiment, the input signal V i It is a negative pulse, that is, the input signal V i The voltage value is always less than the baseline voltage V. i,Dc .

[0072] Refer to together Figure 7The input signal is divided into positive and negative pulses because the bias circuit of the detector (such as the detector in a lidar system) acquires the pulse signal at different locations. When the detector does not detect an echo pulse, its baseline voltage is Vbias. When the detector detects an echo pulse, it generates current, creating a path between the baseline voltage Vbias and ground. The voltage at the output location is less than the baseline voltage Vbias, thus forming a negative pulse signal. Alternatively, when the detector does not detect an echo pulse, its baseline voltage is 0. When the detector detects an echo pulse, it generates current, creating a path between the baseline voltage Vbias and ground. The voltage at the output location is greater than 0, thus forming a positive pulse signal.

[0073] Furthermore, after the detector detects the pulse signal, it needs to be amplified by a front-end amplifier. The front-end amplifier can be a positive amplifier or an inverting amplifier, and it can also change the pulse signal to generate a positive pulse signal or a negative pulse signal, thereby transmitting it to the peak hold circuit.

[0074] and Figure 3 The difference in the illustrated embodiment is that both the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors, and the capacitor C... H Perform a discharge operation.

[0075] Accordingly, the sources of the first MOSFET M1 and the second MOSFET M2 are both grounded; the first terminal of the first resistor R1 is coupled to the output terminal of the amplifier and the drain of the first MOSFET M1, respectively. Capacitor C H The first terminal is coupled to the drain of the second MOS transistor M2, and the capacitor C H The second terminal is connected to the power supply voltage VDD.

[0076] In this embodiment, the output terminal of the transconductance amplifier is coupled to the source of the first MOS transistor M1, and the control capacitor C... H A unidirectional current is supplied to the current mirror, and the capacitor C H Discharge until the negative pulse peak is reached.

[0077] Further, please refer to Figure 8 ,and Figure 6 The illustrated embodiment differs in that the impedance unit includes a second resistor R2 and a compensation capacitor Cc. The first end of the second resistor R2 is coupled to the output terminal of the first current source structure Ib1, and the second end of the second resistor R2 is coupled to the input terminal of the second current source structure Ib2. The compensation capacitor Cc is connected in parallel with the second resistor R2. That is, the first end of the compensation capacitor Cc is coupled to the output terminal of the first current source structure Ib1, and the second end of the compensation capacitor Cc is coupled to the input terminal of the second current source structure Ib2.

[0078] Understandably, in Figure 6 and Figure 8 In the peak hold circuit shown, the first current source structure is a constant current source Ib1, and the second current source structure is a constant current source Ib2, which can also be replaced by... Figure 5 The first and second current source structures shown are structures formed by a single current source through two current mirrors, and the embodiments of the present invention do not limit this.

[0079] about Figure 6 and Figure 8 For more information on the working principle and operation mode of the peak hold circuit shown, please refer to [link / reference]. Figures 1 to 5 The relevant descriptions in the text will not be repeated here.

[0080] This invention also discloses a pulse acquisition circuit, please refer to... Figure 9 The pulse acquisition circuit includes: a pulse amplifier 901, a peak hold circuit 902, and an analog-to-digital converter 903.

[0081] The input terminal of the peak hold circuit 902 is coupled to the output terminal of the pulse amplifier 901; the input terminal of the analog-to-digital converter 903 is coupled to the output terminal of the peak hold circuit 902.

[0082] In a specific implementation, the pulse amplifier 901 can be a trans-impedance amplifier (TIA). The detected pulse signal is amplified by the amplifier, the peak hold circuit 902 holds the peak voltage of the amplified pulse signal, and the analog-to-digital converter 903 samples the signal output by the peak hold circuit to obtain the peak data of the pulse.

[0083] Please refer to Figure 10 The present invention also provides a lidar, the lidar comprising:

[0084] The transmitting unit 1001 is configured to emit a detection beam for detecting the target object 1003; and

[0085] The receiving unit 1002 is configured to receive the echo beam reflected by the detection beam on the target object 1003 and convert the echo beam into an echo signal.

[0086] The lidar includes the peak hold circuit. The peak hold circuit is used to hold the pulse peak value of the echo signal measured by the lidar.

[0087] Furthermore, the lidar may also include the pulse acquisition circuit described in the foregoing embodiments.

[0088] Where L represents the transmission path of the probe beam and L' represents the transmission path of the echo beam.

[0089] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0090] In the embodiments of this application, "multiple" refers to two or more.

[0091] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0092] In this application, the term "connection" refers to various connection methods, such as direct connection or indirect connection, to achieve communication between devices. This application does not impose any limitations on this.

[0093] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0094] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0095] In the several embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, and systems can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation; for example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can be physically comprised separately, or two or more units can be integrated into one unit. The integrated unit described above can be implemented in hardware or in the form of hardware plus software functional units.

[0098] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute some steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A peak hold circuit, characterized in that, include: An amplifier, wherein the negative input terminal of the amplifier is connected to an input signal, and the positive input terminal of the amplifier is connected to the output signal of the peak hold circuit; A level shifter, the input of which is coupled to the output of the amplifier, is used to generate a voltage difference so that the amplifier is always in a linear operating state. A current follower, the input of which is coupled to the output of the amplifier and the output of the level shifter, and the output of the current follower generates the output signal. The amplifier is a transconductance amplifier.

2. The peak hold circuit according to claim 1, characterized in that, The level shifter includes a first current source structure, an impedance unit, and a second current source structure. The output terminal of the first current source structure is coupled to the first terminal of the impedance unit, and the second terminal of the impedance unit is coupled to the input terminal of the second current source structure. The input terminal of the first current source structure is connected to a power supply voltage, and the output terminal of the second current source structure is grounded.

3. The peak hold circuit according to claim 2, characterized in that, Both the first current source structure and the second current source structure are constant current sources.

4. The peak hold circuit according to claim 2, characterized in that, The first current source structure includes: Constant current source; The first current mirror includes a third MOS transistor and a fourth MOS transistor. The gate of the third MOS transistor is coupled to the gate of the fourth MOS transistor, the source of the third MOS transistor is coupled to the source of the fourth MOS transistor, the drain of the third MOS transistor is coupled to the first terminal of the constant current source, and the drain of the fourth MOS transistor is coupled to the first terminal of the impedance unit.

5. The peak hold circuit according to claim 4, characterized in that, The second current source structure includes: The second current mirror includes a fifth MOS transistor and a sixth MOS transistor. The gate of the fifth MOS transistor is coupled to the gate of the sixth MOS transistor, the source of the fifth MOS transistor is coupled to the source of the sixth MOS transistor, the drain of the fifth MOS transistor is coupled to the second terminal of the constant current source, and the drain of the sixth MOS transistor is coupled to the second terminal of the impedance unit.

6. The peak hold circuit according to claim 2, characterized in that, The impedance unit includes: A first resistor, the first end of which is coupled to the output terminal of the first current source structure, and the second end of which is coupled to the input terminal of the second current source structure.

7. The peak hold circuit according to claim 2, characterized in that, The impedance unit includes: The second resistor has a first end coupled to the output terminal of the first current source structure and a second end coupled to the input terminal of the second current source structure. A compensation capacitor is connected in parallel with the second resistor.

8. The peak hold circuit according to claim 2, characterized in that, The current follower is a current mirror, and the current mirror includes: A first MOSFET and a second MOSFET, wherein the gate of the first MOSFET is coupled to the first terminal of the impedance unit, the drain of the first MOSFET is coupled to the second terminal of the impedance unit, the gate of the second MOSFET is coupled to the first terminal of the impedance unit, and the drain of the second MOSFET is the output terminal of the current follower, thereby generating the output signal.

9. The peak hold circuit according to claim 8, characterized in that, The voltage value of the input signal is less than the reference voltage value of the input pulse. Both the first MOS transistor and the second MOS transistor are NMOS transistors. The source of both the first MOS transistor and the source of the second MOS transistor are grounded. The first end of the impedance unit is coupled to the output end of the amplifier and the drain of the first MOS transistor, respectively.

10. The peak hold circuit according to claim 8, characterized in that, The voltage value of the input signal is greater than the reference voltage value of the input pulse. Both the first MOS transistor and the second MOS transistor are PMOS transistors. The source of the first MOS transistor and the source of the second MOS transistor are both connected to the power supply voltage. The second terminal of the impedance unit is coupled to the output terminal of the amplifier and the drain of the first MOS transistor, respectively.

11. The peak hold circuit according to claim 2, characterized in that, The current output by the first current source structure is equal to the current output by the second current source structure.

12. The peak hold circuit according to claim 1, characterized in that, Also includes: An energy storage unit is provided, wherein the energy storage unit is used to store electric charge, the first end of the energy storage unit is coupled to the output end of the current follower, the second end of the energy storage unit is grounded or connected to a power supply voltage, and the current follower is used to charge or discharge the energy storage unit according to the output signal of the amplifier.

13. The peak hold circuit according to claim 12, characterized in that, The energy storage unit includes a capacitor, the first end of which is coupled to the output of the current follower, and the second end of which is grounded or connected to a power supply voltage.

14. The peak hold circuit according to claim 1, characterized in that, Also includes: A reset unit is used to reset the output signal of the peak hold circuit. The input terminal of the reset unit is coupled to the positive input terminal of the amplifier, and the output terminal of the reset unit is grounded or connected to a baseline voltage, which is the reference voltage of the input pulse.

15. The peak hold circuit according to claim 14, characterized in that, The reset unit includes a MOS transistor, the gate of which is connected to a reset signal, the drain of which is coupled to the positive input terminal of the amplifier, and the source of which is grounded or connected to the baseline voltage.

16. A pulse acquisition circuit, characterized in that, include: Pulse amplifier; The peak hold circuit as described in any one of claims 1 to 15, wherein the input terminal of the peak circuit is coupled to the output terminal of the pulse amplifier; An analog-to-digital converter, wherein the input of the analog-to-digital converter is coupled to the output of the peak hold circuit.

17. A lidar, characterized in that, Includes the peak hold circuit as described in any one of claims 1 to 15.

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