A reset operation processing method, device and medium
By introducing a reset controller into the BMC chip, the reset operations of each IP controller are managed in a unified manner, which solves the problem of wasted hardware logic and realizes the efficient reuse of reset operations.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2022-06-30
- Publication Date
- 2026-07-31
AI Technical Summary
The redundant implementation of reset logic in each IP controller of the existing BMC chip leads to a waste of hardware logic and low reuse rate of reset operations.
A reset controller is introduced into the BMC chip. This controller obtains the reset requirements of each on-chip controller and external device PIN controller, sets the register definition corresponding to the reset controller, initializes and instantiates it, and calls the operation function to trigger the reset operation.
It saves hardware logic resources, improves the reusability of reset operations, complies with SoC design specifications, and improves resource utilization efficiency.
Smart Images
Figure CN115113709B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip control, and in particular to a method, apparatus and medium for resetting operations. Background Technology
[0002] With the use and development of Baseboard Management Controller (BMC) chips, the functions of on-chip controllers and external device PIN controllers have also increased. When the System-on-Chip (SoC) is physically powered on, the timing of each on-chip controller and the complex external device PIN controller needs to be reset during the initialization phase; or when the controller or external device malfunctions, the reset signal may restore its abnormal state to the initial state; or when the controller supports low-power mode, it can be restored to normal operation mode from the suspended state to the wake-up state through the reset operation. It can be seen that the reset operation is becoming increasingly important.
[0003] Currently, mainstream BMC chips do not implement an independent unified reset operation on their SoCs. Instead, each module implements its own reset logic to drive the initialization of the Integration Proportion (IP) controller, triggering the reset operation by writing to a specified register. Since the reset logic is the same for each IP controller, the reset logic is implemented repeatedly in each IP controller, resulting in wasted hardware logic.
[0004] Therefore, improving the reusability of reset operations is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a method, apparatus, and medium for resetting operations, which saves hardware logic resources and improves the reusability of resetting operations.
[0006] To solve the above-mentioned technical problems, the present invention provides a reset operation processing method applied to a BMC chip, comprising:
[0007] Obtain the reset requirements of each on-chip controller and each external device PIN controller;
[0008] The reset definition of the register corresponding to the reset controller is set according to the reset requirements of both, where the reset controller is located at the BMC chip;
[0009] The reset controller is initialized to put it into a ready state, and the operation function of the initialized reset controller is instantiated.
[0010] When a driver performs a reset operation, the control reset controller calls the instantiated operation function and writes it to the register to trigger the reset operation, where the reset operation is any reset operation of the on-chip controller or the external device PIN controller.
[0011] Preferably, the register is a 32-bit register, and the reset definition of the register corresponding to the reset controller is set according to the reset requirements of both, including:
[0012] The system obtains a first number of reset requests from the on-chip controller, a second number of reset requests from the external device PIN controller, and a third number of offset addresses for the registers supporting reset signals, wherein the first and second numbers are both less than or equal to the third number, and the offset addresses are 32 offset addresses.
[0013] Enable the reset signals of the on-chip controller and the external device PIN controller by setting the first offset address and the second offset address respectively;
[0014] Set the trigger level states of the on-chip controller and the external device PIN controller to the third offset address and the fourth offset address, respectively;
[0015] Set the reset pulse width of the on-chip controller and the external device PIN controller respectively from the fifth offset address to the seventeenth offset address and from the eighteenth offset address to the thirtieth offset address;
[0016] Set the real-time level status of the on-chip controller and the external device PIN controller at offset addresses 31 and 32, respectively.
[0017] Preferably, initializing the reset controller includes:
[0018] Obtain the driver information and device tree information corresponding to the reset controller;
[0019] The probe function is called when the device node in the device tree information matches the ID information in the driver information.
[0020] The probe function is used to parse the device tree information to obtain the hardware information corresponding to the reset controller.
[0021] Obtain the external resources corresponding to the reset controller and initialize them to the initialization state corresponding to the reset controller. The external resources include at least a clock signal and a reset signal.
[0022] Enable the reset controller to complete its initialization.
[0023] Preferably, the initialized reset controller is instantiated with an operation function, including:
[0024] Obtain the core structure corresponding to the initialized reset controller;
[0025] Obtain the corresponding set of operation functions based on the core structure;
[0026] Instantiate the callback function for the set of operation functions.
[0027] Preferably, it further includes:
[0028] Hardware information is stored in a software structure for abstraction to facilitate subsequent processing.
[0029] To solve the above-mentioned technical problems, the present invention also provides a reset operation processing device applied to a BMC chip, including on-chip controllers, external device PIN controllers, a reset controller, and a controller.
[0030] Each on-chip controller is connected to the reset controller;
[0031] Each external device's PIN controller is connected to the reset controller;
[0032] The controller is connected to the reset controller to obtain the reset requirements of each on-chip controller and each external device PIN controller, set the reset definition of the register corresponding to the reset controller according to the reset requirements, initialize the reset controller so that the reset controller is in a ready state, and instantiate the operation function of the initialized reset controller.
[0033] When a driver performs a reset operation, the control reset controller calls the instantiated operation function and writes it to the register to trigger the reset operation, where the reset operation is any reset operation of the on-chip controller or the external device PIN controller.
[0034] Preferably, it also includes a GPIO controller:
[0035] The GPIO controller connects to one of the PIN controllers of each external device to perform other operations of the GPIO controller when no reset operation is present.
[0036] To address the aforementioned technical problems, the present invention also provides a reset operation processing device applied to a BMC chip, comprising:
[0037] The acquisition module is used to acquire the reset requirements of each on-chip controller and the reset requirements of each external device PIN controller.
[0038] The configuration module is used to set the reset definition of the register corresponding to the reset controller according to the reset requirements of both, where the reset controller is located at the BMC chip;
[0039] The initialization module is used to initialize the reset controller so that the reset controller is in a ready state, and to instantiate the operation functions of the initialized reset controller;
[0040] The write module is used to control the reset controller to call the instantiated operation function and write to the register to trigger the reset operation when a driver reset operation is performed. The reset operation can be any reset operation of the on-chip controller or the PIN controller of an external device.
[0041] To solve the above-mentioned technical problems, the present invention also provides a processing device for a reset operation, comprising:
[0042] Memory, used to store computer programs;
[0043] A processor, used to implement the steps of a processing method such as the reset operation described above when executing a computer program.
[0044] To address the aforementioned technical problems, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the processing method described above for resetting the operation.
[0045] This invention provides a reset operation processing method applied to a BMC chip, comprising: acquiring the reset requirements of each on-chip controller and each external device PIN controller; setting the reset definition of the register corresponding to the reset controller according to the reset requirements of both, wherein the reset controller is located at the BMC chip; initializing the reset controller to put it in a ready state, and instantiating the initialized reset controller into an operation function; when driving a reset operation, controlling the reset controller to call the instantiated operation function and write to the register to trigger the reset operation, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller. This method, by setting a reset controller, incorporates the reset logic of each IP controller into the reset controller, defines the reset content of the register according to the reset requirements, saves hardware logic resources, and improves the reusability of reset operations.
[0046] This invention also provides a reset operation processing device applied to a BMC chip, comprising: on-chip controllers, external device PIN controllers, a reset controller, and a controller; each on-chip controller is connected to the reset controller; each external device PIN controller is connected to the reset controller; the controller is connected to the reset controller and is used to acquire the reset requirements of each on-chip controller and each external device PIN controller; set the reset definition of the register corresponding to the reset controller according to the reset requirements of both, wherein the reset controller is located at the BMC chip; initialize the reset controller to put it in a ready state, and instantiate the operation function of the initialized reset controller; when driving a reset operation, control the reset controller to call the instantiated operation function and write to the register to trigger the reset operation, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller. This device, by setting a reset controller, allows the reset logic of each IP controller to be introduced into the reset controller, and defines the reset content of the register according to the reset requirements, saving hardware logic resources and improving the reusability of reset operations.
[0047] In addition, the present invention also provides a processing device and medium for a reset operation, which has the same beneficial effects as the reset operation processing method described above. Attached Figure Description
[0048] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 A flowchart illustrating a reset operation processing method provided in an embodiment of the present invention;
[0050] Figure 2 A schematic diagram of the initialization process of a reset controller provided in an embodiment of the present invention;
[0051] Figure 3 This is a structural diagram of a reset operation processing device provided in an embodiment of the present invention;
[0052] Figure 4 A structural diagram of a processing device for another reset operation provided in an embodiment of the present invention;
[0053] Figure 5 This is a structural diagram of a reset operation processing device provided in another embodiment of the present invention. Detailed Implementation
[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.
[0055] The core of this invention is to provide a method, apparatus, and medium for resetting operations, which saves hardware logic resources and improves the reusability of resetting operations.
[0056] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0057] It should be noted that the reset operation processing method provided by the present invention is applicable to the SoC of BMC chip. It extracts the original reset logic that exists in the PIN controller of each on-chip controller and external device and centrally implements it in the reset controller. When a certain IP controller needs to be reset, it operates the register of the reset controller to generate a reset signal.
[0058] Figure 1 A flowchart of a reset operation processing method provided in an embodiment of the present invention is shown below. Figure 1 As shown, this method is applied to a BMC chip and includes:
[0059] S11: Obtain the reset requirements of each on-chip controller and each external device PIN controller;
[0060] S12: Set the reset definition of the register corresponding to the reset controller according to the reset requirements of both, where the reset controller is located at the BMC chip;
[0061] S13: Initialize the reset controller to put it in a ready state, and instantiate the operation function of the initialized reset controller;
[0062] S14: When driving a reset operation, the control reset controller calls the instantiated operation function and writes it to the register to trigger the reset operation, where the reset operation is any reset operation of the on-chip controller or the external device PIN controller.
[0063] Specifically, step S11 involves obtaining the reset requirements of each on-chip controller and each external device PIN controller. An on-chip controller is an integrated circuit that combines many elements of a computer system into a single chip. Each external device PIN controller is a PIN input for an external device. The two types of reset requirements differ, and even among controllers of the same type, the reset requirements vary. Registers need to be defined according to the reset requirements of each controller.
[0064] In step S12, the reset definition of the register corresponding to the reset controller is set according to the reset requirements of both. Since the reset controller is located at the BMC chip and is not an external device, its reset signal can be set according to the number of bits supported by the register. For example, the register level supports a maximum of 32 on-chip reset signals, so the reset signal corresponding to the reset requirement of the on-chip controller must be less than or equal to 32, and the reset signal corresponding to the reset requirement of the external device PIN controller must be less than or equal to 32, shared with the GPIO pin. It should be noted that the definition of the register is determined according to the actual register mapping address. The basic register bit is 32 bits, 4 bytes, the memory address requires 4 bits, the base address is the first address, and the offset address is a positive integer, which is also an incrementing number. For example, the base address is 10, the offset is 4, so the actual address is 14. The starting address of each peripheral can also be further decomposed into a base address and an offset address. The specific setting process is not the focus of this embodiment of the invention, so it is not specifically limited.
[0065] Step S13 initializes the reset controller, putting it into a ready state. This initialization includes both hardware and software initialization; the process involves abstracting hardware information and representing it in software form, controlling the hardware through software. Any embedded application running on actual hardware must perform basic system initialization at startup. The reset handler, a block of code written in assembly language, is executed immediately upon system startup to complete the system initialization. For kernels with local memory, necessary configurations need to be completed during initialization.
[0066] Step S13 involves instantiating the operation function of the initialized reset controller. Instantiation, in object-oriented programming, refers to the process of creating an object from a class; it's the process of making an abstract concept class concrete into a physical entity of that class. Instantiation typically consists of the syntax: `ClassNameObjectName = newClassName(parameter1, parameter2...parametern)`. Initialization is the process of assigning values to the object, while instantiation is the process of allocating memory for the object using `new`. In this embodiment, the instantiation is performed using the corresponding callback function. When the controller or external device PIN controller driver needs to perform a reset operation, it doesn't directly manipulate the raw hardware registers but instead calls the unified function interface encapsulated by the `reset subsystem` to complete the reset.
[0067] In step S14, when a drive reset operation is performed, the reset controller calls the instantiated operation function and writes it to the register to trigger the reset operation. This reset operation is either the on-chip controller's or the external device's PIN controller's reset operation. In other words, when either controller needs to perform a reset operation, it is determined to be a drive reset operation. The reset controller then calls the instantiated operation function and writes the operation register, causing the specified reset state in the drive register to generate a reset signal, thus triggering the reset operation. It should be noted that the current reset operation can be either of the two controller types; two reset operations cannot exist simultaneously.
[0068] This invention provides a reset operation processing method applied to a BMC chip, comprising: acquiring the reset requirements of each on-chip controller and each external device PIN controller; setting the reset definition of the register corresponding to the reset controller according to the reset requirements of both, wherein the reset controller is located at the BMC chip; initializing the reset controller to put it in a ready state, and instantiating the initialized reset controller into an operation function; when driving a reset operation, controlling the reset controller to call the instantiated operation function and write to the register to trigger the reset operation, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller. This method, by setting a reset controller, incorporates the reset logic of each IP controller into the reset controller, defines the reset content of the register according to the reset requirements, saves hardware logic resources, and improves the reusability of reset operations.
[0069] Based on the above embodiments, since there are multiple cases of register bit length, this embodiment is limited to the case of 32-bit register. Step S12, which sets the reset definition of the register corresponding to the reset controller according to the reset requirements of both, includes:
[0070] The system obtains a first number of reset requests from the on-chip controller, a second number of reset requests from the external device PIN controller, and a third number of offset addresses for the registers supporting reset signals, wherein the first and second numbers are both less than or equal to the third number, and the offset addresses are 32 offset addresses.
[0071] Enable the reset signals of the on-chip controller and the external device PIN controller by setting the first offset address and the second offset address respectively;
[0072] Set the trigger level states of the on-chip controller and the external device PIN controller to the third offset address and the fourth offset address, respectively;
[0073] Set the reset pulse width of the on-chip controller and the external device PIN controller respectively from the fifth offset address to the seventeenth offset address and from the eighteenth offset address to the thirtieth offset address;
[0074] Set the real-time level status of the on-chip controller and the external device PIN controller at offset addresses 31 and 32, respectively.
[0075] Specifically, the register layer supports a maximum of 32 on-chip reset signals, with 21 actually routed to the on-chip controller, supporting the reset needs of 21 on-chip controllers. This is because, based on current technology, the maximum number of on-chip controllers is 21, hence the setting of 21 to support their reset requirements. External reset signals also support a maximum of 32, all of which are routed and shared with GPIO. Since the current registers are 32 bits, a maximum of 32 external device signals are supported.
[0076] In this embodiment, the first number of reset requirements for the on-chip controller and the second number of reset requirements for the external device PIN controller are both less than or equal to the third number of offset addresses of the register supporting the reset signal.
[0077] The number of offset addresses provided in this embodiment can be adjusted according to actual circumstances. For example, the first offset address here does not necessarily correspond to 0x00. As a preferred embodiment, it is as follows:
[0078] 1. 0x00 & 0x04
[0079] 0x00 is used to enable the on-chip controller reset signal. Each bit from bit0 to bit20 corresponds to an on-chip controller reset signal. Bits21 to bit31 are reserved and can be written to 1 to enable.
[0080] 0x04 is used to enable the external reset signal. All 32 bits have a corresponding pin. Write 1 to enable.
[0081] 2. 0x08 & 0x0c
[0082] 0x08 is used to set the trigger level of the on-chip controller reset signal. Writing 1 to the corresponding bit indicates a high-level trigger, and writing 0 indicates a low-level trigger.
[0083] 0x0c is used to set the trigger level of the external reset signal. Writing 1 to the corresponding bit indicates a high-level trigger, and writing 0 indicates a low-level trigger.
[0084] 3. 0x10~0x2c
[0085] The reset pulse width setting is important because some controllers or external devices require a pulse of a specific width for the reset operation. If the reset pin is operated in software, the resulting pulse width cannot be guaranteed to be accurate enough. Therefore, the ResetController implements the pulse width setting at the hardware level.
[0086] 0x10 to 0x1c are allocated to the on-chip controller, and 0x20 to 0x2c are allocated to the external reset signal. Each register has 4 bits corresponding to a reset pulse setting, with a total of 15 selectable width levels: 0x0 corresponds to 250*2^0us, 0x1 corresponds to 250*2^1us, and 0x02 corresponds to 250*2^2us.
[0087] 0x20 to 0x2c are assigned to external reset signals, with the same definition as 0x10 to 0x1c.
[0088] 4. 0x30 & 0x34
[0089] This indicates the real-time level status on the reset line, which is used for software lookup. 0x30 corresponds to the on-chip controller reset signal, and 0x34 corresponds to the external reset signal. The corresponding bit is 1 to indicate a high level and 0 to indicate a low level.
[0090] The reset definition provided by this invention, which sets the register corresponding to the reset controller according to the reset requirements of both parties, reduces hardware redundancy design and realizes a reset controller that is more in line with current SoC design specifications.
[0091] Based on the above embodiments, the initialization of the reset controller in step S13 includes:
[0092] Obtain the driver information and device tree information corresponding to the reset controller;
[0093] The probe function is called when the device node in the device tree information matches the ID information in the driver information.
[0094] The probe function is used to parse the device tree information to obtain the hardware information corresponding to the reset controller.
[0095] Obtain the external resources corresponding to the reset controller and initialize them to the initialization state corresponding to the reset controller. The external resources include at least a clock signal and a reset signal.
[0096] Enable the reset controller to complete its initialization.
[0097] Figure 2 A schematic diagram of the initialization process of a reset controller provided in an embodiment of the present invention is shown below. Figure 2 As shown, this step specifically includes:
[0098] S21: When the device node in the device tree information matches the ID information in the driver information, the probe function is called;
[0099] S22: Use the probe function to parse the device tree information to obtain the hardware information corresponding to the reset controller;
[0100] S23: Obtain the external resources corresponding to the reset controller and initialize them to the initialization state corresponding to the reset controller;
[0101] S24: Initialize, enable, and reset the controller.
[0102] Specifically, it obtains the driver information corresponding to the reset controller, as well as the device tree mechanism information, and isolates the hardware information and the driver's own code logic to ensure code purity. The code framework is based on the Linux kernel reset subsystem and is presented as platform_device.
[0103] The device tree mechanism aims to solve the problem of messy code in the `arch / arm` directory of the kernel source code: With the rapid development of the ARM ecosystem, the `arch / arm` directory of the kernel source code contains source files related to dozens of ARM chips and hundreds of development boards. Many hardware resources related to interrupts, registers, etc., of development boards and processors are defined in this directory using `.c` or `.h` files. For the kernel, coupling with this hardware leads to a chaotic kernel code structure, requiring each kernel image running on a development board to be compiled and configured separately, making it incompatible. The device tree mechanism decouples the Linux kernel from the hardware platform: each hardware platform's hardware resources are described using a device tree file (xxx.dts), instead of being defined in `arch / arm` using `.c` or `.h` files. The Linux kernel is a general-purpose kernel; during startup, it initializes a specific platform by resolving the hardware resources in the device tree.
[0104] When the device node defined in the device tree information matches the of_device_id information (ID information) in the driver, the probe function in the driver information is called. The probe function is the final step in device driver registration. After the device and its corresponding driver are paired on the bus, the system calls the probe function of the platform device to complete the final work of driver registration.
[0105] The `probe` function parses the device tree information to obtain the hardware information corresponding to the reset controller. It then acquires the external resources corresponding to the reset controller and initializes them to the required state. These external resources include at least a clock signal and a reset signal. The reset signal can be obtained from the reset definition in the register. Once both hardware and software information are acquired, the entire system is enabled. At this point, the Reset Controller hardware and software are in a ready state.
[0106] In a preferred embodiment, when the device tree information is parsed using the probe function to obtain the hardware information corresponding to the reset controller, the hardware information is saved to a software structure for abstraction for subsequent processing. To ensure software compatibility during hardware operation, the hardware abstraction is represented in software form.
[0107] The present invention provides an initialization method for the reset controller, which strips away hardware information and driver code logic to ensure code purity and put the hardware and software into a ready state.
[0108] Based on the above embodiments, step S13, which instantiates the operation function of the initialized reset controller, includes:
[0109] Obtain the core structure corresponding to the initialized reset controller;
[0110] Obtain the corresponding set of operation functions based on the core structure;
[0111] Instantiate the callback function for the set of operation functions.
[0112] Specifically, the core structure `struct reset_controller_dev` corresponding to the initialized reset controller is obtained. This core structure contains `struct reset_control_ops`, which is software-oriented and controls the hardware in a software manner. Callback functions are instantiated, and based on the register reset definitions in the above embodiments, their callback functions are as follows:
[0113] a.sw1000_reset_reset generates a pulse reset signal;
[0114] b.sw1000_reset_assert triggers the reset signal target level status;
[0115] c.sw1000_reset_deassert restores the reset signal to its default level.
[0116] d.sw1000_reset_status returns the real-time level status of the reset signal line.
[0117] The callback function varies depending on the reset operation and can be set according to the actual situation. It will not be explained here.
[0118] This invention provides a method for obtaining the core structure corresponding to the initialized reset controller; obtaining the corresponding set of operation functions based on the core structure; and instantiating the callback functions of the set of operation functions. When the controller or external device PIN controller driver needs to perform a reset operation, it does not directly operate on the raw hardware registers, but instead calls the unified function interface encapsulated by resetsubsystem to complete the reset purpose. This achieves the effect of isolation between the consumer driver and the provider driver, conforms to the Linux device driver model, and has better maintainability.
[0119] Figure 3 This is a structural diagram of a reset operation processing device provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the device 1 is applied to the BMC chip and includes on-chip controllers 2, external device PIN controllers 3, reset controllers 4 and controllers 5;
[0120] Each on-chip controller 2 is connected to the reset controller 4;
[0121] Each external device PIN controller 3 is connected to the reset controller 4;
[0122] Controller 5 is connected to reset controller 4 and is used to obtain the reset requirements of each on-chip controller 2 and each external device PIN controller 3. According to the reset requirements, the reset definition of the register corresponding to reset controller 4 is set, where reset controller 4 is located at BMC chip; reset controller 4 is initialized so that reset controller 4 is in a ready state, and the operation function of the initialized reset controller 4 is instantiated.
[0123] When a driver performs a reset operation, the control reset controller 4 calls the instantiated operation function and writes it to the register to trigger the reset operation, where the reset operation is either the on-chip controller 2 or the external device PIN controller 3.
[0124] Specifically, the connection method extracts the original reset logic that exists inside each on-chip controller 2 and external device PIN controller 3, and centralizes it in the reset controller 4. The reset controller 4 leads out a reset signal line to each on-chip controller 2 and external device PIN controller 3. When a certain on-chip controller 2 or external device PIN controller 3 needs to be reset, the corresponding register of the reset controller 4 is operated to drive the specified reset signal line to generate a reset signal.
[0125] The control method of controller 5 can refer to the embodiment of the above-described reset operation processing method, and will not be described in detail here.
[0126] This invention provides a reset operation processing device applied to a BMC chip, comprising: on-chip controllers, external device PIN controllers, a reset controller, and a controller; each on-chip controller is connected to the reset controller; each external device PIN controller is connected to the reset controller; the controller is connected to the reset controller and is used to acquire the reset requirements of each on-chip controller and each external device PIN controller; the reset definition of the register corresponding to the reset controller is set according to the reset requirements of both, wherein the reset controller is located at the BMC chip; the reset controller is initialized to put the reset controller into a ready state, and the initialized reset controller is instantiated with an operation function; when a reset operation is driven, the reset controller is controlled to call the instantiated operation function and write to the register to trigger the reset operation, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller. This device, by setting a reset controller, allows the reset logic of each IP controller to be introduced into the reset controller, and defines the reset content of the register according to the reset requirements, saving hardware logic resources and improving the reusability of reset operations.
[0127] Based on the above embodiments, for devices externally connected to the BMC, if a reset operation is required, a dedicated General Purpose Input Output (GPIO) pin resource will be needed in the hardware design. However, this pin cannot be used for other purposes, resulting in waste of the pin. Therefore, the device also includes: a GPIO controller;
[0128] The GPIO controller connects to one of the PIN controllers of each external device to perform other operations of the GPIO controller when no reset operation is present.
[0129] Specifically, for external hardware devices, their reset pins can be used as ordinary GPIOs when no reset operation is required, improving pin resource utilization. Since the reset controller and GPIO controller signal lines are first routed to the PIN controller, the actual physical pins can be selectively connected to either the reset controller or the GPIO controller by manipulating the PIN controller. If no reset operation is currently required, other operations of the GPIO controller are executed.
[0130] The GPIO controller provided in this embodiment of the invention is connected to one PIN controller of each external device PIN controller, and is used to perform other operations of the GPIO controller when no reset operation is present. Multiplexing the external reset pin and the GPIO pin improves pin resource utilization.
[0131] The foregoing has described in detail various embodiments of the reset operation processing method. Based on this, the present invention also discloses a reset operation processing apparatus corresponding to the above method, applied to a BMC chip. Figure 4 This is a structural diagram of another reset operation processing device provided in an embodiment of the present invention. Figure 4 As shown, the processing device for the reset operation includes:
[0132] The acquisition module 11 is used to acquire the reset requirements of each on-chip controller and the reset requirements of each external device PIN controller.
[0133] Setting module 12 is used to set the reset definition of the register corresponding to the reset controller according to the reset requirements of both.
[0134] Initialization module 13 is used to initialize the reset controller so that the reset controller is in a ready state, and to instantiate the operation function of the initialized reset controller;
[0135] The write module 14 is used to control the reset controller to call the instantiated operation function and write it into the register to trigger the reset operation when the driver reset operation is performed. The reset operation is any reset operation of the on-chip controller or the external device PIN controller.
[0136] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.
[0137] For a description of the structural diagram of another reset operation processing device provided in the embodiments of the present invention, please refer to the above method embodiments. The present invention will not be described again here, but it has the same beneficial effects as the above reset operation processing method.
[0138] Figure 5A structural diagram of a reset operation processing device provided in another embodiment of the present invention is shown below. Figure 5 As shown, the device includes:
[0139] Memory 21 is used to store computer programs;
[0140] Processor 22, for implementing a reset operation process when executing a computer program.
[0141] The reset operation processing device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.
[0142] The processor 22 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 22 may be implemented using at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 22 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 22 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 22 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.
[0143] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 21 is used to store at least the following computer program 201, which, after being loaded and executed by the processor 22, is capable of implementing the relevant steps of the reset operation processing method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 21 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. The operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the reset operation processing method, etc.
[0144] In some embodiments, the reset operation processing device may further include a display screen 23, an input / output interface 24, a communication interface 25, a power supply 26, and a communication bus 27.
[0145] Those skilled in the field can understand, Figure 5 The structure shown does not constitute a limitation on the processing device for the reset operation and may include more or fewer components than shown.
[0146] The processor 22 implements the reset operation processing method provided in any of the above embodiments by calling the instructions stored in the memory 21.
[0147] For a description of the structural diagram of a reset operation processing device provided in another embodiment of the present invention, please refer to the above method embodiment. The present invention will not be described again here, but it has the same beneficial effects as the above reset operation processing method.
[0148] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by processor 22, implements the steps of the processing method for the reset operation described above.
[0149] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0150] For an introduction to the computer-readable storage medium provided by the present invention, please refer to the above method embodiments. The present invention will not be described in detail here, but it has the same beneficial effects as the above reset operation processing method.
[0151] The present invention has provided a detailed description of a clock, a method for controlling clock calibration, a clock calibration device, and a medium. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.
[0152] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
Claims
1. A processing method of a reset operation, characterized by, Applied to BMC chips, including: Obtain the reset requirements of each on-chip controller and each external device PIN controller; The reset definition of the register corresponding to the reset controller is set according to the reset requirements of both, wherein the reset controller is located at the BMC chip; The reset controller is initialized to put it into a ready state, and the initialized reset controller is then instantiated with operation functions. The instantiation refers to the corresponding callback functions. When the controller or external device PIN controller driver needs to perform a reset operation, it does not directly manipulate the raw hardware registers, but calls the unified function interface encapsulated by `resetsubsystem` to complete the reset. Specifically, this includes: obtaining the core structure `struct reset_controller_dev` corresponding to the initialized reset controller; obtaining the corresponding set of operation functions based on the core structure; and instantiating the callback functions of the operation function set. The callback functions are: `w1000_reset_reset` to generate a pulse reset signal; `sw1000_reset_assert` to trigger the target level state of the reset signal; `sw1000_reset_deassert` to restore the reset signal to the default level state; and `sw1000_reset_status` to return the real-time level state of the reset signal line. When the reset operation is driven, the reset controller is controlled to call the instantiated operation function and write to the register to trigger the reset operation, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller; Correspondingly, the register is a 32-bit register, and the step of setting the reset definition of the register corresponding to the reset controller according to the reset requirements of both includes: The system obtains a first number of reset requests from the on-chip controller and a second number of reset requests from the external device PIN controller, as well as a third number of offset addresses for the register that support reset signals, wherein the first number and the second number are both less than or equal to the third number, and the offset address is 32 offset addresses. Enable the reset signals of the on-chip controller and the external device PIN controller by setting the first offset address and the second offset address respectively; Set the trigger level states of the on-chip controller and the external device PIN controller respectively using the third offset address and the fourth offset address; Set the reset pulse width of the on-chip controller and the external device PIN controller respectively from the fifth offset address to the seventeenth offset address and from the eighteenth offset address to the thirtieth offset address; Set the real-time level states of the on-chip controller and the external device PIN controller to the thirty-first offset address and the thirty-second offset address, respectively.
2. The processing method of reset operation according to claim 1, wherein, The initialization of the reset controller includes: Obtain the drive information and device tree information corresponding to the reset controller; When the device node in the device tree information matches the ID information in the driver information, the probe function is called; The device tree information is parsed using the probe function to obtain the hardware information corresponding to the reset controller; Obtain the external resources corresponding to the reset controller and initialize them to the initialization state corresponding to the reset controller, wherein the external resources include at least a clock signal and a reset signal; Enable the reset controller to complete its initialization.
3. The processing method of reset operation according to claim 2, wherein, The step of instantiating the operation function of the initialized reset controller includes: Obtain the core structure corresponding to the initialized reset controller; Obtain the corresponding set of operation functions based on the core structure; Instantiate the callback functions of the set of operation functions.
4. The processing method of reset operation according to claim 2, wherein, Also includes: The hardware information is saved into the software structure for abstraction for subsequent processing.
5. A processing device for a reset operation, characterized by It is applied to BMC chips, including on-chip controllers, external device PIN controllers, reset controllers, and controllers; Each of the on-chip controllers is connected to the reset controller; Each of the external device PIN controllers is connected to the reset controller; The controller is connected to the reset controller and is used to obtain the reset requirements corresponding to each on-chip controller and each external device PIN controller. Based on these requirements, the controller sets the reset definition of the registers corresponding to the reset controller, which is located at the BMC chip. The controller is initialized to be in a ready state, and the initialized controller is instantiated with operation functions. This instantiation involves callback functions. When the controller or external device PIN controller driver needs to perform a reset operation, it does not directly operate on the raw hardware registers but calls the unified function interface encapsulated by the reset subsystem to complete the reset. Specifically, this includes: obtaining the core structure `struct reset_controller_dev` corresponding to the initialized reset controller; obtaining the corresponding set of operation functions based on the core structure; and instantiating the callback functions of the operation function set. The callback functions are: `w1000_reset_reset` to generate a pulse reset signal; `sw1000_reset_assert` to trigger the target level state of the reset signal; `sw1000_reset_deassert` to restore the reset signal to the default level state; and `sw1000_reset_status` to return the real-time level state of the reset signal line. When the reset operation is driven, the reset controller is controlled to call the instantiated operation function and write to the register to trigger the reset operation, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller; Correspondingly, the register is a 32-bit register, and the step of setting the reset definition of the register corresponding to the reset controller according to the reset requirements of both includes: The system obtains a first number of reset requests from the on-chip controller and a second number of reset requests from the external device PIN controller, as well as a third number of offset addresses for the register that support reset signals, wherein the first number and the second number are both less than or equal to the third number, and the offset address is 32 offset addresses. Enable the reset signals of the on-chip controller and the external device PIN controller by setting the first offset address and the second offset address respectively; Set the trigger level states of the on-chip controller and the external device PIN controller respectively using the third offset address and the fourth offset address; Set the reset pulse width of the on-chip controller and the external device PIN controller respectively from the fifth offset address to the seventeenth offset address and from the eighteenth offset address to the thirtieth offset address; Set the real-time level states of the on-chip controller and the external device PIN controller to the thirty-first offset address and the thirty-second offset address, respectively.
6. The processing device of reset operation according to claim 5, wherein, It also includes the GPIO controller: The GPIO controller is connected to one of the PIN controllers of each of the external device PIN controllers, and is used to perform other operations of the GPIO controller when the reset operation is not present.
7. A processing device for a reset operation, characterized by Applied to BMC chips, including: The acquisition module is used to acquire the reset requirements of each on-chip controller and the reset requirements of each external device PIN controller. The configuration module is used to set the reset definition of the registers corresponding to the reset controller according to the reset requirements of both. An initialization module is used to initialize the reset controller so that it is in a ready state, and to instantiate the operation functions of the initialized reset controller. The instantiation refers to the corresponding callback functions. When the controller or external device PIN controller driver needs to perform a reset operation, it does not directly operate on the raw hardware registers, but calls the unified function interface encapsulated by the reset subsystem to complete the reset purpose. Specifically, this includes: obtaining the core structure corresponding to the initialized reset controller, `struct reset_controller_dev`; obtaining the corresponding set of operation functions based on the core structure; and instantiating the callback functions of the operation function set. The callback functions are: `w1000_reset_reset` to generate a pulse reset signal; `sw1000_reset_assert` to trigger the target level state of the reset signal; `sw1000_reset_deassert` to restore the reset signal to the default level state; and `sw1000_reset_status` to return the real-time level state of the reset signal line. The write module is used to control the reset controller to call the instantiated operation function and write to the register to trigger the reset operation when the reset operation is driven, wherein the reset operation is any reset operation of the on-chip controller or the external device PIN controller; Correspondingly, the register is a 32-bit register, and the step of setting the reset definition of the register corresponding to the reset controller according to the reset requirements of both includes: The system obtains a first number of reset requests from the on-chip controller and a second number of reset requests from the external device PIN controller, as well as a third number of offset addresses for the register that support reset signals, wherein the first number and the second number are both less than or equal to the third number, and the offset address is 32 offset addresses. Enable the reset signals of the on-chip controller and the external device PIN controller by setting the first offset address and the second offset address respectively; Set the trigger level states of the on-chip controller and the external device PIN controller respectively using the third offset address and the fourth offset address; Set the reset pulse width of the on-chip controller and the external device PIN controller respectively from the fifth offset address to the seventeenth offset address and from the eighteenth offset address to the thirtieth offset address; Set the real-time level states of the on-chip controller and the external device PIN controller to the thirty-first offset address and the thirty-second offset address, respectively.
8. A processing device for a reset operation, characterized by include: Memory, used to store computer programs; A processor, configured to implement the steps of the processing method for the reset operation as described in any one of claims 1 to 4 when executing the computer program.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the processing method for the reset operation as described in any one of claims 1 to 4.