Managing capacity reduction attributed to storage device failures

Abstract

This application relates to managing capacity reduction attributed to storage device failure. A system and method for managing a reduction in capacity of a memory subsystem. An example method involving a memory subsystem: detecting a failure of at least one memory device in a set, wherein the failure affects stored data; notifying a host system of a change in capacity of the set of memory devices; receiving an indication from the host system to continue at a reduced capacity; and updating the set of memory devices to change the capacity to the reduced capacity.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to a reduction in the capacity of the memory subsystem being managed. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. Memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a system comprising: a collection of memory devices; and a processing means operatively coupled to the collection of memory devices to perform operations including: detecting a fault in at least one memory device in the collection, wherein the fault affects stored data; notifying a host system of a change in the capacity of the collection of memory devices; receiving from the host system an instruction to continue at a reduced capacity; and updating the collection of memory devices to change the capacity to the reduced capacity.

[0004] Another aspect of this disclosure provides a method comprising: detecting a fault in at least one memory device in a set of memory devices, wherein the fault affects stored data; notifying a host system of a change in the capacity of the set of memory devices; receiving from the host system an instruction to continue at a reduced capacity by a processing device; and updating the set of memory devices by the processing device to change the capacity to the reduced capacity.

[0005] Another aspect of this disclosure provides a non-transitory computer-readable medium for storing instructions that, when executed by a processing device, cause the processing device to perform operations including: detecting a plurality of faults in a set of memory devices, wherein a first fault affects data stored on a first memory device and a second fault affects data stored on a second device; notifying a host system of a change in the capacity of the set of memory devices after each of the plurality of faults; receiving from the host system an instruction to continue with a reduced capacity after each of the plurality of faults; and updating the set of memory devices after each of the plurality of faults to change the capacity to the reduced capacity. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system comprising a host system and a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 According to some embodiments of this disclosure Figure 1 Detailed block diagram of the host system and memory subsystem.

[0009] Figure 3 This is a block diagram of a memory subsystem comprising a partitioned namespace having multiple zones, according to some embodiments of the present disclosure.

[0010] Figure 4 This is a detailed block diagram of a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 5 This is a detailed block diagram of a host system according to some embodiments of the present disclosure.

[0012] Figure 6 This is a flowchart of a method performed by a memory subsystem to manage capacity reduction according to some embodiments of the present disclosure.

[0013] Figure 7 This is a flowchart of another method performed by a memory subsystem to manage capacity reduction according to some embodiments of the present disclosure.

[0014] Figure 8 This is a flowchart of another method performed by a memory subsystem to manage capacity reduction according to some embodiments of the present disclosure.

[0015] Figure 9 This is a flowchart of another method performed by a memory subsystem to manage capacity reduction according to some embodiments of the present disclosure.

[0016] Figure 10 This is a flowchart of a method executed by a host system to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure.

[0017] Figure 11 This is a flowchart of another method executed by a host system to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure.

[0018] Figure 12 This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0019] Various aspects of this disclosure enable the host system and memory subsystem to manage faults by maintaining operation at reduced capacity. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following description, in conjunction with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that contains one or more memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0020] The memory subsystem may be susceptible to failures that reduce its capacity and adversely affect the host system. For example, a memory subsystem may contain multiple memory devices, and one or more of these devices may fail, reducing the subsystem's capacity. In the past, when one memory device failed, the entire memory subsystem was replaced. Modern memory subsystems may contain many memory devices (e.g., 256 dies) and can store large amounts of data (e.g., 128 terabytes). The failure of a single memory device means that many other memory devices are still functioning. Replacing a memory subsystem with functioning memory devices wastes the remaining memory devices and often requires relocating large amounts of data.

[0021] Modern memory subsystems typically provide fault tolerance in a manner transparent to the host system. A memory subsystem is manufactured with a certain amount of storage space, such that a first portion of this storage space is available to the host system, while a second portion is reserved for internal use (e.g., over-provisioning or redundancy). The first portion of the storage space available to the host system is called the storage capacity. When a fault occurs that reduces the total amount of storage space, the memory subsystem can reduce the size of the second portion reserved for internal use so that the size of the first portion available to the host remains the same (e.g., the storage capacity remains unchanged). This can be performed transparently to the host system because the memory subsystem can recover the data stored on the failed memory device and store it at another location available to the host system. This type of transparent fault tolerance can be limited in terms of the types of faults it can handle and the amount of storage space loss it can tolerate, and although it can maintain storage capacity, it may adversely affect the performance or reliability of the memory subsystem.

[0022] Various aspects of this disclosure address the above and other drawbacks by enabling the host system and memory subsystem to manage reductions in the capacity of the memory subsystem. In one embodiment, the memory subsystem can detect faults in the memory subsystem that affect the storage capacity available to the host system. The memory subsystem may comprise a collection of memory devices, and the fault may affect any part of the memory subsystem and access to data stored on one or more of the memory devices in the collection. In one instance, one or more of the memory devices may fail (e.g., die failure, plane failure) or become inaccessible (e.g., channel or connector failure). In another instance, the memory devices may store more than one bit of information per memory cell (e.g., 4 bits per cell), and the memory devices may fail to function as intended, and may be shifted down to store fewer bits of information per memory cell (e.g., 3 bits per cell instead of 4 bits per cell). In any of these instances, the fault may result in a reduction in storage capacity, and the memory subsystem may communicate with the host system to manage the reduction in the capacity of the memory subsystem. For example, the memory subsystem can notify the host system of a failure and indicate the amount of affected storage space, remaining capacity, or a combination thereof. The host system can confirm the failure and indicate whether the memory subsystem should be updated to operate with reduced capacity. The update can retain data unaffected by the failure, recover data affected by the failure, relocate data inside or outside the memory subsystem, or a combination thereof.

[0023] The advantages of this disclosure include, but are not limited to, enhanced efficiency, duration, and usability of the memory subsystem. Specifically, the technique is advantageous because it allows the memory subsystem to remain in use for extended periods before replacement, thus reducing the total cost of ownership (TCO). In one example, whenever one of the memory devices fails (e.g., a NAND die fails), the memory subsystem can update its configuration using the remaining memory devices to operate at a lower capacity. This update can be repeated and occurs in response to each failure until the last memory device fails. This allows the memory subsystem to withstand multiple failures over time and remain in operation for extended periods before replacement. Other advantages include enabling the memory subsystem to reduce capacity while maintaining its reliability, performance, and efficiency. As discussed above, the memory subsystem can maintain a constant capacity in response to failures by using a portion of the storage space for internal use and making that portion available to the host system. The used portion may already be used for over-provisioning or redundancy, and its removal may degrade the performance, reliability, or efficiency of the memory subsystem. Additional advantages include enabling the host system and memory subsystem to reduce the capacity of the memory subsystem without minimizing the use of internally available storage space. The techniques disclosed herein also enable the host system and memory subsystem to retain data during capacity reduction. Host systems typically handle capacity reduction by reformatting the memory subsystem, which erases data on the memory subsystem. Before reformatting, the host system copies the data from the memory subsystem to temporary storage, and then, after reformatting, copies, restores, corrects, or otherwise recreates the data back to the memory subsystem. The techniques disclosed herein reduce or avoid computational resources consumed by copying (e.g., processor cycles, I / O, temporary storage) by retaining fault-insensitive data and, in some instances, by restoring some or all of the fault-insensitive data. Other advantages will be apparent to those skilled in the art of data storage devices and memory devices discussed below.

[0024] Figure 1 This description describes an example computing system 100 comprising a host system 120 and a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof. Each memory device 130 or 140 may be one or more memory components.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device containing memory and processing means (e.g., processor).

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components or devices that can be an indirect or direct communication connection (e.g., without intermediate components or devices), whether wired or wireless, including connections such as electrical, optical, magnetic and the like.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0029] Host system 120 may be coupled to memory subsystem 110 via a physical host interface that can communicate on a system bus. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Dual Data Rate (DDR), Low Power Dual Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint ("3D crosspoint") memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into instructions for accessing the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for memory management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] The computing system 100 includes a storage structure 124 in a host system 120 and a host negotiation component 214 in a memory subsystem 110. The storage structure 124 may be configured to accommodate a reduction in the capacity of the memory subsystem 110, as discussed throughout the figures. In some embodiments, the host system 120 includes at least a portion of capacity management functionality. In other embodiments or combinations, the controller 115 and / or processing device 223 of the host system 120 includes at least a portion of capacity management functionality. For example, the controller and processing device (processor) of the host system 120 may be configured to execute instructions stored in memory for performing operations to manage a reduction in the capacity of the memory subsystem and for configuring the storage structure 124 in view of the capacity reduction as described herein.

[0041] Figure 2 This is a detailed block diagram of a computing system 100 that includes a host system 120 and a memory subsystem 110 that can adapt to failures by reducing the capacity of the memory subsystem 110. One or more of the failures may occur simultaneously or at different times and may spread over an extended period of time (e.g., days, weeks, years). Techniques enable the host system 120 and memory subsystem 110 to repeatedly adapt to the capacity reduction caused by each failure. In the illustrated example, the memory subsystem 110 may be associated with multiple memory devices 130A-Z, capacities 232A-Z, failures 234A-Z, and data 236A-B.

[0042] Memory devices 130A-Z may include high-density non-volatile memory devices in which data retention is required when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND flash memory device. (The above is in conjunction with...) Figure 1The memory device 130 describes other instances of non-volatile memory devices. A non-volatile memory device is a package having a set of blocks (e.g., physical blocks) of one or more dies, each block potentially containing a set of pages. A page may contain a set of cells (e.g., memory cells), and each cell may be electronic circuitry for storing information. Depending on the cell type, a cell may store one or more bits of binary information and may have various logical states associated with the number of bits being stored. Logical states may be represented by binary values ​​(e.g., "0" and "1") or combinations of such values. Instance cell types include single-level cells (e.g., 1 bit per cell), multi-level cells (e.g., 2 bits per cell), three-level cells (e.g., 3 bits per cell), four-level cells (e.g., 4 bits per cell), other quantities, or combinations thereof.

[0043] The memory device set may include one or more memory devices of the memory subsystem 110. The set may include all or some of the memory devices of the memory subsystem. Figure 2 In the example shown, the memory device set of memory subsystem 110 may comprise multiple memory devices 130A-Z, each separate and independent from the others (e.g., different dies). In other examples, the memory device set may comprise a single memory device, and the single memory device may comprise one or more regions, segments, or portions managed individually or jointly. In any example, the memory device set may be associated with different capacities (e.g., capacities 232A-Z) over time due to device failures.

[0044] Capacities 232A-Z represent the capacity of memory subsystem 110 at different points in time. Each of capacities 232A-Z may be a storage capacity indicating the data storage space available to host system 120 (e.g., the maximum amount of data the host system can store on the memory subsystem). Storage capacity may be based on the capacity or size of the set of memory devices. In one instance, the terms capacity and size are used interchangeably. In another instance, the terms capacity and size may differ, and size may be the total storage space size, while capacity may be a portion of the total storage space size that is available outside the host system. The remaining portion of the total size may be used for internal purposes (e.g., over-provisioning, storing parity data, etc.). In other instances, the term capacity may also or alternatively refer to or be based on channel capacity and corresponds to the rate at which data can be accessed, written, read, copied, moved, or transferred to or from one or more memory subsystems 110, memory devices 130A-Z, host system 120, or combinations thereof.

[0045] The capacity of the collection of memory devices 130A-Z can change over time, and capacity 232A can be the initial capacity, while capacity 232Z can be an updated capacity (e.g., a reduced capacity). The initial capacity can be the original capacity of the memory subsystem 110 at the time of design, manufacturing, assembly, installation, initialization, or other times. The updated capacity can be the capacity of the memory subsystem at a subsequent point in time, and can be the same as, less than, or greater than the initial capacity. Figure 2 In the example shown, capacity 232A may be the initial capacity of memory subsystem 110 at installation time (e.g., 1 terabyte), based on all memory devices 130A-Z in the set being fully functional. Capacity 232Z may be the updated capacity of memory subsystem 110 after the set of memory devices 130A-Z has encountered one or more failures 234A-Z (e.g., 900 gigabytes).

[0046] Faults 234A-Z may include any fault affecting the capacity of memory subsystem 110. A fault may cause a portion of memory subsystem 110 to cease functioning as designed. This portion may include memory devices (e.g., NAND dies, memory cells), memory controllers (e.g., controller 115 or 135), connectors (e.g., package connectors, interfaces), interconnects, expanders, buses, other portions or combinations thereof of memory subsystem 110 or host system 120. A fault may affect data stored by memory subsystem 110, causing data to be inaccessible, incorrect, inaccurate, unreliable, unpredictable, missing, erased, or otherwise affected, or a combination thereof. In one instance, a fault may cause the portion to completely cease functioning (e.g., stop operating). In another instance, a fault may cause the portion to partially cease functioning, and the portion may continue to operate but fail to meet one or more thresholds (e.g., below a minimum threshold or above a maximum threshold). The one or more thresholds may include or relate to performance thresholds, reliability thresholds, capacity thresholds, redundancy thresholds, other thresholds, or combinations thereof. Figure 2 and 4 The fault detection component 212 discusses fault detection and the use of thresholds in more detail.

[0047] Faults 234A-Z may include hardware faults, software faults, other faults, or combinations thereof. Hardware faults may be any fault caused by the hardware of memory subsystem 110. Examples of hardware faults may include die faults, connector faults, communication channel faults, package faults, other hardware faults, or combinations thereof. Software faults may be any fault caused by the computer code of memory subsystem 110 (e.g., computer code executed by the controller of memory subsystem 110, such as firmware, microcode, machine code, opcode, hardware instructions, or program code). A single hardware or software fault may affect a portion of the memory device, the entire memory device, or multiple memory devices of memory subsystem 110. Faults 234A-Z may be attributable to defects, flaws, defects, or deficiencies in memory devices, connectors, buses, expanders, packages, other parts of memory subsystem 110 or host system 120, or combinations thereof.

[0048] Faults can occur at any time and can be identified or detected before, during, or after they affect the capacity of memory subsystem 110. In one instance, one or more of faults 234A-Z (e.g., operational failure) may occur after host system 120 is using the device. In another instance, one or more of faults 234A-Z may occur before use by host system 120 but are not detected until after use by host system 120 (e.g., latent fault, hidden fault). In either instance, faults 234A-Z may occur simultaneously or at different times, and these different times may be separated by one or more minutes, hours, days, weeks, years, decades, or other durations. In the example shown, faults 234A-Z may occur at different times and affect different parts of memory subsystem 110. For example, fault 234A may occur at the first time (time t) and may affect the entire memory device 130A (e.g., a die failure resulting in 100% loss of memory space). Fault 234B may occur at a second time (t+1 month) and may affect a portion of memory device 130B (e.g., a cell fault causing a 50% loss of memory space in the memory device). Fault 234Z may occur at a third time (t+1 year) and may be a single fault affecting multiple memory devices 130Y-Z (e.g., a bus fault). In any of the provided examples, the fault may adversely affect data 236A-B stored by memory subsystem 110 and cause some of the data 236A-B to become inaccessible.

[0049] Data 236A-B may be data stored by memory subsystem 110 in one or more memory devices. Data 236A-B may be data provided to memory subsystem 110, or may be data generated by memory subsystem 110. Data provided to memory subsystem 110 may be referred to as user data or external data, and may be externally accessible data that can be provided by host system 120 or another memory subsystem. Data generated by memory subsystem 110 may be referred to as internal data, and may be data that is not externally accessible and is used for internal purposes (e.g., management, mapping, maintenance, wear leveling, redundancy, etc.).

[0050] The memory subsystem 110 may include one or more components for managing faults and communicating with the host system 120 to manage capacity changes of the memory subsystem 110. Figure 2 In the example shown, memory subsystem 110 includes a fault detection component 212, a host negotiation component 214, and a capacity update component 216. Fault detection component 212 enables memory subsystem 110 to examine itself to detect faults and determine the impact on the capacity of memory subsystem 110. Host negotiation component 214 enables memory subsystem 110 to communicate with host system 120 to indicate the occurrence and / or consequences of a fault. Host negotiation component 214 can also interact with host system 120 to recover and relocate data. Capacity update component 216 enables memory subsystem 110 to reduce its capacity with or without retained data, and reconstructs internal data (e.g., reconstructs parity data) based on the reduced capacity. Components 212, 214, and 216 relate to... Figure 4 This can be discussed in more detail, and can be communicated with the host system 120 via communication channel 227.

[0051] Communication channel 227 communicatively couples memory subsystem 110 to host system 120. Communication channel 227 may include one or more interfaces, connectors, interconnects, adapters, other hardware or software components, or combinations thereof. Communication channel 227 may implement standard or proprietary communication protocols, which include or are based on Non-Volatile MemoryExpress. TM (NVMe), Advanced Host Controller Interface TM (AHCI), Serial Advanced Technology Attachment Interface TM (e.g., SATA, mSATA), Peripheral Component Interconnect TM(e.g., PCI, PCIe), Small Computer System Interface TM (SCSI, iSCSI), Integrated Drive Electronics TM (e.g., IDE, EIDE), InfiniBand TM Compute ExpressLink TM (CXL), other communication technologies, or combinations thereof. The memory subsystem 110 and the host system 120 may use the communication channel 227 to transmit one or more messages 229A-B.

[0052] Messages 229A-B may be messages relating to faults or capacity changes caused by faults. Messages may be the same as or similar to signals, interrupts, notifications, events, indications, packets, frames, datagrams, other communication units, or combinations thereof. Messages may be signals without message content, or signals containing message content at the beginning (e.g., header), middle (e.g., payload, body), or end (e.g., tail, footer, endnote). Message content may contain identification data (e.g., event, event type, command, source or destination identifier), pointer data (e.g., address of a set or other data structure), other data, or combinations thereof (e.g., message data). In one instance, one or more of messages 229A-B may be asynchronous event notifications (AEN), asynchronous event requests (AER), other asynchronous or synchronous events, or combinations thereof. Figure 3 In the example shown, message 229A can be transmitted from memory subsystem 110 to host system 120, and message 229B can be transmitted from host system 120 to memory subsystem 110. Regarding Figure 4 and Figure 5 Messages 229A and 229B will be discussed in more detail.

[0053] Host system 120 may include an operating system 221, which includes one or more components enabling it to communicate with memory subsystem 110 using messages 229A-B and manage a reduction in the capacity of memory subsystem 110. Host system 120 may include one or more processing devices 223 and main memory 225 to execute operating system 221 and fault determination component 222, data retention component 224, and storage system component 226. Fault determination component 222 enables host system 120 to determine that memory subsystem 110 has detected a fault causing a reduction in capacity. Data retention component 224 enables host system 120 to continue using the memory subsystem with reduced capacity and to retain data, recover data, or a combination thereof. Storage system component 226 enables host system 120 to reconfigure one or more storage structures (e.g., file systems or databases) based on the fault and the reduced capacity. Figure 5 Components 222, 224, and 226 are discussed in more detail.

[0054] Figure 3 This is a detailed block diagram of a memory subsystem 110 containing multiple zones. The memory subsystem 110 can be connected to... Figure 1 and 2 The memory subsystem 110 is the same as or similar to that of the memory device 130A-Z and may include multiple memory devices 130A-Z. Memory devices 130A-Z may consist of memory cells arranged in a two-dimensional grid. Memory cells may be etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes the address of the memory cell. Block 331 may refer to a storage unit of a memory device (e.g., 130A) for storing data and may include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks 331 may be grouped together to form a larger storage unit called a region. Each of the memory devices 130A-Z may contain one or more regions.

[0055] The memory subsystem 110 may be configured with namespaces comprising multiple regions 330A-Z. A namespace may contain the address spaces of one or more of the memory devices 130A-Z. A namespace is a number of non-volatile memories that can be formatted into blocks (e.g., logical blocks or physical blocks). The controller of the memory subsystem 110 (e.g., controller 115 or 135) may support multiple namespaces referenced using namespace identification data (e.g., namespace ID, start LBA). Namespaces may be associated with namespace data structures created, updated, or deleted using namespace management and namespace attachment commands. Namespace data structures may indicate capabilities and settings specific to a particular namespace. In one instance, the namespace data structures and namespaces may correspond to partition namespaces.

[0056] Partition Namespace (ZNS) TM This can be provided by NVM Express. TM (NVMe TM A partitioned namespace is an organized, sequential namespace. A memory device configured with a partitioned namespace may be referred to as a partitioned namespace memory device or a ZNS memory device, and may implement a partitioned namespace command set as defined by NVMe. In a partitioned namespace, the address space of each of the memory devices 130A-Z may be divided into one or more regions 330A-Z. When using a partitioned namespace, writes can be performed sequentially starting from the beginning of a region, and writes can be performed at larger granularities (e.g., 64 kilobytes), and the region may be inaccessible for the duration of a write operation. Therefore, if a read request for data stored in the same or a different region is received while a write operation is in progress, the memory subsystem 110 must pause the write operation to perform the read. In one example, the partitioned namespace may be implemented by the controller of a solid-state drive (SSD) and includes regions 330A-Z, where one or more regions may exist for each of the one or more memory devices 130A-Z. The use of regions is advantageous because it enables more efficient management of storage space as the capacity of the memory device increases. For example, a set of one or more regions can be specified for use by a specific application (e.g., an application, process, or thread) executed by a host system or another system having access to the memory device.

[0057] Each of zones 330A-Z can be a contiguous or discontinuous portion (e.g., a block range) of a memory device that is identified and managed as a single memory cell. Each zone may correspond to zone identification data, which can be used to uniquely identify the zone and may be the same as or similar to a zone identifier (zone ID), zone descriptor, zone label, or other terminology. A zone may be a memory storage cell (e.g., a memory unit) and may have a predefined size that can be based on the size of another memory storage cell (e.g., a block, cell, page, die, device, or subsystem) (e.g., an integer multiple). Memory subsystem 110 may use a fixed size (e.g., constant size or static size) for zones, where all zones may have the same size, or may use a variable size (e.g., resizable, dynamic size), where zones used by memory subsystem 110 may have different sizes. The size of a zone may be determined (e.g., selected or detected) by memory subsystem 110, memory devices 130A-Z, host system 120, storage system, device driver, other entities, or a combination thereof.

[0058] An update area may include resetting the area and writing to it. Resetting the area may involve one or more operations that include erasing, updating, configuring, or formatting the area or its data (e.g., content or metadata). The host system or memory subsystem may initiate the reset, and one or more of the operations may be performed by the host system, the memory subsystem (e.g., controller 115), the memory device (e.g., controller 135), other processors, or a combination thereof. In one instance, resetting the area may update the position of the area's write pointer to a new position (e.g., resetting the write pointer to the beginning of the area). Typically, writes to the area are performed sequentially from the write pointer. Sequential writes may be performed continuously from the top of the memory device (e.g., a smaller address on the IC die) to the bottom of the memory device (e.g., a larger address on the IC die).

[0059] Figure 4 This is a block diagram illustrating exemplary components of the memory subsystem 110. In one example, the memory subsystem 110 may be a solid-state drive (SSD) that includes a memory device, local memory 119 (e.g., DRAM), and one or more processing devices (e.g., a memory controller) for performing logic for the components. In the illustrated example, the memory subsystem 110 may be associated with... Figures 1 to 3The memory subsystem 110 is the same as or similar to the memory subsystem controller 115, the local media controller 135, or a combination thereof, and may include a fault detection component 212, a host negotiation component 214, and a capacity update component 216. Features of the components and modules may be implemented in computer code (e.g., firmware, software, or other computer programs), hardware (e.g., circuitry), or a combination thereof. More or fewer components or modules may be included without loss of generality, and two or more of the components or modules may be combined into a single unit, or the features of the components may be separated into two or more units.

[0060] Fault detection component 212 enables memory subsystem 110 to detect and log faults that may affect the capacity of memory subsystem 110. As discussed above, faults can affect stored data or the ability to access stored data and can be associated with any part of memory subsystem 110 (e.g., one or more of memory devices, controllers, connectors, interfaces, etc.). Figure 4 In the example shown, the fault detection component 212 may include an inspection module 410, an inventory module 412, and a capacity determination module 414.

[0061] The verification module 410 enables the memory subsystem 110 to verify one or more portions of the memory subsystem 110 to detect indications of faults. These portions may include memory devices (e.g., NAND dies), memory controllers (e.g., controller 115 or 135), connectors (e.g., package connectors, interfaces), interconnects, buses, expanders, other portions of the memory subsystem 110 or host system 120, or combinations thereof, or related to them. The verification module 410 provides a device self-test and includes executable logic that enables processing devices of the memory subsystem 110 (e.g., controller 115 or 135) to verify the portions indirectly or directly.

[0062] Directly inspecting a portion of the memory subsystem may involve inspecting one or more data structures representing that portion and storing indications of faults. Fault indications may be signals, messages, or data indicating the presence, magnitude, type, location, number, other aspects of the fault, or combinations thereof. Data structures may be or may contain one or more logs (e.g., error logs, access logs), pointers (e.g., the memory address of the fault), identifiers (e.g., area identifiers, logical block addresses), flags (e.g., bit flags, processor registers), lists (e.g., linked lists), indexes, queues, arrays, tables, matrices, other data structures, or combinations thereof.

[0063] Directly inspecting a portion of a memory subsystem may involve scanning or testing that portion of the memory subsystem that is faulty. Scanning the portion may be the same as or similar to searching and may involve accessing or attempting to access the portion and analyzing the results of the access (e.g., checking if a value is readable, an accessible location, or a response is received). Testing the portion may involve accessing the portion and comparing the access results to expected data (e.g., comparing a read value to an expected value or a threshold). Testing may also, or alternatively, provide input for subsequent testing. For example, testing may provide input (e.g., writing data, sending a signal) and subsequently examine the input or its corresponding output (e.g., reading the written data, checking the response to a signal).

[0064] Verifying the portion may involve generating or updating one or more measurements. These measurements may indicate the reliability, performance, other aspects, or a combination thereof, of the portion of the memory subsystem. The measurements may include one or more numerical values, character values, statistical values, probability values, other values, or combinations thereof, and may represent quantities, percentages, ratios, averages, medians, standard deviations, or other mathematical properties. In one instance, the measurement may be a reliability measurement indicating the ability of the portion (e.g., a memory device, memory cell) to reliably store data. The reliability measurement may be based on the number of times the portion reliably or unreliably stores data, and the value may increase or decrease when the data stored by the portion contains errors (e.g., bit flips, invalid values, error voltages).

[0065] Inventory module 412 enables memory subsystem 110 to inventory faults by updating inventory with fault-related data. Fault-related data may be stored in local memory 119 as fault data 442. Fault data 442 may be the same as or similar to health data and may include data identifying or describing the impact of the fault, the cause of the fault, indications of the fault, other aspects of the fault, or combinations thereof. The impact of the fault may be the result or consequence of the fault and may include a set of storage cells (e.g., blocks, areas), memory devices, controllers, other parts of memory subsystem 110, or combinations thereof. In one example, inventory module 412 may generate a set of one or more storage cells affected by a fault and store it as fault data 442. This set may be referred to as a faulty set, an inaccessible set, a defective set, a malfunctioning set, a flawed set, or other terms. It can also detect and record (e.g., inventory) the cause of a failure, which may involve temperature (e.g., extreme heat or cold), humidity (e.g., wetness or dryness), electricity (e.g., leakage, current or voltage surge, short circuit, electrostatic discharge), magnetism (e.g., magnetic field, magnetic force), electromagnetic (e.g., electromagnetic interference (EMI), electromagnetic radiation (EMR)), other causes, or combinations thereof.

[0066] The capacity determination module 414 enables the memory subsystem 110 to determine its capacity before, during, or after a failure. As discussed above, capacity can be a storage capacity based on the storage space size of a set of one or more memory devices. The storage capacity can be smaller than the storage space size of the set and can depend on the amount of storage space used internally (e.g., internal data and data structures). Capacity determination can be based on whether the memory subsystem 110 provides over-provisioning, wear leveling, error detection, error correction, recovery, redundancy, garbage collection, compression, encryption, other features, or combinations thereof. In one instance, the capacity determination module 414 can calculate a change or new capacity (e.g., a reduced capacity) based on a set of memory cells affected by the failure, a set of memory cells unaffected by the failure, all memory cells, or a combination thereof. The calculation can involve summing (e.g., adding) the capacity or size of one or more of these sets and storing the result as capacity data 446.

[0067] The capacity determination module 414 can determine one or more new capacities, each of which may be referred to as fault-inducing capacities. When determining fault-inducing capacities, there may be trade-offs (e.g., inverse relationships) between the capacity and one or more other characteristics of the memory subsystem (e.g., performance, reliability, recoverability, other characteristics, or combinations thereof). A first fault-inducing capacity may correspond to a capacity that keeps other characteristics constant or substantially constant (e.g., 5% of the original capacity). For example, the first fault-inducing capacity may be used to maintain a constant (e.g., the same amount or proportion) reduction in available internal storage space (e.g., a 10% capacity reduction), which minimizes or eliminates any reduction in space used for over-provisioning and parity data. A second value may correspond to a capacity that minimizes the change in capacity at the cost of other characteristics (e.g., reduced performance and recoverability). For example, this fault-inducing capacity may minimize the capacity reduction (e.g., a 1% reduction compared to a 10% reduction) by allowing a larger reduction in available internal storage space (which adversely affects over-provisioning, parity data, or other internal use). In one instance, fault-induced capacity can be calculated using one or more mathematical functions (e.g., equations, formulas) representing relationships between features (e.g., trade-offs between capacity and performance). Mathematical functions can be solved to maximize, minimize, keep constant, or combine thereof, one or more of the features.

[0068] The host negotiation component 214 enables the memory subsystem 110 to communicate with the host system 120 to negotiate changes in the capacity of the memory subsystem 110. In one example, the host negotiation component 214 may include a notification module 420, a data recovery module 422, a data relocation module 424, an instruction receiving module 426, other modules, or combinations thereof.

[0069] Notification module 420 enables memory subsystem 110 to notify the host system of a fault. Notification to the host system may involve generating a notification indicating the existence of a fault, the type of fault, a portion of the memory subsystem affected by the fault, other information, or a combination thereof. The notification may be in the form of a message (e.g., message 229A) sent by memory subsystem 110 and transmitted to the host system via a communication channel. Notification module 420 may transmit one or more messages corresponding to the same fault. A first message may notify the host system that a fault has been detected (e.g., a fault has occurred, a fault has been presented, a fault exists) and may include an indication that capacity has been reduced. The indication may include an indication of whether capacity has changed (e.g., binary yes / no), an indication of the amount of capacity change (e.g., 100GB loss), an indication of the amount of data affected (e.g., the amount of affected external and / or internal data), an indication of one or more values ​​for new capacity, other values, or a combination thereof. A second message may notify the host system of a set of one or more memory cells affected by the fault. The set of storage cells can be a block (e.g., a logical block address), a region (e.g., a region identifier), a device (e.g., a die, a package), a set of other cells, or a combination thereof. The set of storage cells can correspond to a single memory device or different memory devices. A second or subsequent message may also, or alternatively, indicate whether the data affected by the fault can be accessed, corrected, or recovered. The first and second messages may be combined into a single message or propagate across more messages.

[0070] Data recovery module 422 enables memory subsystem 110 to recover stored data affected by a fault. Recovering stored data may involve accessing recovery data 444 and performing error detection (e.g., detecting data changes), error correction (e.g., correcting changed data), data recovery (recovering erased data), or a combination thereof. Recovery data 444 may be stored in local memory 119 and may include error detection data (e.g., error detection codes, checksums, cyclic redundancy checks (CRC)), error correction data (e.g., error correction codes (ECC), forward error correction (FEC), erase codes), redundant data (e.g., duplicate data, parity data), other data, or a combination thereof. Data recovery module 422 may attempt to access data in one or more of the faulty memory cells. Data recovery module 422 may use recovery data 444 to detect error-free and retainable data. Data recovery module 422 may also, or alternatively, use recovery data 444 to correct accessible data or regenerate inaccessible data.

[0071] When the data recovery module 422 generates inaccessible data, the memory subsystem 110 may no longer have sufficient storage capacity to store the generated data. The data recovery module 422 enables the memory subsystem 110 to indicate to the host system that the memory device set can recover the data but cannot store it. The portion of data that the memory subsystem cannot store may be referred to as excess data (e.g., data exceeding the reduced capacity). The memory subsystem can then receive a storage location from the host system to store the recovered data and provide the recovered data for storage at the storage location. This process is discussed in more detail with respect to the data relocation module 424.

[0072] Data relocation module 424 enables memory subsystem 110 to relocate data within memory subsystem 110. Relocating data may involve operations including reading, writing, moving, copying, duplicating, deduplicating, encrypting, decrypting, compressing, decompressing, other operations, or combinations thereof. Data relocation module 424 can relocate data from a first location (e.g., original location, source location) to one or more second locations (e.g., new location, destination location, target location). The first and second locations may be internal locations within memory subsystem 110, external locations outside memory subsystem 110, or combinations thereof. Internal locations may include locations within one or more memory devices (e.g., NAND dies) or within local memory 119 of memory subsystem 110 (e.g., controller DRAM). External locations may include locations on a host system outside memory subsystem 110. Host system locations may be internal to the host system (e.g., within a PC or server) or external to the host system (e.g., on a computer network). External locations may include locations in the host system’s primary storage device (e.g., main memory 225), the host system’s secondary storage device (e.g., another storage subsystem, hard disk drive (HDD)), storage devices outside the host system (e.g., network attached storage device (NAS), storage area network (SAN)), the host system’s processor (e.g., CPU, GPU, network adapter), other locations, or combinations thereof.

[0073] Locations can be determined by either the memory subsystem 110 or the host system 120, based on input data from the host system, the memory subsystem, other systems, or a combination thereof. The memory subsystem 110 can receive data from the host system indicating one or more of the locations. In one example, the host system can provide an external location (e.g., a target location) to the memory subsystem 110, and the memory subsystem 110 can transfer data to the external location. In another example, the host system can provide an internal location (e.g., a source location) without providing a specific external location, and the memory subsystem 110 can respond to the host system with data transfers (e.g., responses, replies) that can resemble conventional access requests (e.g., read requests). In yet another example, the host system can provide both internal and external locations to the memory subsystem 110, and the memory subsystem 110 can copy or move (e.g., relocate) data from the internal location to the external location.

[0074] The memory subsystem 110 can transfer data to an external location of the host system, with or without transferring the data to the CPU of the host system. In one example, the memory subsystem 110 can transfer data to the CPU of the host system via a communication channel, wherein the data is temporarily stored by the CPU while being transferred to the external location. In another example, the memory subsystem 110 can transfer data to an external location via a communication channel without transferring the data to the CPU, thus avoiding the need for the CPU to temporarily store the data. A subsequent example may use techniques similar to or the same as Direct Memory Access (DMA), Direct Data Input / Output (DDIO), Remote Direct Memory Access (RDMA), other I / O acceleration techniques, or combinations thereof.

[0075] Direct Memory Access (DMA) is a feature of some host systems that enables certain hardware subsystems to access the host system's memory (e.g., main memory 225) independently of the Central Processing Unit (CPU). Hardware subsystems may include one or more memory subsystems (e.g., SSD controllers), hard disk drive (HDD) controllers, network interface controllers (NICs), graphics controllers, sound cards, other hardware devices, or combinations thereof. The host system and / or memory subsystems enable the use of DMA to transfer data. Without DMA, the CPU temporarily stores the transferred data (e.g., a temporary copy) while using programmed input / output, and this data is typically occupied for the entire duration of a read or write operation. With DMA, the CPU can configure one or more hardware subsystems to access the host system and / or other host system memory locations, allowing the CPU to perform other operations while data is being transferred. This feature is particularly useful when large amounts of data are being transferred and the CPU cannot keep up with the data transfer rate. DMA offloads costly memory operations (e.g., large copies) from the CPU to other hardware subsystems, and the CPU can subsequently receive an interrupt upon completion of the operation. Remote Direct Memory Access (RDMA) is a form of direct memory access in which a hardware system within a host machine can transfer data to a location outside the host system via the CPU. This can be accomplished by enabling a hardware subsystem (e.g., memory subsystem 110) to transfer data to the memory of a network interface controller (e.g., a network adapter, NIC), which can then transfer data via a network to a device outside the host system (e.g., a NAS, SAN, remote host system).

[0076] Instruction receiving module 426 enables memory subsystem 110 to receive and process instructions indicating whether to continue operation with a reduced capacity. The capacity of memory subsystem 110 may be reduced before, during, or after receiving the instruction. In one instance, the capacity may be reduced before receiving the instruction, and the instruction may cause the memory subsystem to continue operation with the reduced capacity. In another instance, the capacity may remain the same after an error is detected, and the instruction may cause the memory subsystem to reduce its capacity and continue operation with the reduced capacity. This may occur when memory subsystem 110 detects a fault and is able to temporarily avoid further capacity reduction. This may involve delayed reduction (e.g., delayed shifting down multi-level cells) or temporarily compensating for any capacity reduction by using internal space (e.g., reducing over-provisioning or redundant storage space), compressing existing data, relocating data, other operations, or combinations thereof. In either instance, the instruction may cause memory subsystem 110 to eventually operate with a reduced capacity.

[0077] Instructions may include one or more instructions, commands, signals, messages, machine codes, operations, opcodes, or combinations thereof. Instructions may be associated with data (e.g., instruction data or content) that serves as an indication of whether to change capacity (e.g., reduce capacity) or to continue or stop operation at a previously changed capacity. In one instance, the data may indicate one or more capacities and may include the original capacity (1TB), the new capacity (900GB), an incremental change in capacity (e.g., a reduction of 100GB), other capacity values, or combinations thereof. In another instance, the data may indicate a binary response (yes / no, true / false) regarding whether to continue changing capacity or to operate at the changed capacity. In either instance, the memory subsystem 110 may respond to instructions by executing the capacity update component 216.

[0078] Capacity update component 216 enables memory subsystem 110 to update its configuration in response to a fault. This may involve updating the set of memory devices and one or more data structures in light of the changed capacity. As discussed above, capacity may correspond to the portion of storage space available for external use by the host system and may be a subset of the total storage space of memory subsystem 110, since a portion of the storage space is available for internal use. Capacity update component 216 may perform one or more actions in response to the detection of a specific fault, and may reduce capacity, maintain capacity constant, or increase capacity. In one instance, capacity update component 216 may configure memory subsystem 110 to operate at a reduced capacity in response to a fault. In another instance, capacity update component 216 may temporarily minimize capacity reduction (e.g., maintain capacity constant) after a fault is detected, and then subsequently reduce capacity for long-term operation. As discussed above, temporarily minimizing or avoiding capacity reduction may involve delaying capacity reduction by temporarily using internally used storage space, by compressing stored data, by postponing the reduction in size of multi-level cells, or by providing read access to inaccessible data through the use of parity data. Delayed capacity reduction enables the host system to analyze and react to faults and impending or existing capacity reductions. In one instance, capacity update component 216 may include locking module 430, capacity reduction module 432, rebuild module 434, other modules, or combinations thereof.

[0079] Locking module 430 enables memory subsystem 110 to restrict host system access to a portion of memory subsystem 110. Locking module 430 can restrict access by adding (e.g., creating, generating, applying, activating), removing (e.g., deleting, destroying, deactivating), modifying (e.g., editing, updating), or enforcing one or more locks. The locks can restrict access by disabling (e.g., prohibiting, blocking, stopping, closing) or enabling (e.g., allowing, permitting, authorizing) one or more different types of access (e.g., read access, write access, other access, or combinations thereof). The locks may include one or more read locks, write locks, or other locks. A read lock can disable the host system so that it has neither read nor write access to the portion of the memory subsystem corresponding to (e.g., applied to) the lock. A write lock can disable the host system so that it has no write access while allowing the host system to perform read access.

[0080] A lock may be initiated by memory subsystem 110 or host system 120 and may be applied to a specific portion of memory subsystem 110 or host system 120. For example, a lock may be applied to one or more memory subsystems, memory devices, regions, blocks, memory cells, dies, packages, communication channels, connectors, interconnects, other portions of the memory subsystem, or combinations thereof. The lock may restrict access to any or all portions or combinations of portions of the host system. Restricted access may be applied to some or all processes (e.g., kernel, super manager, applications, file systems), processors (e.g., CPU / GPU), hardware subsystems (graphics card, network interface), other portions of the host system, or combinations thereof.

[0081] Locking module 430 can apply a lock to a portion of the memory subsystem affected by a fault (e.g., the faulty portion). The locked portion can be the same as, smaller than, or larger than the specific faulty portion. This can occur when the granularity at which the lock can be applied differs from that of the faulty portion. For example, a lock can be applied to the entire die or region, even if a small portion of the die or region is affected by the fault. The term "faulty portion" can refer to the specific portion affected by the fault, or to a larger portion that includes the unaffected portion. In one instance, the locking module can apply a write lock to the faulty portion, and the write lock can disable the host system's ability to write data to said portion, but allow the host system to read data from said portion. Some of the data may be inaccessible due to the fault and can be recovered by memory subsystem 110.

[0082] The capacity reduction module 432 enables the memory subsystem 110 to update its configuration to reduce capacity. Updating the configuration may involve performing one or more deactivation operations, truncation operations, shift-down operations, or combinations thereof. A deactivation operation may involve deactivating one or more of the faulty portions so that they are no longer considered usable for storing data (e.g., external and / or internal data). Deactivation may be the same as or similar to marking, unmapping, disabling, shutting down, removing, deleting, destroying, blocking, marking, erasing, wiping, other actions, or combinations thereof. A truncation operation may involve reallocating storage devices and reducing the total capacity by deleting a predetermined amount at the beginning, middle, or end of the storage space (e.g., internal or externally accessible address space). The predetermined amount may be based on the amount of storage space affected by the fault and may be the same as, less than, or greater than the amount of storage space that failed.

[0083] The size reduction operation can also be used, or alternatively, to reduce capacity. As discussed above, the memory subsystem 110 may include multilevel cells (MLCs) that store more than one bit of information per memory cell. The size reduction operation can reconfigure one or more of the memory subsystem 110 and memory devices to reduce the number of bits stored per memory cell from a first size (e.g., a larger size, the original size) to a second size (e.g., a smaller size, the reduced size). The first and second sizes of memory cells may include single-level cells (SLCs), two-level cells (DLCs), three-level cells (TLCs), four-level cells (QLCs), five-level cells (PLCs), other cell sizes, or combinations thereof. Each size reduction can reduce the memory cell by one or more levels, and the size reduction can be repeated multiple times until the multilevel cell becomes a single-level cell or is discarded.

[0084] The operation to update the configuration can be applied to any part of the memory subsystem. The operation can be applied to a target portion of one or more specific memory cells, blocks, regions, dies, chipsets, chipsets, packages, other devices, or combinations thereof. The operation can affect the target portion affected by the fault and one or more other portions of the memory subsystem 110. Performing the operation on the target portion can cause some or all of the other portions of the memory subsystem to be updated (e.g., remapping, renumbering, relabeling, repartitioning, reindexing). In one instance, the operation on the target portion can cause the preceding and subsequent portions (e.g., all other portions) to be updated. In another instance, the operation on the target portion can cause the subsequent portions to be updated without updating the preceding portions. In either instance, the operation can reduce the capacity of the memory subsystem by reconfiguring it.

[0085] The reconstruction module 434 enables the memory subsystem 110 to update the data stored by the memory subsystem based on a reduced capacity (e.g., a new configuration). Updating the data may involve adding data, removing data, or changing data in one or more data structures. The data may correspond to the capacity and may include pointer data (starting address), mapped data (e.g., logical-to-physical mapping), table data, index data, other data, or combinations thereof. In one instance, this may involve regenerating recovery data (e.g., parity data), compressing data, encrypting data, or combinations thereof.

[0086] Figure 4 The components and modules may be a superset or subset of the components and modules included in a particular embodiment of the memory subsystem 110. In the examples discussed above, the memory subsystem 110 may include all components and modules. In other examples, the memory subsystem 110 may lack the features of the data recovery module 422, data relocation module 424, reconstruction module 434, inventory module 412, or other modules, and may be performed by another means as discussed below with respect to the host system 120, or may be unnecessary for a particular embodiment.

[0087] Figure 5 To illustrate the use of one or more communication channels (not shown) and Figure 4 A block diagram of exemplary components of the host system 120 to which the memory subsystem is connected. (About...) Figure 5 The features described in the components and modules can be implemented in the computer code (e.g., firmware, software, or other computer programs) or hardware (e.g., circuitry) of the host system 120 or memory subsystem 110. More or fewer components or modules may be included without loss of generality. For example, two or more of the components may be combined into a single component, or the features of a component may be divided into two or more components. In the illustrated example, the host system 120 may be connected to… Figures 1 to 2 The host system 120 is the same as or similar to the host system 120 and may include a fault determination component 222, a data retention component 224, and a storage system component 226. In other instances, the host system 120 may lack the features of the local recovery module 520, the remote recovery module 522, or other modules, and may rely on another means (e.g., the memory subsystem 110) to perform the features, or, for a particular embodiment, the features may be absent.

[0088] Fault determination component 222 enables host system 120 to identify and inventory faults affecting the capacity of memory subsystem 110. As discussed above, faults can affect stored data or the ability to access stored data and can be associated with any part of memory subsystem 110 (e.g., one or more of memory devices, controllers, connectors, interfaces, etc.). In one example, fault determination component 222 may include notification receiving module 510 and logging module 512.

[0089] The notification receiving module 510 enables the host system 120 to receive a notification about a fault from the memory subsystem 110. The notification allows the host system to determine that the memory subsystem has encountered a fault that reduces its storage capacity. The notification may be generated by the memory subsystem and indicates the existence of the fault, the type of fault, a portion of the memory subsystem affected by the fault, other information, or a combination thereof. The notification may be in the form of a message (e.g., message 229A) sent by the memory subsystem 110 and transmitted to the host system 120 via a communication channel. The notification receiving module 510 may receive one or more messages corresponding to the same fault. A first message may notify the host system of the existence of a fault (e.g., a fault has occurred, a fault has been presented) and may include, if appropriate, an indication that the capacity of the memory subsystem has been reduced. The indication may include one or more values ​​indicating whether the capacity has changed (e.g., binary yes / no), the amount of capacity change (e.g., 100GB loss), the amount of data affected (e.g., external data and / or internal data), a new capacity, other values, or combinations thereof. A second message may notify the host system of a set of one or more storage cells affected by the fault. The set of storage cells can be a block (e.g., a logical block address), a region (e.g., a region identifier), a device (e.g., a die, a package), a set of other cells, or a combination thereof. The set of storage cells can correspond to a single memory device or different memory devices. A second or subsequent message may also, or alternatively, indicate whether the data affected by the fault can be accessed, corrected, or recovered. The first and second messages may be combined into a single message or propagate across more messages.

[0090] The logging module 512 enables the host system 120 to log faults by updating inventory with fault-related data. The fault-related data can be stored as fault data 442 in main memory 225. Fault data 442 can be... Figure 4The fault data 442 is the same as or similar to the fault data 442, and can be received from the memory subsystem 110 or generated, supplemented, summarized, or expanded by the host system 120. Fault data 442 can be health data containing data identifying or describing the impact of a fault, the cause of the fault, an indication of the fault, other aspects of the fault, or a combination thereof. The impact of the fault can be the result and / or response of the fault, and can correspond to a set of storage cells (e.g., blocks, areas, memory devices, controllers, other parts of the memory subsystem 110, or combinations thereof). In one example, the logging module 512 can receive or generate a set of one or more storage cells affected by a fault and store it as fault data 442. This set can be referred to as a faulty set, an inaccessible set, a defective set, a malfunctioning set, a flawed set, or other terms. It can also record (e.g., inventory) the cause of the failure, which may involve temperature (e.g., extreme heat or cold), humidity (e.g., wetness or dryness), electricity (e.g., leakage, current or voltage surge, short circuit, electrostatic discharge), magnetism (e.g., magnetic field, magnetic force), electromagnetic (e.g., electromagnetic interference (EMI), electromagnetic radiation (EMR)), other causes or combinations thereof.

[0091] When the capacity of the memory subsystem has decreased, the data retention component 224 enables the host system 120 to enhance data retention on the memory subsystem. Previously, the host system would respond to memory subsystem failures by indicating that the memory subsystem should be replaced or by reformatting the memory subsystem to operate at a lower capacity. Reformatting the memory subsystem is a resource-intensive operation that removes data from the memory subsystem and consumes significant time, processing power, temporary storage space, I / O, and other valuable resources. The data retention component 224 enhances data retention by retaining data that has withstood the failure and, where appropriate, correcting or recovering data affected by the failure. Figure 5 In the example shown, the data retention component 224 may include a local recovery module 520, a remote recovery module 522, and a data rearrangement module 524.

[0092] The local recovery module 520 enables the host system 120 to recover data affected by a failure of the memory subsystem using resources local to the host system 120. Resources local to the host system 120 may include any hardware, software, or data within the host system 120. When the host system 120 is contained within a computer enclosure (e.g., computer chassis, shell, rack, frame, chassis, bladeboard), the resources are internal to the host system. This may include primary data storage devices (e.g., main memory), secondary data storage devices (e.g., memory subsystem 110, HDD), other devices, or combinations thereof. In one instance, the local recovery module 520 may recover failure-affected data (e.g., lost data) by accessing data from backups, accessing data from the original source, using recovered data to generate lost data, other recovery mechanisms, or combinations thereof. In another instance, the local recovery module 520 may cause the memory subsystem to recover failure-affected data, as described above regarding... Figure 4 The data recovery module 422 is described above. The host system 120 may request access to data affected by a fault, and the memory subsystem may generate the data before, during, or after the host system 120 requests it. The memory subsystem may indicate to the host system that the data has been recovered or may perform data recovery transparently to the host system 120 without requiring such indication. In some cases, the local recovery module 520 may not be able to recover data affected by a memory subsystem fault, and the remote recovery module 522 may be used.

[0093] Remote recovery module 522 enables host system 120 to recover data affected by a failure by using one or more resources remote from host system 120. Resources remote from host system 120 can be any hardware, software, or data outside the computer enclosure of host system 120. This includes communicable resources coupled to host system 120 using one or more wires, cables, connectors, computer networks (e.g., LAN, WAN, Internet), or combinations thereof. In one instance, remote recovery module 522 can recover data affected by a failure by accessing data from another host system. Host system 120 and the other host system can be nodes in a storage distribution network, which may have associated replicas or backups, peers in a cluster, other relationships, or combinations thereof.

[0094] The data rearrangement module 524 enables the host system 120 to rearrange data on the memory subsystem 110, the host system 120, or a combination thereof. Data rearrangement may involve one or more operations, including reading, writing, moving, copying, duplicating, deduplicating, encrypting, decrypting, compressing, decompressing, other operations, or combinations thereof. The data rearrangement module 524 can copy data from a first location (e.g., the original location, the source location) to one or more second locations (e.g., a new location, a destination location, a target location). The first and second locations may be in volatile or non-volatile memory and may be internal locations within the memory subsystem 110, external locations outside the memory subsystem 110, or combinations thereof. External locations may include locations within the host system (e.g., inside a computer enclosure) or locations outside the host system 120 (e.g., on a network). External locations may include locations within the host system’s primary storage device (e.g., main memory), the host system’s secondary storage device (e.g., another storage subsystem, hard disk drive (HDD)), storage devices outside the host system (e.g., network attached storage device (NAS), storage area network (SAN)), the host system’s processor (e.g., CPU, GPU, network adapter), other locations, or combinations thereof.

[0095] The location may be determined based on data from the host system 120, the memory subsystem, other systems or devices, or a combination thereof. The host system may provide data indicating one or more of the locations to the memory subsystem. In one example, the host system 120 may provide an external location (e.g., a target location) to the memory subsystem, and the memory subsystem may transfer data to the external location. In another example, the host system may provide an internal location (e.g., a source location) without providing a specific external location, and the memory subsystem may return data at the internal location, which may resemble a conventional access request (e.g., a read request). In yet another example, the host system 120 may provide both an internal and an external location to the memory subsystem, and the memory subsystem may copy or move (e.g., relocate) data from the internal location to the external location.

[0096] The host system 120 is configurable for Direct Memory Access (DMA), allowing the memory subsystem to transfer data to an external location without transferring it to the host system's CPU. DMA is particularly advantageous because the data rearrangement module 524 can arrange very large amounts of data (e.g., 100GB to 1TB) and can perform data transfers with minimal CPU involvement in managing the transfers. The CPU can be configured with DMA features and listen for signals (e.g., interception) to determine when a transfer is complete. (The above refers to...) Figure 4 The data relocation module 424 of the memory subsystem 110 in the middle discusses DMA in more detail.

[0097] Storage system component 226 enables host system 120 to adapt to a reduction in the capacity of the memory subsystem by reconfiguring its storage system. The storage system can be any data storage system, and can be a file system, database system, distributed storage system, virtual storage system, other storage systems, or combinations thereof. The storage system can be managed by code that executes as part of the kernel, device drivers, applications, other parts of the host operating system, or combinations thereof. Figure 5 In the example shown, storage system component 226 may include a capacity management module 530, an instruction providing module 532, and a storage structure update module 534.

[0098] The capacity management module 530 enables the host system 120 to determine and control the capacity of the memory subsystem 110 before, during, or after a failure. As discussed above, capacity can be a storage capacity based on the storage space size of a collection of one or more memory devices. The storage capacity can be smaller than the storage space size of the collection and can depend on the amount of storage space used internally (e.g., internal data and data structures). Determining capacity may involve communicating with the memory subsystem and determining or controlling the memory subsystem's use of over-provisioning, wear leveling, error detection, error correction, recovery, redundancy, garbage collection, compression, encryption, other features, or combinations thereof. In one instance, the capacity management module 530 may determine (e.g., calculate, detect) a change in capacity or a new capacity (e.g., a reduced capacity) based on data received from the memory subsystem.

[0099] The capacity management module 530 enables the host system 120 to perform functions identical or similar to those described above regarding the capacity determination module 414 of the memory subsystem. For example, the host system 120 may determine one or more fault-inducing capacities. When determining the fault-inducing capacity, trade-offs may exist between the capacity and one or more other characteristics of the memory subsystem (e.g., performance, reliability, recoverability, other characteristics, or combinations thereof) (e.g., an inverse relationship between capacity and over-provisioning). A first fault-inducing capacity may correspond to a capacity that keeps other characteristics constant or substantially constant (e.g., 5% of the original capacity). For example, the first fault-inducing capacity may be used to maintain a constant (e.g., the same amount or proportion) reduction in available internal storage space (e.g., a 10% reduction), minimizing or eliminating any reduction in space used for over-provisioning and parity data. A second value may correspond to a capacity that minimizes changes in capacity at the cost of other characteristics (e.g., reduced performance and recoverability). For example, this fault-inducing capacity can be minimized by allowing a significant reduction in the storage space available for internal use (which adversely affects over-provisioning, parity data, or other internal use). In one instance, one or more fault-inducing capacities can be calculated using one or more mathematical functions (e.g., equations, formulas) representing relationships between features (e.g., feature selection). The mathematical functions can be solved such that one or more of the features are maximized, minimized, or kept constant.

[0100] The instruction providing module 532 enables the host system 120 to instruct the memory subsystem to operate at reduced capacity while preserving the data in the memory system. Instructions can be transmitted after a fault is detected and before, during, or after the memory subsystem has been reconfigured to operate at reduced capacity. In one example, the memory subsystem may notify the host system 120 and wait for the host system 120 to provide instructions before reconfiguring the memory subsystem for reduced capacity. In another example, the memory subsystem may begin the capacity reduction process before, during, or after the host system provides instructions and notifies the host system 120 of the fault.

[0101] Instructions may be generated by host system 120 and may contain content (e.g., data) or be associated with content (e.g., data). Instructions may contain one or more individual or combined instructions, commands, signals, messages, machine codes, operations, opcodes, or combinations thereof. Content may serve as an indication of whether to change capacity (e.g., reduce capacity) or to continue or stop operation at a previously changed capacity. In one instance, data may indicate a binary response (yes / no, true / false) regarding whether to continue changing capacity or to operate at the changed capacity. In one instance, data may indicate one or more capacities and may contain the original capacity (1TB), the new capacity (900GB), an incremental change in capacity (e.g., a reduction of 100GB), other capacity values, or combinations thereof. In any instance, host system 120 may transmit instructions and update storage structure 124 using storage structure update module 534.

[0102] The storage structure update module 534 enables the host system 120 to adapt to a reduction in the capacity of the memory subsystem by configuring (e.g., reconfiguring) the storage structure 124 of the storage system. The storage structure update module 534 can execute as one or more system procedures (e.g., kernel procedures), user procedures (e.g., application procedures), or a combination thereof. The storage structure 124 may include one or more data structures for managing the storage and retrieval of data from one or more memory subsystems. The storage structure 124 may include data structures and rules for organizing data and may involve separating data into individually identifiable and accessible storage units. Some or all of the storage structure 124 may be stored in main memory 225, memory subsystem 110, other primary or secondary storage devices, or a combination thereof. In one example, the storage structure 124 may be a file system, as discussed in more detail below.

[0103] A file system may contain multiple layers, which may include logical file systems (e.g., logical layers), virtual file systems (e.g., virtual layers), physical file systems (e.g., physical layers), other layers, or combinations thereof. A logical file system manages interaction with applications and provides an application programming interface (e.g., a file system API) that exposes file system operations (e.g., open, close, create, delete, read, write, execute) to other computer programs. A logical layer of the file system manages security and permissions and maintains open file table entries and each procedure file descriptor. A logical file system may pass requested operations (e.g., write requests) to one or more other layers for processing. A virtual file system enables the operating system to support multiple parallel instances of a physical file system, each of which may be referred to as a file system implementation. A physical file system manages the physical operations of storage devices (e.g., memory subsystem 110). A physical file system handles buffers and manages main memory and is responsible for the physical placement of storage cells in specific locations on memory devices 130A-Z. The physical file system may contain device mapping logic and may interact with a device driver (e.g., an SSD driver) or a channel to interact with the memory subsystem 110. One or more of the file system layers may be explicitly separated or combined together to store file system data.

[0104] File system data can be any data associated with a file system and can include data received by the file system (e.g., user data) or data generated by the file system. File system data can represent data from one or more external file system objects, internal file system objects, or a combination thereof. External file system objects can be file system objects that can be accessed externally by a computer program (e.g., an application) using the file system API. External file system objects can contain files (e.g., file data and metadata), directories (e.g., folders), links (e.g., soft links, hard links), or other objects. Internal file system objects can be file system objects that remain inside the file system and are not accessible using the file system API. Internal file system objects can contain storage tree objects (e.g., extent maps, extent trees, block trees), stream objects (e.g., stream identifiers), file group data (e.g., groups of similar files), storage units, block groups, extents, or other internal data structures.

[0105] Each file system object can be associated with object data and object metadata. Object data can be the content of the object (e.g., file data), and object metadata can be information about the object (e.g., file metadata). Object metadata can indicate the object's attributes, such as storage location (e.g., extent, block group, storage unit), data source (e.g., stream, application, user), data type (e.g., text, image, audio, video), size (e.g., file size, directory size), time (e.g., creation time, modification time, access time), ownership (e.g., user ID, group ID), permissions (e.g., read, write, execute), file system location (e.g., parent directory, absolute path, local path), other attributes, or combinations thereof. In one instance, file system data can contain data for a new file, and the new file can contain file data and file metadata. File data can contain the content of the file (e.g., image content, audio content), and file metadata can contain one or more attributes of the content (e.g., identifiers corresponding to extent z, stream s, and / or application a).

[0106] Object data and object metadata (e.g., attributes, tree nodes) can be stored together in the same data structure at the same storage location, or they can be stored separately in different data structures at different storage locations. For example, storage structure 124 can store object metadata in an inode (e.g., an index section) data structure, and the inode data structure can have one or more pointers to the object data. An index section can be a data structure in a Unix-style file system that describes a file system object. Each index section can indicate the attributes and storage location (e.g., block address) of the file system object's data. A directory can be represented as an "index section" and can contain each of its own entries, its parent entries (e.g., a parent directory), and its child entries (e.g., subdirectories or files).

[0107] A file system can divide allocated space into block groups, which can be variable-sized allocation areas. Allocation areas can be used to store object metadata (e.g., extent tree nodes, inodes) and object data (e.g., file content, extents). A block group (BG) can be understood as a contiguous region allocated to a storage device that holds file system objects (e.g., a series of LBAs) for file system data used by the file system. This contiguous region can be represented as a range of block numbers (e.g., physical addresses). Large files can be split into individually tracked block groups to make file allocation and management feasible during a series of necessary allocations and writes to storage devices 130A-Z. The default ratio of object data to object metadata is 1:2. It aims to use the concept of the Orlov block allocator to allocate related file system objects together and resist fragmentation by leaving free space between groups. (However, Ext3 block groups have fixed locations calculated based on the size of the file system, while those block groups in a B-tree file system are dynamic and created on demand.) Each block group can be associated with a block group identifier (e.g., a block group entry). In a file system tree, an index section may contain references to the corresponding block group (e.g., pointers to storage units).

[0108] Figure 6 This is a flowchart of a method 600 executed by a memory subsystem to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure. Method 600 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0109] At operation 610, the processing logic can detect a fault in at least one memory device in the set, wherein the fault affects stored data. In one example, the memory subsystem is a solid-state drive (SSD), and the processing device is a memory controller for the SSD. In one example, the processing device can detect multiple faults that occur at different times and affect different memory devices in the set.

[0110] At operation 620, the processing logic may notify the host system (e.g., host system 120) of a change in the capacity of a set of memory devices (e.g., memory devices 130A to 130Z). This notification may involve transmitting a first message to the host system to indicate a fault, and a second message to the host system to indicate the set of memory cells affected by the fault. The first and / or second messages are asynchronous event notification (AEN) messages. In one example, the processing device may notify the host system after each fault and reduce the capacity after each fault.

[0111] At operation 630, the processing logic may receive an instruction from the host system to continue with reduced capacity. In one example, the operation may involve determining whether the capacity following a second failure meets a threshold capacity. The threshold capacity may be a predetermined minimum capacity of the memory device set. In response to meeting the threshold capacity, the processing device may indicate to the host system that the memory device set can operate with reduced capacity. In response to not meeting the threshold capacity, the processing device may indicate to the host system that the memory device set is inoperable.

[0112] At operation 640, the processing logic may update the set of memory devices to change the capacity to a reduced capacity. This may involve locking the failed portion of at least one memory device. The locking may include a write lock that enables reads from the host system and disables writes from the host system. In one instance, the processing device may provide the host system with data recovered in response to a read request from the host system for the failed portion. The processing device may also, or alternatively, delete data from at least one memory device and generate recovery data for the set of memory devices based on the reduced capacity. In other instances of method 600, the operation may include recovering stored data affected by one or more failures using the recovery data stored in the set of memory devices.

[0113] Figure 7 This is a flowchart of a method 700 executed by a memory subsystem to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure. Method 700 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0114] At operation 710, the processing logic can configure the memory device to have a partitioned namespace containing multiple regions. The partitioned namespace can be provided by NVM Express. TM (NVMe TM A partitioned namespace is an organized, sequential namespace. Within a partitioned namespace, the address space of each memory device can be divided into one or more partitions. Each partition can be a contiguous or non-contiguous portion (e.g., a block range) of a memory device that is identified and managed as a single memory cell. Each partition can correspond to partition identification data, which can be used to uniquely identify the partition and can be the same as or similar to a partition identifier (partition ID), partition descriptor, partition label, or other terms. A partition can be a memory storage cell (e.g., a memory unit) and can have a predefined size that can be based on the size (e.g., an integer multiple) of another memory storage cell (e.g., a block, cell, page, die, device, or subsystem). In one example, the memory subsystem is a solid-state drive (SSD), and the processing device is the memory controller of the SSD.

[0115] At operation 720, the processing logic may notify the host system of a fault associated with one of a plurality of zones, and said fault may affect stored data. In one instance, the notification may involve transmitting a message to the host system indicating a set of one or more zones of the memory device affected by the fault.

[0116] At operation 730, the processing logic may receive from the host system an instruction to continue with the reduced capacity. In one instance, the processing device may also, or alternatively, indicate to the host system that the capacity of the memory device set is insufficient to store the recovered data. The processing device may receive from the host system the storage location for storing the recovered data. The storage location may be in the host system's main memory.

[0117] At operation 740, the processing logic can recover the stored data in the affected area. The recovery of the stored data may involve accessing the recovered data (e.g., parity data) stored by the memory device, and generating the affected stored data based on the recovered data.

[0118] At operation 750, the processing logic may update the memory device set to change its capacity to a reduced capacity. The update may involve locking a region associated with a failure of at least one memory device. The locking may use a write lock that enables reads from the host system and disables writes from the host system. The processing device may provide the host system with data recovered in response to a read request for the region. The processing device may also update a partition namespace to reduce its capacity, which may involve deactivating regions and deleting all data in those regions. The processing device may generate recovery data for the memory device set based on the reduced capacity.

[0119] Figure 8This is a flowchart of a method 800 executed by a memory subsystem to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure. Method 800 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0120] At operation 810, the processing logic can detect a fault in a memory device that stores multiple bits per memory cell. Fault detection may involve calculating a reliability measurement based on the memory device's ability to store multiple bits per memory cell. The processing device can determine the presence of a fault in response to comparing the reliability measurement with a predetermined threshold. In one example, the memory subsystem is a solid-state drive (SSD), and the processing device is the memory controller of the SSD.

[0121] At operation 820, the processing logic may send a message indicating a reduced capacity of the memory device set to the host system. Sending the message may involve sending a first message to the host system to indicate a fault, and a second message to the host system to indicate the set of memory cells affected by the fault. The first message and / or the second message may be an asynchronous event notification (AEN) message.

[0122] At operation 830, the processing logic may receive a message from the host system indicating that it will continue with the reduced capacity. In one instance, the processing device may instruct the host system that the memory device set contains data exceeding the reduced capacity. The processing device may receive a storage location from the host system to store the recovered data and provide the data exceeding the reduced capacity to the storage location. The storage location may be in the host system's main memory or at another location.

[0123] At operation 840, the processing logic may update the set of memory devices based on the reduced capacity. The update involves reducing the number of bits stored per memory cell in one or more memory devices in the set. In one instance, the memory devices comprise multi-level cells (MLCs) (e.g., composed of them), and reducing the number of bits stored per memory cell involves moving a four-level cell (QLC) down to a three-level cell (TLC).

[0124] Method 800 may also, or alternatively, involve a processing device detecting a second fault in the same memory device. The second fault may be detected based on the memory device's inability to store a reduced number of bits per memory cell. The processing device may respond to the second fault by updating the set of memory devices to further reduce the number of bits stored per memory cell (e.g., from TLC to SLC).

[0125] Figure 9 This is a flowchart of a method 900 executed by a memory subsystem to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure. Method 900 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0126] At operation 910, the processing logic can detect faults in multiple memory devices within the set. A fault can render data inaccessible from the memory device. In one instance, the memory device fault is a hardware failure of at least one of the connector, communication channel, or die.

[0127] At operation 920, the processing logic can determine that the capacity of the memory device set has been changed to a reduced capacity. In one example, the memory subsystem is a solid-state drive (SSD), and the processing device is the memory controller of the SSD.

[0128] At operation 930, the processing logic may notify the host system of the reduced capacity. The notification indicates a set of storage units containing data that is inaccessible due to a fault. In one instance, the notification involves the processing device transmitting a message to the host system indicating a set of logical blocks containing inaccessible data. In another instance, the notification involves the processing device transmitting a message to the host system indicating a set of one or more areas containing inaccessible data.

[0129] At operation 940, the processing logic can recover data from the host system's set of storage units after a failure. This recovery involves the processing device recovering a portion of the data that is inaccessible using parity data stored on the set of memory devices.

[0130] At operation 950, the processing logic may update the set of memory devices to store the recovered data and change the capacity to a reduced capacity. The update may involve locking the faulty portion of at least one memory device. The locking may include a write lock that enables reads from the host system and disables writes from the host system. The processing device may provide the recovered data to the host system in response to a read request for the faulty portion. The processing device may delete data from at least one memory device and generate or update parity data for the set of memory devices based on the reduced capacity.

[0131] Figure 10 This is a flowchart of a method 1000 executed by a host system to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure. Method 1000 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0132] At operation 1010, the processing logic can determine whether a fault affects the storage capacity of the memory subsystem. The fault may include a failure of at least one of the die, connector, or communication channel of the memory subsystem. The memory subsystem may store data from one or more storage structures of the storage system. In one example, the memory subsystem may be a solid-state drive (SSD), and the host system may perform a device driver that communicates with the memory controller of the SSD. Determining a fault may involve the host system receiving a message from the memory subsystem indicating the presence of a fault, and the message may be or contain one or more asynchronous event notification (AEN) messages.

[0133] At operation 1020, the processing logic may instruct the memory subsystem to operate with reduced capacity while preserving the data stored in the storage structure. In one instance, the storage structure may be a file system, and the processing device may configure the storage structure based on the reduced capacity of the memory subsystem.

[0134] At operation 1030, the processing logic can receive a set of memory cells in the memory subsystem affected by a fault. In one instance, the set of memory cells contains a collection of one or more logical blocks (e.g., logical block addresses) containing inaccessible data. In another instance, the set of memory cells contains a collection of one or more regions containing inaccessible data.

[0135] At operation 1040, the processing logic can recover data from the set of memory cells affected by the fault. In one instance, data recovery involves receiving data recovered by the memory subsystem using parity data. In another instance, data recovery involves receiving data from a copy of data on another host system. In either instance, the processing device can store the received data at a storage location in the memory subsystem or in another memory subsystem.

[0136] Figure 11 This is a flowchart of a method 1100 executed by a host system to manage the reduction of the capacity of a memory subsystem according to some embodiments of the present disclosure. Method 1100 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, specialized logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing means), or a combination thereof. Although shown in a particular order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0137] At operation 1110, the processing logic may receive an indication that the storage capacity of the memory subsystem is affected by a fault. This reception may involve receiving a first message indicating the existence of a fault and a second message indicating a set of memory cells affected by the fault. The first and second messages may be asynchronous event notification (AEN) messages. The memory subsystem includes memory cells, each storing multiple bits of data and capable of storing a storage structure. In one example, the memory subsystem may be a solid-state drive (SSD), and the host system performs a device driver that communicates with the memory controller of the SSD. In one example, the processing device may configure the storage structure (e.g., a file system) based on a reduced capacity of the memory subsystem.

[0138] At operation 1120, the processing logic can instruct the memory subsystem to operate with a reduced capacity. The reduced capacity can be a result of reducing the number of bits stored per memory cell in the memory subsystem. In one example, a memory cell storing multiple bits per cell can be a four-level cell, and instructing the memory subsystem to operate with a reduced capacity causes the four-level cell to be moved down to a three-level cell.

[0139] At operation 1130, the processing logic may receive an indication that the memory subsystem contains data exceeding the reduced capacity. This may occur when the memory subsystem is at or near full capacity upon detection of a fault. The memory subsystem may be able to recover inaccessible (e.g., lost) data, but does not have a location to store the recovered data.

[0140] At operation 1140, the processing logic can provide a storage location to the memory subsystem. The storage location can be outside the memory subsystem and is large enough to store the recovered data.

[0141] At operation 1150, the processing logic enables the memory subsystem to store the memory structure's data at the storage location. Enabling the memory subsystem to store data may involve the host system enabling the memory subsystem to transfer data using Direct Memory Access (DMA). In one example, the host system may receive an indication that the memory subsystem's storage capacity is affected by an additional fault and may instruct the memory subsystem to operate at a reduced capacity. This reduced capacity may reduce the number of bits stored per memory cell to a single bit per memory cell.

[0142] Figure 12 This describes an instance machine of computer system 1200, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 1200 may correspond to a host system (e.g., Figures 1 to 2 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 (Memory subsystem 110). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0143] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0144] The example computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1218, which communicate with each other via a bus 1230.

[0145] Processing device 1202 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 1202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein. Computer system 1200 may further include a network interface device 1208 for communication via network 1220.

[0146] Data storage system 1218 may include machine-readable storage medium 1224 (also referred to as non-transitory computer-readable medium) on which one or more instruction sets 1226 or software embodying any one or more of the methods or functions described herein are stored. Instructions 1226 may also reside wholly or at least partially within main memory 1204 and / or processing device 1202 during execution by computer system 1200, which also constitute machine-readable storage medium. Machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 may correspond to... Figure 1 The memory subsystem 110.

[0147] In one embodiment, instruction 1226 includes instructions for implementing the corresponding Figure 5The machine-readable storage medium 1224 is shown as a single medium in the exemplary embodiment, but the term "non-transitory machine-readable storage medium" should be considered to include a single medium or multiple media storing the one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0148] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document, and generally in general, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0149] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0150] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each connected to a computer system bus.

[0151] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0152] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., non-transitory computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, and the like.

[0153] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Collection of memory devices; as well as A processing device operatively coupled to the memory device assembly to perform operations including: Detecting a fault in at least one memory device in the set, wherein the fault affects stored data; Notify the host system of the change in the capacity of the memory device set; Receive an instruction from the host system to continue with reduced capacity; Update the set of memory devices to change the capacity to the reduced capacity; An indication that the set of memory devices includes data exceeding the reduced capacity is sent to the host system; Receive from the host system the storage location for storing the data exceeding the reduced capacity; and The data exceeding the reduced capacity is stored in the storage location.

2. The system of claim 1, wherein the system includes a solid-state drive (SSD), and wherein the processing device is a memory controller of the solid-state drive.

3. The system according to claim 1, wherein the notification includes: A first message is transmitted to the host system to indicate the fault, wherein the first message is an asynchronous event notification (AEN) message. as well as A second message is transmitted to the host system to indicate the set of storage units affected by the fault.

4. The system of claim 1, wherein the operation further comprises: Detecting multiple faults occurring at different times, wherein each of the multiple faults affects different memory devices in the set of memory devices; The host system is notified after each of the plurality of faults; as well as The capacity of the memory device set is reduced after each of the plurality of faults.

5. The system according to claim 1, wherein the operation further comprises: Determine whether the capacity after the second failure meets a threshold capacity, wherein the threshold capacity is a predetermined minimum capacity for the set of memory devices; In response to meeting the threshold capacity, the host system is instructed that the memory device set can operate at a reduced capacity; as well as In response to the failure to meet the threshold capacity, the host system is instructed that the set of memory devices is inoperable.

6. The system of claim 1, wherein the operation further comprises the processing means using recovery data from the set of memory devices to recover the stored data.

7. The system of claim 1, wherein the operation further comprises: Locking the faulty portion of the at least one memory device, wherein the locking includes a write lock that enables reading from the host system and disables writing to the host system; Provide the host system with data recovered in response to a read request for the faulty portion; Delete the data in the at least one memory device; as well as Recovery data for the memory device set is generated based on the reduced capacity.

8. A method comprising: Detecting a fault in at least one memory device in a set of memory devices, wherein the fault affects stored data; Notify the host system of the change in the capacity of the memory device set; The processing unit receives an instruction from the host system to continue under reduced capacity; The processing device updates the memory device set to change the capacity to the reduced capacity; An indication that the set of memory devices includes data exceeding the reduced capacity is sent to the host system; Receive from the host system the storage location for storing the data exceeding the reduced capacity; as well as The data exceeding the reduced capacity is stored in the storage location.

9. The method of claim 8, wherein the processing device is a memory controller of a solid-state drive.

10. The method of claim 8, wherein the notification comprises: A first message is transmitted to the host system to indicate the fault, wherein the first message is an asynchronous event notification (AEN) message. as well as A second message is transmitted to the host system to indicate the set of storage units affected by the fault.

11. The method of claim 8, further comprising: Detecting multiple faults occurring at different times, wherein each of the multiple faults affects different memory devices in the set of memory devices; The host system is notified after each of the plurality of faults; as well as The capacity of the memory device set is reduced after each of the plurality of faults.

12. The method of claim 8, further comprising: Determine whether the capacity after the second failure meets a threshold capacity, wherein the threshold capacity is a predetermined minimum capacity for the set of memory devices; In response to meeting the threshold capacity, the host system is instructed that the memory device set can operate at a reduced capacity; as well as In response to the failure to meet the threshold capacity, the host system is instructed that the set of memory devices is inoperable.

13. The method of claim 8, further comprising recovering the stored data by the processing means using recovery data from the set of memory devices.

14. The method of claim 8, further comprising: Locking the faulty portion of at least one memory device in the set, wherein the locking includes a write lock that enables reading from the host system and disables writing to the host system; Provide the host system with data recovered in response to a read request for the faulty portion; Delete the data in the at least one memory device; as well as Recovery data for the memory device set is generated based on the reduced capacity.

15. A non-transitory computer-readable medium storing instructions that, when executed by a processing means, cause the processing means to perform operations, the operations including: Detect multiple faults in a set of memory devices, wherein a first fault affects data stored on a first memory device and a second fault affects data stored on a second device; After each of the plurality of faults, the host system is notified of the change in the capacity of the memory device set; The host system receives an instruction to continue with reduced capacity after each of the plurality of failures; The memory device set is updated after each of the plurality of faults to change the capacity to the reduced capacity; An indication that the set of memory devices includes data exceeding the reduced capacity is sent to the host system; Receive from the host system the storage location for storing the data exceeding the reduced capacity; as well as The data exceeding the reduced capacity is stored in the storage location.

16. The non-transitory computer-readable medium of claim 15, wherein the processing means is a memory controller of a solid-state drive.

17. The non-transitory computer-readable medium of claim 15, wherein the notification comprises: A first message is transmitted to the host system to indicate the first fault, wherein the first message is an asynchronous event notification (AEN) message. as well as A second message is transmitted to the host system to indicate the set of storage units affected by the first fault.

18. The non-transitory computer-readable medium of claim 15, wherein the plurality of faults occur at different times, and each of the plurality of faults affects different memory devices in the set of memory devices.

19. The non-transitory computer-readable medium of claim 15, wherein the operation further comprises: Determine whether the capacity after the second fault meets a threshold capacity, wherein the threshold capacity is a predetermined minimum capacity for the set of memory devices; as well as In response to meeting the threshold capacity, the host system is instructed that the memory device set can operate at a reduced capacity.

20. The non-transitory computer-readable medium of claim 15, wherein the operation further comprises: Locking the faulty portion of at least one memory device in the set, wherein the locking includes a write lock that enables reading from the host system and disables writing to the host system; Provide the host system with data recovered in response to a read request for the faulty portion; Delete the data in the at least one memory device; as well as Recovery data for the memory device set is generated based on the reduced capacity.

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