PCIe bandwidth allocation system and method

Abstract

The application relates to a PCIe bandwidth allocation system and method. The system comprises a mainboard and a subboard; a signal input end of the mainboard is connected to a signal output end of the subboard; the subboard comprises a first complex programmable logic device and at least one in-situ signal detection unit connected in series; the in-situ signal detection unit comprises a non-standard board card insertion slot and a resistor connected in series, and a current detection operational amplifier module connected in parallel to both sides of the resistor. The PCIe bandwidth allocation system can quickly and efficiently realize bandwidth allocation of a non-standard board card.

Description

Technical Field

[0001] This application relates to the field of automatic bandwidth allocation technology, and in particular to a PCIe bandwidth allocation system and method. Background Technology

[0002] In server system design, different PCIe devices are needed to meet various functional requirements. Motherboard design typically uses the PCIe high-speed bus (Peripheral Component Interconnect Express) to transmit high-speed signals. PCIe is a high-speed serial point-to-point dual-channel high-bandwidth transmission, where each connected device has its own dedicated channel bandwidth and does not share the bus bandwidth. A wide variety of devices can be connected to the PCIe high-speed bus, such as network cards, NVMe hard drives, and SAS / RAID cards. When connecting different PCIe devices, the BIOS needs to be configured with the correct bandwidth to ensure proper device operation.

[0003] In existing technologies, common bandwidth allocation methods include the following: First, fixed bandwidth allocation; that is, allocating a fixed amount of bandwidth to external devices; however, this method increases the risk of resource waste. Second, the motherboard automatically allocates bandwidth based on the information identifier of standard boards; however, this method requires either that the boards connected to the server be custom-developed by the application user or manufactured according to standard protocols. Third, bandwidth allocation is requested via I2C based on the presence signal connected to the PCA9555; however, in practical applications, only standard boards can connect to the PCA9555, so this method cannot allocate bandwidth to non-standard boards. Fourth, the system pre-generates bandwidth allocation information in the EEPROM; the motherboard CPLD reads the bandwidth allocation information from the EEPROM via I2C and transmits it to the southbridge chip via the LPC bus to achieve correct PCIe bandwidth allocation; however, this method has poor flexibility and cannot adjust the bandwidth allocation information in a timely manner based on actual application conditions. In addition, with the increasing application of servers, edge servers, vehicle servers, and other devices need to be compatible with external devices such as 4G modules, 5G modules, Wi-Fi modules, and NX modules. However, the standard definitions of these devices are not yet unified, and in actual application scenarios, their pin information is not defined according to the standard interface definition. Therefore, in practical application scenarios, bandwidth management and allocation cannot be performed based on the device's pin information.

[0004] Therefore, there is an urgent need to propose a PCIe bandwidth allocation system and method that can quickly and efficiently allocate bandwidth to non-standard boards. Summary of the Invention

[0005] Therefore, it is necessary to provide a PCIe bandwidth allocation system and method that can efficiently and quickly allocate bandwidth to non-standard cards without modifying the motherboard circuitry, in order to address the aforementioned technical problems.

[0006] On the one hand, a PCIe bandwidth allocation system is provided, the system being used to implement bandwidth allocation for non-standard boards, the system comprising: a motherboard and a daughterboard;

[0007] The signal input terminal of the motherboard is connected to the signal output terminal of the daughterboard;

[0008] The sub-board includes: a first complex programmable logic device and an in-situ signal detection unit connected in series, wherein the in-situ signal detection unit is at least one;

[0009] The in-situ signal detection unit includes: a non-standard board slot and a resistor connected in series, and a current detection operational amplifier module connected in parallel across the resistor.

[0010] In one embodiment, the first complex programmable logic device is provided with an analog-to-digital conversion module, and the analog-to-digital conversion module is provided in a one-to-one correspondence with the in-situ signal detection unit;

[0011] The in-situ signal detection unit is connected in series to the signal input terminal of the analog-to-digital conversion module.

[0012] In one embodiment, the first complex programmable logic device has a dedicated register; the signal output terminal of the analog-to-digital converter module is communicatively connected to the signal input terminal of the dedicated register.

[0013] In one embodiment, the motherboard includes: a second complex programmable logic device (CPL), a southbridge chip, and a central management controller; the signal output terminal of the southbridge chip is communicatively connected to the signal input terminal of the central management controller; the signal input terminal of the southbridge chip is communicatively connected to the signal output terminal of the second CPL; and the signal input terminal of the second CPL is communicatively connected to the signal output terminal of the first CPL.

[0014] In one embodiment, the second complex programmable logic device is provided with a technology-oriented enhanced serial peripheral interface; the southbridge chip communicates with the second complex programmable logic device through the technology-oriented enhanced serial peripheral interface.

[0015] In one embodiment, the daughterboard is provided with a standard board mounting module for mounting standard boards; the second complex programmable logic device is provided with an I2C arbitration communication unit; the signal input terminal of the I2C arbitration communication unit is respectively connected to the signal output terminal of the standard board mounting module and the signal output terminal of the first complex programmable logic device, and the signal output terminal of the I2C arbitration communication unit is connected to the southbridge chip via an enhanced serial peripheral interface.

[0016] On the other hand, a PCIe bandwidth allocation method is provided, the method comprising:

[0017] The current sensing operational amplifier module detects and amplifies the current load data on both sides of the resistor, and feeds back the amplified current load data to the first complex programmable logic device in real time through the analog-to-digital conversion module. The current sensing operational amplifier module, the resistor, and the analog-to-digital conversion module are configured accordingly.

[0018] The first complex programmable logic device writes the current load data into a dedicated register;

[0019] The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, so as to realize PCIe bandwidth allocation.

[0020] In one embodiment, the second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, including: when the current load data shows that the current load on both sides of the resistor is not 0, it is determined that the non-standard board slot is occupied; if the current load data shows that the current load on both sides of the resistor is 0, it is determined that the non-standard board slot is not occupied.

[0021] In one embodiment, the second complex programmable logic device reads the dedicated register to obtain the status of the non-standard board slots in order to realize PCIe bandwidth allocation. This includes: the second complex programmable logic device obtaining the number of non-standard boards in an occupied state and sending the number of non-standard boards to the southbridge chip; the southbridge chip generating bandwidth allocation information based on the number of non-standard boards and sending it to the central management controller; and the central management controller realizing PCIe bandwidth allocation based on the bandwidth allocation information.

[0022] In one embodiment, if a non-standard board is inserted into the non-standard board slot and a standard board is attached to the standard board mounting module, the I2C arbitration communication unit accesses the dedicated register or the standard board mounting module according to the preset arbitration communication rules.

[0023] In another aspect, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0024] The current sensing operational amplifier module detects and amplifies the current load data on both sides of the resistor, and feeds back the amplified current load data to the first complex programmable logic device in real time through the analog-to-digital conversion module. The current sensing operational amplifier module, the resistor, and the analog-to-digital conversion module are configured accordingly.

[0025] The first complex programmable logic device writes the current load data into a dedicated register;

[0026] The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, so as to realize PCIe bandwidth allocation.

[0027] In another aspect, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0028] The current sensing operational amplifier module detects and amplifies the current load data on both sides of the resistor, and feeds back the amplified current load data to the first complex programmable logic device in real time through the analog-to-digital conversion module. The current sensing operational amplifier module, the resistor, and the analog-to-digital conversion module are configured accordingly.

[0029] The first complex programmable logic device writes the current load data into a dedicated register;

[0030] The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, so as to realize PCIe bandwidth allocation.

[0031] In the aforementioned PCIe bandwidth allocation system and method, the system includes a motherboard and a daughterboard; the signal input terminal of the motherboard is connected to the signal output terminal of the daughterboard; the daughterboard includes a first complex programmable logic device and an in-situ signal detection unit connected in series, wherein there is at least one in-situ signal detection unit; the in-situ signal detection unit includes a non-standard card slot and a resistor connected in series, and a current detection operational amplifier module connected in parallel across the resistor. Without altering the original circuit structure of the motherboard, the system determines whether a non-standard card is inserted into the non-standard card slot by monitoring the current load of the non-standard card slot, and performs bandwidth allocation based on the non-standard card. Attached Figure Description

[0032] Figure 1 This is a block diagram of a PCIe bandwidth allocation system in one embodiment;

[0033] Figure 2 This is a block diagram of a PCIe bandwidth allocation system in one embodiment;

[0034] Figure 3 This is a schematic diagram of a PCIe bandwidth allocation method in one embodiment;

[0035] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] This application provides a PCIe bandwidth allocation system, such as Figure 1 As shown, the system is used to implement bandwidth allocation for non-standard boards. The system includes a motherboard and a daughterboard. The signal input terminal of the motherboard is connected to the signal output terminal of the daughterboard. The daughterboard includes a first complex programmable logic device and an in-situ signal detection unit connected in series, wherein there is at least one in-situ signal detection unit. The in-situ signal detection unit includes a non-standard board slot and a resistor connected in series, and a current detection operational amplifier module connected in parallel across the resistor.

[0038] In one embodiment, such as Figure 2 As shown, the first complex programmable logic device includes an analog-to-digital converter module, and the analog-to-digital converter module is configured in a one-to-one correspondence with the in-situ signal detection unit; the in-situ signal detection unit is connected in series to the signal input terminal of the analog-to-digital converter module.

[0039] In one embodiment, such as Figure 2 As shown, the first complex programmable logic device has a dedicated register; the signal output terminal of the analog-to-digital converter module is communicatively connected to the signal input terminal of the dedicated register.

[0040] In one embodiment, the motherboard includes: a second complex programmable logic device (CPL), a southbridge chip, and a central management controller (CMD); the signal output terminal of the southbridge chip is communicatively connected to the signal input terminal of the CMD; the signal input terminal of the southbridge chip (PCH) is communicatively connected to the signal output terminal of the second CPL; and the signal input terminal of the second CPL is communicatively connected to the signal output terminal of the first CPL.

[0041] In one embodiment, the second complex programmable logic device is provided with a technology-enhanced serial peripheral interface (ESPI); the southbridge chip communicates with the second complex programmable logic device through the technology-enhanced serial peripheral interface (ESPI interface).

[0042] In one embodiment, the daughterboard is provided with a standard board mounting module for mounting standard boards; the second complex programmable logic device is provided with an I2C arbitration communication unit; the signal input terminal of the I2C arbitration communication unit is respectively communicatively connected to the signal output terminal of the standard board mounting module and the signal output terminal of the first complex programmable logic device, and the signal output terminal of the I2C arbitration communication unit is communicatively connected to the southbridge chip via an enhanced serial peripheral interface. Figure 2 As shown, the I2C arbitration communication unit includes an I2C arbitration module and an I2C Master module. The standard board connection module can be a PCA9555 module.

[0043] In one embodiment, the motherboard is provided with a central management controller, which is communicatively connected to the second complex programmable logic device to detect the operating environment of the motherboard and daughterboard, such as temperature.

[0044] The modules in the aforementioned PCIe bandwidth allocation system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or they can be stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0045] The system includes a motherboard and a daughterboard; the signal input terminal of the motherboard is connected to the signal output terminal of the daughterboard; the daughterboard includes a first complex programmable logic device and an in-situ signal detection unit connected in series, wherein there is at least one in-situ signal detection unit; the in-situ signal detection unit includes a non-standard board slot and a resistor connected in series, and a current detection operational amplifier module connected in parallel across the resistor. Without altering the original circuit structure of the motherboard, the system determines whether a non-standard board is inserted into the non-standard board slot by monitoring the current load of the non-standard board slot, and performs bandwidth allocation based on the non-standard board.

[0046] In one embodiment, such as Figure 3 As shown, a PCIe bandwidth allocation method is provided, including the following steps:

[0047] The current sensing operational amplifier module detects the current load on both sides of the resistor and feeds back the current load data to the first complex programmable logic device in real time through the analog-to-digital conversion module. The current sensing operational amplifier module, the resistor, and the analog-to-digital conversion module are configured accordingly.

[0048] The first complex programmable logic device writes the current load data into a dedicated register;

[0049] The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, so as to realize PCIe bandwidth allocation.

[0050] In one embodiment, the motherboard and the daughterboard are electrically connected, that is, the daughterboard is externally connected to the motherboard, and the power supply for the daughterboard is a stay power supply. When the motherboard is powered on, the daughterboard will also be powered on.

[0051] In one embodiment, the first complex programmable logic device (CPLD) obtains the status of the non-standard board slot based on the current load data, including: if the current load data shows that the current load on both sides of the resistor is not 0, then it is determined that the non-standard board slot is occupied; if the current load data shows that the current load on both sides of the resistor is 0, then it is determined that the non-standard board slot is not occupied. Based on the occupancy status of the non-standard board slot, the first CPLD determines whether any non-standard boards are plugged into the non-standard board slot, i.e., it determines how many non-standard boards need bandwidth allocation. Specifically, for an X16 PCIe daughterboard, if the number of non-standard card slots is 8, it means that the daughterboard supports a maximum of 8 non-standard cards. If current load is detected on both sides of the resistor in each non-standard card slot, the bandwidth allocation requested is 8X2. If current load is detected on both sides of the resistor in non-standard card slots 1, 3, 5, and 7, the bandwidth allocation requested is 4X4. If current load is detected on both sides of the resistor in non-standard card slots 1 and 5, the bandwidth allocation requested is 2X8. If current load is detected on both sides of the resistor in non-standard card slot 1, the bandwidth allocation requested is X16.

[0052] In one embodiment, the first complex programmable logic device (CPL) obtains the status of the non-standard board's insertion slot based on the current load data. This includes: an analog-to-digital conversion module, corresponding one-to-one with the in-situ detection unit, performing analog-to-digital conversion on the current load data amplified by the current detection operational amplifier module; the first CPL storing the current load data after analog-to-digital conversion into a dedicated register for access by the motherboard. The motherboard reads the current load data stored in the dedicated register via the I2C bus and transmits the current load data to the southbridge chip via the enhanced serial peripheral interface (ESI). The southbridge chip allocates bandwidth to the non-standard board based on the current load data.

[0053] In one embodiment, if a non-standard board is inserted into the non-standard board slot and a standard board is attached to the standard board mounting module, the I2C arbitration communication unit obtains the number of the non-standard board or accesses the standard board according to the preset arbitration communication rules.

[0054] Specifically, the I2C arbitration communication unit includes an I2C arbitration module and an I2C Master module. The second complex programmable logic device (CPLD) accesses the standard board connection module to allocate bandwidth to the standard boards connected to it. The second CPLD also accesses current load data in a dedicated register to allocate bandwidth to non-standard boards. The I2C arbitration communication module is used to arbitrate the order in which the second CPLD accesses the dedicated register or the standard board connection module; that is, the second CPLD cannot access either the dedicated register or the standard board connection module simultaneously. It should be understood that this application does not limit the arbitration communication rules; that is, those skilled in the art can generate different arbitration communication rules according to actual application scenarios.

[0055] In one embodiment, the second complex programmable logic device reads the dedicated register to obtain the status of the non-standard board slots in order to realize PCIe bandwidth allocation. This includes: the second complex programmable logic device obtaining the number of non-standard boards in an occupied state and sending the number of non-standard boards to the southbridge chip; the southbridge chip generating bandwidth allocation information based on the number of non-standard boards and sending it to the central management controller; and the central management controller realizing PCIe bandwidth allocation based on the bandwidth allocation information.

[0056] The method includes: a current-sensing operational amplifier module detecting the current load across a resistor and feeding the current load data back to a first complex programmable logic device (CPL) in real time via an analog-to-digital converter (ADC). The current-sensing operational amplifier module, resistor, and ADC are configured accordingly. The first CPL writes the current load data into a dedicated register. A second CPL reads the current load data from the dedicated register to obtain the status of the non-standard board slot, thereby achieving PCIe bandwidth allocation. This method monitors the current load of the non-standard board slot to determine whether a non-standard board is connected to it. Based on the presence of the non-standard board, bandwidth allocation is achieved. Furthermore, the PCIe bandwidth allocation method described in this application can also be applied to bandwidth allocation for standard boards, offering advantages such as high flexibility, simple processing, speed, and high efficiency.

[0057] It should be understood that, although Figure 4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0058] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements a PCIe bandwidth allocation method. The display screen can be a liquid crystal display (LCD) or an e-ink display. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0059] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0060] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to perform the following steps:

[0061] The current sensing operational amplifier module detects and amplifies the current load data on both sides of the resistor, and feeds back the amplified current load data to the first complex programmable logic device in real time through the analog-to-digital conversion module. The current sensing operational amplifier module, the resistor, and the analog-to-digital conversion module are configured accordingly.

[0062] The first complex programmable logic device writes the current load data into a dedicated register;

[0063] The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, so as to realize PCIe bandwidth allocation.

[0064] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0065] When the current load data shows that the current load on both sides of the resistor is not 0, it is determined that the non-standard board slot is occupied.

[0066] If the current load data shows that the current load on both sides of the resistor is 0, then it is determined that the non-standard board slot is not occupied.

[0067] In one embodiment, when the processor executes the computer program, it further performs the following steps: the second complex programmable logic device obtains the number of non-standard boards in an occupied state and sends the number of non-standard boards to the southbridge chip; the southbridge chip generates bandwidth allocation information based on the number of non-standard boards and sends it to the central management controller; the central management controller implements PCIe bandwidth allocation based on the bandwidth allocation information.

[0068] In one embodiment, when the processor executes the computer program, it further performs the following steps: if a non-standard board is inserted into the non-standard board slot and a standard board is attached to the standard board mounting module, then the I2C arbitration communication unit accesses the dedicated register or the standard board mounting module according to the preset arbitration communication rules.

[0069] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0070] The current sensing operational amplifier module detects and amplifies the current load data on both sides of the resistor, and feeds back the amplified current load data to the first complex programmable logic device in real time through the analog-to-digital converter module. The current sensing operational amplifier module, the resistor, and the analog-to-digital converter module are configured accordingly. The first complex programmable logic device writes the current load data into a dedicated register. The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, so as to realize PCIe bandwidth allocation.

[0071] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0072] The second complex programmable logic device obtains the number of non-standard boards in an occupied state and sends the number of non-standard boards to the southbridge chip; the southbridge chip generates bandwidth allocation information based on the number of non-standard boards and sends it to the central management controller; the central management controller implements PCIe bandwidth allocation based on the bandwidth allocation information.

[0073] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0074] If the current load data shows that the current load on both sides of the resistor is not 0, then the non-standard board slot is determined to be occupied; if the current load data shows that the current load on both sides of the resistor is 0, then the non-standard board slot is determined to be unoccupied.

[0075] In one embodiment, when the computer program is executed by a processor, it further performs the following steps:

[0076] If a non-standard board is inserted into the non-standard board slot and a standard board is attached to the standard board mounting module, the I2C arbitration communication unit accesses the dedicated register or the standard board mounting module according to the preset arbitration communication rules.

[0077] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A PCIe bandwidth allocation method, characterized in that, The method is applied to a PCIe bandwidth allocation system for implementing bandwidth allocation for non-standard boards. The system includes a motherboard and a daughterboard; the motherboard includes a second complex programmable logic device; the signal input terminal of the motherboard is connected to the signal output terminal of the daughterboard. The sub-board includes: a first complex programmable logic device and an in-situ signal detection unit connected in series, wherein the in-situ signal detection unit is at least one; The in-situ signal detection unit includes: a non-standard board slot and a resistor connected in series, and a current detection operational amplifier module connected in parallel across the resistor; the method includes: The current sensing operational amplifier module detects and amplifies the current load data on both sides of the resistor, and feeds back the amplified current load data to the first complex programmable logic device in real time through the analog-to-digital conversion module. The current sensing operational amplifier module, the resistor, and the analog-to-digital conversion module are configured accordingly. The first complex programmable logic device writes the current load data into a dedicated register; The second complex programmable logic device reads the current load data in the dedicated register to obtain the status of the non-standard board slot, thereby realizing PCIe bandwidth allocation, including: When the current load data shows that the current load on both sides of the resistor is not 0, it is determined that the non-standard board slot is occupied. If the current load data shows that the current load on both sides of the resistor is 0, then it is determined that the non-standard board slot is not occupied. The first complex programmable logic device determines whether there are any non-standard boards plugged into the non-standard board slots based on the occupancy status of the non-standard board slots, so as to determine the number of non-standard boards that need to be allocated bandwidth. The second complex programmable logic device obtains the number of non-standard boards that need bandwidth allocation and sends the number of non-standard boards that need bandwidth allocation to the southbridge chip; The southbridge chip generates bandwidth allocation information based on the number of non-standard boards that require bandwidth allocation, and sends it to the central management controller. The central management controller allocates PCIe bandwidth based on the bandwidth allocation information.

2. The PCIe bandwidth allocation method according to claim 1, characterized in that, If a non-standard board is inserted into the non-standard board slot and a standard board is attached to the standard board mounting module, the I2C arbitration communication unit accesses the dedicated register or the standard board mounting module according to the preset arbitration communication rules.

3. The PCIe bandwidth allocation method according to claim 1, characterized in that, The first complex programmable logic device is provided with an analog-to-digital conversion module, and the analog-to-digital conversion module is provided in a one-to-one correspondence with the in-situ signal detection unit; The in-situ signal detection unit is connected in series to the signal input terminal of the analog-to-digital conversion module.

4. The PCIe bandwidth allocation method according to claim 3, characterized in that, The first complex programmable logic device has a dedicated register; The signal output terminal of the analog-to-digital converter module is communicatively connected to the signal input terminal of the dedicated register.

5. The PCIe bandwidth allocation method according to claim 1, characterized in that, The motherboard also includes: a southbridge chip and a central management controller; The signal output terminal of the southbridge chip is communicatively connected to the signal input terminal of the central management controller. The signal input terminal of the southbridge chip is communicatively connected to the signal output terminal of the second complex programmable logic device. The signal input terminal of the second complex programmable logic device is communicatively connected to the signal output terminal of the first complex programmable logic device.

6. The PCIe bandwidth allocation method according to claim 5, characterized in that, The second complex programmable logic device is provided with a technology-oriented enhanced serial peripheral interface; The southbridge chip communicates with the second complex programmable logic device via the enhanced serial peripheral interface through the aforementioned technology.

7. The PCIe bandwidth allocation method according to claim 6, characterized in that, The sub-board is equipped with a standard board mounting module for mounting standard boards; The second complex programmable logic device is equipped with an I2C arbitration communication unit; The signal input terminal of the I2C arbitration communication unit is respectively connected to the signal output terminal of the standard board mounting module and the signal output terminal of the first complex programmable logic device. The signal output terminal of the I2C arbitration communication unit is connected to the southbridge chip via the enhanced serial peripheral interface.

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