Storage system

Abstract

An embodiment of the present application provides a storage system capable of achieving miniaturization. A storage system of an embodiment is provided with a circuit board, a connector, a first storage system, and a second storage system. The connector is mounted to the circuit board and includes a first slot having a first terminal group in which a plurality of terminals are arranged in a first direction, and a second slot having a second terminal group in which a plurality of terminals are arranged in the first direction, apart from the first slot in a second direction intersecting the first direction. The order of arrangement of the terminals in the first direction of the first terminal group is opposite to the order of arrangement of the terminals in the first direction of the second terminal group. The first storage system is inserted into the first slot and connected to the first terminal group. The second storage system is inserted into the second slot and connected to the second terminal group.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-47259 (filed on March 22, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to storage systems. Background Technology

[0003] A storage system is known, comprising a circuit board, a connector mounted on the circuit board, and a storage module mounted on the connector. Summary of the Invention

[0004] One embodiment of the present invention aims to solve the problem of providing a storage system capable of miniaturization.

[0005] One embodiment of the storage system includes a circuit board, a connector, a first storage system, and a second storage system. The connector is mounted on the circuit board and includes a first slot having a first terminal group with a plurality of terminals arranged in a first direction, and a second slot having a second terminal group with a plurality of terminals arranged in the first direction, extending away from the first slot in a second direction intersecting the first direction. The order of the terminals in the first terminal group in the first direction is reversed compared to the order of the terminals in the second terminal group in the first direction. The first storage system is inserted into the first slot and connected to the first terminal group, and includes a first substrate and a first semiconductor storage component mounted on the first substrate. The second storage system is inserted into the second slot and connected to the second terminal group, and includes a second substrate and a second semiconductor storage component mounted on the second substrate. Attached Figure Description

[0006] Figure 1 This is a perspective view showing the overall structure of the storage system according to the implementation method.

[0007] Figure 2 This is a block diagram illustrating a portion of the functional structure of the storage system in an implementation method.

[0008] Figure 3 This is a diagram illustrating the implementation of an SSD module.

[0009] Figure 4 This is a cross-sectional view showing the storage system of the implementation method.

[0010] Figure 5 yes Figure 4 The connector shown is a cross-sectional view along line F5-F5.

[0011] Figure 6This is a diagram showing the terminal arrangement of the four terminal portions in the embodiment.

[0012] Figure 7 This is a cross-sectional view showing the connector and circuit board of the embodiment.

[0013] Figure 8 This is a top view showing the connector and circuit board of the embodiment.

[0014] Figure 9 This diagram illustrates the lane reverse function of the implementation method.

[0015] Figure 10 This is a cross-sectional view of the connector and circuit board of the first modified embodiment.

[0016] Figure 11 This is a cross-sectional view of the storage system of the second variation of the embodiment.

[0017] Label Explanation

[0018] 1. Storage systems 1A and 1B; 16 Circuit board; 20 and 20A Connectors; 21 Connector housing; 22A First slot; 22B Second slot; 30A First SSD module (first storage system); 31A First board; 32A First storage controller; 33A First semiconductor storage component; 30B Second SSD module (second storage system); 31B Second board; 32B Second storage controller; 33B Second semiconductor storage component; 91 First conductive part; 92 Second conductive part; 93 Third conductive part; 94 Fourth conductive part; S1 First surface; S2 Second surface; S3 Third surface; S4 Fourth surface; TG1 First terminal group; TG2 Second terminal group; TG3 Third terminal group; TG4 Fourth terminal group. Detailed Implementation

[0019] The storage system of the embodiment will now be described with reference to the accompanying drawings. In the following description, structures having the same or similar functions will be assigned the same reference numerals. Furthermore, repeated descriptions of those structures will sometimes be omitted. "Parallel," "orthogonal," or "same" may also include cases of "generally parallel," "generally orthogonal," or "generally the same," respectively. "Connection" is not limited to mechanical connections and may also include electrical connections. That is, "connection" is not limited to direct connection to an object, and may also include connections to an object with other elements sandwiched between them.

[0020] (Implementation Method)

[0021] <1. Overall Structure of the Storage System>

[0022] Figure 1This is a perspective view showing the overall structure of the storage system 1 according to the embodiment. The storage system 1 is, for example, an information processing device (or electronic device) such as a notebook computer. However, the storage system 1 is not limited to the above example, and various information processing devices such as portable personal computers, server devices, mobile information terminal devices, and vehicle-mounted devices are also suitable.

[0023] The storage system 1 includes, for example, a main unit 2 and a display unit 3 that can be opened and closed relative to the main unit 2. The main unit 2 includes an input device 2a such as a keyboard. The display unit 3 includes a display device 3a capable of displaying images or videos.

[0024] In this embodiment, the main unit 2 includes a notification device 13. The notification device 13 notifies an external source (e.g., a user) that the SSD (Solid State Drive) module 30 is operational when it is, as described later. The notification device 13 includes, for example, an LED (Light Emitting Diode) 13a that is visually identifiable from the outside of the main unit 2, and control circuitry that controls the illumination of the LED 13a. The notification device 13 notifies the user, for example, that the SSD module 30 is operational by causing the LED 13a to flash.

[0025] Figure 2 This is a block diagram illustrating a portion of the functional structure of storage system 1. Storage system 1 includes, for example, a host controller 11, host memory 12, a notification device 13, a host bridge 14, a power supply circuit 15, a connector 20, and multiple SSD modules 30. The multiple SSD modules 30 include a first SSD module 30A and a second SSD module 30B. In this embodiment, an example of a host device 10 comprising the host controller 11, host memory 12, notification device 13, host bridge 14, and power supply circuit 15 is provided. The connector 20 may also be provided as part of the host device 10.

[0026] The host controller 11 is implemented by executing programs (software) through a hardware processor such as a CPU (Central Processing Unit) mounted on the storage system 1. However, all or part of the functions of the host controller 11 can be implemented either through hardware (circuit section; including circuitry) such as ASIC (Application Specific Integrated Circuit), PLD (Programmable Logic Device), or FPGA (Field Programmable Gate Array), or through the cooperation of software and hardware.

[0027] The host controller 11 controls the entire storage system 1. For example, the host controller 11 performs writing, reading, or erasing of data to the SSD module 30. In this embodiment, the host controller 11 transmits and receives data with the SSD module 30 via the main bridge 14 and the connector 20.

[0028] The host memory 12 is composed of DRAM (Dynamic Random Access Memory) or similar components disposed in the storage system 1. The host memory 12 serves as a data cache, for example, temporarily storing data transferred between the host controller 11 and the SSD module 30. The host memory 12 is connected to the host controller 11 via the main bridge 14. However, the host memory 12 may also be directly connected to the host controller 11.

[0029] The main bridge 14 is positioned between the host controller 11 and the host memory 12 and connector 20. The main bridge 14 includes a host interface circuit (host I / F) 14f. The host I / F 14f is connected to the SSD module 30 via wiring on the circuit board 16 (described later) and connector 20. The host I / F 14f sends and receives data, commands, and addresses between the host controller 11 and the SSD module 30. The host I / F 14f conforms to communication interface standards such as PCIe (PCI Express), NVMe (NVM Express), SATA (Serial Advanced Technology Attachment), or SAS (Serial Attached SCSI). The main bridge 14 is an example of a "bridge circuit".

[0030] The power supply circuit 15 is disposed on the circuit board 16 described later and is connected to the connector 20. The power supply circuit 15 supplies power to the SSD module 30 via the connector 20.

[0031] Connector 20 is disposed between the main bridge 14 and the power supply circuit 15 and the SSD module 30. Connector 20 allows for the removable mounting of the SSD module 30, connects the main bridge 14 to the SSD module 30, and connects the power supply circuit 15 to the SSD module 30. Details regarding connector 20 will be described later.

[0032] The first SSD module 30A and the second SSD module 30B are storage devices that store data received from the host device 10 in a non-volatile manner. The first SSD module 30A is an example of a "first storage system". The second SSD module 30B is an example of a "second storage system". In this embodiment, without distinguishing between the first SSD module 30A and the second SSD module 30B, they are referred to as "SSD module 30".

[0033] <2. Structure of SSD Module>

[0034] Next, the structure of the SSD module 30 will be explained.

[0035] Figure 3 This is a diagram representing SSD module 30 (e.g., the first SSD module 30A). Figure 3 (a) is a diagram obtained from observing the SSD module 30 (e.g., the first SSD module 30A) from the surface. Figure 3 (b) in the diagram is a view of the SSD module 30 (e.g., the first SSD module 30A) from the rear. That is, Figure 3 (b) in the middle is to Figure 3 The diagram in (a) shows the SSD module 30 flipped over. The first SSD module 30A has a first substrate 31A, a first memory controller 32A, and one or more first semiconductor memory components 33A.

[0036] The first substrate 31A is a circuit board or printed wiring board having an insulator such as glass epoxy resin and wiring patterns disposed on the surface and inner layers of the insulator. The first substrate 31A has a first surface S1 and a second surface S2 located on the side opposite to the first surface S1. In this embodiment, a first memory controller 32A and a plurality of first semiconductor memory components 33A are mounted on the first surface S1. On the other hand, the memory controller and semiconductor memory components are not mounted on the second surface S2.

[0037] The first substrate 31A has a first end 30e1 mounted on the connector 20 and a second end 30e2 located on the opposite side of the first end 30e1. The first end 30e1 has a terminal portion 34 including a plurality of terminals 35. The plurality of terminals 35 are disposed on the surfaces of the first substrate 31A (i.e., the first surface S1 and the second surface S2) and exposed on the surfaces of the first substrate 31A. The plurality of terminals 35 includes a plurality of terminals 35a disposed on the first surface S1 of the first substrate 31A and a plurality of terminals 35b disposed on the second surface S2 of the first substrate 31A. Each of the plurality of terminals 35 has an elongated flat plate shape. The terminal portion 34 conforms to the same communication interface standard as the host I / F14f. The terminal portion 34 conforms to, for example, the M.2 standard. A fixing member 153 (see below) is provided at the second end 30e2. Figure 4 The recess 36 is fixed.

[0038] A first memory controller 32A is disposed between a first end 30e1 of a first substrate 31A and a plurality of first semiconductor memory components 33A. The first memory controller 32A has a host connection interface circuit (host connection I / F) 32f. The host connection I / F 32f connects to the host I / F 14f of the main bridge 14 (see reference 14) via a terminal portion 34 of the first substrate 31A and a connector 20. Figure 2 The host connection I / F32f conforms to the same communication interface standard as the host I / F14f of the main bridge 14.

[0039] The first memory controller 32A is connected to a plurality of first semiconductor memory devices 33A via wiring provided on the first substrate 31A. The first memory controller 32A controls the plurality of first semiconductor memory devices 33A. For example, the first memory controller 32A performs writing, reading, and erasing of data on the plurality of first semiconductor memory devices 33A based on commands received from the host device 10.

[0040] The first semiconductor storage device 33A is a non-volatile semiconductor storage device that stores data in a non-volatile manner, such as a NAND flash memory. However, the first semiconductor storage device 33A is not limited to the above example, and may also be an MRAM (Magnetoresistive Random Access Memory) or other types of storage devices.

[0041] The first SSD module 30A may also have a volatile memory 37A mounted on the first substrate 31A (see reference) in addition to the structure described above. Figure 11 The volatile memory 37A is composed of DRAM or the like. The volatile memory 37A includes a data cache that temporarily stores data transferred between the host device 10 and the first semiconductor memory unit 33A.

[0042] Similarly, the second SSD module 30B includes a second substrate 31B, a second memory controller 32B, and one or more second semiconductor memory components 33B. In this embodiment, the second SSD module 30B is a memory module of the same type as the first SSD module 30A. Therefore, in the above description of the first SSD module 30A, "first SSD module 30A" can be replaced with "second SSD module 30B", "first substrate 31A" can be replaced with "second substrate 31B", "first surface S1" can be replaced with "third surface S3", "second surface S2" can be replaced with "fourth surface S4", "first memory controller 32A" can be replaced with "second memory controller 32B", "first semiconductor memory component 33A" can be replaced with "second semiconductor memory component 33B", and "volatile memory 37A" can be replaced with "volatile memory 37B".

[0043] In this embodiment, the first SSD module 30A and the second SSD module 30B are storage modules of the exact same type, including their component configurations. However, "same type of storage module" is not limited to storage modules of exactly the same type; it can refer to storage modules that conform to the same standards. For example, the number and capacity of the semiconductor storage components mounted on the first SSD module 30A and the second SSD module 30B may also be different.

[0044] <3. Structures associated with the connector>

[0045] <3.1 Overall Structure Around the Connector>

[0046] Figure 4 This is a cross-sectional view showing the storage system 1. Here, the X, Y, and Z directions are defined. The X and Y directions are directions along the first surface 16a of the circuit board 16, described later. The X direction is the direction from the connector 20 toward the SSD module 30. The Y direction is a direction intersecting the X direction (e.g., orthogonal), and is the width direction of the SSD module 30. The Z direction is the direction from the circuit board 16 toward the connector 20, and is the thickness direction of the circuit board 16. The Y direction is an example of a "first direction." The Z direction is an example of a "second direction." Hereinafter, it will sometimes be referred to as... Figure 4 The posture is used as a reference to refer to "up" or "down". However, these representations do not specify the direction of gravity.

[0047] like Figure 4As shown, the storage system 1, in addition to the host controller 11, main bridge 14, connector 20, first SSD module 30A and second SSD module 30B mentioned above, also includes a circuit board 16, heat dissipation component 40, first heat conduction component 41A and second heat conduction component 41B.

[0048] <3.2 Structure of the Circuit Board>

[0049] The circuit board 16 is, for example, the motherboard of the storage system 1. The circuit board 16 has an insulator such as glass epoxy resin and wiring patterns disposed on the inner and outer layers of the insulator. The wiring patterns include multiple wirings extending between the main bridge 14 and the connector 20, and multiple wirings extending between the power supply circuit 15 and the connector 20. The circuit board 16 has a first surface 16a and a second surface 16b located opposite to the first surface 16a. For example, the host controller 11, the main bridge 14, and the connector 20 are mounted on the first surface 16a of the circuit board 16. The first surface 16a is an example of a "mounting surface".

[0050] <3.3 Connector Structure>

[0051] Next, connector 20 will be described. Connector 20 is a multi-stage insertion connector. Connector 20 has, for example, a connector housing 21, a first slot 22A, and a second slot 22B. Connector housing 21 is formed of an insulating resin component or the like. Connector housing 21 forms the outline of connector 20, and for use... Figure 5 The connector housing 21 is supported by multiple terminals 51, 52, 53, and 54 included in the four terminal groups TG1, TG2, TG3, and TG4, which will be described later. The connector housing 21 is cuboid in shape along the Y direction.

[0052] The first slot 22A and the second slot 22B are insertion ports provided in the connector housing 21. The first slot 22A and the second slot 22B are each open in the X direction and extend in the Y direction. The first slot 22A and the second slot 22B are, for example, slots conforming to the M.2 standard. The first slot 22A and the second slot 22B are located at different heights in the Z direction and are separated from each other in the Z direction. In this embodiment, the second slot 22B is located in the Z direction between the first slot 22A and the circuit board 16. The first SSD module 30A is inserted into the first slot 22A in a removable manner. The second SSD module 30B is inserted into the second slot 22B in a removable manner.

[0053] Figure 5 yes Figure 4 The connector 20 shown is a cross-sectional view along line F5-F5.

[0054] The first slot 22A has a first terminal group TG1 and a third terminal group TG3. The first terminal group TG1 is located on the lower side (second surface S2 side) of the first substrate 31A of the first SSD module 30A inserted into the first slot 22A. In other words, the first terminal group TG1 is located between the third terminal group TG3 and the second slot 22B in the Z direction. The first terminal group TG1 has a plurality of terminals 51 arranged in the Y direction. The plurality of terminals 51 contact the terminal portion 34 of the first substrate 31A of the first SSD module 30A from below (second surface S2 side) and are connected to the plurality of terminals 35b included in the terminal portion 34.

[0055] The third terminal group TG3 is located on the upper side (first surface S1 side) of the first substrate 31A of the first SSD module 30A, which is inserted into the first slot 22A. In other words, the first substrate 31A of the first SSD module 30A is inserted between the first terminal group TG1 and the third terminal group TG3. The third terminal group TG3 has a plurality of terminals 53 arranged in the Y direction. The plurality of terminals 53 contact the terminal portion 34 of the first substrate 31A of the first SSD module 30A from above (first surface S1 side) and are connected to the plurality of terminals 35a included in the terminal portion 34.

[0056] On the other hand, the second slot 22B has a second terminal group TG2 and a fourth terminal group TG4. The second terminal group TG2 is located on the lower side (fourth surface S4 side) of the second substrate 31B of the second SSD module 30B inserted into the second slot 22B. In other words, the second terminal group TG2 is located between the fourth terminal group TG4 and the first slot 22A in the Z direction. The second terminal group TG2 has a plurality of terminals 52 arranged in the Y direction. The plurality of terminals 52 contact the terminal portion 34 of the second substrate 31B of the second SSD module 30B from below (fourth surface S4 side) and connect with the plurality of terminals 35b included in the terminal portion 34. This will be described in detail later.

[0057] The fourth terminal group TG4 is located on the upper side (third surface S3 side) of the second substrate 31B of the second SSD module 30B, which is inserted into the second slot 22B. In other words, the second substrate 31B of the second SSD module 30B is inserted between the second terminal group TG2 and the fourth terminal group TG4. The fourth terminal group TG4 has a plurality of terminals 54 arranged in the Y direction. The plurality of terminals 54 contact the terminal portion 34 of the second substrate 31B of the second SSD module 30B from above (third surface S3 side) and connect with the plurality of terminals 35a included in the terminal portion 34. This will be described in detail later.

[0058] In this embodiment, the second slot 22B has a terminal arrangement (or signal arrangement) that is reversed (rotated) relative to the first slot 22A. "Terminal arrangement" means the arrangement (i.e., the order) of multiple functions (power, ground, various signals) assigned to multiple terminals. Furthermore, the same signal is assigned to the first terminal group TG1 and the second terminal group TG2. Further, the same signal is assigned to the third terminal group TG3 and the fourth terminal group TG4.

[0059] Specifically, the terminal arrangement order in the Y direction of the first terminal group TG1 is the reverse of the terminal arrangement order in the Y direction of the second terminal group TG2. Figure 5 In the example shown, multiple terminals 51 of the first terminal group TG1 are assigned so that from Figure 5 Starting from the right side, the terminal numbers (pin numbers) are P2, P4, P6, ..., PM (M is any even number). On the other hand, the multiple terminals 52 of the second terminal group TG2 are assigned so that... Figure 5 Starting from the left, the terminal numbers (pin numbers) are P2, P4, P6, ..., PM. Furthermore, in terminal group TG1 (first terminal group) and terminal group TG2 (second terminal group), terminals with the same terminal number (same pin number) are assigned the same function (e.g., the same signal).

[0060] Similarly, the order of the terminals in the Y direction of the third terminal group TG3 is the reverse of the order of the terminals in the Y direction of the fourth terminal group TG4. For example, in Figure 5 In the example shown, multiple terminals 53 of the third terminal group TG3 are assigned to each other so that from Figure 5 Starting from the right side, the terminal numbers (pin numbers) are P1, P3, P5, ..., PN (N is any odd number). On the other hand, the multiple terminals 54 of the fourth terminal group TG4 are assigned so that... Figure 5 Starting from the left, the terminal numbers (pin numbers) are P1, P3, P5, ..., PN. Furthermore, in the third terminal group TG3 and the fourth terminal group TG4, terminals with the same terminal number (same pin number) are assigned the same function (e.g., the same signal).

[0061] Figure 6 This diagram illustrates the terminal arrangement of four terminal groups TG1, TG2, TG3, and TG4. Here, terminal group TG1 has a first end E1 in the Y direction and a second end E2 located opposite to the first end E1. "End" refers, for example, to the area in terminal group TG1 where one (or two) terminals 51 are located, starting from one end in the Y direction. The same definition applies to terminal groups TG2, TG3, and TG4.

[0062] [Terminal Group 1]

[0063] The first terminal group TG1 includes, for example, a power supply terminal 61A, a reset signal terminal 62A, bus signal terminals 63A and 64A, PLP (Power Loss Protection) signal terminals 65A and 66A, and a status signal terminal 67A. The power supply terminal 61A, reset signal terminal 62A, bus signal terminals 63A and 64A, PLP signal terminals 65A and 66A, and status signal terminal 67A are each an example of a "first terminal".

[0064] Power terminals 61A are terminals that supply power to the first SSD module 30A. Power terminals 61A are respectively disposed at the first end E1 and the second end E2 of the first terminal group TG1. In this embodiment, starting from one end E1 of the first terminal group TG1, two terminals 51 are power terminals 61A. Further, starting from one end E2 of the second terminal group TG1, three terminals 51 are power terminals 61A.

[0065] The reset signal terminal 62A is a terminal that outputs a reset signal to reset the first SSD module 30A. The reset signal is, for example, a pre-reset signal sent from the host controller 11 when the host controller 11 first recognizes the first SSD module 30A. In this embodiment, the reset signal for the first SSD module 30A is the same as the reset signal for the second SSD module 30B. The reset signal terminal 62A is located in the Y direction between the second end E2 of the first terminal group TG1 and the central portion C of the first terminal group TG1. Furthermore, the reset signal terminal 62A is located in the Y direction closer to the central portion C of the first terminal group TG1 than closer to the second end E2 of the first terminal group TG1.

[0066] Bus signal terminals 63A and 64A include a bus data terminal 63A and a bus clock terminal 64A. Bus data terminal 63A is a terminal that carries a signal accompanying it, capable of determining the address information of either the first SSD module 30A or the second SSD module 30B. The "address information" referred to here can be either address information indicating the destination of the signal transmission or address information indicating the source of the signal transmission. For example, a determination command accompanying the address information of the transmission destination, targeting either the first SSD module 30A or the second SSD module 30B, flows through bus data terminal 63A. This determination command is different from a request to write, read, or erase data from the SSD module 30; for example, it might be a command requesting temperature information from the SSD module 30. Furthermore, a data signal accompanying the address information of the source SSD module 30 (e.g., a signal indicating temperature information of the SSD module 30) flows through bus data terminal 63A as a response to the aforementioned determination command. Bus clock terminal 64A is a terminal for reading the clock signal used to read the data signal flowing in bus data terminal 63A. Bus signal terminals 63A and 64A are, for example, terminals used as the SM bus (System Management Bus) in the PCIe standard. Bus signal terminals 63A and 64A are located in the Y direction between the second end E2 of the first terminal group TG1 and the center C of the first terminal group TG1. Furthermore, bus signal terminals 63A and 64A are located in the Y direction closer to the center C of the first terminal group TG1 than to the second end E2 of the first terminal group TG1.

[0067] PLP signal terminals 65A and 66A include the first PLP signal terminal 65A and the second PLP signal terminal 66A.

[0068] The first PLP signal terminal 65A is a terminal that outputs a predetermined signal (hereinafter referred to as the "first PLP signal") from the host controller 11 to the first SSD module 30A when the power supply to the first SSD module 30A is cut off. For example, when the power supply to the first SSD module 30A is cut off, the host controller 11 uses the first PLP signal to change the voltage that was previously maintained at a first voltage (e.g., a high level voltage) to a second voltage (e.g., a low level voltage) that is different from the first voltage. When the first PLP signal is detected, the first SSD module 30A performs, for example, a data backoff process to write data temporarily stored in the volatile memory 37A to the first semiconductor memory unit 33A.

[0069] The second PLP signal terminal 66A is a terminal that inputs a predetermined signal (hereinafter referred to as the "second PLP signal") from the first SSD module 30A to the host controller 11 when the data backoff process of the first SSD module 30A has ended normally. For example, when the first SSD module 30A starts the data backoff process, it changes the voltage that was previously maintained at a first voltage (e.g., a high-level voltage) to a second voltage (e.g., a low-level voltage) with a voltage level different from the first voltage. Furthermore, when the data backoff process has ended normally, the first SSD module 30A, as the second PLP signal, restores the voltage that was previously maintained at the second voltage to the first voltage. Thus, the host controller 11 detects that the data backoff process has ended normally. Upon detecting that the data backoff process has ended normally, the host controller 11 cuts off the power supply to the first SSD module 30A.

[0070] The first PLP signal terminal 65A and the second PLP signal terminal 66A are located in the Y direction between the first end E1 of the first terminal group TG1 and the central portion C of the first terminal group TG1. The first PLP signal terminal 65A is located in the Y direction closer to the first end E1 of the first terminal group TG1 than to the central portion C of the first terminal group TG1. The second PLP signal terminal 66A is located in the Y direction closer to the central portion C of the first terminal group TG1 than to the first end E1 of the first terminal group TG1.

[0071] The status signal terminal 67A is a terminal from the first SSD module 30A that receives a status signal indicating that the first SSD module 30A is working (e.g., during data writing, reading, or erasing). For example, when the first SSD module 30A is working, the status signal is maintained at a first voltage (e.g., a high-level voltage) by the first SSD module 30A. On the other hand, when the first SSD module 30A is not working, the status signal is maintained at a second voltage (e.g., a low-level voltage) by the first SSD module 30A, which is different from the first voltage. When the voltage level of the status signal terminal 67A is maintained at the first voltage, the host controller 11 notifies the outside world that the SSD module 30A is working by flashing the LED 13a of the notification device 13 of the main unit 2.

[0072] [Second Terminal Group]

[0073] The second terminal group TG2, like the first terminal group TG1, includes, for example, a power supply terminal 61B, a reset signal terminal 62B, bus signal terminals 63B and 64B, PLP signal terminals 65B and 66B, and a status signal terminal 67B. The power supply terminal 61B, reset signal terminal 62B, bus signal terminals 63B and 64B, PLP signal terminals 65B and 66B, and status signal terminal 67B are each an example of a "second terminal".

[0074] Power terminal 61B is a terminal that supplies power to the second SSD module 30B. Power terminals 61B are respectively disposed at the first end E1 and the second end E2 of the second terminal group TG2. In this embodiment, starting from one end E1 of the first terminal group TG2, three terminals 52 are power terminals 61B. Further, starting from one end E2 of the second terminal group TG2, two terminals 52 are power terminals 61B.

[0075] The reset signal terminal 62B is a terminal that outputs a reset signal to reset the second SSD module 30B. The reset signal is, for example, a pre-reset signal sent from the host controller 11 when the host controller 11 first recognizes the second SSD module 30B. The reset signal terminal 62B is located in the Y direction between the first end E1 of the second terminal group TG2 and the center C of the second terminal group TG2. Furthermore, the reset signal terminal 62B is located in the Y direction closer to the center C of the second terminal group TG2 than closer to the first end E1 of the second terminal group TG2.

[0076] Bus signal terminals 63B and 64B include a bus data terminal 63B and a bus clock terminal 64B. Bus data terminal 63B is a terminal that carries a signal accompanying a signal capable of determining the address information of either the first SSD module 30A or the second SSD module 30B. For example, a determination command carrying address information of the destination SSD module 30A or the second SSD module 30B flows through bus data terminal 63B. Additionally, in response to the determination command, a data signal carrying the address information of the source SSD module 30 flows through bus data terminal 63B. Bus clock terminal 64B is a terminal that carries a clock signal used to read the data signal flowing through bus data terminal 63B. Bus signal terminals 63B and 64B are, for example, terminals used as the SM bus in the PCIe standard. Bus signal terminals 63B and 64B are located in the Y direction between the first end E1 of the second terminal group TG2 and the central portion C of the second terminal group TG2. Furthermore, the bus signal terminals 63B and 64B are located in the Y direction closer to the center C of the second terminal group TG2 than to the first end E1 of the second terminal group TG2.

[0077] PLP signal terminals 65B and 66B include the first PLP signal terminal 65B and the second PLP signal terminal 66B.

[0078] The first PLP signal terminal 65B is the terminal from the host controller 11 that outputs the first PLP signal to the second SSD module 30B when the power supply to the second SSD module 30B is cut off. The first PLP signal for the second SSD module 30B is the same as the first PLP signal for the first SSD module 30A. When the second SSD module 30B detects the first PLP signal, it performs, for example, a data backoff process to write data temporarily stored in the volatile memory 37B to the second semiconductor memory unit 33B. In this embodiment, when the power supply to both the first SSD module 30A and the second SSD module 30B is cut off, the host controller 11 outputs the first PLP signal from both the first PLP signal terminal 65A of the first terminal group TG1 and the first PLP signal terminal 65B of the second terminal group TG2.

[0079] The second PLP signal terminal 66B is the terminal that inputs the second PLP signal from the second SSD module 30B to the host controller 11 when the data backoff process of the second SSD module 30B has ended normally. The second PLP signal output from the second SSD module 30B to the host controller 11 is the same signal as the first PLP signal output from the first SSD module 30A to the host controller 11. When the host controller 11 detects that the data backoff process of the second SSD module 30B has ended normally, it cuts off the power supply to the second SSD module 30B. In this embodiment, when the voltage state of the second PLP signal terminal 66A of the first terminal group TG1 and the second PLP signal terminal 66B of the second terminal group TG2 returns from the second voltage to the first voltage, the host controller 11 considers that the data backoff process of the first SSD module 30A and the second SSD module 30B has ended normally, and cuts off the power supply to the first SSD module 30A and the second SSD module 30B.

[0080] The first PLP signal terminal 65B and the second PLP signal terminal 66B are located in the Y direction between the second end E2 and the center C of the second terminal group TG2. The first PLP signal terminal 65B is located in the Y direction closer to the second end E2 of the second terminal group TG2 than to the center C of the second terminal group TG2. The second PLP signal terminal 66B is located in the Y direction closer to the center C of the second terminal group TG2 than to the second end E2 of the second terminal group TG2.

[0081] The status signal terminal 67B is a terminal from the second SSD module 30B that receives a status signal indicating that the second SSD module 30B is working when it is operating (e.g., during data writing, reading, or erasing). For example, when the second SSD module 30B is working, the status signal is maintained at a first voltage (e.g., a high-level voltage) by the second SSD module 30B; when the second SSD module 30B is not operating, the status signal is maintained at a second voltage (e.g., a low-level voltage) that is different from the first voltage. When the voltage level of the status signal terminal 67B is maintained at the first voltage, the host controller 11 notifies the outside world that the SSD module 30B is working by flashing the LED 13a of the notification device 13 of the main unit 2.

[0082] [Third Terminal Group]

[0083] Terminal group TG3 includes ground terminal 71A, first transmitting terminals 81A to fourth transmitting terminals 84A, and first receiving terminals 85A to fourth receiving terminals 88A. "Ground terminal 71A" is another example of "first terminal". First transmitting terminals 81A to fourth transmitting terminals 84A and first receiving terminals 85A to fourth receiving terminals 88A are examples of "third terminals".

[0084] Grounding terminal 71A is a terminal connected to the ground of the first substrate 31A of the first SSD module 30A. Grounding terminals 71A are respectively provided at the first end E1 and the second end E2 of the third terminal group TG3. In this embodiment, starting from one end E1 of the first end of the third terminal group TG3, two terminals 53 are grounding terminals 71A. Further, starting from one end E2 of the second end of the third terminal group TG3, three terminals 53 are grounding terminals 71A.

[0085] The first transmit terminals 81A to 84A and the first receive terminals 85A to 88A are terminals used for transmitting and receiving data between the host device 10 and the first SSD module 30A. For example, the first transmit terminals 81A to 84A are terminals where write data to be written to the first SSD module 30A flows from the host device 10 to the first SSD module 30A. On the other hand, the first receive terminals 85A to 88A are terminals where read data read from the first SSD module 30A flows from the first SSD module 30A to the host device 10. The first transmit terminals 81A to 84A and the first receive terminals 85A to 88A are, for example, terminals corresponding to PCIe standard lanes.

[0086] [4th Terminal Group]

[0087] Terminal group TG4, like terminal group TG3, includes ground terminal 71B, first transmitting terminals 81B to fourth transmitting terminals 84B, and first receiving terminals 85B to fourth receiving terminals 88B. "Ground terminal 71B" is another example of "second terminal". First transmitting terminals 81B to fourth transmitting terminals 84B and first receiving terminals 85B to fourth receiving terminals 88B are each examples of "fourth terminal".

[0088] Grounding terminal 71B is a terminal connected to the ground of the second substrate 31B of the second SSD module 30B. Grounding terminals 71B are respectively disposed at the first end E1 and the second end E2 of the fourth terminal group TG4. In this embodiment, starting from one end E1 of the first end of the fourth terminal group TG4, three terminals 54 are grounding terminals 71B. Further, starting from one end E2 of the second end of the fourth terminal group TG4, two terminals 54 are grounding terminals 71B.

[0089] The first transmit terminals 81B to the fourth transmit terminals 84B and the first receive terminals 85B to the fourth receive terminals 88B are terminals used for transmitting and receiving data between the host device 10 and the second SSD module 30B. For example, the first transmit terminals 81B to the fourth transmit terminals 84B are terminals from the host device 10 to the second SSD module 30B for write data to be written to it. On the other hand, the first receive terminals 85B to the fourth receive terminals 88B are terminals from the second SSD module 30B to the host device 10 for read data read from it. The first transmit terminals 81B to the fourth transmit terminals 84B and the first receive terminals 85B to the fourth receive terminals 88B are, for example, terminals corresponding to the PCIe standard lines.

[0090] Figure 7 This is a cross-sectional view showing the circuit board 16 and the connector 20. The connector 20 has multiple conductive portions 90 that connect the first terminal group TG1, the second terminal group TG2, the third terminal group TG3, and the fourth terminal group TG4 to the circuit board 16. The conductive portions 90 are integrally formed with the corresponding terminals 51, 52, 53, and 54. The conductive portions 90 extend from the terminals 51, 52, 53, and 54 toward the circuit board 16 inside the connector housing 21.

[0091] In this embodiment, the plurality of conductive portions 90 include a first conductive portion 91 connected to a first specific terminal 51S included in the first terminal group TG1 and a second conductive portion 92 connected to a second specific terminal 52S included in the second terminal group TG2. Furthermore, when viewed in the Z direction, the first conductive portion 91 and the second conductive portion 92 are electrically connected within the mounting area MA of the connector 20. The mounting area MA means the area overlapping with the connector 20 when viewed in the Z direction. "Electrically connected within the mounting area MA of the connector 20 when viewed in the Z direction" is not limited to the case where the connection is inside the connector housing 21, but may also include the case where the connection is on the surface or inner layer of the circuit board 16 included in the mounting area MA (see the first variation described later).

[0092] In this embodiment, the first conductive portion 91 and the second conductive portion 92 are joined by a connecting portion CN1 provided inside the connector housing 21 and connected to the circuit board 16. Furthermore, the first conductive portion 91 and the second conductive portion 92 are connected to the main bridge 14 or the power circuit 15 via a common wiring 100 provided on the circuit board 16 for the first specific terminal 51S and the second specific terminal 52S.

[0093] In this embodiment, as an example of a group having the above-described connection relationship between the first specific terminal 51S and the second specific terminal 52S, there is a group having a power terminal 61A of the first terminal group TG1 and a power terminal 61B of the second terminal group TG2. In this case, the first conductive part 91 connected to the power terminal 61A of the first terminal group TG1 and the second conductive part 92 connected to the power terminal 61B of the second terminal group TG2 are combined inside the connector housing 21 and connected to the circuit board 16 via a common wiring 101 (see reference). Figure 8 It is connected to the power supply circuit 15.

[0094] Furthermore, in this embodiment, as another example of the group of the first specific terminal 51S and the second specific terminal 52S, there is a group having a reset signal terminal 62A of the first terminal group TG1 and a reset signal terminal 62B of the second terminal group TG2. In this case, the first conductive part 91 connected to the reset signal terminal 62A of the first terminal group TG1 and the second conductive part 92 connected to the reset signal terminal 62B of the second terminal group TG2 are combined inside the connector housing 21 and connected to the circuit board 16 via a common wiring 102 (see reference). Figure 8 It is connected to the main bridge 14.

[0095] Furthermore, as other examples of the group of the first specific terminal 51S and the second specific terminal 52S, there is a group having a bus data terminal 63A of the first terminal group TG1 and a bus data terminal 63B of the second terminal group TG2, a group having a bus clock terminal 64A of the first terminal group TG1 and a bus clock terminal 64B of the second terminal group TG2, a group having a first PLP signal terminal 65A of the first terminal group TG1 and a first PLP signal terminal 65B of the second terminal group TG2, a group having a second PLP signal terminal 66A of the first terminal group TG1 and a second PLP signal terminal 66B of the second terminal group TG2, and a group having a status signal terminal 67A of the first terminal group TG1 and a status signal terminal 67B of the second terminal group TG2.

[0096] In this embodiment, the plurality of conductive portions 90 disposed inside the connector 20 include a third conductive portion 93 connected to a third specific terminal 53S included in the third terminal group TG3, and a fourth conductive portion 94 connected to a fourth specific terminal 54S included in the fourth terminal group TG4. In this embodiment, the third conductive portion 93 and the fourth conductive portion 94 are insulated from each other and are respectively connected to the circuit board 16. Furthermore, the third conductive portion 93 and the fourth conductive portion 94 are independently connected to the main bridge 14 via individual wirings 110 and 120 disposed on the circuit board 16 for the third specific terminal 53S and the fourth specific terminal 54S.

[0097] In this embodiment, as an example of a group having the aforementioned connection relationship between the third specific terminal 53S and the fourth specific terminal 54S, there is a group having the first transmitting terminal 81A of the third terminal group TG3 and the first transmitting terminal 81B of the second terminal group TG2. In this case, in this embodiment, the third conductive part 93 connected to the first transmitting terminal 81A of the third terminal group TG3 and the fourth conductive part 94 connected to the first transmitting terminal 81B of the fourth terminal group TG4 are respectively connected to the circuit board 16. Furthermore, the third conductive part 93 and the fourth conductive part 94 are respectively connected via individual wirings 111 and 121 (see reference). Figure 8 They are connected independently to the main bridge 14. The same applies to the second transmitting terminals 82A to the fourth transmitting terminals 84A and the first receiving terminals 85A to the fourth receiving terminals 88A of the third terminal group TG3, and the second transmitting terminals 82B to the fourth transmitting terminals 84B and the first receiving terminals 85B to the fourth receiving terminals 88B of the fourth terminal group TG4.

[0098] In this embodiment, the plurality of conductive portions 90 disposed inside the connector 20 include a fifth conductive portion 95 connected to a fifth specific terminal (e.g., ground terminal 71A) included in the third terminal group TG3 and a sixth conductive portion 96 connected to a sixth specific terminal (e.g., ground terminal 71B) included in the fourth terminal group TG4. Furthermore, when viewed in the Z direction, the fifth conductive portion 95 and the sixth conductive portion 96 are electrically connected within the mounting area MA of the connector 20. In this embodiment, the fifth conductive portion 95 and the sixth conductive portion 96 are joined by a coupling portion CN2 disposed inside the connector housing 21, and connected via a common wiring 108 (see reference 108) disposed on the circuit board 16. Figure 8 And connected to the ground of the circuit board 16.

[0099] Figure 8 This is a top view showing the circuit board 16 and the connector 20. In this embodiment, the power terminal 61A of the first end E1 of the first terminal group TG1 and the power terminal 61B of the second end E2 of the second terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 101A provided on the circuit board 16. Furthermore, the power terminals 61A and 61B of the second end E2 of the first terminal group TG1 and the first end E1 of the second terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 101B provided on the circuit board 16. Wiring 101A and 101B are connected to the power circuit 15.

[0100] Furthermore, the power terminals 61A and 61B of the first end E1 of the first terminal group TG1 and the first end E1 of the second terminal group TG2 can also be connected inside the connector housing 21 and connected to the common wiring 101A provided on the circuit board 16. Further, the power terminals 61A and 61B of the second end E2 of the first terminal group TG1 and the second end E2 of the second terminal group TG2 can also be connected inside the connector housing 21 and connected to the common wiring 101B provided on the circuit board 16. Wiring 101A and 101B are connected to the power circuit 15. In this case, terminals that are physically close to each other are connected to each other, thus simplifying the wiring layout within the connector housing 21.

[0101] Similarly, the reset signal terminal 62A of the first terminal group TG1 and the reset signal terminal 62B of the second terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 102 provided on the circuit board 16. The bus data terminal 63A of the first terminal group TG1 and the bus data terminal 63B of the second terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 103 provided on the circuit board 16. The bus clock terminal 64A of the first terminal group TG1 and the bus clock terminal 64B of the second terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 104 provided on the circuit board 16. The first PLP signal terminal 65A of the first terminal group TG1 and the first PLP signal terminal 65B of the second terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 105 provided on the circuit board 16. The second PLP signal terminal 66A of terminal group TG1 and the second PLP signal terminal 66B of terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 106 provided on the circuit board 16. The status signal terminal 67A of terminal group TG1 and the status signal terminal 67B of terminal group TG2 are connected inside the connector housing 21 and connected to the common wiring 107 provided on the circuit board 16. Wiring 102 to 107 are connected to the main bridge 14.

[0102] On the other hand, the transmitting terminals 81A-84A of the third terminal group TG3, the receiving terminals 85A-88A of the third terminal group TG3, the transmitting terminals 81B-84B of the fourth terminal group TG4, and the receiving terminals 85B-88B of the fourth terminal group TG4 are led out to the circuit board 16 in a mutually insulated state inside the connector 20, and are respectively connected one-to-one with the wiring (lines) 111-114, 115-118, 121-124, and 125-128 provided on the circuit board 16. The wiring 111-118 and 121-128 are connected to the main bridge 14.

[0103] Figure 9 This diagram illustrates the line reversal function of the host device 10. The line reversal function described below is implemented, for example, by the main bridge 14 or by the cooperation of the main bridge 14 and the host controller 11.

[0104] The main bridge 14 has terminals 131-138 and 141-148 corresponding to wiring (lines) 111-118 and 121-128. Terminals 131-134 for the first SSD module 30A are arranged in the order of first transmitting terminal 131, second transmitting terminal 132, third transmitting terminal 133, and fourth transmitting terminal 134, as physical locations within the main bridge 14. Similarly, terminals 135-138 for the first SSD module 30A are arranged in the order of first receiving terminal 135, second receiving terminal 136, third receiving terminal 137, and fourth receiving terminal 138, as physical locations within the main bridge 14. Here, the wiring (lines) 111-118 of the circuit board 16 for the first SSD module 30A are arranged in the same order as the terminals 131-138 of the main bridge 14, as physical locations within the circuit board 16. Therefore, the terminals 131-138 of the main bridge 14 and the wiring 111-118 of the circuit board 16 can be directly connected one-to-one.

[0105] On the other hand, terminals 141 to 144 of the second SSD module 30B in the main bridge 14 are arranged in the same direction as terminals 131 to 134 of the first SSD module 30A in the order of first transmitting terminal 141, second transmitting terminal 142, third transmitting terminal 143, and fourth transmitting terminal 144, as physical locations in the main bridge 14. Similarly, terminals 145 to 148 of the second SSD module 30B are arranged in the order of first receiving terminal 145, second receiving terminal 146, third receiving terminal 147, and fourth receiving terminal 148, as physical locations in the main bridge 14. However, in this embodiment, the second SSD module 30B is mounted to the connector 20 in reverse order, as described later. Therefore, the wiring (lines) 121 to 128 of the circuit board 16 for the second SSD module 30B are arranged in the opposite order to terminals 141 to 148 of the main bridge 14. Therefore, the terminals 141-148 of the main bridge 14 and the wiring 121-128 of the circuit board 16 cannot be directly connected one-to-one. In order to make the terminals 141-148 of the main bridge 14 and the wiring 121-128 of the circuit board 16 physically match, the wiring 121-128 needs to be interchanged in a cross-shaped manner within the circuit board 16.

[0106] In this embodiment, the host device 10 reverses the order of terminals 141-148 of the main bridge 14 in software using a line reversal function. As a result, the host device 10 transmits signals that were originally transmitted from the first transmitting terminal 141, the second transmitting terminal 142, the third transmitting terminal 143, and the fourth transmitting terminal 144, respectively, from the fourth transmitting terminal 144, the third transmitting terminal 143, the second transmitting terminal 142, and the first transmitting terminal 141. Furthermore, the host device 10 treats signals received by the fourth receiving terminal 148, the third receiving terminal 147, the second receiving terminal 146, and the first receiving terminal 145 as signals that were originally received by the first receiving terminal 145, the second receiving terminal 146, the third receiving terminal 147, and the fourth receiving terminal 148, respectively. Therefore, in this embodiment, it is not necessary to rearrange the order of wiring 121-128 within the circuit board 16; wiring 121-128 can be arranged using a relatively simple wiring layout.

[0107] Here, return Figure 4 The remaining structures will be explained.

[0108] In this embodiment, the first SSD module 30A and the second SSD module 30B are arranged parallel to the first surface 16a of the circuit board 16 when mounted on the connector 20. The first SSD module 30A is inserted into the first slot 22A with the first surface S1 of the first substrate 31A facing upward and the second surface S2 facing downward. Furthermore, a plurality of terminals 35b on the second surface S2 of the first substrate 31A are connected to the first terminal group TG1 of the first slot 22A, and a plurality of terminals 35a on the first surface S1 of the first substrate 31A are connected to the third terminal group TG3. On the other hand, the second SSD module 30B is mounted on the connector 20 in a reversed position relative to the first SSD module 30A (a position after rotating in opposite directions). That is, the second SSD module 30B is inserted into the second slot 22B with the third surface S3 of the second substrate 31B facing downward and the fourth surface S4 facing upward. Furthermore, multiple terminals 35b on the fourth surface S4 of the second substrate 31B are connected to the second terminal group TG2 of the second slot 22B, and multiple terminals 35a on the third surface S3 of the second substrate 31B are connected to the fourth terminal group TG4. In other words, the first SSD module 30A and the second SSD module 30B are mounted on the connector 20 with their second surfaces S2 and fourth surfaces S4, respectively, facing each other, without the storage controller 32 and semiconductor storage components 33.

[0109] Next, the fixed structure of the two SSD modules 30 will be explained.

[0110] like Figure 4As shown, a mounting boss 151 is provided on the first surface 16a of the circuit board 16. The boss 151 is located at a position corresponding to the second end 30e2 of the SSD module 30. A mating hole 151h is provided on the boss 151 for engagement with the mounting member 153, which will be described later. The second SSD module 30B is mounted on the boss 151. The boss 151 is, for example, made of metal.

[0111] A spacer 152 is provided between the first SSD module 30A and the second SSD module 30B. The spacer 152 is positioned between the first SSD module 30A and the second SSD module 30B to maintain a distance between them. The spacer 152 has a through hole 152h for a fixing component 153 to be inserted. The spacer 152 is, for example, made of metal.

[0112] The fixing member 153 has a head 153a and a shaft portion 153b. The head 153a extends from the side opposite to the pad 152 toward the first SSD module 30A. The shaft portion 153b passes through the recess 36 of the second end 30e2 of the first SSD module 30A, the through hole 152h of the pad 152, and the recess 36 of the second end 30e2 of the second SSD module 30B, and engages with the engagement hole 151h of the boss 151. Thus, the positions of the two SSD modules 30 are fixed. The fixing member 153 is, for example, made of metal.

[0113] Next, the heat dissipation mechanisms of the two SSD modules 30 will be explained.

[0114] The heat dissipation component 40 is located in the Z direction between the first SSD module 30A and the second SSD module 30B. The heat dissipation component 40 extends, for example, in the X direction within the gap between the first SSD module 30A and the second SSD module 30B. The heat dissipation component 40 can be a heat sink with multiple fins, a heat pipe connected to a heat sink, or a water-cooled heat dissipation device supplied with cooling water from a cooling water supply device.

[0115] The first heat-conducting component 41A is disposed between the first substrate 31A of the first SSD module 30A and the heat dissipation component 40, and is in contact with both the first substrate 31A and the heat dissipation component 40. The first heat-conducting component 41A is formed, for example, of a thermal interface material (TIM). The TIM is, for example, lubricating grease or an elastomer sheet.

[0116] Similarly, the second heat conduction component 41B is disposed between the second substrate 31B of the second SSD module 30B and the heat dissipation component 40, and is in contact with the second substrate 31B of the second SSD module 30B and the heat dissipation component 40. The second heat conduction component 41B is formed, for example, of a heat dissipation material (TIM).

[0117] <2. Function>

[0118] In this embodiment, such as Figure 8 As shown, power is supplied to the plurality of power terminals 61A and 61B of the connector 20 via a common wiring 101 provided on the circuit board 16. In addition, the plurality of ground terminals 71A and 71B of the connector 20 are connected to the ground of the circuit board 16 via a common wiring 108 provided on the circuit board 16.

[0119] Furthermore, a common reset signal is sent to both SSD modules 30 via a common wiring 102 provided on the circuit board 16. Additionally, a communication bus for the two SSD modules 30 is formed via common wirings 103 and 104 provided on the circuit board 16. Furthermore, signals for indicative of the start or completion of data backoff processing for the two SSD modules 30 are transmitted and received via common wirings 105 and 106 provided on the circuit board 16. Additionally, a signal for identifying whether the two SSD modules 30 are operating is received via common wiring 107 provided on the circuit board 16.

[0120] A portion of the heat generated by the two SSD modules 30 is transmitted through the wiring pattern included in the first substrate 31A or the second substrate 31B to the second end 30e2 of the first substrate 31A or the second end 30e2 of the second substrate 31B, and then transmitted to the circuit board 16 via the fixing member 153. Furthermore, another portion of the heat generated by the two SSD modules 30 is transmitted to the outside of the two SSD modules 30 through the heat dissipation member 40. Thus, heat dissipation of the two SSD modules 30 is promoted.

[0121] <4. Advantages>

[0122] Here, we consider the scenario where multiple SSD modules are laid flat (installed one by one on different connectors). In this case, a dedicated space is required corresponding to the number of SSD modules. Furthermore, if separate cooling systems are installed for each SSD module, the required space will increase accordingly.

[0123] Therefore, it is considered to use a multi-stage connector with multiple slots to overlap multiple SSD modules 30. However, when the terminals of multiple slots are arranged in the same way, the component configuration in the multiple SSD modules 30 may be biased, which may reduce performance from the perspective of heat dissipation or other aspects. For example, when multiple SSD modules are overlapped with the same vertical orientation, the first storage controller (high-heat component) mounted on the first SSD module faces the opposite side to the second SSD module. However, the second storage controller (high-heat component) mounted on the second SSD module is located in the space between the substrates of the first SSD module and the second SSD module, which may sometimes lead to a larger heat dissipation mechanism and sometimes reduce heat dissipation performance.

[0124] On the other hand, in this embodiment, the storage system 1 includes a circuit board 16, a connector 20, a first SSD module 30A, and a second SSD module 30B. The connector 20 has a first slot 22A and a second slot 22B separated in the Z direction. With this structure, firstly, multiple SSD modules 30 are arranged in an overlapping manner, thus reducing the installation area. As a result, miniaturization of the storage system 1 is possible.

[0125] Furthermore, in this embodiment, the terminal arrangement of the first terminal group TG1 of the first slot 22A and the terminal arrangement of the second terminal group TG2 of the second slot 22B are opposite in the Y direction. With this structure, it is easy to arrange the components mounted on the first SSD module 30A and the second SSD module 30B in a vertically and / or horizontally symmetrical manner. This improves temperature balance among the multiple SSD modules 30, for example. It also enables miniaturization of the heat dissipation mechanisms for the multiple SSD modules 30. This further enables miniaturization of the storage system 1.

[0126] In this embodiment, the connector 20 has a connector housing 21, a first conductive portion 91 connected to a first specific terminal 51S included in the plurality of terminals 51 of the first terminal group TG1, and a second conductive portion 92 connected to a second specific terminal 52S included in the plurality of terminals 52 of the second terminal group TG2. Viewed in the thickness direction of the circuit board 16, the first conductive portion 91 and the second conductive portion 92 are interconnected within the mounting area MA of the connector 20. With this structure, the connection structure between the connector 20 and the circuit board 16 can be simplified, and a portion of the wiring provided on the circuit board 16 can be shared. Therefore, further miniaturization of the storage system 1 is possible.

[0127] In this embodiment, the first slot 22A has a first terminal group TG1 and a third terminal group TG3. The first terminal group TG1 is located between the third terminal group TG3 and the second slot 22B. The second slot 22B has a second terminal group TG2 and a fourth terminal group TG4. The second terminal group TG2 is located between the fourth terminal group TG4 and the first slot 22A. Furthermore, the conductive portions 91 and 92 of the two specific terminals 51S and 52S included in two adjacent terminal groups TG1 and TG2 of these four terminal groups TG1, TG2, TG3, and TG4 are interconnected within the mounting area MA of the connector 20. With this structure, the connection structure between the connector 20 and the circuit board 16 can be simplified and a portion of the wiring provided on the circuit board 16 can be shared with a relatively simple structure. As a result, further miniaturization of the storage system 1 can be achieved.

[0128] <5. Variations>

[0129] Next, several variations will be described. In each variation, the structure other than that described below is the same as the embodiment described above.

[0130] <5.1 First Variation>

[0131] Figure 10 This is a cross-sectional view showing the connector 20A and circuit board 16 of the storage system 1A in the first modification. In the first modification, the plurality of conductive portions 90 include a first conductive portion 91 connected to a first specific terminal 51S included in the first terminal group TG1 and a second conductive portion 92 connected to a second specific terminal 52S included in the second terminal group TG2. Furthermore, in the mounting area MA of the connector housing 21 as seen in the thickness direction of the circuit board 16, the first conductive portion 91 and the second conductive portion 92 are joined by a bonding portion CN1 provided on the surface or inner layer of the circuit board 16 and connected to a common wiring 100. With this structure, the miniaturization of the storage system 1 can be achieved in the same way as in the above-described embodiment. The bonding portion CN2 that joins the fifth conductive portion 95 and the sixth conductive portion 96 can also be provided on the surface or inner layer of the circuit board 16 in the same way as the bonding portion CN1.

[0132] <5.2 Second Variation>

[0133] Figure 11 This is a cross-sectional view showing the storage system 1B of the second modification. In the second modification, a first storage controller 32A is mounted on the second surface S2 of the first substrate 31A of the first SSD module 30A. A volatile memory 37A and a plurality of first semiconductor storage components 33A are mounted on the first surface S1 of the first substrate 31A.

[0134] On the other hand, a second memory controller 32B is mounted on the fourth surface S4 of the second substrate 31B of the second SSD module 30B. A volatile memory 37B and a plurality of second semiconductor memory components 33B are mounted on the third surface S3 of the second substrate 31B.

[0135] Furthermore, the first SSD module 30A and the second SSD module 30B are mounted on the connector 20 with their second surface S2 and fourth surface S4 facing each other. The heat dissipation component 40 is connected to the first storage controller 32A via the first heat conduction component 41A. Further, the heat dissipation component 40 is connected to the second storage controller 32B via the second heat conduction component 41B.

[0136] With this structure, the storage system 1 can also be miniaturized in the same way as the above-described implementation.

[0137] The embodiments and modifications have been described above, but the embodiments and modifications are not limited to the examples described above. These embodiments and modifications can also be combined with each other. For example, the first slot 22A and the second slot 22B of the connector 20 can also have longer openings in the Z direction (the thickness direction of the circuit board 16). In this case, the first SSD module 30A and the second SSD module 30B are mounted on the connector 20 in a position perpendicular to the circuit board 16. In addition, the first slot 22A and the second slot 22B of the connector 20 can also be opened in the Z direction.

[0138] According to at least one embodiment described above, the storage system includes a circuit board, a connector, a first storage module, and a second storage module. The connector has a first slot and a second slot. The terminal arrangement of the first terminal group of the first slot is opposite to the terminal arrangement of the second terminal group of the second slot. With this structure, miniaturization of the storage system is possible.

[0139] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and likewise within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system comprising: Circuit board; A connector, mounted on the circuit board, includes a first slot having a first terminal group with a plurality of terminals arranged in a first direction and a second slot having a second terminal group having a plurality of terminals arranged in the first direction, which is located away from the first slot in a second direction intersecting the first direction. The first slot and the second slot have openings in the same orientation in a third direction intersecting the first and second directions. The order of the terminals in the first direction of the first terminal group is reversed compared to the order of the terminals in the first direction of the second terminal group. A first storage system, inserted into the first slot and connected to the first terminal group, includes a first substrate and a first semiconductor storage component mounted on the first substrate; and A second storage system, which is inserted into the second slot and connected to the second terminal group, includes a second substrate and a second semiconductor storage component mounted on the second substrate.

2. The storage system according to claim 1, The first substrate has a first surface on which a first memory controller for controlling the first semiconductor memory component is mounted, and a second surface located on the opposite side of the first surface. The second substrate has a third surface on which a second memory controller for controlling the second semiconductor memory component is mounted, and a fourth surface located on the opposite side of the third surface. The first storage system and the second storage system are mounted on the connector with the second surface facing the fourth surface.

3. The storage system according to claim 1, The first substrate has a first surface and a second surface located on the opposite side of the first surface, on which a first memory controller for controlling the first semiconductor memory component is mounted. The second substrate has a third surface and a fourth surface located opposite to the third surface, on which a second memory controller for controlling the second semiconductor memory component is mounted. The first storage system and the second storage system are mounted on the connector with the second surface facing the fourth surface.

4. The storage system according to any one of claims 1 to 3, The second storage system is mounted on the connector in an inverted position relative to the first storage system.

5. The storage system according to any one of claims 1 to 3, The connector has a connector housing, a first conductive portion connected to a first terminal included in the plurality of terminals of the first terminal group, and a second conductive portion connected to a second terminal included in the plurality of terminals of the second terminal group. When viewed in the thickness direction of the circuit board, the first conductive portion and the second conductive portion are connected within the mounting area of ​​the connector.

6. The storage system according to claim 5, The first conductive part and the second conductive part are connected inside the connector housing.

7. The storage system according to claim 5, When viewed in the thickness direction of the circuit board, the first conductive portion and the second conductive portion are connected via the surface or inner layer of the circuit board within the area where the connector is installed.

8. The storage system according to claim 5, It also includes a bridge circuit or a power supply circuit disposed on the circuit board. The first conductive portion and the second conductive portion are connected to the bridge circuit or the power supply circuit via a common wiring disposed on the circuit board.

9. The storage system according to claim 5, The group of the first terminal and the second terminal is a group of power supply terminals that supply power to the first storage system and power supply terminals that supply power to the second storage system, a group of ground terminals connected to the first storage system and ground terminals connected to the second storage system, or a group of terminals that receive a signal indicating that the write operation of the first storage system has been completed normally and a group of terminals that receive a signal indicating that the write operation of the second storage system has been completed normally.

10. The storage system according to claim 5, The group of the first terminal and the second terminal is a group of terminals that outputs a reset signal that resets the first storage system and the second storage system, or a group of terminals that flows with a signal that can determine the address information of one of the first storage system and the second storage system.

11. The storage system according to any one of claims 1 to 3, The first slot has a third terminal group having a plurality of terminals arranged in the first direction opposite to the first terminal group and facing the first storage system. The first terminal group is located between the third terminal group and the second slot in the second direction. The second slot has a fourth terminal group having a plurality of terminals arranged in the first direction opposite to the second terminal group and facing the second storage system. The second terminal group is located between the fourth terminal group and the first slot in the second direction. The connector has a connector housing, a first conductive portion connected to a first terminal including the plurality of terminals of the first terminal group, and a second conductive portion connected to a second terminal including the plurality of terminals of the second terminal group. When viewed in the thickness direction of the circuit board, the first conductive portion and the second conductive portion are connected in the mounting area of ​​the connector.

12. The storage system according to claim 11, It also includes a bridge circuit mounted on the circuit board. The connector further includes a third conductive portion connected to the third terminal included in the plurality of terminals of the third terminal group and a fourth conductive portion connected to the fourth terminal included in the plurality of terminals of the fourth terminal group, wherein the third conductive portion and the fourth conductive portion are independently connected to the bridge circuit. The first conductive portion and the second conductive portion are connected to the bridge circuit via a common wiring disposed on the circuit board.

13. The storage system according to any one of claims 1 to 3, The circuit board has a mounting surface on which the connector is mounted. The first storage system and the second storage system are configured parallel to the mounting surface of the circuit board.

14. The storage system according to any one of claims 1 to 3, It also includes a heat dissipation component, which is disposed between the first storage system and the second storage system and connected to the first storage system and the second storage system.

15. A storage system comprising: Circuit board; A connector, mounted on the circuit board, includes a first slot having a first terminal group with a plurality of terminals arranged in a first direction, and a second slot having a second terminal group having a plurality of terminals arranged in the first direction, extending away from the first slot in a second direction intersecting the first direction. The first slot and the second slot have openings in the same orientation in a third direction intersecting both the first and second directions. The order of the terminals in the first direction of the first terminal group is reversed compared to the order of the terminals in the first direction of the second terminal group. A storage system, which is inserted into the first slot and connected to the first terminal group, includes a substrate and a semiconductor storage component mounted on the substrate.

Images