Signal delay control and related devices, systems, and methods

Abstract

The present application relates to signal delay control and related apparatus, systems, and methods. An apparatus includes a delay element and a control circuit electrically connected to the delay element. The delay element is configured to receive a skewed data signal and a delay code indicative of an amount of delay. The delay element is further configured to provide a delayed data signal that is delayed by the amount of delay relative to the skewed data signal. The control circuit is configured to provide the delay code that is selected to reduce a timing skew of the delayed data signal relative to a timing skew of the skewed data signal. A system includes a first device, a second device including the apparatus, and a transmission line electrically connected between the first device and the second device. A method includes calibrating the delay code.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Patent Application Serial No. 17 / 204,681, entitled “SIGNAL DELAY CONTROL AND RELATED APPARATUSES, SYSTEMS, AND METHODS”, filed on March 17, 2021. Technical Field

[0003] This disclosure generally relates to the control of data signal delay, and more specifically to the control of data signal delay and / or duty cycle for memory read and / or write operations. Background Technology

[0004] Electrical transmission lines can be used for electrical connections between devices. As examples, conductive traces on printed circuit boards (PCBs), device pins, conductive structures within the device itself (e.g., conductive material in and / or on semiconductor devices), wires, and other conductive structures can serve as transmission lines for conducting signals between devices. Different transmission lines can delay the signals transmitted by them by different amounts of time (e.g., depending on the physical and / or electrical dimensions of the transmission line). Summary of the Invention

[0005] In some embodiments, a device includes a delay element and control circuitry. The delay element includes a data input, a delay adjustment, and a data output. The data input is configured to receive a skewed data signal. The delay adjustment is configured to receive a delay code indicating a delay amount. The data output is configured to provide a delayed data signal in response to the skewed data signal. The delayed data signal is delayed by the delay element relative to the skewed data signal by the delay amount indicated by the delay code. The control circuitry is electrically connected to the delay adjustment. The control circuitry is configured to provide the delay code to the delay adjustment. The delay code is selected to reduce the timing skew of the delayed data signal relative to the timing skew of the skewed data signal.

[0006] In some embodiments, an electrical system includes a first device, a transmission line, and a second device. The first device includes a first input / output terminal configured to provide a data signal. The transmission line is electrically connected to the first input / output terminal of the first device. At least one of the transmission lines has an associated transmission delay that differs from one or more other transmission delays associated with one or more other transmission lines. The second device includes a second input / output terminal, a delay element, and control circuitry. The second input / output terminal is electrically connected to the transmission line. The second input / output terminal is configured to receive a skewed data signal via the transmission line. The skewed data signal has a skewed timing relative to the data signal. The delay element is electrically connected to the second input / output terminal. The delay element is configured to receive the skewed data signal and provide a delayed data signal. The delay associated with the delay element is electrically controllable in response to a delay code provided to the delay element. The control circuitry is configured to provide the delay code to the delay element. The delay code is selected to reduce the skewed timing of the delayed data signal relative to the skewed timing of the skewed data signal.

[0007] In some embodiments, a method for calibrating a delay element includes: providing a delay code to the delay element; delaying a skewed data signal, including a known data value, by an amount indicated by the delay code to provide a delayed data signal; sampling the delayed data signal; and comparing the sampled data signal with the known data value. The method further includes repeating the providing, delaying, sampling, and comparing operations for one or more other sets of delay codes corresponding to other delay amounts, and selecting the delay code and one or more other delay codes that correspond to a correct comparison between the sampled data signal and the known data value. Attached Figure Description

[0008] Although this disclosure concludes with claims that particularly point out and expressly claim protection for particular embodiments, various features and advantages of embodiments within the scope of this disclosure may be more readily apparent from the following description when read in conjunction with the accompanying drawings, wherein:

[0009] Figure 1 This is a block diagram of an electrical system according to some embodiments;

[0010] Figure 2 yes Figure 1 A block diagram of a part of the electrical system;

[0011] Figure 3 This illustrates one operation according to some embodiments. Figure 1 A flowchart of a method for operating an electrical system;

[0012] Figure 4A yes Figure 2 The signal timing diagram of a portion of the signal shows a fault when one of the sampled delayed data signals is detected;

[0013] Figure 4B It is the minimum delay amount provided by the control circuit to the delay element in response to the delay code. Figure 2 Signal timing diagram of part of the signal;

[0014] Figure 4C It is the intermediate delay amount provided by the control circuit to the delay element in the delay code. Figure 2 Signal timing diagram of part of the signal;

[0015] Figure 4D It is the response to the maximum delay amount provided by the control circuit to the delay element in the delay code. Figure 2 Signal timing diagram of part of the signal;

[0016] Figure 4E It is the minimum duty cycle provided to the input buffer by the control circuit in response to the duty cycle code. Figure 2 Timing diagram of a portion of the signal;

[0017] Figure 4F It is in response to the maximum duty cycle provided to the input buffer by the control circuit in the duty cycle code. Figure 2 Timing diagram of a portion of the signal;

[0018] Figure 4G It is in response to the selected duty cycle provided to the input buffer by the control circuit in the duty cycle code. Figure 2 Timing diagram of a portion of the signal;

[0019] Figure 5 This is a block diagram of another electrical system according to some embodiments;

[0020] Figure 6 yes Figure 5 A block diagram of a part of the electrical system;

[0021] Figure 7 This illustrates one operation according to some embodiments. Figure 5 A flowchart of a method for operating an electrical system;

[0022] Figure 8A yes Figure 6 The signal timing diagram of a portion of the signal shows a fault when one of the sampled delayed data signals is detected;

[0023] Figure 8B It is the minimum delay amount provided by the control circuit to the delay element in response to the delay code. Figure 6 Signal timing diagram of part of the signal;

[0024] Figure 8C It is the intermediate delay amount provided by the control circuit to the delay element in the delay code. Figure 6 Signal timing diagram of part of the signal;

[0025] Figure 8D It is the response to the maximum delay amount provided by the control circuit to the delay element in the delay code. Figure 6 Signal timing diagram of part of the signal;

[0026] Figure 9 This is a block diagram of a computing system according to some embodiments;

[0027] Figure 10 It can be used Figure 1 Electrical systems Figure 5 electrical systems and Figure 9 A circuit diagram illustrating an example of an electrically controllable delay element in a computing system;

[0028] Figure 11 It can be used Figure 1 electrical systems and Figure 5 A circuit diagram illustrating an example of a pattern generation circuit in an electrical system;

[0029] Figure 12 This is a flowchart illustrating a method for calibrating a delay element according to some embodiments;

[0030] Figure 13 This is a block diagram of a computing system according to some embodiments; and

[0031] Figure 14 It is a block diagram of a circuit that can be used in some embodiments to implement the various functions, operations, actions, processes and / or methods disclosed herein. Detailed Implementation

[0032] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document and illustrate specific exemplary embodiments in which the present disclosure may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of the present disclosure.

[0033] The illustrations presented herein are not intended to be actual views of any particular method, system, apparatus, or structure, but are merely idealized representations used to describe embodiments of this disclosure. In some cases, similar structures or components in the various figures may retain the same or similar designations for the reader's convenience; however, similarity in designations does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0034] The following description may include examples that will enable those skilled in the art to practice the disclosed embodiments. The use of the terms “exemplary,” “by example,” and “for example” means that the description is explanatory, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the embodiments or the scope of this disclosure to specific components, steps, features, functions, etc.

[0035] It is readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of various embodiments is not intended to limit the scope of this disclosure, but merely to represent various embodiments. Although various aspects are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless explicitly indicated otherwise.

[0036] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise stated herein. Components, circuits, and functions may be shown in block diagram form to avoid obscuring this disclosure with unnecessary details. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise stated herein. Moreover, the block definitions and logical divisions between the blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other division solutions. In most cases, it is not necessary to obtain a complete understanding of this disclosure, and details regarding timing considerations, etc., that are within the capabilities of those skilled in the art, are omitted.

[0037] Those skilled in the art will understand that information and signals can be represented using any of a variety of different technologies and processes. For ease of presentation and description, some figures may show a signal as a single signal. Those skilled in the art will understand that a signal can represent a signal bus, wherein the bus can have various bit widths, and this disclosure can be implemented on any number of data signals including a single piece of data.

[0038] The various illustrative logic blocks, modules, and circuits incorporated in the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may refer herein to a main processor or simply a processor) may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a combination of one or more microprocessors with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, and the general-purpose computer is configured to execute computational instructions (e.g., software code) related to the embodiments of this disclosure.

[0039] Implementations can be described based on processes depicted as flowcharts, program diagrams, structural diagrams, or block diagrams. While flowcharts may describe actions as a sequential process, many of these actions can be performed in a different order, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process can correspond to a method, thread, function, program, subroutine, subroutine, other structure, or a combination thereof. Moreover, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, the functionality can be stored or transmitted as one or more instructions or code via a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another.

[0040] Any reference to elements in this document, such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish two or more elements or instances of elements. Therefore, references to a first element and a second element do not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0041] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes, to the extent that a person skilled in the art would understand, that the given parameter, property, or condition satisfies a certain degree of variation, such as within acceptable manufacturing tolerances. For example, depending on whether a particular parameter, property, or condition is substantially satisfied, it may be satisfied by at least 90%, at least 95%, or even at least 99%.

[0042] As used herein, the term “electrical connection” refers to a direct electrical connection (i.e., without any intermediate electrical connection) and an indirect electrical connection (i.e., with one or more intermediate electrical connection).

[0043] As used herein, the terms “skew” and “skewed timing” when applied to signals refer to a time misalignment between signal transition points. For example, digital signals may use different logic level voltage potentials (e.g., logic high voltage potential or “1” and logic low voltage potential or “0”) to transmit information. Although transitions between different logic level voltage potentials, or rising and falling edges, may be substantially synchronized in time when provided by a first device, these transitions may be asynchronous or skewed when transmitted to a second device. This skew between signal transition points (e.g., rising and falling edges) may be caused by different transmission delays associated with different transmission lines transmitting the signal from the first device to the second device. Other factors such as device packaging may also cause skew.

[0044] A computing system may include a computing host device (e.g., a processor such as a central processing unit) electrically connected to a memory device (e.g., a dynamic random access memory (DRAM) device). The host device may be electrically connected to the memory device via traces on a printed circuit board (PCB), such as a motherboard or logic board. Due to the different transmission delays associated with the different transmission lines (e.g., traces) used to conduct the data input / output signal DQ, the data input / output signal DQ transmitted between the computing host device and the memory device may be skewed, potentially resulting in a skew of up to approximately 110-120 picoseconds (ps) between the signals. Furthermore, additional skew may be introduced due to module and / or packaging effects, potentially resulting in a skew of up to approximately 30-40 ps. Thus, by the time the data input / output signal DQ is received, there may be a skew of up to approximately 150 ps, ​​which, assuming operation at 3200 MHz, could be approximately half a unit time interval. Such skew can cause the sampling of the DQ signal to be relatively close to the transition point between bits, potentially leading to sampling data bit errors. In addition, duty cycle distortion may occur in DQ signals, which may lead to more errors in the sampled data bits.

[0045] One way to compensate for this skew is to match the length of transmission lines carrying DQ signals from the same byte of information (e.g., electronic traces on the motherboard, conductor strips in a device, conductor strips for pins and wires in a device package, etc.), which can reduce differences in transmission delay. However, doing so can lead to unnecessary bends in the transmission lines to match the transmission line length, which can result in significant board and / or chip space consumption. Moreover, crosstalk between transmission lines of similar length can be relatively high.

[0046] By using write timing training sequences to align the DQ signal with the clock used to sample the DQ signal, errors caused by skew and duty cycle distortion can be reduced. However, such training sequences can be relatively time-consuming and may only be executed during the execution of Basic Input / Output System (BIOS) code at system startup. Therefore, such write timing training sequences may not be suitable for compensating for voltage and / or temperature drift after BIOS code execution. Furthermore, read timing training sequences may not be suitable for reducing DQ signal skew during read operations.

[0047] The embodiments disclosed herein use electrically controllable delay elements, electrically controllable duty cycle elements (e.g., input buffers), or both, to compensate for skew and duty cycle distortion without requiring physically matched transmission lines (e.g., PCB traces, device conductors, package wiring, and pins). Timing skew can be compensated for in addition to using training sequences during BIOS code execution, and input duty cycle error correction can be performed. Therefore, voltage and / or temperature drift can be compensated for by calibrating the delay and / or duty cycle at any time during operation. Furthermore, per-DQ signal training can be implemented.

[0048] The embodiments disclosed herein implement per-pin timing control that can be implemented in a memory device. By using the embodiments presented herein, read and write signal integrity can be improved by eliminating channel skew in each pin. Since timing control can be performed in the memory device, skew from various components (motherboard, modules, and packages) can be eliminated. The embodiments disclosed herein can also improve system design efficiency, as otherwise a significant amount of time would be wasted on matching transmission line lengths.

[0049] The embodiments disclosed herein can improve signal integrity quality in system channels. Skewed signals transmitted by mismatched transmission lines with free routing can reduce the rank margin tool (RMT) margin of received and / or transmitted signals, and lower development costs. For DRAM memory devices, the margin can be maximized if the skewed input of each DQ line can be deskewed at the front end of the DRAM device. The embodiments disclosed herein implement a simple method for training / calibrating delays and / or duty cycles at any time during operation. Voltage and temperature drift can also be compensated for during operation. For write (RMT-Tx) margin, DRAM memory devices according to the embodiments disclosed herein can implement per-bit deskew and duty cycle correction logic. For read (RMT-Rx) margin, the embodiments disclosed herein can reuse weighted delay codes to intentionally achieve slight skew in the DQ lines, thereby reducing crosstalk.

[0050] In some embodiments, a device includes a delay element and control circuitry. The delay element includes a data input, a delay adjustment, and a data output. The data input is configured to receive a skewed data signal. The delay adjustment is configured to receive a delay code indicating a delay amount. The data output is configured to provide a delayed data signal in response to the skewed data signal. The delayed data signal is delayed by the delay element relative to the skewed data signal by the delay code. The control circuitry is electrically connected to the delay adjustment. The control circuitry is configured to provide a delay code to the delay adjustment. The delay code is selected to reduce the timing skew of the delayed data signal relative to the timing skew of the skewed data signal.

[0051] In some embodiments, an electrical system includes a first device, a transmission line, and a second device. The first device includes a first input / output terminal configured to provide a data signal. The transmission line is electrically connected to the first input / output terminal of the first device. At least one of the transmission lines has an associated transmission delay that differs from one or more other transmission delays associated with one or more other transmission lines. The second device includes a second input / output terminal, a delay element, and control circuitry. The second input / output terminal is electrically connected to the transmission line. The second input / output terminal is configured to receive a skewed data signal via the transmission line. The skewed data signal has a skewed timing relative to the data signal. The delay element is electrically connected to the second input / output terminal. The delay element is configured to receive the skewed data signal and provide a delayed data signal. The delay associated with the delay element is electrically controllable in response to a delay code provided to the delay element. The control circuitry is configured to provide the delay code to the delay element. The delay code is selected to reduce the skewed timing of the delayed data signal relative to the skewed timing of the skewed data signal.

[0052] In some embodiments, a method for calibrating a delay element includes: providing a delay code to the delay element; delaying a skewed data signal containing a known data value by an amount indicated by the delay code to provide a delayed data signal; sampling the delayed data signal; and comparing the sampled data signal with the known data value. The method further includes repeating the providing, delaying, sampling, and comparing operations for one or more other sets of delay codes corresponding to other delay amounts, and selecting the delay code and one or more other delay codes that correspond to a correct comparison between the sampled data signal and the known data value.

[0053] Figure 1This is a block diagram of an electrical system 100 according to some embodiments. The electrical system 100 includes a first device 130, a second device 134, and transmission lines 160a-160c electrically connected between the first device 130 and the second device 134. The first device 130 includes output buffers 104a-104c electrically connected to first input / output terminals 158a-158c. The first input / output terminals 158a-158c are configured to provide data signals 150a-150c to the second device 134 via transmission lines 160a-160c. In some embodiments, the first device 130 includes a computing host, and the second device 134 includes a memory device. In such embodiments, the data signals 150a-150c may include data signals DQ for memory write operations. For example, Figure 1 Data signals DQ[0], DQ[1], ..., DQ[N] are shown to be provided from the first device 130 to the second device 134.

[0054] At least one of the transmission lines 160a-160c has an associated transmission delay that differs from one or more other transmission delays associated with one or more other transmission lines 160a-160c. As a non-limiting example, transmission line 160b is shown to include a length longer than either transmission line 160a or transmission line 160c, corresponding to a longer transmission delay.

[0055] The second device 134 includes second input / output terminals 162a-162c electrically connected to transmission lines 160a-160c. The second input / output terminals 162a-162c are configured to receive skewed data signals 142a-142c via transmission lines 160a-160c. Because transmission lines 160a-160c have different transmission delays, the skewed data signals 142a-142c have skewed timing relative to data signals 150a-150c.

[0056] The second device 134 further includes delay elements 126a-126c electrically connected to the second input / output terminals 162a-162c (e.g., via input buffers 106a-106c). Delay elements 126a-126c are configured to receive skew data signals 142a-142c and provide delayed data signals 144a-144c. The delay associated with delay elements 126a-126c is electrically controllable in response to a delay code 146 provided to the delay elements 126a-126c. Specifically, delay elements 126a-126c include data input terminals 136a-136c, delay adjustment terminals 140a-140c, and data output terminals 138a-138c. Data input terminals 136a-136c are configured to receive skew data signals 142a-146c. Delay adjustment terminals 140a-140c are configured to receive a delay code 146 indicating a delay amount. Data output terminals 138a-138c are configured to provide a delayed data signal in response to a skew data signal and delay code 146. The delayed data signals 144a-144c are delayed relative to the skew data signals 142a-142c by delay elements 126a-126c by the delay amount indicated by delay code 146. The second device 134 also includes control circuitry 108 configured to provide delay code 146 to delay elements 126a-126c. The first device 130 also includes input buffers 106a-106c electrically connected between the second input / output terminals 162a-162c and the delay elements 126a-126c. Control circuitry 108 is configured to provide duty cycle code 148 to input buffers 106a-106c to adjust the duty cycle of the skew data signals 142a-142c.

[0057] The second device 134 further includes a sampling circuit 152 electrically connected to the data output terminals 138a-138c of the delay elements 126a-126c. The sampling circuit is configured to sample the delayed data signals 144a-144c. As a non-limiting example, the sampling circuit 152 may include latches 118a, 118b, 120a, 120b, 122a, and 122b, which are configured to latch the delayed data signals 144a-144b in response to a clock signal 124. Latches 118a and 118b may correspond to the delay element 126a (e.g., for DQ[0]), latches 120a and 120b may correspond to the delay element 126b (e.g., for DQ[1]), and latches 122a and 122b may correspond to the delay element 126c (e.g., for DQ[N]). Therefore, each of the DQ signals can include a pair of differential signals, which includes an even-numbered DQ signal and an odd-numbered DQ signal. Figure 1In the illustrated embodiment, the delay elements 126a-126c can adjust the delay on a per-DQ basis, or in other words, on a per-pair differential DQ signal basis.

[0058] The second device 134 further includes a comparator circuit 156 and a pattern generation circuit 110. The pattern generation circuit 110 is configured to generate a comparison signal 154 including a known data value and provide the comparison signal 154 to the comparator circuit 156. The comparator circuit 156 includes comparators 112a, 112b, 114a, 114b, 116a, and 116b. Comparators 112a and 112b are electrically connected to 118a and 118b. Comparators 114a and 114b are electrically connected to latches 120a and 120b. Comparators 116a and 116b are electrically connected to latches 122a and 122b. The comparator circuit 156 is configured to compare the sampled data signal with the known data value indicated by the comparison signal 154 for skew data signals 142a-142c, corresponding to different delay codes 146 for different delay amounts, in response to calibrate the delay amount. Comparator circuit 156 can perform a comparison in response to a delayed version of clock signal 124. Therefore, second device 134 may include a clock delay element 128 configured to delay clock signal 124. The delay added by clock delay element 128 can provide sampling circuit 152 with sufficient time to sample delayed data signals 144a-144c, enabling comparator circuit 156 to perform the comparison.

[0059] Control circuit 108 is configured to select delay code 146 and / or duty cycle code 148 to reduce the skew timing of delayed data signals 144a-144c compared to the skew timing of skewed data signals 142a-142c received by delay elements 126a-126c. Control circuit 108 is configured to calibrate delay code 146 by applying different delay codes 146 to delay elements 126a-126c (e.g., based on DQ / DQ) and selecting delay code 146 corresponding to the correct comparison between delayed data signals 144a-144c and comparison signal 154 (e.g., using...). Figure 12 Method 1200). To perform the calibration operation, the first device 130 includes a pattern generation circuit 102 configured to generate a pattern of known data values ​​for data signals 150a-150c. The second device 134 includes a pattern generation circuit 110 configured to generate the same pattern of known data values ​​for comparison signal 154.

[0060] During calibration, pattern generation circuit 102 can generate data signals 150a-150c that include known data values ​​(the same known data values ​​indicated by comparison signal 154 provided by pattern generation circuit 110) and transmit data signals 150a-150c to output buffers 104a-104c. Each of the data signals 150a-150c can include a stream of known data values. Output buffers 104a-104c can provide data signals 150a-150c to transmission lines 160a-160c via first input / output terminals 158a-158c. Data signals 150a-150c may be skewed, and transmission lines 160a-160c can transmit skewed data signals 142a-142c to second input / output terminals 162a-162c of the second device 134.

[0061] The second input / output terminals 162a-162c can transmit the skew data signals 142a-142c to the input buffers 106a-106c, which in turn can transmit the skew data signals 142a-142c to the data input terminals 136a-136c of the delay elements 126a-126c. The control circuit 108 can transmit the first value of the delay code 146 to the delay elements 126a-126c via the delay adjustment terminals 140a-140c. Therefore, the transmission of the delayed data signals 144a-144c to the sampling circuit 152 via the data output terminals 138a-138c can be delayed by the amount indicated by the first value of the delay code 146. The sampling circuit 152 can latch the delayed data signals 144a-144c in response to the clock signal 124, and the comparison circuit 156 can compare the latched value of the delayed data signals 144a-144c with the comparison signal 154. The comparator circuit 156 can indicate to the control circuit 108 whether the value latched into the sampling circuit 152 is the same as the known value indicated by the comparison signal 154.

[0062] Control circuit 108 can then modulate delay code 146 and receive an indication of whether the result value latched to sampling circuit 152 matches the known value indicated by comparison signal 154. Control circuit 108 can repeat modulation of delay code 146 for multiple different values, and for each of delay elements 126a-126c, select those values ​​from the multiple different values ​​that correspond to a correct comparison between the latched value of delayed data signals 144a-144c and the known data value of comparison signal 154. In this way, control circuit 108 can calibrate delay elements 126a-126c. A similar calibration operation can be performed on input buffers 106a-106c (e.g., by modulating with different values ​​of duty cycle code 148 to calibrate input buffers 106a-106c).

[0063] In embodiments where the processor first device 130 is a computing host and the second device 134 is a memory device (e.g., as referred to below) Figure 9 (As discussed), electrical system 100 can perform write operations. A data signal, including data to be written to the memory core of the memory device, can be provided (e.g., by the processing core of the computer host) to output buffers 104a-104c, which buffer the data signal and provide it to transmission lines 160a-160c. Transmission lines 160a-160c can transmit a skewed data signal to the memory device. Input buffers 106a-106c can buffer the skewed data signal (e.g., correct the duty cycle of the skewed data signal in response to a duty cycle code 148 provided by control circuit 108) and provide the skewed data signal to delay elements 126a-126c. Delay element 126a can reduce the skew of the skewed data signal by increasing the delay in response to a delay code 146 provided by control circuit 108, and provide the delayed data signal to sampling circuit 152. In response to clock signal 124, sampling circuit 152 can sample the delayed data signal to latch the data bits to be written to the memory core of the memory device. Since the write operation utilizes the same output buffers 104a-104c, channel 132, input buffers 106a-106c, and delay elements 126a-126c used for calibrating delay code 146 and duty cycle code 148, the calibrated delay code 146 and duty cycle code 148 can reduce the skew and duty cycle distortion of the delayed data signal compared to the skewed data signal during the write operation.

[0064] Figure 2 yes Figure 1 A block diagram of a portion 200 of an electrical system 100. This portion 200 includes a pattern generation circuit 102, an output buffer 104a, a first input / output terminal 158a, a transmission line 160a, a second input / output terminal 162a, an input buffer 106a, a delay element 126a (which includes a data input terminal 136a, a delay adjustment terminal 140a, and a data output terminal 138a), latches 118a and 118b, a clock delay element 128, comparators 112a and 112b, a pattern generation circuit 110, and a control circuit 108, as referenced above. Figure 1 Discussed. Figure 2 The above reference is also shown. Figure 1 The data signal 150a, the skewed data signal 142a, and the delayed data signal 144a are discussed.

[0065] Figure 2 Also shown are the duty cycle code 204 provided by control circuit 108 to input buffer 106a and the delay code 206 provided by control circuit 108 to delay adjustment terminal 140a of delay element 126a. Duty cycle code 204 is as described above. Figure 1 The duty cycle code 148 discussed above, and the delay code 206 are the references mentioned above. Figure 1 One of the delayed codes discussed is 146. Furthermore, Figure 2 A duty cycle-changing data signal 202 is shown provided by input buffer 106a to data input terminal 136a of delay element 126a in response to a skew data signal 142a received at second input / output terminal 162a. The duty cycle-changing data signal 202 has a duty cycle that changes in response to a duty cycle code 204 relative to the duty cycle of the skew data signal 142a. For example, the duty cycle-changing data signal 202 may have a duty cycle that changes by an amount of duty cycle indicated by the duty cycle code 204 relative to the duty cycle of the skew data signal 142a.

[0066] also, Figure 2 The diagram shows the latched even-numbered data bits 208a provided by latch 118a to comparator 112a, and the latched odd-numbered data bits 208b provided by latch 118b to comparator 112b. Furthermore, Figure 2 Comparison signals 210a and 210b are shown, which are referenced above. Figure 1 Two signals in comparison signal 154 are discussed. Comparator 112a is configured to compare the latched even-numbered data bits 208a with comparison signal 210a, and uses the comparison result 212a to indicate whether the latched even-numbered data bits 208a have passed the comparison, which is provided by comparator 112a to control circuit 108. Similarly, comparator 112b is configured to compare the latched odd-numbered data bits 208b with comparison signal 210b, and uses the comparison result 212b to indicate whether the latched odd-numbered data bits 208b have passed the comparison, which is provided by comparator 112b to control circuit 108. Thus, control circuit 108 can be informed whether the delay introduced by delay element 126a allows latches 118a and 118b to latch the correct data value.

[0067] Figure 1 Part 200 of the electrical system 100 Figure 2 The following diagram illustrates a method 300 for calibrating an electrical system 100, which will be referenced below. Figure 3 Let's discuss this in more detail.

[0068] Figure 3 This illustrates operation according to some embodiments. Figure 1 The flowchart of method 300 for electrical system 100. Also refer to... Figure 2 and Figure 3 In operation 302, method 300 includes detecting sampling delay data signals 144a-144c ( Figure 1A failure occurs when one of the latches 118a, 118b, 120a, 120b, 122a, or 122b is triggered. As a non-limiting example, this failure is due to the triggering of latches 118a, 118b, 120a, 120b, 122a, or 122b. Figure 1 The time misalignment, or skew, between the latched delayed data signals 144a-144c and the clock signal 124 is caused by the comparator circuit 156. Figure 1 It may not be able to properly latch all bits of the delayed data signals 144a-144c. Figure 4A An example of a fault is shown when detecting one of the sampled delayed data signals 144a-144c.

[0069] Figure 4A yes Figure 2 The timing diagram of signal 200 and signal 400 shows a fault when sampling delayed data signals 144a-144c. Also refer to... Figure 2 , Figure 3 and Figure 4A Signal 400 includes Figure 2 The signal 400 includes a skew data signal 142a, a delayed data signal 144a, a clock signal 124, a latched even data bit 208a, a latched odd data bit 208b, a comparison signal 210a, a delayed clock signal 214, and a comparison result 212a. Signal 400 also includes a pass / fault indication 402, which can be driven to a logic high voltage potential in response to detecting a fault (e.g., failure to determine that the latched even data bit 208a equals the comparison signal 210a), and driven to a logic low voltage potential in response to detecting a pass (e.g., determining that the latched even data bit 208a equals the comparison signal 210a).

[0070] As a non-limiting example, the skew data signal 142a includes bits D0, D1, D2, and D3. For example... Figure 4A As shown, the skew data signal 142a may exhibit some timing misalignment with the clock signal 124. The skew data signal 142a may also exhibit some duty cycle distortion (e.g., bits D0 and D2 are shorter in time than D1 and D3).

[0071] The delayed data signal 144a is a delayed version of the skewed data signal 142a. The rising edge of the clock signal 124 can be used to trigger latch 118a to sample the even-numbered bits (bits D0 and D2) of the delayed data signal 144a, and the falling edge of the clock signal 124 can be used to trigger latch 118b to sample the odd-numbered bits (bits D1 and D3) of the delayed data signal. Although the falling edge of the clock signal 124 can be aligned with a sufficiently stable portion of the odd-numbered data bits D1 and D3 of the delayed data signal 144a so that latch 118b can sample the correct values ​​of the odd-numbered data bits D1 and D3, the rising edge of the clock signal 124 may be too close to the bit transitions of the delayed data signal 144a to sample the correct values ​​of the even-numbered data bits D0 and D2. Therefore, although latching odd data bits 208b indicates the correct values ​​of odd bits D1 and D3, latching even data bits 208a may not indicate the correct values ​​of even bits D0 and D2. Therefore, in latching even data bits 208a, these bits are represented as "D?", and the fault indicator 402 is shown at a logic high voltage level to indicate a fault in latched even bits D0 and D2.

[0072] The delayed clock signal 214 is a delayed version of the clock signal 124 (e.g., delayed by clock delay element 128). The delayed clock signal 214 triggers comparator 112a to compare a comparison signal 210a, including even data bits D0 and D2, with latched even data bits 208a. Since the correct even data bits D0 and D2 are not latched, comparator 112a can signal a fault in the comparison result 212a (e.g., by driving the comparison result 212a to a logic high voltage potential). Therefore, according to Figure 3 In operation 302, in response to the comparison result 212a provided by comparator 112a, control circuit 108 can detect a fault when sampling delayed data signal 144a occurs. Of course, any of comparators 112a, 112b, 114a, 114b, 116a, and 116b can provide a comparison result indicating a fault when control circuit 108 fails to detect one of the sampling delayed data signals 144a-144c.

[0073] In operation 304, method 300 includes sweeping the delay code 206 from the minimum delay amount to the maximum delay amount. Figure 4B The signal 400, which responds to the minimum delay, is shown. Figure 4C Signal 400 shows the intermediate delay amount in response (e.g., the median between the minimum and maximum delay amounts). Figure 4D The signal 400, which responds to the maximum delay, is shown.

[0074] Figure 4BIt is in response to the minimum delay amount provided by the control circuit 108 to the delay element 126a in delay code 206. Figure 2 The timing diagrams for the 200 and 400 signals are provided. Also refer to... Figure 2 , Figure 3 and Figure 4B Since the delay code 206 provided to the delay element 126a indicates the minimum delay amount (e.g., zero delay), the delayed data signal 144a can be substantially the same as the skewed data signal 142a.

[0075] Although the falling edge of clock signal 124 may occur at a point in time when the odd data bits D1 and D3 are sufficiently stable to allow for correct sampling of the odd data bits D1 and D3, the rising edge of clock signal 124 may occur too close to the bit transition in the delayed data signal 144a to allow for correct sampling of the even data bits D0 and D2. Therefore, when comparator 112a compares the latched even data bits 208a with the comparison signal 210a, comparator 112a uses the comparison result 212a to send a fault signal to control circuit 108 (e.g., by driving the comparison result 212a to a logic high voltage potential).

[0076] Figure 4C It is in response to the intermediate delay amount provided by the control circuit 108 to the delay element 126a in delay code 206. Figure 2 The timing diagrams for the 200 and 400 signals are provided. Also refer to... Figure 2 , Figure 3 and Figure 4C As part of operation 304 (sweep delay code), the delayed data signal 144a is delayed by less than [a certain value] relative to the skewed data signal 142a. Figure 4A The quantity shown, but greater than Figure 4B The quantities shown. Therefore, the rising edge of clock signal 124 is time-aligned with the stable portions of even-numbered bits D0 and D2 of delayed data signal 144a, and the falling edge of clock signal 124 is time-aligned with the stable portions of odd-numbered bits D1 and D3 of delayed data signal 144a. Therefore, in response to clock signal 124, latches 118a and 118b, corresponding to the logic level low voltage potential in pass / fail indication 402 (pass), correctly latch even-numbered bits D0 and D2 and odd-numbered bits D1 and D3 to latch even-numbered data bits 208a and latch odd-numbered data bits 208b, respectively. In response to delayed clock signal 214, comparators 112a and 112b use comparison result 212a to indicate to control circuit 108 that the comparison passed (e.g., by holding comparison result 212a at a logic level low voltage potential to indicate that even-numbered bits D0 and D2 passed the comparison).

[0077] Figure 4DIt is in response to the maximum delay amount provided by the control circuit 108 to the delay element 126a in delay code 206. Figure 2 The timing diagrams for the 200 and 400 signals are provided. Also refer to... Figure 2 , Figure 3 and Figure 4D As part of operation 304 (sweep delay code), the delayed data signal 144a is delayed relative to the skewed data signal 142a by a maximum delay amount, which is greater than... Figure 4A , Figure 4B and Figure 4C The delay amount is shown. After the delayed data signal 144a is delayed by the maximum delay amount, the rising and falling edges of the clock signal 124 are not aligned with the stable portion of the delayed data signal 144a. As a result, both latched even data bits 208a and latched odd data bits 208b may include incorrect values, indicating a fault via fault indicator 402 and comparison result 212a.

[0078] In operation 306, method 300 includes setting delay code 146 ( Figure 1 This indicates the delay amount corresponding to the highest number of correct comparisons (e.g., for part 200, between latching even data bits 208a and comparison signal 210a, and between latching odd data bits 208b and comparison signal 210b). As discussed above, see reference Figure 4C The intermediate delay amount discussed results in all correct bits being latched. In this example, delay code 206 can be set to the intermediate delay amount because the intermediate delay amount results in the highest number of correct comparisons.

[0079] In operation 308, method 300 includes sweeping the duty cycle code from a minimum duty cycle to a maximum duty cycle. For example, Figure 4E The signal 400 in response to the minimum duty cycle is shown. Figure 4F The signal 400 in response to the maximum duty cycle is shown. Figure 4G The signal 400 is shown in response to the selected duty cycle.

[0080] Figure 4E It is in response to the minimum duty cycle provided by the control circuit 108 to the input buffer 106a in duty cycle code 204. Figure 2 The timing diagram for part 200 signals and part 400 signals. Also refer to... Figure 2 , Figure 3 and Figure 4E As part of operation 308 (sweep duty cycle code), in response to the minimum duty cycle provided in duty cycle code 204, the duty cycles of bits D0, D1, D2, and D3 of the delayed data signal 144a are adjusted. Therefore, in Figure 4EIn this context, the delayed data signal 144a is a delayed version of the skew data signal 142a (e.g., delayed by an intermediate delay code set in operation 306), wherein its duty cycle is adjusted relative to the skew data signal 142a by an amount indicated by the minimum duty cycle.

[0081] After the duty cycle of the delayed data signal 144a is adjusted to the minimum duty cycle, the falling edge of the clock signal 124 is aligned with the stable portions of the odd-numbered bits D1 and D3 of the delayed data signal 144a. However, the rising edge of the clock signal 124 is not aligned with the stable portions of the even-numbered bits D0 and D2 of the delayed data signal 144a. Therefore, latch 118a can sample incorrect values ​​of the even-numbered bits to latch the even-numbered data bits 208a, indicating a fault via fault indicator 402, and the comparison result 212a can also indicate a fault.

[0082] Figure 4F It is in response to the maximum duty cycle provided by the control circuit 108 to the input buffer 106a in the duty cycle code 204. Figure 2 The timing diagram for part 200 signals and part 400 signals. Also refer to... Figure 2 , Figure 3 and Figure 4F As part of operation 308 (sweep duty cycle code), in response to the maximum duty cycle provided in duty cycle code 204, the duty cycles of bits D0, D1, D2, and D3 of the delayed data signal 144a are adjusted. Therefore, in Figure 4F In this context, the delayed data signal 144a is a delayed version of the skew data signal 142a (e.g., delayed by an intermediate delay code set in operation 306), wherein its duty cycle is adjusted relative to the skew data signal 142a by an amount indicated by the maximum duty cycle. Figure 4F As shown, relative to the duty cycle of the skewed data signal 142a, the duty cycles of the even-numbered bits D0 and D2 of the delayed data signal 144a have increased, while the duty cycles of the odd-numbered bits D1 and D3 of the delayed data signal 144a have decreased.

[0083] After the duty cycle of the delayed data signal 144a is adjusted to the maximum duty cycle, the rising edge of the clock signal 124 is aligned with the stable portions of the even-numbered bits D0 and D2 of the delayed data signal 144a. However, the falling edge of the clock signal 124 is not aligned with the stable portions of the odd-numbered bits D1 and D3 of the delayed data signal 144a. Therefore, latch 118b can sample incorrect values ​​of the odd-numbered bits to latch the odd-numbered data bits 208b, indicating a fault via fault indicator 402, and the comparison result 212b can also indicate a fault.

[0084] Figure 4G It is in response to the selected duty cycle provided by the control circuit 108 to the input buffer 106a in the duty cycle code 204. Figure 2 The timing diagram for part 200 signals and part 400 signals. Also refer to... Figure 2 , Figure 3 and Figure 4G In operation 310, method 300 includes setting duty cycle code 148 ( Figure 1 This indicates the duty cycle corresponding to the highest number of correct comparisons. Figure 4G In this configuration, duty cycle code 204 is set to a selected duty cycle corresponding to the highest number of correct comparisons between latched even data bits 208a and comparison signal 210a, and between latched odd data bits 208b and comparison signal 210b. In some embodiments, operation 308 may check several different duty cycles between the minimum and maximum duty cycles.

[0085] Latching even-numbered data bits 208a and odd-numbered data bits 208b reflects the correct values ​​of bits D0, D1, D2, and D3. Therefore, in response to the delayed clock signal 214, pass / fault indicator 402 indicates pass, and comparison result 212a indicates pass. Although in Figure 4G It is not shown in the figure, but the comparison result 212b will also indicate that it passed.

[0086] Note that in Figure 4E In the delayed data signal 144a, the duty cycle distortion is reduced compared to the skewed data signal 142a. For example, the time lengths of even-numbered bits D0 and D2 have increased, while the time lengths of odd-numbered bits D1 and D3 have decreased. Therefore, in the delayed data signal 144a, even-numbered bits D0 and D2 can have essentially the same time length as odd-numbered bits D1 and D3. In contrast, the even-numbered bits D0 and D2 of the skewed data signal 142a are shorter in time than the odd-numbered bits D1 and D3 of the skewed data signal 142a.

[0087] Figure 5 This is a block diagram of another electrical system 500 according to some embodiments. Electrical system 500 includes a first device 518 and a channel 522, similar to reference [reference]. Figure 1 The first device 130 and channel 132 are discussed. For example, the first device 518 includes a pattern generation circuit 502 and output buffers 504a-504c, similar to the reference. Figure 1 The discussed pattern generation circuit 102 and output buffers 104a-104c are also mentioned. Furthermore, channel 522 includes components similar to the reference circuit. Figure 1The transmission lines 160a-160c discussed are transmission lines 538a-538c. The pattern generation circuit 502 is configured to provide data signals 536a-536c to output buffers 504a-504c, which transmit the data signals 536a-536c to transmission lines 538a-538c. Transmission line 538a transmits skewed data signals 540a-540c to the second device 524 of the electrical system 500.

[0088] The second device 524 is similar to Figure 1 The second device 134, but the second device 524 is configured to adjust the delay of the skew data signals 540a-540c bit by bit, instead of as Figure 1 The second device 134 is based on DQ-by-DQ execution. Furthermore, the electrical system 500 may not be configured to adjust the duty cycle of the skew data signals 540a-540c, such as... Figure 1 The second device 134 performs the operation. Of course, without departing from the scope of this disclosure, duty cycle adjustments similar to those discussed above can be performed by the second device 524.

[0089] The second device 524 includes input buffers 506a-506c configured to receive skew data signals 540a-540c. The second device 524 also includes delay elements 532a-532f, configured to delay the skew data signals 540a-540c to generate delayed data signals 542a-542f in response to a delay code 526 provided to the delay elements 532a-532f by the control circuitry 508 of the second device 524. The second device 524 also includes a sampling circuit 528 including latches 520a-520f configured to latch the values ​​of the delayed data signals 542a-542f in response to a clock signal 514. The second device 524 further includes a pattern generation circuit 510 configured to generate a comparison signal 530, and a comparator circuit 534 including comparators 512a-512f, which are configured to compare the latched value latched by the sampling circuit 528 with the comparison signal 530. The pattern generation circuit 510 is configured to generate the same data as the pattern generation circuit 502 to perform calibration of the delay code 526. The second device 524 includes a clock delay element 516 configured to delay the clock signal 514 to generate a delayed clock signal (not shown), thereby triggering the comparator circuit 534 to compare the latched data bits with the comparison signal 530.

[0090] In some embodiments, the first device 518 may be a computing host, and the second device 524 may be a memory device. In such embodiments, the electrical system 500 may include memory data input / output lines DQ[0], DQ[1], ..., and DQ[N].

[0091] Figure 6 yes Figure 5 A block diagram of part 600 of the electrical system 500. Part 600 includes the above reference. Figure 5 The discussed circuits include pattern generation circuit 502, output buffer 504a, transmission line 538a, input buffer 506a, delay elements 532a and 532b, latches 520a and 520b, clock delay element 516, comparators 512a and 512b, pattern generation circuit 510, and control circuit 508. Figure 6 The above reference is also shown. Figure 5 The data signals discussed are 536a, skew data signal 540a, and delayed data signals 542a and 542b.

[0092] Figure 6 Delay codes 610a and 610b, provided by control circuit 508 to delay elements 532a and 532b, are also shown. Delay codes 610a and 610b are referenced above. Figure 5 Two of the delayed codes 526 are being discussed.

[0093] also, Figure 6 The diagram shows the latched even-numbered data bits 606a provided by latch 520a to comparator 512a, and the latched odd-numbered data bits 606b provided by latch 520b to comparator 512b. Furthermore, Figure 6 Comparison signals 602a and 602b are shown; they are referenced above. Figure 5 Two signals in the comparison signal 530 are discussed. Comparator 512a is configured to compare the latched even-numbered data bit 606a with comparison signal 602a, and uses the comparison result 608a to indicate whether the latched even-numbered data bit 606a passed the comparison. Comparator 512a provides this comparison result to control circuit 508. Similarly, comparator 512b is configured to compare the latched odd-numbered data bit 606b with comparison signal 602b, and uses the comparison result 608b to indicate whether the latched odd-numbered data bit 606b passed the comparison. Comparator 512b provides this comparison result to control circuit 508. Therefore, control circuit 508 can be notified whether the delay introduced by delay elements 532a and 532b allows latches 520a and 520b to latch the correct data value.

[0094] Figure 5 The electrical system of part 500 in part 600 Figure 6 The method 700 for calibrating electrical system 500 is shown below, which will be referenced in the following text. Figure 7 Let's discuss this in more detail.

[0095] Figure 7 This illustrates operation according to some embodiments. Figure 5 The flowchart of method 700 for electrical system 500. Also refer to... Figure 6 and Figure 7 In operation 702, method 700 includes detecting sampling delay data signals 542a-542f ( Figure 5 A failure occurs when one of the latches 520a-520f is triggered. As a non-limiting example, this is due to the triggering of latches 520a-520f. Figure 5 The time misalignment, or skew, between the latched delayed data signals 542a-542f and the clock signal 514, is caused by the comparator circuit 534. Figure 5 It may not be able to properly latch all bits of the delayed data signals 542a-542f. Figure 8A An example of a fault is shown when detecting one of the sampled delayed data signals 542a-542f.

[0096] Figure 8A yes Figure 6 The timing diagram of signal 600 and signal 800 shows a fault when one of the sampled delayed data signals 542a-542f is encountered. Also refer to... Figure 6 , Figure 7 and Figure 8A Signal 800 includes Figure 6 The signal 800 includes a skew data signal 540a, delayed data signals 542a and 542b, a clock signal 514, latched even data bits 606a, latched odd data bits 606b, a comparison signal 602a, a delayed clock signal 604, and a comparison result 608a. Signal 800 also includes a pass / fault indication 802, which can be driven to a logic high voltage potential in response to detecting a fault (e.g., failure to determine that latched even data bits 606a equals comparison signal 602a), and driven to a logic low voltage potential in response to detecting a pass (e.g., determining that latched even data bits 606a equals comparison signal 602a).

[0097] As a non-limiting example, the skew data signal 540a includes bits D0, D1, D2, and D3. For example... Figure 8A As shown, the skew data signal 540a may exhibit some timing misalignment with the clock signal 514. The skew data signal 540a may also exhibit some duty cycle distortion (e.g., bits D0 and D2 are shorter in time than D1 and D3).

[0098] Delayed data signals 542a and 542b are delayed versions of the even and odd portions of the skewed data signal 540a, respectively. The rising edge of clock signal 514 can be used to trigger latch 520a to sample the even-numbered bits (bits D0 and D2) of delayed data signal 542a, and the falling edge of clock signal 514 can be used to trigger latch 520b to sample the odd-numbered bits (bits D1 and D3) of delayed data signal 542b. Although the falling edge of clock signal 514 can be aligned with a sufficiently stable portion of the odd-numbered data bits of delayed data signal 542b to enable latch 520b to sample the correct values ​​of odd-numbered data bits D1 and D3, the rising edge of clock signal 514 may be too close to the bit transitions of delayed data signal 542a to sample the correct values ​​of even-numbered data bits D0 and D2. Therefore, although latching odd data bits 606b indicates the correct values ​​of odd bits D1 and D3, latching even data bits 606a may not indicate the correct values ​​of even bits D0 and D2. Therefore, in latching even data bits 606a, these bits are represented as "D?", and the fault indicator 802 is shown at a logic high voltage level to indicate a fault in latched even bits D0 and D2.

[0099] The delayed clock signal 604 is a delayed version of the clock signal 514 (e.g., delayed by the clock delay element 516). The delayed clock signal 604 triggers comparator 512a to compare a comparison signal 602a, including even data bits D0 and D2, with latched even data bits 606a. Since the correct even data bits D0 and D2 are not latched, comparator 512a can signal a fault in the comparison result 608a (e.g., by driving the comparison result 608a to a logic high voltage potential). Therefore, according to Figure 7 In operation 702, in response to the comparison result 608a provided by comparator 512a, control circuit 508 can detect a fault when sampling delayed data signal 542a. Of course, any of comparators 512a-512f can provide a comparison result indicating a fault that fails to trigger control circuit 508 to detect one of the correctly sampled delayed data signals 542a-542f.

[0100] In operation 704, method 700 includes sweeping the delay code 526 from the minimum delay amount to the maximum delay amount. Figure 8B The signal 800, which responds to the minimum delay, is shown. Figure 8C A signal 800 is shown that responds to an intermediate delay amount (e.g., the middle number between the minimum and maximum delay amounts), and Figure 8D The signal 800 in response to the maximum delay is shown.

[0101] Figure 8BIt is the minimum delay amount provided by the control circuit 508 to the delay elements 532a and 532b in response to the delay codes 610a and 610b. Figure 6 The timing diagrams for the 600MHz and 800MHz signals are provided. Also refer to... Figure 6 , Figure 7 and Figure 8B Since the delay codes 610a and 610b provided to the delay elements 532a and 532b indicate a minimum delay (e.g., zero delay), the delayed data signals 542a and 542b can be delayed by a minimum amount relative to the skewed data signal 540a.

[0102] Although the falling edge of clock signal 514 may occur at a point in time when the odd data bits D1 and D3 of delayed data signal 542b are sufficiently stable to allow for correct sampling of odd data bits D1 and D3, the rising edge of clock signal 514 may occur too close to the bit transitions in delayed data signal 542a, making it impossible to correctly sample even data bits D0 and D2. Therefore, when comparator 512a compares the latched even data bits 606a with comparison signal 602a, comparator 512a uses the comparison result 608a to send a fault signal to control circuit 508 (e.g., by driving comparison result 608a to a logic high voltage potential for even bits D0 and D2).

[0103] Figure 8C It is in response to the intermediate delay amount provided by the control circuit 508 to the delay elements 532a and 532b in delay codes 610a and 610b. Figure 6 The timing diagrams for the 600MHz and 800MHz signals are provided. Also refer to... Figure 6 , Figure 7 and Figure 8C As part of operation 704 (sweep delay code), the delayed data signals 542a and 542b are delayed by less than [a certain value] relative to the skewed data signal 540a. Figure 8A The quantity shown, but greater than Figure 8BThe quantities shown. Therefore, the rising edge of clock signal 514 is time-aligned with the stable portions of even bits D0 and D2 of delayed data signal 542a, and the falling edge of clock signal 514 is time-aligned with the stable portions of odd bits D1 and D3 of delayed data signal 542b. Therefore, in response to clock signal 514, latches 520a and 520b, corresponding to the logic level low potential in pass / fail indication 802 (pass), correctly latch even bits D0 and D2 and odd bits D1 and D3 to latch even data bits 606a and latch odd data bits 606b, respectively. In response to delayed clock signal 604, comparators 512a and 512b use comparison result 608a to indicate to control circuit 508 that the comparison passed (e.g., by holding comparison result 608a at a logic level low potential to indicate that even bits D0 and D2 passed the comparison). Although Figure 8C Not shown in the diagram, but the comparison result 608b can be used. Figure 6 () to indicate similar passages for odd-numbered positions.

[0104] Figure 8D It is in response to the maximum delay amount provided by the control circuit 508 to the delay elements 532a and 532b in delay codes 610a and 610b. Figure 6 The timing diagrams for the 600MHz and 800MHz signals are provided. Also refer to... Figure 6 , Figure 7 and Figure 8D As part of operation 704 (sweep delay code), the delayed data signals 542a and 542b are delayed relative to the skewed data signal 540a by a maximum delay amount greater than [amount missing]. Figure 8A , Figure 8B and Figure 8C The delay amount is shown. After the delayed data signals 542a and 542b are delayed by the maximum delay amount, the rising and falling edges of the clock signal 514 are not aligned with the stable portions of the delayed data signals 542a and 542b. As a result, both latched even data bits 606a and latched odd data bits 606b may include incorrect values, indicating a fault via fault indicator 802 and comparison result 608a.

[0105] In operation 706, method 700 includes setting delay code 526 ( Figure 5 This indicates the delay amount corresponding to the highest number of correct comparisons (e.g., for portion 600, between latching even data bits 606a and comparison signal 602a, and between latching odd data bits 606b and comparison signal 602b). As discussed previously, see reference... Figure 8CThe intermediate delay amount discussed results in all correct bits being latched. In this example, delay codes 610a and 610b can be set to the intermediate delay amount because the intermediate delay amount results in the highest number of correct comparisons.

[0106] Of course, since each bit includes an electrically controllable delay element ( Figure 5 The operation 706, which sets the delay code 526, allows for individual adjustment of the delay of each delay element 532a-532f, and enables different delay codes 526 to be provided to each delay element 532a-532f. In operation 706, even delay elements receiving the same skewed data signal (e.g., delay elements 532a and 532b that both receive the skewed data signal 540a) can be set with different delay codes 526 (e.g., the delay code 610a provided to delay element 532a may be different from the delay code 610b provided to delay element 532b).

[0107] Figure 9 This is a block diagram of a computing system 900 according to some embodiments. The computing system 900 includes a computing host 922 (e.g., a central processing unit), a memory device 926 (e.g., a DRAM device), and a channel 924 electrically connecting the computing host 922 to the memory device 926. The channel includes transmission lines 918a-918c. In some embodiments, transmission lines 918a-918c may include conductive traces on a motherboard. The computing host 922 includes a processing core 904 electrically connected to input buffers 906a-906c. The input terminals of the input buffers 906a are electrically connected to transmission lines 918a-918c. The memory device 926 includes a memory core 908 (e.g., a DRAM core) electrically connected to latches 912a-912f, data multiplexers 920a-920c electrically connected to latches 912a-912f, delay elements 914a-914c electrically connected to data multiplexers 920a-920c, output buffers 910a-910c electrically connected between delay elements 914a-914c and transmission lines 918a-918c, and control circuitry 902 configured to provide delay code 928 to delay elements 914a-914c to control the delay of delay elements 914a-914c.

[0108] During a read operation where memory device 926 provides data read from memory core 908 to processing core 904 via channel 924, latches 912a-912f latch the data stored by memory core 908 in response to a read data strobe signal (read clock 916). Data multiplexers 920a-920c multiplex and latch the data, and provide the multiplexed data to delay elements 914a-914c. 914a-914c delays the multiplexed data signal by the delay code 928 provided by control circuitry 902, and output buffers 910a-910c buffer the delayed data. Memory device 926 provides the buffered data to transmission lines 918a-918c, which transmit data to the computing host 922. Input buffers 906a-906c buffer the data received via transmission lines 918a-918c and provide the buffered data to processing core 904.

[0109] Control circuitry 902 can select delay code 928 to compensate for skew in data transmitted to computing host 922. In some embodiments, control circuitry 902 can perform a calibration operation (e.g., Figure 3 Method 300) determines how much to delay each delay element to reduce skew. For example, the computing host 922 may include Figure 1 The pattern generation circuit 102 and output buffers 104a-104c are included. Output buffers 104a-104c can be electrically connected in parallel with input buffers 906a-906c between the processing core 904 and transmission lines 918a-918c. Therefore, data reads, data writes, and calibration data can all pass through essentially the same channel 924 between the computing host 922 and the memory device 926. Furthermore, the memory device 926 may include circuits electrically connected to transmission lines 160a-160c and 126a-126c. Figure 1 The circuit includes input buffers 106a-106c, sampling circuit 152, clock delay element 128, comparator circuit 156, and pattern generation circuit 110. Furthermore, control circuit 902 can be configured to perform the operations discussed above for control circuit 108.

[0110] Since reading data, writing data, and calibration data can all pass through essentially the same channel 924 between the computing host 922 and the memory device 926, the data provided is... Figure 1 The same delay code 146 of the delay elements 126a-126c (which have been calibrated as discussed above) can also be provided as delay code 928 to delay elements 914a-914c to reduce skew in the data provided to the processing core 904 during read operations.

[0111] In some embodiments, the delay code 928 can be weighted to slightly skew the data provided to the processing core 904. The chosen weights can be small enough that the processing core 904 does not introduce errors when sampling the data. However, a slight skew can reduce crosstalk compared to completely eliminating the crosstalk expected by skew.

[0112] Note that, although Figure 9 This demonstrates the use of per-DQ delay adjustment to reduce read operation skew, but it can achieve the same results as... Figure 5 A similar architecture is used to provide bit-by-bit latency adjustment for read operations. As a non-restrictive example, Figure 7 Method 700 can be used to calibrate such computing systems to reduce skew bit by bit.

[0113] Figure 10 It can be used Figure 1 Electrical system 100 Figure 5 Electrical system 500 and Figure 9 A circuit diagram illustrating an example of an electrically controllable delay element 1000 in a computing system 900. Specifically, the electrically controllable delay element 1000 can be used for delay elements 126a-126c, delay elements 532a-532f, and / or delay elements 914a-914c. The electrically controllable delay element 1000 includes alternating strings of buffers 1012 and multiplexers 1014. In other words, the electrically controllable delay element 1000 includes strings of logic gates connected in series, wherein every other logic gate is a buffer 1012, and every other logic gate is a multiplexer 1014. One input of each multiplexer 1014 can be electrically connected to the input IN of the electrically controllable delay element 1000, and the other input of each multiplexer 1014 can be electrically connected to the output of the preceding buffer 1012. Therefore, all the aforementioned logic gates of the electrically controllable delay element 1000 preceding any given multiplexer 1014 can be bypassed, thereby reducing the total delay of the electrically controllable delay element 1000 by allowing the input of the multiplexer 1014, which is electrically connected to the input IN of the electrically controllable delay element 1000, to pass through. The output of each buffer 1012 preceding one of the multiplexers 1014 can be electrically connected to one of the inputs of the preceding multiplexer 1014, and the input of each buffer 1012 preceding one of the multiplexers 1014 can be electrically connected to the output of the preceding multiplexer 1014.

[0114] The electrically controllable delay element 1000 also includes a delay adjustment terminal 1016, which includes a channel selection input of the multiplexer 1014. The delay adjustment terminal 1016 is configured to receive a delay code 1010 (e.g., from...). Figure 1 Control circuit 108 Figure 5 Control circuit 508 and / or Figure 9The control circuit 902 (control circuit). The total delay of the electrically controllable delay element 1000 relative to the data signal at the output terminal OUT of the electrically controllable delay element 1000 and the input terminal IN of the electrically controllable delay element 1000 can be electrically controlled in response to the delay code 1010.

[0115] In the fine delay portion 1002 of the electrically controllable delay element 1000, the buffer 1012 can be electrically connected between the controllable power supply high-voltage potential node 1006 and the power supply low-voltage potential node 1008. In the fine delay portion 1002, the power supply voltage potential VDL is controlled to achieve small steps between different delays. Control circuitry (e.g., control circuitry 108, 508, 902) can be configured to control the power supply voltage potential VDL. In the coarse delay portion 1004 of the electrically controllable delay element 1000, the buffer 1012 can be electrically connected to a substantially immutable power supply node (not shown). Therefore, the delay caused by the coarse delay portion 1004 can be achieved by the gate itself, with longer steps in delay adjustment compared to that achievable in the fine delay portion 1002.

[0116] Figure 10 The electrically controllable delay element 1000 can provide precise electrically controllable delay. The chip area or "substrate surface" occupied by the electrical system 100 can be relatively small because the logic gates of the electrically controllable delay element 1000 can be implemented using small complementary metal-oxide-semiconductor (CMOS) technology.

[0117] Figure 11 It is possible Figure 1 Electrical system 100 and Figure 5 A circuit diagram illustrating an example of a pattern generation circuit 1100 used in an electrical system 500. Specifically, the pattern generation circuit 1100 can be used for... Figure 1 The pattern generation circuit 102 and the pattern generation circuit 110, and / or Figure 5 Pattern generation circuits 502 and 510 are used. In response to the clock signal CLK, pattern generation circuit 1100 is configured to provide pseudo-random data bits D5F, D5R, D4F, ..., D0R, which can... Figure 1 Data signals 150a-150c and comparison signal 154 (e.g., Figure 2 The comparison signals 210a and 210b) and Figure 5 Data signals 536a-536c and comparison signal 530 (e.g., Figure 6 The comparison signals 602a and 602b are transmitted.

[0118] The pattern generation circuit 1100 includes a chain of linear feedback shift registers (LFSRs), comprising a string of shift registers 1102 scattered with one or more XOR gates 1104. The output of the last shift register 1102 is fed back as an input to the first shift register 1102. The output of each shift register 1102 is configured to provide data bits D5F, D5R, D4F, ..., D0R.

[0119] The pattern generation circuit 1100 is capable of generating pseudo-random data, occupying only a small chip area, and operates solely based on a clock input (CLK). The pseudo-random data generated by the pattern generation circuit 1100 can be suitable for use in electrical systems (e.g., Figure 1 Electrical system 100 Figure 5 Electrical system 500 and Figure 9 The known values ​​of the data signal and comparison signal during the delay and / or duty cycle calibration of the computing system (900).

[0120] Figure 12 This is a flowchart illustrating a method 1200 for calibrating a delay element according to some embodiments. In operation 1202, method 1200 includes providing a delay code to the delay element. As a non-limiting example, the delay code and the delay element may be... Figure 1 The delay code 146 and delay elements 126a-126c shown are... Figure 5 The delay code 526 and delay elements 532a-532f shown, or Figure 9 The delay code 928 and delay elements 914a-914c are shown.

[0121] Examples of the inputs and outputs of the pattern generation circuit 1100 are shown in Table 1 below:

[0122] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 1 0 1 0 1 0 1 0 1 0 1 0 3 1 1 0 1 0 1 0 1 0 1 0 1 4 0 1 1 0 1 0 1 0 1 0 1 0 5 0 0 1 1 0 1 0 1 0 1 0 1 6 0 0 0 1 1 0 1 0 1 0 1 0 7 1 0 0 0 1 1 0 1 0 1 0 1 8 1 1 0 0 0 1 1 0 1 0 1 0 9 0 1 1 0 0 0 1 1 0 1 0 1 10 1 0 1 1 0 0 0 1 1 0 1 0

[0123] Table 1: Inputs and Outputs of Pattern Generation Circuit 1100

[0124] In operation 1204, method 1200 includes delaying a skewed data signal containing known data by an amount indicated by a delay code using a delay element to provide a delayed data signal. In operation 1206, method 1200 includes sampling the delayed data signal, and in operation 1208, method 1200 includes comparing the sampled data signal with known data. As a non-limiting example, methods such as... Figure 11 The LSFR pattern generator of the pattern generation circuit 1100 is used to generate known data.

[0125] In operation 1210, method 1200 includes operations of repeatedly providing (operation 1202), delaying (operation 1204), sampling (operation 1206), and comparing (operation 1208) one or more sets of other delay codes corresponding to other delay amounts. In operation 1212, method 1200 includes selecting a delay code from one or more other delay codes that corresponds to a correct comparison between a sampled data signal and a known data value.

[0126] Figure 13 This is a block diagram of a computing system 1300 according to some embodiments. The computing system 1300 includes one or more processors 1304 operatively coupled to one or more memory devices 1302, one or more non-volatile data storage devices 1310, one or more input devices 1306, and one or more output devices 1308. In some embodiments, the computing system 1300 includes a personal computer (PC), such as a desktop computer, laptop computer, tablet computer, mobile computer (e.g., smartphone, personal digital assistant (PDA), etc.), web server, or other computer device.

[0127] In some embodiments, one or more processors 1304 may include a central processing unit (CPU) or other processors configured to control the computing system 1300. In some embodiments, one or more memory devices 1302 include random access memory (RAM), such as volatile data memory (e.g., dynamic RAM (DRAM), static RAM (SRAM), etc.). In some embodiments, one or more non-volatile data memory devices 1310 include hard disk drives, solid-state drives, flash memory, erasable programmable read-only memory (EPROM), other non-volatile data memory devices, or any combination thereof. In some embodiments, one or more input devices 1306 include a keyboard 1314, a pointing device 1318 (e.g., a mouse, trackpad, etc.), a microphone 1312, a small keypad 1316, a scanner 1320, a camera 1328, other input devices, or any combination thereof. In some embodiments, an output device 1308 includes an electronic display 1322, a speaker 1326, a printer 1324, other output devices, or any combination thereof.

[0128] In some embodiments, the computing system 1300 includes Figure 1 Electrical system 100 Figure 5 Electrical systems 500 and / or Figure 9 The computing system 900. As a non-limiting example, the processor 1304 may include... Figure 1 First device 130 Figure 5 The first device 518 and / or Figure 5 The computing host 922. Also, as a non-limiting example, the memory device 1302 may include... Figure 1 The second device 134 Figure 5 The second device 524 and / or Figure 9 The memory device 926. Therefore, the memory device 1302 can be configured to calibrate the delay and / or duty cycle of signals transmitted between the processor 1304 and the memory device 1302, as discussed with respect to the various embodiments disclosed herein.

[0129] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 14 Non-limiting examples of implementations of the functional elements disclosed herein are shown. In some embodiments, some or all portions of the functional elements disclosed herein may be executed by hardware specifically configured to perform the functional elements.

[0130] Figure 14 This is a block diagram of circuit 1400, which in some embodiments can be used to implement various functions, operations, actions, processes, and / or methods disclosed herein. Circuit 1400 includes one or more processors 1402 (sometimes referred to herein as "processor 1402") operably coupled to one or more data storage devices (sometimes referred to herein as "memory 1404"). Memory 1404 includes machine-executable code 1406 stored thereon, and processor 1402 includes logic circuitry 1408. Machine-executable code 1406 includes information describing functional elements that can be implemented (e.g., executed by) logic circuitry 1408. Logic circuitry 1408 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1406. When executing the functional elements described by machine-executable code 1406, circuit 1400 should be considered as dedicated hardware configured to execute the functional elements disclosed herein. In some embodiments, processor 1402 may be configured to execute the functional elements described by machine executable code 1406 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0131] When implemented by the logic circuitry 1408 of the processor 1402, the machine-executable code 1406 is configured to adapt the processor 1402 to perform the operations of the embodiments disclosed herein. For example, the machine-executable code 1406 may be configured to adapt the processor 1402 to perform... Figure 3 Method 300 Figure 7 Method 700 and / or Figure 12 Method 1200 may be at least a part or all of the method. As another example, machine-executable code 1406 may be configured to adapt processor 1402 to execute code targeting... Figure 1Control circuit 108 Figure 5 Control circuit 508 and / or Figure 9 The control circuit 902 discusses at least some or all of the operations. As a particular non-limiting example, as part of a calibration operation, machine-executable code 1406 may be configured to adapt processor 1402 to sweep delay codes and / or duty cycle codes to calibrate delay elements and / or duty cycle adjustment elements (e.g., input buffers). As another particular non-limiting example, machine-executable code 1406 may be configured to adapt processor 1402 to adjust the delay and / or duty cycle of the data signal DQ in memory read and / or write operations.

[0132] Processor 1402 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer, and a general-purpose computer is configured to perform functional elements corresponding to machine-executable code 1406 (e.g., software code, firmware code, hardware description) associated with embodiments of this disclosure. Note that the general-purpose processor (which may also be referred to herein as a main processor or simply a host) may be a microprocessor, but alternatively, processor 1402 may include any conventional processor, controller, microcontroller, or state machine. Processor 1402 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, a combination of one or more microprocessors with a DSP core, or any other such configuration.

[0133] In some embodiments, memory 1404 includes volatile data memory (e.g., random access memory (RAM)), non-volatile data memory (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), etc.). In some embodiments, processor 1402 and memory 1404 may be implemented as a single device (e.g., a semiconductor device product, a system-on-a-chip (SoC), etc.). In some embodiments, processor 1402 and memory 1404 may be implemented as separate devices.

[0134] In some embodiments, the machine-executable code 1406 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in memory 1404, directly accessed by processor 1402, and executed by processor 1402 using at least logic circuitry 1408. Also as a non-limiting example, the computer-readable instructions may be stored in memory 1404, transferred to a memory device (not shown) for execution, and executed by processor 1402 using at least logic circuitry 1408. Therefore, in some embodiments, logic circuitry 1408 includes electrically configurable logic circuitry 1408.

[0135] In some embodiments, machine-executable code 1406 may describe hardware (e.g., circuitry) to be implemented in logic circuitry 1408 to perform functional elements. This hardware may be described at any level, ranging from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), may be used. As a non-limiting example, Verilog may be used. TM SYSTEMVERILOG TM Or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL) TM ).

[0136] As needed, HDL descriptions can be transformed into descriptions at many other levels of abstraction. As a non-limiting example, a high-level description can be transformed into a logic-level description, such as Register Transfer Language (RTL), gate-level (GL) description, layout-level description, or mask-level description. As a non-limiting example, micro-operations performed by the hardware logic circuitry of logic circuitry 1408 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL, then transformed into a GL description by a synthesis tool, and the GL description can be transformed by a placement and routing tool into a layout-level description corresponding to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic, discrete hardware components, or combinations thereof. Therefore, in some embodiments, machine-executable code 1406 may include HDL, RTL, GL descriptions, mask-level descriptions, other hardware descriptions, or any combination thereof.

[0137] In embodiments where machine-executable code 1406 includes a hardware description (at any level of abstraction), a system (not shown, but including memory 1404) may be configured to implement the hardware description described by machine-executable code 1406. As a non-limiting example, processor 1402 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1408 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 1408. Again, as a non-limiting example, logic circuitry 1408 may include hardwired logic manufactured by a manufacturing system (not shown, but including memory 1404) according to the hardware description of machine-executable code 1406.

[0138] Regardless of whether the machine-executable code 1406 includes computer-readable instructions or a hardware description, when implementing the functional elements of the machine-executable code 1406, the logic circuit 1408 is adapted to execute the functional elements described by the machine-executable code 1406. Note that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0139] As used herein, the terms "module" or "component" can refer to a specific hardware implementation configured to perform the actions of a module or component and / or a software object or software routine that can be stored on and / or executed by the general-purpose hardware of a computing system (e.g., a computer-readable medium, processing device, etc.). In some embodiments, the different components, modules, engines, and services described herein can be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some systems and methods described herein are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0140] As used in this disclosure, the term "combination" referring to multiple elements can include any combination of all elements or any of a variety of different sub-combinations of some elements. For example, the phrase "A, B, C, D or a combination thereof" can refer to any one of A, B, C or D; a combination of each of A, B, C and D; and any sub-combination of A, B, C or D, such as A, B and C; A, B and D; A, C and D; B, C and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0141] The terms used in this disclosure, particularly in the appended claims (e.g., the body of the appended claims), generally refer to “open” terms (e.g., the term “including” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “having at least”, the term “includes” should be interpreted as “including but not limited to”, etc.).

[0142] Furthermore, if a specific number of introduced claim statements are required, such intent will be explicitly stated in the claims, and if no such statements are present, such intent does not exist. For example, to aid understanding, the appended claims may use the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that introducing a claim statement with the indefinite article “a” limits any particular claim containing such an introduced claim statement to an embodiment containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” (e.g., “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce claim statements.

[0143] Furthermore, even if a specific number of the introduced claims are explicitly stated, it should be understood that such a statement should be interpreted as meaning at least the number stated (e.g., simply stating "two statements" without other modifiers means at least two statements or two or more statements). Moreover, in cases where conventions similar to "at least one of A, B, and C" or "one or more of A, B, and C" are used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0144] Furthermore, any transitional words or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to include the possibility of including one, any, or both of these terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0145] While this disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications can be made to the illustrated and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being covered within the scope of this disclosure as desired by the inventors.

Claims

1. A device for controlling delay, comprising: A delay element, at least one of which includes an alternating string of a buffer and a multiplexer, the delay element comprising: The data input terminal is configured to receive a skew data signal; A delay adjustment terminal, configured to receive a delay code indicating the amount of delay; and A data output terminal is configured to provide a delayed data signal in response to the skew data signal, the delayed data signal being delayed by the delay element relative to the skew data signal by the delay amount indicated by the delay code; as well as A control circuit electrically connected to the delay adjustment terminal is configured to provide the delay code to the delay adjustment terminal and select the delay code to reduce the timing skew of the delayed data signal relative to the timing skew of the skewed data signal.

2. The device of claim 1, further comprising a sampling circuit electrically connected to the data output terminal, the sampling circuit being configured to sample the delayed data signal.

3. The device of claim 2, wherein the sampling circuit includes a latch configured to latch the delayed data signal in response to a clock signal.

4. The apparatus of claim 2, further comprising a comparator circuit configured to compare the sampled delayed data signal with a known data value of the skew data signal in response to different delay codes corresponding to different delay amounts, to calibrate the different delay amounts.

5. The device of claim 4, further comprising a pattern generation circuit, the pattern generation circuit being configured to: Generate the known data values; and The known data value is provided to the comparator circuit.

6. The device of claim 5, wherein the pattern generation circuit comprises a shift register string with one or more XOR gates distributed throughout.

7. The device of claim 1, comprising a memory device including the delay element.

8. An electrical system comprising: A first device, the first device including a first input / output terminal configured to provide a data signal, the first device including a computing host; A transmission line electrically connected to the first input / output terminal of the first device, at least one of the transmission lines having an associated transmission delay that is different from one or more other transmission delays associated with one or more other transmission lines; and A second device comprising a memory device configured to operate as a random access memory device for the computing host, the second device comprising: A second input / output terminal is electrically connected to the transmission line and is configured to receive a skewed data signal via the transmission line, the skewed data signal having a skewed timing relative to the data signal. A delay element electrically connected to the second input / output terminal, the delay element being configured to receive the skew data signal and provide a delayed data signal, in response to a delay code provided to the delay element, the delay associated with the delay element being electrically controllable; A read delay element electrically connected to the second input / output terminal, the read delay element being configured to provide a delayed read data signal, the delayed read data signal including data read from the memory core of the memory device; as well as A control circuit configured to provide the delay code to the delay element and a read delay code to the read delay element, select the delay code to reduce the skew timing of the delayed data signal relative to the skew timing of the skewed data signal, and select the read delay code to reduce the skew of the read data provided to the computing host in response to the delayed read data signal.

9. The electrical system of claim 8, wherein the control circuit is configured to select the delay code to reduce the skew timing of the delayed data signal compared to the skew timing of the skew data signal received by the delay element.

10. The electrical system of claim 8, wherein at least one of the delay elements comprises an alternating string of buffers and multiplexers.

11. The electrical system of claim 8, wherein the data signal includes a data signal for a memory write operation.

12. The electrical system of claim 8, wherein the control circuit is configured to select the read delay code to introduce sufficient skew into the delayed read data signal to reduce crosstalk between signals transmitted through the transmission line.

13. The electrical system of claim 8, wherein the second device includes an input buffer electrically connected between the second input / output terminal and the delay element.

14. The electrical system of claim 13, wherein the control circuit is configured to provide a duty cycle code to the input buffer to adjust the duty cycle of the skew data signal.

15. The electrical system according to claim 8, wherein: The first device further includes a pattern generation circuit configured to generate a pattern for the data signal; The second device further includes: A pattern generation circuit, configured to generate a pattern for a comparison signal; and A comparator circuit configured to compare the delayed data signal with the comparison signal; The control circuit is configured to calibrate the delay code in response to a comparison performed by the comparator circuit.

16. The electrical system of claim 15, wherein the control circuit is configured to calibrate the delay code by applying different delay codes to the delay element and selecting a delay code corresponding to the correct comparison between the delayed data signal and the comparison signal.

17. A method for calibrating a delay element, the method comprising: Delay codes are provided to delay elements, at least one of which includes an alternating string of buffers and multiplexers; The delay element delays the skewed data signal containing known data values ​​by the amount of delay indicated by the delay code to provide a delayed data signal; The delayed data signal is sampled; The sampled delayed data signal is compared with the known data value; Repeat the provided, delayed, sampled, and compared operations for one or more other sets of delay codes corresponding to other delay amounts; and The delay code is selected from the delay code and one or more other delay codes that correspond to the correct comparison between the sampled delayed data signal and the known data value.

18. The method of claim 17, further comprising delaying the memory write data signal by the delay element by a selected delay amount corresponding to the selected delay code.

19. The method of claim 18, further comprising delaying the memory read data signal by a selected delay amount corresponding to the selected delay code by a read delay element.

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