light sleep power state

Abstract

This application is directed to a light sleep power state. A memory system can include a memory array and a controller. The memory system can transition from a first power state having a first current to a second power state having a second current that is less than the first current, where the first power state is associated with executing a received command and the second power state is associated with deactivating one or more components of the memory array. The memory system can initiate a timer after transitioning from the first power state to the second power state. The memory system can determine that the timer satisfies a threshold, and based on the timer satisfying the threshold, transition from the second power state to a third power state having a third current that is less than the second current.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 648,394, entitled “Shalllow Hibernate Power State,” filed January 19, 2022, and U.S. Provisional Patent Application No. 63 / 162,140, ​​entitled “Shalllow Hibernate Power State,” filed March 17, 2021, each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to shallow sleep power states. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and so on. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless they are periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time, even in the absence of an external power supply. Summary of the Invention

[0006] Describe a device. In some instances, the device may include a memory array and a controller coupled to the memory array, the controller being configured to cause the device to: transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command and the second power state is associated with deactivating one or more components associated with the memory array; initiate a timer at least in part based on the transition from the first power state to the second power state; determine, at least in part based on the initiation of the timer, that the timer satisfies a threshold; and transition from the second power state to a third power state having a third current lower than the second current, at least in part based on the determination that the timer satisfies the threshold.

[0007] A non-transitory computer-readable medium storing code is described. In some instances, the non-transitory computer-readable medium storing code may include instructions that, when executed by a processor of an electronic device, cause the electronic device to: transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command and the second power state is associated with deactivating one or more components associated with a memory array; initiate a timer at least in part based on the transition from the first power state to the second power state; determine, at least in part based on the initiation of the timer, that the timer satisfies a threshold; and transition from the second power state to a third power state having a third current lower than the second current, at least in part based on the determination that the timer satisfies the threshold.

[0008] Describe a method. In some instances, the method may include: transitioning from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command, and the second power state is associated with deactivating one or more components associated with a memory array; initiating a timer at least in part based on the transition from the first power state to the second power state; determining, at least in part based on the initiation of the timer, that the timer satisfies a threshold; and transitioning from the second power state to a third power state having a third current lower than the second current, at least in part based on the determination that the timer satisfies the threshold. Attached Figure Description

[0009] Figure 1 Examples of systems supporting shallow sleep power states are shown, based on the examples disclosed herein.

[0010] Figure 2An example of a state diagram supporting shallow sleep power states is shown, based on the examples disclosed herein.

[0011] Figure 3 An example of a timing diagram supporting shallow sleep power states is shown, based on the examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system supporting shallow sleep power states according to the examples disclosed herein is shown.

[0013] Figure 5 The flowcharts shown below illustrate one or more methods for supporting shallow sleep power states, based on examples disclosed herein. Detailed Implementation

[0014] A system may include a memory system and a host system coupled to the memory system. The host system may transmit commands to the memory system. In some instances, the memory system may be in a first power state, such as an operational power state, where the memory system can utilize a relatively high amount of power to perform operations received from the host system or background operations associated with commands. Some host systems have procedures for conserving power in response to the host system not being operational. In some instances, the host system may be in an idle state and may prevent the transmission of any commands to the memory system; for example, the host system may not perform any operations. In such instances, the memory system may transition from the first power state to a second power state that consumes less power than the first power state; for example, the memory system may transition to the second power state to conserve power in response to the absence of commands from the host system (e.g., the command queue of the memory system is empty). Some systems are battery powered, such that both the host system and the memory system are battery powered. In such systems, reducing power consumption in the host system and the memory system can provide benefits to the user and extend the overall battery life of the system. In some instances, the host system can enter a sleep mode; for example, the host system can enter a low-power mode that reduces its power consumption while still retaining data. In such instances, the memory system can transition to a third state that consumes less power than the first and second power states; for example, the memory system can enter a power-saving mode in response to the host system being in sleep mode.

[0015] In some cases, the host system can enter idle mode for a relatively long period, for example, a few seconds. In such instances, the memory system may consume excess power by remaining in the second power state for the entire duration of the host system's idle mode. For example, if the idle mode duration is relatively long, the memory system could save more power by transitioning to the third power state instead of the second power state. In other instances, the host system can enter idle mode for a relatively short period, for example, a few microseconds. In such instances, the memory system may have reduced latency by remaining in the second power state. For example, if the memory system transitions to the third power state instead of the second power state while the host system is idle, the memory system might take longer to transition back to the first power state and become active. In other words, a trade-off may exist between power consumption and latency in response to the memory system being in the second or third power state.

[0016] In response to the host system being idle, it may be desirable for the memory system to operate in an intermediate power state (e.g., a third power state). An intermediate power state allows the memory system to conserve power while still responding to host commands for a relatively short period. In some cases, an intermediate power state may include clock strobing, deactivating some oscillators, and putting the memory system's cache memory to sleep.

[0017] This document describes systems, techniques, and apparatuses for dynamically transitioning a memory system between various power consumption states (e.g., voltage or level) based on host system performance, link speed, or host system configuration. For example, a memory system may transition from a first power state to a second power state in response to a host system being in an idle mode. The memory system may then initiate a first timer and transition to a fourth power state (e.g., a power state between the second and third power states) in response to the timer satisfying a first threshold. The memory system may then initiate a second timer and transition to a third power state in response to the second timer satisfying a second threshold. In some cases, the memory system may configure the first and second thresholds based on host system performance, link speed, or host system requests. By dynamically transitioning between the second, third, and fourth power states, the memory system can reduce power consumption and latency. For example, the memory system can reduce latency and can quickly transition from the second or fourth power state to the first power state in response to the host system rapidly exiting the idle mode. In other instances, the memory system can save power by transitioning to the third power state in response to the host system being in an idle mode for a relatively long time.

[0018] The features of this disclosure are firstly in reference to Figure 1 The features of this disclosure are described in the context of systems, devices, and circuits. Figure 2 and 3 The state diagrams and timing diagrams are described in the context of this disclosure. These and other features of this disclosure are further supported by references to... Figure 4 and 5 The device diagrams and flowcharts for the shallow sleep power state are shown and described in the context of the device diagrams and flowcharts.

[0019] Figure 1 An example of a system 100 supporting a shallow sleep power state is shown, according to the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0021] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0022] System 100 may include a host system 105 that can be coupled to memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an instance of a controller or control component configured to cause host system 105 to perform various operations according to instances described herein. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more chips, one or more caches (e.g., memory local to host system 105 or included in host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 105 may use memory system 110, for example, to write data to memory system 110 and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0023] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., exchanging or otherwise transmitting control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interfaces, Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM socket interfaces), Open NAND Flash Interface (ONFI), and Low Power Double Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in host system controller 106 of host system 105 and memory system controller 115 of memory system 110 or otherwise supported between them. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110 or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0024] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, if the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0025] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a controller or control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130, and other such operations, which may be collectively referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0026] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0027] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations described herein belonging to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry system.

[0028] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory capable of storing operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory available for internal storage or computation by the memory system controller 115, for example, internal storage or computation related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may be used as a cache for the memory system controller 115. For example, depending on the caching strategy, if data is read from or written to memory device 130, then data may be stored in local memory 120, and the data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 (e.g., reduced latency relative to memory device 130).

[0029] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, which perform the functions described herein as belonging to memory system controller 115. Generally, in some cases, one or more functions described herein as belonging to memory system controller 115 may actually be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130 that is at least partially managed by memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0030] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Alternatively or additionally, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0031] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that can operate on one or more memory cells of the respective memory device 130. The local controller 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein. For example, as Figure 1 As shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0032] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a single piece of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0033] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information. If each cell is configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if each cell is configured to store three bits of information, it may be referred to as a three-level cell (TLC); if each cell is configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density than SLC memory cells, but in some cases, this may involve narrower read or write margins or greater complexity in supporting circuitry.

[0034] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may have one or more limitations, such as the same operation being performed on memory cells within different pages 175 that have the same page address within the respective plane 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0035] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may be alternatively referred to as a bit line) (e.g., coupled thereto).

[0036] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but can be erased at a second granularity level (e.g., at the block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., partially parallel programmed or read as a single programming or read operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., partially parallel erased as a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, used page 175 may not be updated until the entire block 170 containing page 175 is erased.

[0037] System 100 may include any number of non-transitory computer-readable media that support shallow sleep power states. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions described herein that pertain to host system 105, memory system controller 115, or memory device 130. For example, such instructions, when executed by host system 105 (e.g., host system controller 106), memory system controller 115, or memory device 130 (e.g., local controller 135), may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions described herein.

[0038] In some cases, memory system 110 may use memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0039] In some instances, the memory system 110 may utilize multiple power states depending on the commands and instructions received from the host system 105. For example, while executing a command received from the host system 105, the memory system 110 may be in an active mode with components active. In other instances, based on a sleep process initiated by the host system, the memory system 110 may be in a power-saving state; for example, the host system 105 may reduce power consumption and deactivate power to peripheral components. In other instances, based on the host system 105 being idle—e.g., not being used by a program or user—the memory system 110 may be in an intermediate power state. Compared to a power-saving mode, the memory system 110 can transition back to an active mode from an intermediate power mode more quickly, but it may also consume more power in an intermediate power mode compared to a power-saving mode. In other words, the memory system can undergo a trade-off between power consumption and latency.

[0040] As described herein, when host system 105 is idle, memory system 110 may utilize dynamic power states based on host system 105 performance and power targets. For example, memory system 110 may transition to a first power state in response to host system 105 entering an idle state. Memory system 110 may initiate a first timer upon entering the first power state and transition to a second power state with lower current in response to the first timer satisfying a first threshold. In some instances, memory system 110 may initiate a second timer upon entering the second power state and transition to a third power state with current lower than that of the second power state in response to the timer satisfying a second threshold. That is, the memory system may gradually transition to a third power state mode associated with the power-saving mode of memory system 110. This allows memory system 110 to quickly transition back to an active mode in response to commands received while memory system 110 is in the first and second power modes, while also allowing memory system 110 to conserve power in the third power state; for example, memory system 110 may conserve power during long idle periods while maintaining performance during shorter idle periods.

[0041] Figure 2 An example of a state diagram 200 supporting shallow sleep power states is shown, according to the examples disclosed herein. State diagram 200 may illustrate memory systems that can be employed and transition therebetween (e.g., reference...). Figure 1 The possible power states of the described memory system 110. In some instances, the state diagram may be an example of a power mode state machine of a UFS device. State diagram 200 shows power states such as power on 205, active 210, before sleep 215, idle 220, sleep 225, before active 230, before power off 235, power off 240, and hibernation 245. In some instances, state diagram 200 may show the possible power states of a UFS memory system.

[0042] In some instances, the memory system may be configured to be in a powered-on state 205. The memory system may initiate an initialization process in response to being in the powered-on state 205. For example, the memory system may respond to power supply coupling with the memory system—for example, in response to the host system (e.g., reference...). Figure 1 The described host system 105) activates the memory system—thus entering a power-on state 205. In such instances, the memory system may begin initializing the memory device (e.g., refer to...). Figure 1 The described memory device 130 is provided for use. In some instances, the memory system may transition to the active state 210 after completing the initialization process in the power-on state 205.

[0043] In some cases, the memory system may be configured to be in an active state 210. For example, the memory system may execute commands received from the host system or background operations associated with data maintenance. In some cases, while in active state 210, the memory system may be supplied with a relatively high amount of power; for example, the host system may provide maximum power to the memory system while it is in active state 210. In some instances, the memory system may transition from active state 210 to a pre-sleep state 215, an idle state 220, or a pre-power-off state 240.

[0044] In some instances, the memory system may be configured to be in a pre-sleep state 215. The memory system may begin transitioning to a sleep state 225 in response to being in the pre-sleep state 215. For example, the memory system may begin powering off components, such as by stopping the memory system controller (e.g., reference...). Figure 1 The clock in the described memory system controller 115. In some instances, the memory system may transition from active state 210 to pre-sleep state 215 based on receiving a Start Stop Unit (SSU) command—for example, a command from the UFS protocol. In other instances, the memory system may transition from active state 210 to pre-sleep state 215 based on reading a value from a register—for example, reading zero (0) in the bInitpowermode field of a register. The memory system may transition to sleep state 225 after completing the transition in pre-sleep state 215, or transition from pre-sleep state 215 to active state 230 based on receiving an SSU command.

[0045] In some instances, the memory system may be configured to be in a pre-operation state 230. For example, the memory system may begin to power on components, such as powering on the clock of the memory system controller. In some cases, the memory system may transition to an operational state 210 after completing the operations of the pre-operation state 230.

[0046] In some instances, the memory system may be configured to be in sleep state 225. In some instances, the memory system may consume less power in sleep state 225, for example, by strobing the clock and deactivating the oscillator in the memory system controller. In some instances, the memory system controller may remain powered while in sleep state 225. In some cases, the memory system may transition to pre-operation state 230 based on receiving an SSU command. In some instances, the memory system may be configured to enter hibernation state 245 in response to transitioning from sleep state 225 to pre-operation state 230. In some instances, the memory system may be configured to enter hibernation state 245 in response to being in an idle state.

[0047] In some instances, the memory system may be configured to be in a pre-power-down state 235. For example, the memory system may begin to power down components or transfer data from one location to another in preparation for a power-down state 240, such as transferring data from the memory system controller to the memory device to retain the data. That is, the memory system may transfer data stored in the SRAM of the memory system controller to the memory device. The memory system may transition to the power-down state 240 after performing the operations associated with the pre-power-down state 235.

[0048] In some cases, the memory system can be configured to be in a power-down state 240. For example, in power-down state 240, the memory system can power down the memory system controller, the clock in the memory system, and disconnect logic circuitry (e.g., the CPU). The memory system consumes minimal power in power-down state 240. In some instances, the memory system can transition from power-down state 240 to pre-operation state 230 based on receiving an SSU command. In some instances, the memory system can be configured to enter a hibernation state 245 in response to transitioning from power-down state 240 to pre-operation state 230.

[0049] In other instances, the memory system may be configured to be in an idle state 220. For example, the memory system may be in an idle state in response to no command or operation being executed—for example, after a command received from the host system has ended. The memory system may transition between idle state 220 and active state 210 based on receiving a command or executing an operation. In some cases, the memory system may consume excessive power in idle state 220; for example, the memory system may be in a power state that consumes more power than sleep state 225 or power-off state 240. In other instances, the memory system may have increased latency in response to the transition between idle state 220 and active state 210; for example, the memory system may be in a power state similar to sleep state 225 or power-off state 240 and require a longer time to transition back to active state 210. That is, the memory system may perform the operations of pre-active state 230 and take a longer time to transition between idle state 220 and active state 210 in response to the lower power consumption in idle state 220.

[0050] As described herein, the memory system can transition from an idle state 220 to a dynamic sleep state 245. Sleep state 245 may be associated with power consumption lower than that of the active state 210. Sleep state 245 may also cause the memory system to rapidly transition to the active state 210 in response to a relatively short duration of idle state 220. For example, the memory system may be configured to utilize multiple power levels (e.g., voltages) while in sleep state 245. In some instances, the memory system may transition to a lower voltage based on a timer threshold in response to a relatively long duration of idle state 220, as described in the references. Figure 3 As described. In other instances, in response to receiving a new command from the host system, the memory system can remain at a higher voltage, and the memory system can quickly transition back to the active state 210, avoiding additional latency, as described in the reference. Figure 3 As described. By utilizing dynamic sleep states, in response to a shorter duration of idle state 220, the memory system can reduce power consumption and eliminate latency trade-offs.

[0051] Figure 3 An example of timing diagram 300 supporting shallow sleep power states is shown, according to the examples disclosed herein. Timing diagram 300 may be shown in a memory system (e.g., reference 300). Figure 1 The described memory system 110) enters an idle state (e.g., refer to...). Figure 2 The power states (e.g., supply voltage or power level) of the memory system during the described idle state 220. Timing diagram 300 may show a figure 305 of the power consumption of the memory system coupled to the host system. Figure 305 shows the change of power (e.g., y-axis) over time (e.g., x-axis). Timing diagram 300 may also include a figure 305 of the power consumption of the memory system coupled to the host system (e.g., reference). Figure 1 The described host system 105) is associated with state 335 or commands and state 340 of the communication link or conductive path between the memory system and the host system—for example, coupling the memory system and the host system or the memory system controller (e.g., reference). Figure 1 The memory system controller 115 and memory device described herein (e.g., reference 115) and memory device (e.g., reference 115) are described herein. Figure 1 The state of the UniPro interface of the described memory device 130. Timing diagram 300 can show the memory system in a first power state 315, a second power state 320, a third power state 325 and a fourth power state 330.

[0052] At time 345, the host system and communication link may be in an active state, including sending and receiving commands, and the memory system may be in a first power state 315. In some instances, the memory system may be executing commands or operations received from the host system; for example, the memory system may be executing read, write, or refresh commands. In some cases, the first power state 315 may also be referred to as an active state, for example, the memory system may be executing commands and operations. The memory system may also activate some or all of its components during the first power state 315; for example, the memory system controller, clock, oscillator, and logic circuitry may be activated. The memory system may be configured to perform operations and commands using relatively higher current and power amounts in the first power state 315; for example, the memory system may utilize more power to execute commands and operations compared to when in a power-saving mode. For example, the memory system may utilize 180 mA or more current in response to being in the first power state 315. In some instances, the communication link between the host system and the memory system (e.g., a UniPro interface) may also be in an active state.

[0053] At time 350, the host system may transition to an idle state, the communication link may transition to a sleep state, and the memory system may transition to a second power state 320. In some instances, the host system may enter an idle mode. That is, the host system may not initiate any new commands or operations to the memory system; for example, the host system may not be used by a program or user. In such instances, the communication link between the host system and the memory system may be in a sleep state, for example, a low-power saving mode or a mode in which the communication link saves power until a new command is issued. In some cases, based on the detection that the host system and the communication link are in idle and sleep states respectively, the memory system may transition from a first power state 315 to a second power state 320; for example, the memory system controller may detect no incoming commands and transition to the second power state 320 based on the absence of incoming commands. In some instances, the second power state 320 may have a lower current than the first power state 315 and may be an instance of an L1 power state; for example, the memory system may utilize less power in the second power state 320. For example, the memory system controller may initiate clock strobing in the second power state 320, for instance, the memory system may decouple the clock signal from the memory system controller to reduce power consumption. In such instances, the memory system may utilize less current in the second power state 320 than in the first power state 315, for example, 60 mA in the second power state 320. The memory system controller may also initiate a first timer in response to the transition from the first power state 315 to the second power state 320. That is, the first timer may determine the duration of the second power state 320. In some instances, the memory system may receive commands from the host system while in the second power state 320. That is, although not shown in timing diagram 300, in some instances, the host system may have a short idle period and initiate commands while the memory system is in the second power state 320. In such instances, the memory system may transition back to the first power state 315 and execute the commands.

[0054] At time 355, the memory system may be in a third power state 325 (which may be an example of an intermediate power state as described herein). In some instances, the memory system controller may determine that a first timer satisfies a first threshold. In such instances, the memory system controller may transition from a second power state 320 to a third power state 325. In some cases, the first threshold for entering the third power state 325 may be configurable. For example, the memory system may configure the first threshold based on host performance targets (e.g., power performance targets) or link communication targets (e.g., link speed). That is, if host performance or link communication targets (e.g., the expected latency for the memory system to execute a command after the host system issues a command) are high, the memory system controller may configure a longer first threshold, and if host performance or link communication targets are low, a shorter first threshold may be configured. For example, if a command is received from the host system and the performance target is high, the memory system may remain in the second power state 320 for a longer period to transition to the first power state 315 more quickly. The first threshold may be between zero (0) and five (5) microseconds (μs). In some instances, the third power state 325 may consume less power than the second power state 320 and may be an instance of an L1.5 power state. In some instances, the memory system may transition the SRAM memory in the memory system controller to a sleep mode when in the third power state 325. The sleep mode of the SRAM may be a state in which data is retained but other operations are not available. Additionally, as part of the third power state, in addition to transitioning the SRAM to a sleep state, the memory system may initiate a clock strobe and deactivate one or more oscillators. In such instances, the memory system controller may utilize less current in the third power state 325 than in the second power state 320, for example, one (1) microampere (1 μA).

[0055] In some instances, the memory system controller may also initiate a second timer in response to a transition to a third power state 325. For example, the second timer may be used to define the length of time spent in the third power state 325 before transitioning to a lower power state, such as a fourth power state 330 where the SRAM is powered off. In some instances, the memory system may receive commands from the host system while in the third power state 325. That is, although not shown in timing diagram 300, in some instances, the host system may have a short idle period and initiate commands while the memory system is in the third power state 325. In such instances, the memory system may transition back to the first power state 315 and execute the commands.

[0056] At time 360, the memory system controller may be in a fourth power state 330. In some instances, the memory system controller may enter the fourth power state based on determining that a second timer meets a second threshold. In such instances, the memory system controller may transition from a third power state 325 to the fourth power state 330. In some cases, the second threshold may be configurable. For example, the memory system may configure the second threshold based on host performance targets (e.g., power performance targets) or link communication targets (e.g., link speed). That is, if the host performance or link communication target is high, the memory system controller may configure a longer second threshold, and if the host performance or link communication target is low, a shorter second threshold may be configured. For example, if a command is received from the host system and the performance target is high, the memory system may remain in the third power state 325 for a longer time to transition to the first power state 315 more quickly. In some instances, the memory system may also configure the second timer based on a value read from a register written by the host system. For example, the host system may determine the duration of the second threshold and write a value indicating the duration to the memory system into a register. In some cases, the host system may completely disable the second timer. In such instances, the memory system can transition directly from the second power state 320 to the fourth power state 330; for example, the memory system controller can transition from the second power state 320 to the fourth power state 330 at time 355. An example of the second threshold could be 100 microseconds (ms).

[0057] In some instances, the fourth power state 330 may consume less power than the third power state 325 and may be an instance of an L2 power state. In some instances, the memory system may transition the SRAM of the memory system to a power-down state. Before powering down the SRAM (e.g., cache memory), the memory system may transfer any information in the SRAM to the NAND. Subsequently, in response to exiting the fourth power state 330, the memory system may transfer the stored data from the NAND back to the SRAM. Thus, if the host system sends a command while the memory system is in the fourth power state 330, the time before the command is executed may be longer due to the transfer of information from the NAND to the SRAM. Alternatively or concurrently, in addition to transitioning the memory system controller to a power-down mode, the memory system may initiate a clock strobe and deactivate the oscillator. In some cases, the memory system may also deactivate logic circuitry in the memory system controller (e.g., deactivate the CPU). In some cases, the memory system controller may utilize less current in the fourth power state 330 than in the third power state 325, for example, 0.3 microamps (1 μA).

[0058] In some instances, the memory system can receive commands from the host system while in the fourth power state 330. That is, although not shown in timing diagram 300, in some instances, the host system can terminate idle cycles and initiate commands when the memory system is in the fourth power state 330. In such instances, the memory system can transition back to the first power state 315 and execute the commands. That is, the memory system can transfer data back to the memory system controller, couple the clock, and activate the logic circuitry and oscillator.

[0059] At time 365, the host system may transition to an active state for the purpose of entering a sleep state, the communication link may transition to an active state, and the memory system may transition to a first power state 315. In some instances, after an idle duration, the host system may initiate a procedure to transition to sleep mode. That is, the host system may remain unused by programs or users and transition from idle mode to sleep mode to save more power. In such instances, the host system may transmit synchronization cache commands and SSU commands to the memory system. In some cases, the communication link may also transition back to an active state to transmit commands from the host system to the memory system. In some instances, the idle duration may be configured by the host system; for example, the host may dynamically determine the idle period based on performance and power targets. For example, the host system may determine to remain idle for no more than three (3) seconds before transitioning to sleep mode. In response to a command, the memory system may transition from a fourth power state 330 to a first power state 315. That is, the memory system may transmit data back to the memory system controller, couple the clock, and activate the logic circuitry and oscillator. Next, the memory system can execute synchronous cache commands and SSU commands.

[0060] At time 375, the memory system may be in a fifth power state. In some instances, the memory system may transition from a first power state 315 to a fifth power state. The fifth power state may be associated with a power-saving mode of the memory system, for example, the host system may decouple the power supply from components of the memory array or the controller. That is, the host system may deactivate the voltage going to the memory system, for example, by disconnecting the VCC voltage. At time 375, the host system may also transition to a sleep mode, for example, enter a standby mode or a pause mode, and deactivate the power going to peripheral components. In some instances, the communication link may also transition back to a hibernation state at time 375.

[0061] By having dynamic power states, the memory system can balance the trade-off between power savings and increased latency. That is, the memory system can enter a fourth power state 330 to save power consumption, and also utilizes a second power state 320 and a third power state 325 to save power consumption and reduce the latency associated with transitioning to the first power state 315.

[0062] Figure 4 A block diagram 400 illustrates a memory system 420 supporting shallow sleep power states according to an example disclosed herein. The memory system 420 may be a reference... Figures 1 to 3 Examples of aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing the various aspects of the shallow sleep power states described herein. For example, memory system 420 may include power component 430, timer component 435, receiving component 440, execution component 445, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0063] Power component 430 may be configured or otherwise support means for transitioning from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command, and the second power state is associated with deactivating one or more components associated with the memory array. In some instances, power component 430 may be configured or otherwise support means for transitioning from the second power state to a third power state having a third current lower than the second current, at least in part based on determining that a timer satisfies a threshold.

[0064] In some instances, power component 430 may be configured or otherwise support a component for transitioning from a third power state to a fourth power state having a fourth current lower than the third current, at least in part based on determining that a timer satisfies a threshold, wherein the fourth power state is entered when the host system is idle. In some instances, power component 430 may be configured or otherwise support a component for transitioning from a fourth power state to a first power state, at least in part based on receiving a command. In some instances, power component 430 may be configured or otherwise support a component for transitioning from a first power state to a fifth power state having a fifth current equal to or less than the fourth current, at least in part based on executing a command, wherein the fifth power state is associated with a voltage supply to a component of the decoupled memory array or controller. In some instances, power component 430 may be configured or otherwise support a component for transitioning from a fourth power state to a first power state, at least in part based on receiving an access command.

[0065] In some instances, power component 430 may be configured or otherwise support means for transitioning from a first power state to a second power state after a second timer is deactivated. In some instances, power component 430 may be configured or otherwise support means for transitioning from a second power state to a fourth power state, at least in part based on determining that a timer meets a threshold and the second timer is deactivated. In some instances, to support the transition from the first power state to the second power state, power component 430 may be configured or otherwise support means for decoupling clock signals from one or more components of the controller.

[0066] In some instances, to support the transition from a first power state to a third power state, power component 430 may be configured or otherwise support components for: decoupling a clock signal from one or more components of the controller, deactivating an oscillator, and putting the device's random access memory to sleep. In some instances, power component 430 may be configured to configure the threshold and the second threshold at least in part based on the device's power performance targets or the device's link targets. In some instances, power component 430 may be configured or otherwise support components for transitioning from a third power state to a first power state at least in part based on receiving an access command. In some instances, power component 430 may associate a fourth power state with an idle state of the host system associated with the device. In some instances, power component 430 may associate the first, second, and third power states with an idle state of the host system associated with the device.

[0067] Timer component 435 may be configured or otherwise support means for initiating a timer at least partially based on a transition from a first power state to a second power state. In some instances, timer component 435 may be configured or otherwise support means for determining, at least partially based on initiating a timer, that a timer meets a threshold. In some instances, timer component 435 may be configured or otherwise support means for initiating a second timer at least partially based on a transition from a second power state to a third power state. In some instances, timer component 435 may be configured or otherwise support means for determining, at least partially based on initiating a second timer, that a second timer meets a second threshold. In some instances, timer component 435 may be configured or otherwise support means for deactivating a second timer at least partially based on reading a value from a register.

[0068] In some instances, timer component 435 may be configured or otherwise supported to include means for initiating a timer at least in part based on a transition from a first power state to a second power state. In some instances, timer component 435 may be configured or otherwise supported to include means for determining whether a timer meets a threshold at least in part based on the initiation of the timer.

[0069] In some instances, the receiving component 440 may be configured or otherwise supported to support means for receiving commands associated with the synchronization cache after a transition from a third power state to a fourth power state. In some instances, the receiving component 440 may be configured or otherwise supported to support means for receiving access commands after a transition from a third power state to a fourth power state. In some instances, the receiving component 440 may be configured or otherwise supported to support means for receiving access commands after a transition from a second power state to a third power state. In some instances, the receiving component 440 may detect no incoming commands during an idle state.

[0070] In some instances, execution component 445 may be configured or otherwise support means for executing commands at least in part based on a transition from a fourth power state to a first power state. In some instances, execution component 445 may be configured or otherwise support means for executing access commands at least in part based on a transition from a fourth power state to a first power state. In some instances, execution component 445 may be configured or otherwise support means for reading values ​​from registers when operating in the first power state. In some instances, to support transitions to the fourth power state, execution component 445 may be configured or otherwise support means for transferring data from the device's random access memory to a memory array and deactivating the random access memory.

[0071] Figure 5 A flowchart illustrating an example disclosed herein demonstrates a method 500 for supporting shallow sleep power states. Operation of method 500 may be implemented by the memory system or its components described herein. For example, operation of method 500 may be provided by reference to... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the function. Alternatively, the memory system may use dedicated hardware to perform aspects of the function.

[0072] At 505, the method may include transitioning from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command, and the second power state is associated with deactivating one or more components associated with the memory array. Operation 505 may be performed according to the examples disclosed herein. In some examples, aspects of operation 505 may be referenced from... Figure 4 The power component 430 described is implemented.

[0073] At 510, the method may include initiating a timer at least in part based on a transition from a first power state to a second power state. Operation 510 may be performed according to the examples disclosed herein. In some instances, aspects of operation 510 may be derived from references... Figure 4 The described timer component 435 is executed.

[0074] At point 515, the method may include determining, at least in part, that a timer satisfies a threshold based on initiating a timer. Operation 515 may be performed according to the examples disclosed herein. In some instances, aspects of operation 515 may be derived from references. Figure 4 The described timer component 435 is executed.

[0075] At 520, the method may include at least in part a transition from a second power state to a third power state having a third current lower than the second current based on determining that a timer satisfies a threshold. Operation 520 may be performed according to the examples disclosed herein. In some instances, aspects of operation 520 may be derived from references... Figure 4 The power component 430 described is implemented.

[0076] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transitioning from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command, and the second power state is associated with deactivating one or more components associated with a memory array; initiating a timer at least in part based on the transition from the first power state to the second power state; determining that a timer meets a threshold at least in part based on the initiation of the timer; and transitioning from the second power state to a third power state having a third current lower than the second current, at least in part based on the determination that the timer meets the threshold.

[0077] Method 500 and some aspects of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: initiating a second timer at least in part based on a transition from a second power state to a third power state; determining that the second timer satisfies a second threshold at least in part based on the initiation of the second timer; and transitioning from the third power state to a fourth power state having a fourth current lower than the third current, at least in part based on the determination that the timer satisfies the threshold, wherein the fourth power state may be entered while the host system may be in an idle state.

[0078] Method 500 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving a command associated with a synchronous cache after transitioning from a third power state to a fourth power state; transitioning from the fourth power state to a first power state at least in part based on receiving the command; executing the command at least in part based on the transition from the fourth power state to the first power state; and transitioning from the first power state to a fifth power state having a fifth current equal to or less than the fourth current at least in part based on executing the command, wherein the fifth power state may be associated with a voltage supply for a component of a decoupled memory array or controller.

[0079] Method 500 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: receiving an access command after transitioning from a third power state to a fourth power state; transitioning from the fourth power state to a first power state at least in part based on receiving the access command; and executing the access command at least in part based on the transition from the fourth power state to the first power state.

[0080] In some cases of method 500 and the devices described herein, the threshold and the second threshold may be configured at least in part based on the power performance target or the link target of the device.

[0081] Method 500 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for reading a value from a register during operation in a first power state and deactivating a second timer at least in part based on the value read from the register.

[0082] Method 500 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for: transitioning from a first power state to a second power state after disabling a second timer; initiating a timer at least in part based on the transition from the first power state to the second power state; determining that a timer meets a threshold at least in part based on the initiation of the timer; and transitioning from the second power state to a fourth power state at least in part based on determining that the timer meets the threshold and disabling the second timer.

[0083] In some cases of method 500 and the device described herein, transitioning to a fourth power state may include operations, features, circuitry, logic, components, or instructions for transferring data from the device’s random access memory to a memory array and deactivating the random access memory.

[0084] In some cases of method 500 and the device described herein, the fourth power state may be associated with the idle state of the host system associated with the device, and the controller detects no incoming commands during the idle state.

[0085] In some instances of method 500 and the device described herein, the transition from a first power state to a second power state may include operations, features, circuitry, logic, components, or instructions for decoupling clock signals from one or more components of the controller.

[0086] In some cases of method 500 and the device described herein, the transition from a first power state to a third power state may include operations, features, circuitry, logic, components, or instructions for: decoupling a clock signal from one or more components of the controller, deactivating an oscillator, and putting the device’s random access memory into a sleep state.

[0087] Method 500 and some examples of the device described herein may further include operations, features, circuitry, logic, components, or instructions for receiving an access command after transitioning from a second power state to a third power state, and transitioning from a third power state to a first power state based at least in part on receiving the access command.

[0088] In method 500 and some instances of the device described herein, the first power state, the second power state, and the third power state may be associated with the idle state of the host system associated with the device.

[0089] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0090] Describe a device. The device may include a memory array and a controller coupled to the memory array, the controller being configured to cause the device to: transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command and the second power state is associated with deactivating one or more components associated with the memory array; initiate a timer at least in part based on the transition from the first power state to the second power state; determine that the timer meets a threshold at least in part based on the initiation of the timer; and transition from the second power state to a third power state having a third current lower than the second current at least in part based on the determination that the timer meets the threshold.

[0091] In some instances, the controller may be further configured to: initiate a second timer at least in part based on a transition from the second power state to the third power state; determine, at least in part based on the initiation of the second timer, that the second timer satisfies a second threshold; and transition from the third power state to a fourth power state having a fourth current lower than the third current, at least in part based on the determination that the timer satisfies the threshold, wherein the fourth power state may be entered while the host system associated with the device may be in an idle state.

[0092] In some cases, the controller may be further configured to: receive a command associated with a synchronous cache after transitioning from the third power state to the fourth power state; transition from the fourth power state to the first power state at least in part based on receiving the command; execute the command at least in part based on the transition from the fourth power state to the first power state; and transition from the first power state to a fifth power state having a fifth current equal to or less than the fourth current at least in part based on executing the command, wherein the fifth power state may be associated with a voltage supply for a component decoupled from the memory array or the controller.

[0093] In some instances, the controller may be further configured to: receive an access command after transitioning from the third power state to the fourth power state; transition from the fourth power state to the first power state at least in part based on receiving the access command; and execute the access command at least in part based on the transition from the fourth power state to the first power state.

[0094] In some instances of the device, the threshold and the second threshold may be configured at least in part based on the device’s power performance target or the device’s link target.

[0095] In some cases, the controller may be further configured to read a value from a register when operating in the first power state, and to disable the second timer at least in part based on the value read from the register.

[0096] In some cases of the device, the controller may be further configured to cause the device to: transition from the first power state to the second power state after the second timer is deactivated; initiate the timer at least in part based on the transition from the first power state to the second power state; determine that the timer satisfies the threshold at least in part based on the initiation of the timer; and transition from the second power state to the fourth power state at least in part based on the determination that the timer satisfies the threshold and the second timer is deactivated.

[0097] In some instances, the controller may be further configured to transition to the fourth power state, transfer data from the device's random access memory to the memory array, and deactivate the random access memory.

[0098] In some cases of the device, the fourth power state may be associated with the idle state of the host system associated with the device, and the controller detects no incoming commands during the idle state.

[0099] In some instances, the controller may be further configured to transition from the first power state to the second power state and decouple the clock signal from one or more components of the memory array.

[0100] In some instances, the controller may be further configured to transition from the first power state to the third power state and decouple the clock signal from one or more components of the memory array, deactivate the oscillator, and put the device's random access memory into a sleep state.

[0101] In some instances, the controller may be further configured to receive an access command after transitioning from the second power state to the third power state, and to transition from the third power state to the first power state at least in part based on receiving the access command.

[0102] In some cases of the device, the first power state, the second power state, and the third power state may be associated with the idle state of the host system associated with the device.

[0103] In some cases, the device may include conductive paths coupled to the memory array and the controller, wherein the first power state, the second power state, and the third power state may be associated with a sleep state of the conductive path.

[0104] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may show a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0105] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that supports the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, the signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0106] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. If, for example, one component of a controller couples other components together, then that component triggers a change that allows signals to flow through conductive paths between those other components, paths that were previously not permitted to allow signal flow.

[0107] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. If there is an open circuit between components, they are isolated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller achieves the following change: preventing signals from flowing between the components using previously permitted conductive paths.

[0108] The terms “if,” “when,” “based on,” or “at least partially based on” are used interchangeably. In some instances, the terms “if,” “when,” “based on,” or “at least partially based on” are used to describe a connection between conditional actions, conditional processes, or parts of a process.

[0109] The term "in response to" can refer to a condition or action that occurs at least partially (if not completely) as a result of a prior condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the prior condition or action (whether directly after the first condition or action or after one or more other intermediate conditions or actions following the first condition or action).

[0110] Additionally, the terms "directly in response to" or "directly in response to" can refer to a condition or action that occurs as a direct result of a preceding condition or action. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a preceding condition or action that is independent of whether other conditions or actions occur. In some instances, a first condition or action may be performed, and a second condition or action may occur directly as a result of a preceding condition or action, such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being performed "based on," "at least in part based on," or "in response to" a certain other step, action, event, or condition may additionally or alternatively (e.g., in alternative instances) be performed "directly in response to" or "directly in response to" such other condition or action.

[0111] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals containing (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0112] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. Terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0113] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "advantageous" over other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0114] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral to differentiate them. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0115] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that different parts of the functions are implemented in different physical locations.

[0116] For example, the various illustrative blocks and components described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0117] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0118] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0119] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, the invention is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: Memory array; as well as A controller coupled to the memory array, the controller being configured to cause the memory system to: Read values ​​from registers when operating in the first power state; as well as The first timer is disabled, at least in part, based on reading the value from the register. The transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command, and the second power state is associated with deactivating one or more components associated with the memory array; A second timer is initiated, at least in part, based on the transition from the first power state to the second power state; The determination of whether the second timer meets a threshold is based at least in part on initiating the second timer, wherein the threshold can be configured at least in part based on the power performance target of the memory system or the link target of the memory system; as well as The transition from the second power state to a third power state with a third current lower than the second current is based at least in part on determining that the second timer meets the threshold.

2. The memory system of claim 1, wherein the controller is further configured to cause the memory system to: The first timer is initiated at least in part based on the transition from the second power state to the third power state; At least in part based on initiating the first timer, determining that the first timer satisfies the second threshold; and The transition from the third power state to a fourth power state with a fourth current lower than the third current is based at least in part on determining that the first timer satisfies the second threshold, wherein the fourth power state is entered when the host system associated with the memory system is in an idle state.

3. The memory system of claim 2, wherein the controller is further configured to cause the memory system to: After transitioning from the third power state to the fourth power state, a command associated with the synchronization cache is received; The transition from the fourth power state to the first power state is based at least in part on receiving the command; The command is executed at least in part based on the transition from the fourth power state to the first power state; as well as At least in part, based on executing the command, the transition from the first power state to a fifth power state having a fifth current equal to or less than the fourth current, wherein the fifth power state is associated with a voltage supply for a component decoupled from the memory array or the controller.

4. The memory system of claim 2, wherein the controller is further configured to cause the memory system to: After transitioning from the third power state to the fourth power state, an access command is received; The transition from the fourth power state to the first power state is based at least in part on receiving the access command; and The access command is executed at least in part based on the transition from the fourth power state to the first power state.

5. The memory system of claim 2, wherein the second threshold can be configured at least in part based on the power performance target of the memory system or the link target of the memory system.

6. The memory system of claim 1, wherein the controller is further configured to cause the memory system to: After the first timer is deactivated, the system transitions from the first power state to the second power state. The second timer is initiated at least in part based on the transition from the first power state to the second power state; and The threshold is determined, at least in part, based on the initiation of the second timer.

7. The memory system of claim 2, wherein transitioning to the fourth power state comprises transferring data from the random access memory of the memory system to the memory array and deactivating the random access memory.

8. The memory system according to claim 2, wherein: The fourth power state is associated with the idle state of the host system linked to the memory system; and The controller detects no incoming commands during the idle state.

9. The memory system of claim 1, wherein the second power state includes decoupling the clock signal from one or more components of the controller.

10. The memory system of claim 1, wherein the transition from the first power state to the third power state comprises decoupling the clock signal from one or more components of the controller, deactivating the oscillator, and putting the random access memory of the memory system into a sleep state.

11. The memory system of claim 1, wherein the controller is further configured to cause the memory system to: After transitioning from the second power state to the third power state, an access command is received; and The transition from the third power state to the first power state is based at least in part on receiving the access command.

12. The memory system of claim 1, wherein the second power state and the third power state are associated with an idle state of a host system connected to the memory system.

13. The memory system of claim 1, further comprising: A conductive path coupled to the memory array and the controller, wherein the first power state, the second power state, and the third power state are associated with a sleep state of the conductive path.

14. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Read values ​​from registers when operating in the first power state; and The first timer is disabled, at least in part, based on reading the value from the register. The transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command and the second power state is associated with deactivating one or more components associated with the memory array. A second timer is initiated, at least in part, based on the transition from the first power state to the second power state; At least in part based on initiating the second timer, determining that the second timer meets a threshold, wherein the threshold can be configured at least in part based on the power performance target of the electronic device or the link target of the electronic device; and The transition from the second power state to a third power state with a third current lower than the second current is based at least in part on determining that the second timer meets the threshold.

15. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The first timer is initiated at least in part based on the transition from the second power state to the third power state; At least in part based on initiating the first timer, determining that the first timer satisfies the second threshold; and At least in part, based on determining that the first timer satisfies the second threshold, the third power state transitions to a fourth power state having a fourth current lower than the third current, wherein the fourth power state is entered when the host system is in an idle state.

16. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After transitioning from the third power state to the fourth power state, a command associated with the synchronization cache is received; The transition from the fourth power state to the first power state is based at least in part on receiving the command; The command is executed at least in part based on the transition from the fourth power state to the first power state; as well as At least in part, based on executing the command, the transition from the first power state to a fifth power state having a fifth current equal to or less than the fourth current, wherein the fifth power state is associated with a supplier of component voltages decoupled from the memory array or the controller coupled to the memory array.

17. The non-transitory computer-readable medium of claim 15, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After transitioning from the third power state to the fourth power state, an access command is received; The transition from the fourth power state to the first power state is based at least in part on receiving the access command; and The access command is executed at least in part based on the transition from the fourth power state to the first power state.

18. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After the first timer is deactivated, the system transitions from the first power state to the second power state. The second timer is initiated at least in part based on the transition from the first power state to the second power state; and The threshold is determined, at least in part, based on the initiation of the second timer.

19. The non-transitory computer-readable medium of claim 14, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: After transitioning from the second power state to the third power state, an access command is received; and The transition from the third power state to the first power state is based at least in part on receiving the access command.

20. A method for memory operations, comprising: Read values ​​from registers when operating in the first power state; as well as The first timer is disabled, at least in part, based on reading the value from the register. The transition from a first power state having a first current to a second power state having a second current lower than the first current, wherein the first power state is associated with executing a received command and the second power state is associated with deactivating one or more components associated with the memory array. A second timer is initiated, at least in part, based on the transition from the first power state to the second power state; At least in part based on initiating the second timer, determining that the second timer meets a threshold, wherein the threshold can be configured at least in part based on a power performance target or a link target; and The transition from the second power state to a third power state with a third current lower than the second current is based at least in part on determining that the second timer meets the threshold.

21. The method of claim 20, further comprising: The first timer is initiated at least in part based on the transition from the second power state to the third power state; At least in part based on initiating the first timer, determining that the first timer satisfies the second threshold; and At least in part, based on determining that the first timer satisfies the second threshold, the third power state transitions to a fourth power state having a fourth current lower than the third current, wherein the fourth power state is entered when the host system is in an idle state.

22. The method of claim 21, further comprising: After transitioning from the third power state to the fourth power state, a command associated with the synchronization cache is received; The transition from the fourth power state to the first power state is based at least in part on receiving the command; The command is executed at least in part based on the transition from the fourth power state to the first power state; as well as At least in part, based on executing the command, the power state transitions from the first power state to a fifth power state having a fifth current equal to or less than the fourth current, wherein the fifth power state is associated with a voltage supply decoupled from the memory array.

23. The method of claim 21, further comprising: After transitioning from the third power state to the fourth power state, an access command is received; The transition from the fourth power state to the first power state is based at least in part on receiving the access command; and The access command is executed at least in part based on the transition from the fourth power state to the first power state.

24. The method of claim 20, wherein the third power state includes decoupling the clock signal from one or more components of the controller, deactivating the oscillator, and putting the random access memory of the memory system into a sleep state.

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