Semiconductor manufacturing method and semiconductor manufacturing apparatus
By using alternating aminosilane-based and non-aminosilane-based gases to form seed layers and amorphous silicon layers in semiconductor manufacturing, and by controlling temperature and pressure, polycrystallineization of amorphous silicon was suppressed, and appropriate monocrystallineization was achieved. This solved the problem of amorphous silicon hindering monocrystallineization in the MILC method and improved semiconductor manufacturing efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2021-08-18
- Publication Date
- 2026-06-16
Smart Images
Figure CN115116823B_ABST
Abstract
Description
[0001] Related applications
[0002] This application enjoys priority based on Japanese Patent Application No. 2021-044822 (filed on March 18, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field
[0003] This embodiment relates to a semiconductor manufacturing method and a semiconductor manufacturing apparatus. Background Technology
[0004] In the manufacture of semiconductor memory devices, when using the MILC (Metal-induced Lateral Crystallization) method to crystallize amorphous silicon in memory holes, the crystallization process is sometimes hindered by the polycrystallization of amorphous silicon. Summary of the Invention
[0005] The problem to be solved by the present invention is to provide a semiconductor manufacturing method and semiconductor manufacturing apparatus that enables amorphous silicon to be appropriately monocrystalline.
[0006] The semiconductor manufacturing method of the embodiments includes forming a first seed layer on a substrate layer using an aminosilane-based first gas. The method further includes forming a first amorphous silicon layer on the first seed layer using an amino-free silane-based second gas. The method further includes forming a second seed layer containing impurities on the first amorphous silicon layer using an aminosilane-based third gas. The method further includes forming a second amorphous silicon layer on the second seed layer using an amino-free silane-based fourth gas. Attached Figure Description
[0007] Figure 1 This is a diagram showing a semiconductor manufacturing apparatus according to the first embodiment.
[0008] Figure 2 This is a flowchart illustrating the semiconductor manufacturing method of the first embodiment.
[0009] Figure 3 This is a cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0010] Figure 4 It continues Figure 3 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0011] Figure 5 It continues Figure 4 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0012] Figure 6It continues Figure 5 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0013] Figure 7 It continues Figure 6 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0014] Figure 8 It continues Figure 7 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0015] Figure 9 It continues Figure 8 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0016] Figure 10 It continues Figure 9 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0017] Figure 11 It continues Figure 10 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0018] Figure 12 This is a diagram illustrating a semiconductor manufacturing apparatus according to the second embodiment.
[0019] Figure 13 This is a diagram illustrating a semiconductor manufacturing apparatus according to the third embodiment. Detailed Implementation
[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figures 1 to 13 In this context, identical or similar elements are annotated with the same symbol, and repeated descriptions are omitted.
[0021] (First Embodiment)
[0022] Figure 1 This is a diagram illustrating the semiconductor manufacturing apparatus 1 according to the first embodiment. (As shown...) Figure 1 As shown, the semiconductor device 1 of the first embodiment includes a processing chamber 2, a boat 3, a first gas supply pipe 4, a second gas supply pipe 5, an outer casing 6, a heating device 7, a gas supply control unit 8, a heating control unit 9, a pump 10, and a pressure control unit 11.
[0023] The processing chamber 2 is a hollow structure capable of accommodating multiple semiconductor substrates 100. An exhaust port 21 is provided in the processing chamber 2 to discharge exhaust gas after processing the semiconductor substrates 100. For example, the exhaust port 21 is formed by an elongated hole extending in the vertical direction, and the width of the exhaust port 21 in the direction orthogonal to the vertical direction is fixed.
[0024] The boat 3 is disposed within the processing chamber 2. The boat 3 has a pillar 31 extending in the vertical direction, in which multiple horizontal slots (not shown) are provided at vertical intervals. By inserting semiconductor substrates 100 into each slot, the boat 3 can maintain multiple semiconductor substrates 100 in a stacked state with the spacing in the vertical direction (that is, the thickness direction of the semiconductor substrates 100).
[0025] A first gas supply pipe 4 is disposed within the processing chamber 2. The first gas supply pipe 4 is a pipe for supplying an aminosilane-based first gas G1 to the semiconductor substrate 100. Specifically, the first gas supply pipe 4 extends vertically from the side towards the boat 3. Multiple first nozzles 41 are provided in the first gas supply pipe 4 for ejecting the first gas G1 to the multiple semiconductor substrates 100 held by the boat 3. The multiple first nozzles 41 are arranged in a one-to-one positional relationship with the multiple semiconductor substrates 100. For example, the number of first nozzles 41 is the same as the number of semiconductor substrates 100 held by the boat 3, and the corresponding first nozzles 41 are roughly at the same vertical position, i.e., the height, as the semiconductor substrates 100. Each first nozzle 41, for example, has a fixed cross-sectional area. By arranging the first nozzles 41 in a one-to-one positional relationship with the semiconductor substrates 100, the thicknesses of the first seed layer 108 and the second seed layer 110, described later, can be homogenized among the multiple semiconductor substrates 100. Furthermore, in Figure 1 In the example shown, there is one first gas supply pipe 4, but multiple first gas supply pipes 4 can also be arranged in the processing chamber 2.
[0026] As the first gas G1 of the aminosilane system, a gas containing at least one aminosilane selected from the group consisting of butylaminosilane, bis(tert-butylamino)silane, dimethylaminosilane, bis(dimethylamino)silane, tris(dimethylamino)silane, diethylaminosilane, bis(diethylamino)silane, dipropylaminosilane, and diisopropylaminosilane can be used, for example.
[0027] A second gas supply pipe 5 is disposed within the processing chamber 2. The second gas supply pipe 5 is a pipe for supplying an amino-free silane-based second gas G2 to the semiconductor substrate 100. Specifically, the second gas supply pipe 5 extends vertically from the side towards the boat 3. Multiple second nozzles 51 are provided in the second gas supply pipe 5 for ejecting the amino-free silane-based second gas G2 to the multiple semiconductor substrates 100 held by the boat 3. Each second nozzle 51 has, for example, a fixed cross-sectional area. Furthermore, in… Figure 1 In the example shown, there is one second gas supply pipe 5, but multiple second gas supply pipes 5 can also be arranged in the processing chamber 2.
[0028] As a second gas G2 in a silane system without amino groups, for example, gases containing SiH2, SiH4, SiH6, Si2H4, Si2H6, and Si can be appropriately used. m H 2m+2 (Where m is a natural number greater than 3) The formula represents silicon hydrides and Si n H 2n (where n is a natural number greater than 3) The gas of at least one silane in the group consisting of silicon hydrides represented by the formula.
[0029] The outer cover component 6 is disposed on the outside of the processing chamber 2 in a manner that covers the processing chamber 2. The outer cover component 6 is provided with an exhaust port 61. Exhaust gas discharged from the exhaust port 21 of the processing chamber 2 is discharged to the outside through the exhaust port 61.
[0030] The heating device 7 is disposed on the outside of the outer cover component 6 in such a way that it surrounds the outer cover component 6. The heating device 7 activates the gases G1 and G2 supplied to the processing chamber 2 by heating the processing chamber 2 from the outside of the outer cover component 6, and simultaneously heats the semiconductor substrate 100.
[0031] The gas supply control unit 8 controls the supply of the first gas G1 to the first gas supply pipe 4. Specifically, the gas supply control unit 8 controls whether the first gas G1 flows into the first gas supply pipe 4 from its gas source and the flow rate. Furthermore, the gas supply control unit 8 controls the supply of the second gas G2 to the second gas G2 through the second gas supply pipe 5. Specifically, the gas supply control unit 8 controls whether the second gas G2 flows into the second gas supply pipe 5 from its gas source and the flow rate. The gas supply control unit 8 may also include, for example, a mass flow controller and a solenoid valve.
[0032] The heating control unit 9 controls the temperature inside the processing chamber 2, which is the processing temperature of the semiconductor substrate 100, by controlling the heating of the heating device 7.
[0033] Pump 10 is positioned downstream of the gas outlet 61. Pump 10 discharges the exhaust gas from the processing chamber 2 after the semiconductor substrate 100 has been processed by venting the exhaust gas from the processing chamber 2.
[0034] The pressure control unit 11 controls the pressure inside the processing chamber 2, which is the processing pressure of the semiconductor substrate 100, by controlling the exhaust of the pump 10.
[0035] Next, a semiconductor manufacturing method according to the first embodiment of the semiconductor device 1 configured as described above will be described.
[0036] Figure 2 This is a flowchart illustrating the semiconductor manufacturing method of the first embodiment. Figure 3 This is a cross-sectional view showing the semiconductor manufacturing method of the first embodiment.
[0037] The semiconductor manufacturing method of the first embodiment has the advantage of utilizing the method according to Figure 2 The flowchart describes the film formation steps of the heat treatment process. At least Figure 2 The film formation step is performed by the semiconductor manufacturing apparatus 1. However, as Figure 2 In the initial state, on the semiconductor substrate 100, using Figure 2 The preceding steps formed Figure 3 The structure shown. (As illustrated) Figure 3 As shown, in Figure 2 In its initial state, the semiconductor substrate 100 is located above the silicon substrate 101 and has a stacked body 104 and a memory film 120. The stacked body 104 is constructed by alternately stacking, for example, an insulating layer 102 comprising a silicon oxide film and a sacrificial layer 103 comprising, for example, a silicon nitride film. The memory film 120 is disposed along the sidewall of a memory aperture MH that penetrates the stacked body 104 in the stacking direction. The memory film 120 has, sequentially from the outer side (i.e., the sidewall side of the memory aperture MH), a barrier insulating layer 105, a charge storage layer 106, and a tunnel insulating layer 107. The barrier insulating layer 105 and the tunnel insulating layer 107 comprise, for example, silicon oxide films. The charge storage layer 106 comprises, for example, a silicon nitride film.
[0038] Figure 4 It continues Figure 3 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment. From Figure 3 Starting from the initial state shown, as Figure 2 As shown, an aminosilane-based first gas G1 is supplied to the semiconductor substrate 100 while it is being heated. At this time, it is preferable that the heating control unit 9 controls the temperature inside the processing chamber 2 to be between 325°C and 450°C. Furthermore, it is preferable that the pressure control unit 11 controls the pressure inside the processing chamber 2 to be between 27 Pa and 1000 Pa. The condition of lower film formation temperature and higher pressure is preferred. By supplying the first gas G1 to the semiconductor substrate 100 while it is being heated, as... Figure 4 As shown, a first seed layer 108 is formed on the tunnel insulating layer 107 (that is, on the inner side of the tunnel insulating layer 107). The first seed layer 108 is a layer that allows silicon nuclei to be uniformly generated on the tunnel insulating layer 107, which serves as a substrate, and which readily adsorbs silane. In addition, when forming the first seed layer 108, an amino-free silane-based gas (e.g., Si2H6) may also be used.
[0039] Figure 5 It continues Figure 4 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the first seed layer 108, as... Figure 2As shown, a second silane-based gas G2 without amino groups is supplied to the semiconductor substrate 100 while heating it. Preferably, the heating control unit 9 controls the temperature inside the processing chamber 2 to be higher than when the first seed layer 108 is formed. More preferably, the temperature inside the processing chamber 2 is between 450°C and 550°C. The pressure inside the processing chamber 2 can be the same as when the first seed layer 108 is formed. By supplying the second gas G2 to the semiconductor substrate 100 while heating it, as... Figure 5 As shown, a first amorphous silicon layer 109 is formed on the first seed layer 108 (that is, on the inner side of the first seed layer 108).
[0040] Figure 6 It continues Figure 5 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the first amorphous silicon layer 109, as... Figure 2 As shown, a first gas G1 is supplied to the semiconductor substrate 100 while it is being heated. At this time, it is preferable that the heating control unit 9 controls the temperature inside the processing chamber 2 to be lower than when the first amorphous silicon layer 109 is formed. More preferably, the temperature inside the processing chamber 2 is between 325°C and 450°C. By supplying the first gas G1 to the semiconductor substrate 100 while it is being heated, as... Figure 6 As shown, a second seed layer 110 is formed on the first amorphous silicon layer 109 (that is, inside the first amorphous silicon layer 109). The second seed layer 110 is a layer that allows silicon nuclei to be uniformly generated on the first amorphous silicon layer 109, which serves as the substrate, and readily adsorbs silane. Unlike the first seed layer 108, which is based on the tunnel insulating layer 107, the second seed layer 110 is based on the first amorphous silicon layer 109. Therefore, the second seed layer 110 can contain C (carbon) and N (nitrogen) as impurities. The preferred dosage of C and N is 10. 13 atms / cm 2 By providing a second seed layer 110, polymorphism of the amorphous silicon layer can be suppressed during the implementation of the MILC method, which will be described later.
[0041] Figure 7 It continues Figure 6 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the second seed layer 110, as... Figure 2 As shown, a second gas G2 is supplied to the semiconductor substrate 100 while it is being heated. At this time, it is preferable that the heating control unit 9 controls the temperature inside the processing chamber 2 to be higher than when the second seed layer 110 is formed. More preferably, the temperature inside the processing chamber 2 is between 450°C and 550°C. By supplying the second gas G2 to the semiconductor substrate 100 while it is being heated, as... Figure 7As shown, a second amorphous silicon layer 111 is formed on the second seed layer 110 (that is, inside the second seed layer 110). Hereinafter, the stacked structure of the first seed layer 108, the first amorphous silicon layer 109, the second seed layer 110 and the second amorphous silicon layer 111 will also be referred to as amorphous silicon layers 108 to 111.
[0042] Figure 8 It continues Figure 7 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the second amorphous silicon layer 111, as shown... Figure 8 As shown, a core layer 112 is formed on the second amorphous silicon layer 111, for example, using ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition), with the core layer 112 located at the center of the memory hole MH. The core layer 112 comprises, for example, a silicon oxide film. The formation of the core layer 112 is carried out at a film-forming temperature at which the amorphous silicon layers 108-111 will not polymorphize.
[0043] Figure 9 It continues Figure 8 This is a cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the core layer 112, the amorphous silicon layers 108-111 are single-crystallized using the MILC method. That is, firstly as... Figure 9 As shown, an n-type impurity (P, As, B, etc.) is doped into the amorphous silicon layers 108-111 by ion implantation, thereby forming a doped amorphous silicon layer 113 on the upper end of the amorphous silicon layers 108-111.
[0044] Figure 10 It continues Figure 9 A cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the doped amorphous silicon layer 113, as... Figure 10 As shown, a metal layer 114 is formed covering the entire surface of the semiconductor substrate 100, for example, using PVD (Physical Vapor Deposition) or MO (Metal Organic)-CVD. The metal layer 114 contains nickel. Furthermore, the metal layer 114 can be any element capable of forming silicides, such as Co or Y. After forming the metal layer 114, a nickel disilicide layer 115 is formed on the upper side of the amorphous silicon layers 108-111 by performing silicide annealing on the metal layer 114 and the amorphous silicon layers 108-111.
[0045] Figure 11 It continues Figure 10This is a cross-sectional view showing the semiconductor manufacturing method of the first embodiment. After forming the nickel disilicide layer 115, the amorphous silicon layers 108-111 and the nickel disilicide layer 115 are heated to a film-forming temperature at which the amorphous silicon layers 108-111 will not polycrystalline. Thus, as... Figure 11 As shown, as the nickel disilicide layer 115 migrates downwards, the amorphous silicon layers 108-111 are monocrystalline 116ed using the nickel disilicide layer 115 as a catalyst. At this time, the impurities (C, N) in the second seed layer 110 suppress the polycrystallineization of the amorphous silicon layers 108-111. By suppressing the polycrystallineization of the amorphous silicon layers 108-111, the migration of the nickel disilicide layer 115 can be prevented from being hindered by polycrystalline formation.
[0046] As explained above, according to the first embodiment, by forming a second seed layer 110 containing impurities between the first amorphous silicon layer 109 and the second amorphous silicon layer 111, the amorphous silicon layers 108 to 111 can be appropriately monocrystalline.
[0047] Furthermore, by using the same first gas G1 for the formation of both the first seed layer 108 and the second seed layer 110, the configuration and process of the semiconductor manufacturing apparatus 1 can be simplified. However, an aminosilane-based gas, which is more prone to containing impurities than the first gas G1, can also be used to form the second seed layer 110. In this case, the polycrystalline formation of the amorphous silicon layers 108-111 can be more effectively suppressed, allowing the amorphous silicon layers 108-111 to be further appropriately monocrystalline.
[0048] (Second Implementation)
[0049] Figure 12 This is a diagram showing the semiconductor manufacturing apparatus 1 according to the second embodiment. So far, an example of a semiconductor manufacturing apparatus 1 with a fixed width of the exhaust port 21 has been described. In contrast, as... Figure 12 As shown, in the second embodiment, the first part 21a (that is, the part with the same height as the first nozzle 41) of the cross-sectional area of the exhaust port 21 is larger than the second part 21b (that is, the part with the same height as the first nozzle 41) which is farther away from the first nozzle 41. Figure 12 In the example shown, the first part 21a is circular. The first part 21a can also be a rectangle or other polygon. According to the second embodiment, the exhaust efficiency can be improved.
[0050] (Third Implementation)
[0051] Figure 13 This is a diagram illustrating the semiconductor manufacturing apparatus 1 according to the third embodiment. So far, an example of a semiconductor manufacturing apparatus 1 with a fixed cross-sectional area of a plurality of first nozzles 41 has been described. In contrast, in the third embodiment, the plurality of first nozzles 41 are located downstream of the aminosilane-based gas ( Figure 13 The first nozzle 41 (on the upper side) is located upstream of the aminosilane gas. Figure 13 Compared to the first nozzle 41 on the lower side of the substrate, the cross-sectional area is larger. As a result, the supply pressure of the first gas G1 to the plurality of semiconductor substrates 100 can be uniformized, and thus the thickness of the first seed layer 108 and the second seed layer 110 can be uniform among the plurality of semiconductor substrates 100.
[0052] Furthermore, in the third embodiment, the portion of the exhaust port 21 near the downstream side of the aminosilane gas outlet 41 may be larger than the portion near the upstream side of the aminosilane gas outlet 41. This can improve the exhaust efficiency.
[0053] While several embodiments have been described above, these embodiments are merely illustrative and not intended to limit the scope of the invention. The novel apparatus and method described herein can be implemented in various other ways. Furthermore, various omissions, substitutions, and modifications can be made to the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to encompass these modifications or variations contained within the scope or spirit of the invention.
[0054] [Explanation of Symbols]
[0055] 107 Tunnel Insulation Layer
[0056] 108 Seed Layer 1
[0057] 109 First amorphous silicon layer
[0058] 110 Second seed layer
[0059] 111 Second amorphous silicon layer.
Claims
1. A semiconductor manufacturing method, comprising: A first seed layer is formed on the substrate using an aminosilane-based first gas; A first amorphous silicon layer is formed on the first seed layer using a second gas based on a silane without amino groups; A second seed layer containing impurities is formed on the first amorphous silicon layer using a third aminosilane-based gas; and A second amorphous silicon layer is formed on the second seed layer using a fourth gas based on a silane without amino groups; The impurities include carbon and nitrogen; The substrate layer is a tunnel insulating layer, which is disposed along the sidewall of the through hole that connects the first and second layers of the laminate disposed above the substrate; The semiconductor manufacturing method further includes: Doped amorphous silicon layers are formed on the first amorphous silicon layer and the second amorphous silicon layer in such a way that they are located in the center of the through hole; A nickel-containing metal layer is formed on the doped amorphous silicon layer; By performing silicide annealing on the metal layer, the first amorphous silicon layer and the second amorphous silicon layer, a nickel disilicide layer is formed on the upper side of the first amorphous silicon layer and the second amorphous silicon layer. As the nickel disilicide layer migrates downwards, the first amorphous silicon layer and the second amorphous silicon layer are monocrystallized using the nickel disilicide layer as a catalyst.
2. The semiconductor manufacturing method according to claim 1, wherein the impurity comprises carbon.
3. The semiconductor manufacturing method according to claim 1, wherein the impurity comprises nitrogen.
4. The semiconductor manufacturing method according to claim 2, wherein the impurity comprises nitrogen.
5. The semiconductor manufacturing method according to claim 1, wherein the substrate layer is a first insulating layer disposed along the sidewall of a through-hole that penetrates the stack of the first and second layers disposed above the substrate.
6. The semiconductor manufacturing method according to claim 2, wherein the substrate layer is a first insulating layer disposed along the sidewall of a through hole that penetrates the stack of the first and second layers disposed above the substrate.
7. The semiconductor manufacturing method according to claim 3, wherein the substrate layer is a first insulating layer disposed along the sidewall of a through hole that penetrates the stack of the first and second layers disposed above the substrate.
8. The semiconductor manufacturing method according to claim 5, further comprising the following steps: A second insulating layer is formed on the second amorphous silicon layer in such a way that it is located in the center of the through hole; A silicide layer is formed on the upper end side of the first amorphous silicon layer and the second amorphous silicon layer; and Using the silicide layer as a catalyst, the first amorphous silicon layer and the second amorphous silicon layer are monocrystalline.
9. The semiconductor manufacturing method according to claim 8, wherein the silicide layer is a nickel disilicide layer.
10. The semiconductor manufacturing method according to claim 1, wherein the third gas is the same gas as the first gas.
11. The semiconductor manufacturing method according to claim 1, wherein the third gas is a gas different from the first gas.
12. The semiconductor manufacturing method according to claim 1, wherein the fourth gas is the same gas as the second gas.
13. The semiconductor manufacturing method according to claim 1, wherein the first gas and the third gas are gases containing at least one aminosilane selected from the group consisting of butylaminosilane, bis(tert-butylamino)silane, dimethylaminosilane, bis(dimethylamino)silane, tris(dimethylamino)silane, diethylaminosilane, bis(diethylamino)silane, dipropylaminosilane, and diisopropylaminosilane.
14. The semiconductor manufacturing method according to claim 1, wherein the second gas and the fourth gas contain gases selected from SiH2, SiH4, SiH6, Si2H4, Si2H6, and Si... m H 2m+2 The formula represents the hydride of silicon, wherein, m is a natural number greater than or equal to 3, and Si n H 2n The gaseous form of at least one silane from the group consisting of silicon hydrides represented by the formula, where n is a natural number of 3 or more.
15. The semiconductor manufacturing method according to claim 1, wherein the nickel disilicide layer is formed between the lower end of the doped amorphous silicon layer and the upper ends of the first amorphous silicon layer and the second amorphous silicon layer by performing the silicide annealing; As the nickel disilicide layer migrates downwards, monocrystalline silicon is formed between the lower end of the doped amorphous silicon layer and the upper end of the nickel disilicide layer.