Method of manufacturing a semiconductor device
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-17
- Publication Date
- 2026-08-07
AI Technical Summary
然而，现有旋涂工艺制备的材料层平坦性差，影响半导体器件的性能
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Figure CN115116845B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and a chip. Background Technology
[0002] In semiconductor circuit manufacturing, thin film materials are sequentially deposited onto a wafer substrate to meet specific requirements. Typically, a spin-coating process is used to prepare the material layers. During spin-coating, an organic polymer sol is uniformly distributed on the wafer substrate under centrifugal force. After the solvent evaporates, a thin film adheres to the wafer substrate. However, existing spin-coating processes result in poor flatness of the material layers, affecting the performance of semiconductor devices.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0004] This disclosure provides a method for fabricating a semiconductor device and a chip, which at least to some extent overcomes the problems of poor material layer planarization and reduced semiconductor circuit performance caused by spin coating processes in related technologies.
[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.
[0006] According to one aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising:
[0007] A substrate is provided having densely patterned regions and sparsely patterned regions;
[0008] A first spin coating is formed on the substrate, covering the dense pattern region and the sparse pattern region;
[0009] A second spool coating is formed on the first spool coating, the viscosity of the second spool coating being less than the viscosity of the first spool coating;
[0010] The first spin coating and the second spin coating are etched, and the etching selectivity ratio of the second spin coating to the first spin coating is controlled within a preset range. The second spin coating and part of the first spin coating are etched away to form a first spin coating with a flat surface.
[0011] In one embodiment of this disclosure, the first spin coating layer is SOC, and the second spin coating layer is an organic BARC material layer.
[0012] In one embodiment of this disclosure, the viscosity of the second spin coating is between 2 cps and 14 cps; the viscosity of the first spin coating is between 20 cps and 50 cps.
[0013] In one embodiment of this disclosure, the thickness of the first swirl coating above the dense pattern region is less than the thickness of the first swirl coating above the sparse pattern region, and the thickness difference between the two ranges from 5 nm to 20 nm.
[0014] In one embodiment of this disclosure, the thickness of the first spin coating is between 100 nm and 500 nm, and the thickness of the second spin coating is between 50 nm and 200 nm.
[0015] In one embodiment of this disclosure, the material of the second spin coating includes one or more of organic BARC and photoresist.
[0016] In one embodiment of this disclosure, the etching selectivity ratio for the second spin coating and the first spin coating is 1:3 to 1:1.
[0017] In one embodiment of this disclosure, the method further includes:
[0018] A buffer layer is formed between the first spin coating layer and the second spin coating layer;
[0019] The first spin coating layer, the buffer layer, and the second spin coating layer are etched, and the etching selectivity ratio of the second spin coating layer, the buffer layer, and the first spin coating layer is controlled to etch away the second spin coating layer, the buffer layer, and part of the first spin coating layer.
[0020] In one embodiment of this disclosure, the buffer layer is an inorganic BARC material layer.
[0021] In one embodiment of this disclosure, the thickness of the buffer layer is between 10 nm and 50 nm.
[0022] In one embodiment of this disclosure, the etching selectivity ratio for the buffer layer and the second spin coating layer is between 5:1 and 10:1.
[0023] In one embodiment of this disclosure, the process parameters for the etching process include:
[0024] The plasma source power is 12000W~22000W, and the radio frequency is 400kHz;
[0025] The bias power is 4100W to 5700W, and the radio frequency is 400MHz.
[0026] The chamber pressure is 10 mtorr to 30 mtorr;
[0027] The process time is 30s to 120s;
[0028] The etching gas flow rates are: C4F8: 15 sccm to 45 sccm, C4F6: 20 sccm to 50 sccm, and O2: 40 sccm to 65 sccm.
[0029] This disclosure provides a method for fabricating a semiconductor device, wherein a first spin coating is spin-coated on a patterned substrate, and a planarized second spin coating is formed on the first spin coating. The first spin coating and the second spin coating are etched back. By controlling the etch selectivity ratio of the first spin coating and the second spin coating, a first spin coating with a planar surface is obtained, thereby improving the performance of the semiconductor device.
[0030] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0031] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0032] Figure 1 A cross-sectional view showing the formation of a first spin coating on a patterned substrate in the related art;
[0033] Figures 2a-2b This shows a cross-sectional view of a patterned substrate forming a first spin coating in the related art;
[0034] Figure 3 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure is shown;
[0035] Figures 4a-4d The diagram shows cross-sectional views of a method for fabricating a semiconductor device according to an embodiment of the present disclosure at different process stages.
[0036] Figure 5 A flowchart illustrating another method for fabricating a semiconductor device according to an embodiment of this disclosure is shown;
[0037] Figures 6a-6e Cross-sectional views of different process stages are shown for another method of fabricating a semiconductor device provided in the embodiments of this disclosure;
[0038] Figures 7a-7bThe AFM test results are shown on the substrate surface from the center to the edge of the array region after spin-coating SOC coating and spin-coating organic BARC coating;
[0039] Figures 8a-8b The AFM test results are shown on the substrate surface of the peripheral circuit area after spin-coating SOC coating and spin-coating organic BARC coating;
[0040] Figures 9a-9b The AFM test results are shown on the surface of the OVL region substrate after spin-coating SOC coating and spin-coating organic BARC coating.
[0041] The reference numerals in the attached figures are explained as follows:
[0042] 100, Substrate; 200, Pattern structure; 201, First uneven region; 202, Second uneven region; 203, Sparse pattern region; 204, Dense pattern region; 300, First swirl coating layer; 400, Second swirl coating layer; 500, Buffer layer. Detailed Implementation
[0043] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0044] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.
[0045] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0046] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.
[0047] Figure 1 This shows a cross-sectional view of a patterned substrate forming a first spin coating, as described in related technologies. Figure 1 As shown, the semiconductor device in the related technology includes a substrate 100, a patterned structure 200 formed on the surface of the substrate 100, and a first spin coating 300 covering the surface of the patterned structure 200. To form patterned structures 200 with different patterns on the surface of the substrate 100, the related technology employs the following steps: preparing a thin film layer on the substrate 100 using techniques such as spin coating or deposition (e.g., chemical vapor deposition, magnetron sputtering), etching to form the corresponding patterned structure 200 as needed, and after forming the patterned structure 200, forming the first spin coating 300 through a spin coating process. The first spin coating 300 can be a material used in the spin coating process, such as SOD material, SOC material, etc. The substrate 100 can be a silicon-based substrate, etc.
[0048] like Figure 1 As shown, multiple patterned structures 200 are formed on the substrate 100. The density of the patterned structures 200 varies in different regions of the substrate 100. In one embodiment of this application, the patterned structure 200 includes patterned region A, patterned region B, and patterned region C. It can be seen that due to the different designs of each patterned region, the patterns in each region have different densities. In one embodiment of this application, the pattern density of patterned region B is greater than that of patterned regions A and C. This type of pattern distribution characteristic results in the first spin coating 300 covering patterned regions B and A and C having different spatial distributions in the corresponding areas after the first spin coating 300 is prepared.
[0049] like Figure 1 As shown, for pattern area B, due to its higher pattern density, a larger amount of the first spin coating 300 needs to be used to fill the gaps in this area. During spin coating, the first spin coating 300 above this area has a relatively flat surface. For pattern areas A and C, their pattern density is lower than that of the denser pattern areas, resulting in a height difference on the surface of the first spin coating 300 formed during the spin coating process. Specifically, a height difference will ultimately exist between pattern area B and pattern area C, as shown in the diagram. Figure 1 The second uneven region 202 described above, between pattern region A and pattern region C, will have a... Figure 1The first uneven region 201 is shown in the figure. For ease of explanation, in one embodiment of this application, pattern region A can be a measurement pattern region located in the wafer dicing area, such as an Overlay Mark region, hereinafter referred to as an OVL region; pattern region B can be an array region, such as an array region; and pattern C can be a peripheral circuit region, hereinafter referred to as a Peri region.
[0050] Furthermore, during the curing process of the spin coating, the first spin coating 300 shrinks as the solvent evaporates, further deteriorating the surface planarization of the first spin coating 300. In semiconductor devices, the film thickness is typically controlled within the nanometer range. When the surface planarization of the spin coating is poor, it will greatly affect subsequent processing steps and significantly reduce the performance of the semiconductor device.
[0051] On the other hand, in addition to the uneven surface of the first spin coating caused by the difference in pattern density formed on the substrate, the properties of the coating material itself used in the spin coating process also make it difficult for the substrate to form a flat surface.
[0052] For example, Figures 2a-2b A cross-sectional view of a first swirl coating formed on a patterned substrate in related technologies is shown. To illustrate the impact of the performance of the first swirl coating on the planarization of the patterned substrate surface, an embodiment of this application is illustrated using a patterned region as an example. Figure 2a In the process, a patterned structure 200 is formed on the substrate 100, the patterned structure 200 including a dense patterned region 203 and a sparse patterned region 204.
[0053] exist Figure 2b In this process, a first spin coating layer 300 is formed using a spin coating process. The first spin coating layer 300 is made of SOC material. Typically, the colloid used in spin coating is an organic polymer material. During spin coating, the viscous force of the colloid is less than the centrifugal force it experiences, and the SOC coating continuously diffuses towards the edge of the substrate 100. The colloid at the edge of the substrate 100 is continuously ejected, and the thickness of the SOC coating gradually decreases. Since the SOC coating has covered the entire surface of the substrate 100, the solvent evaporation rate is accelerated due to the rapidly flowing airflow above the substrate 100, causing the viscous force of the colloid to continuously increase, forming a gel-like substance that is difficult to flow. At this point, the forces acting on the gel-like coating in all directions reach equilibrium, and the thickness of the SOC coating reaches its final state. Finally, at the edge of the gel-like coating, under the action of surface tension, the colloid at the edge of the coating is difficult to eject from the substrate 100, resulting in the thickness of the central region of the first spin coating layer 300 being less than the thickness of the edge region of the first spin coating layer 300.
[0054] Therefore, the difference in pattern density formed on the substrate and the performance of the coating materials used in the spin coating process both affect the planarization of the substrate surface. Figure 2bAs shown, the thickness of the first swirl coating formed on the dense pattern region 203 is less than the thickness of the first swirl coating on the sparse pattern region 204. In one embodiment of this application, the thickness difference between the two can be between 5nm and 20nm.
[0055] Based on this, the technical solution provided in this disclosure provides a first spin coating layer on a patterned substrate, a planarized second spin coating layer is formed on the first spin coating layer, and the first and second spin coating layers are etched back. By controlling the etching selectivity ratio of the first and second spin coating layers, a first spin coating layer with a flat surface is obtained, thereby improving the performance of the semiconductor device.
[0056] It should be noted that, unless otherwise specified, the embodiments of the present invention and the technical features thereof can be combined with each other.
[0057] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.
[0058] Figure 3 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure is shown. Figure 3 As shown, the method for fabricating a semiconductor device provided in this embodiment includes the following steps:
[0059] S302, Provide a substrate having densely patterned regions and sparsely patterned regions;
[0060] S303, A first spin coating is formed on the substrate, covering the dense and sparse pattern areas;
[0061] S306. A second swirl coating is formed on the first swirl coating, wherein the viscosity of the second swirl coating is less than the viscosity of the first swirl coating.
[0062] S308. The first swirl coating and the second swirl coating are etched, and the etching selectivity ratio of the second swirl coating to the first swirl coating is controlled within a preset range. The second swirl coating and part of the first swirl coating are etched away to form a first swirl coating with a flat surface.
[0063] It should be noted that the viscosity of the second spin coating in this embodiment is less than that of the first spin coating. With the low viscosity of the second spin coating material, the low viscosity organic polymer solution is more easily ejected under centrifugal force, forming a flat surface. Based on the formation of a second spin coating with better flattening, a similar etching selectivity is selected, which is conducive to the back etching of the second spin coating and the first spin coating through etching, thereby forming a first spin coating with a flat surface.
[0064] The preset range of the etching selectivity ratio between the second swirl coating and the first swirl coating can be obtained through experiments so that the first swirl coating and the second swirl coating have similar etching rates. On the basis of the flat second swirl coating, the second swirl coating and part of the first swirl coating are etched at the same or similar etching rates so that the etching amount at different positions on the substrate is consistent. After the etching back is completed, the first swirl coating can form a flat surface.
[0065] The method for fabricating a semiconductor device according to embodiments of this disclosure involves spin-coating a first spin coating layer on a patterned substrate, forming a planarized second spin coating layer on the first spin coating layer, etching back the first and second spin coating layers, and obtaining a first spin coating layer with a planar surface by controlling the etching selectivity ratio of the first and second spin coating layers, thereby improving the performance of the semiconductor device.
[0066] The following is combined with Figures 4a-4c The present disclosure describes in detail the process steps of the method for fabricating a semiconductor device according to embodiments of the present disclosure.
[0067] like Figure 4a As shown, a substrate 100 is provided, and a patterned pattern structure 200 is formed on the substrate 100. The pattern structure 200 includes a patterned dense region 203 and a patterned sparse region 204.
[0068] It should be noted that the substrate 100 may include a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, and this application does not make any specific limitation.
[0069] The patterned structure 200 can be a plurality of spaced-apart linear structures formed on the substrate 100. In some embodiments, the linear structures can be isolation structures or conductive structures, etc., and this application does not specifically limit them.
[0070] In one embodiment, the linear structure can be formed using a self-aligned double pattern (SADP) technique. SADP includes the following steps: sequentially depositing a first hard mask layer, a SOC coating, a second hard mask layer, and a photolithography layer on the surface of the layer to be etched, followed by photolithography to form a patterned photolithography layer; etching the second hard mask layer using the patterned photolithography layer as a mask to form a patterned second hard mask layer; subsequently etching the SOC coating using the patterned second hard mask layer as a mask to form a patterned SOC coating; removing the patterned second hard mask layer and depositing sidewall material covering the patterned SOC coating and the first hard mask layer; etching to remove the horizontal sidewall material layer to form a sidewall layer; removing the patterned SOC coating; etching the first hard mask layer using the sidewall layer as a mask to form a patterned first hard mask layer; and etching the layer to be etched using the patterned first hard mask layer as a mask to form a channel. In one embodiment, the first hard mask layer is polycrystalline silicon, the second hard mask layer is silicon oxynitride, and the sidewall material layer is silicon nitride.
[0071] like Figure 4b As shown, a first spin coating 300 is formed on a substrate 100 by a spin coating process, covering the densely patterned region 203 and the sparsely patterned region 204. The first spin coating 300 covers the entire surface of the substrate 100, and the top surface of the first spin coating 300 is a non-planar surface. It should be noted that the first spin coating 300 can be an SOD coating, a SOC coating, or other coatings prepared by spin coating.
[0072] like Figure 4c As shown, after the first spin coating layer 300 is spin coated, a second spin coating layer 400 is formed on the first spin coating layer 300 by a spin coating process. It should be noted that the viscosity of the second spin coating layer 400 is less than that of the first spin coating layer 300, so that the second spin coating layer 400 has a relatively flat surface.
[0073] In one embodiment, the first swirl coating 300 is a SOC (Surface-Oriented Coating), and the second swirl coating 400 is an organic BARC (Body-Analog Reflective Coating) material layer. For example, the second swirl coating 400 can be one or more of organic bottom anti-reflective coatings (BARC) and photoresist.
[0074] In one embodiment, the viscosity of the second spin coating 400 is between 2 cps and 14 cps; the viscosity of the first spin coating 300 is between 20 cps and 50 cps.
[0075] In one embodiment, the first swirl coating above the dense pattern region 203 and the first swirl coating above the sparse pattern region 204 have a height difference, and the thickness of the second swirl coating 400 depends on the height difference of the surface of the first swirl coating 300.
[0076] In one embodiment, the thickness of the first spin coating 300 is between 100nm and 500nm, and the thickness of the second spin coating 400 is between 50nm and 200nm.
[0077] like Figure 4d As shown, the second spin coating 400 and the first spin coating 300 are etched to remove all of the second spin coating 400 and part of the first spin coating 300, resulting in a flat surface for the first spin coating 300. It should be noted that during the etching process, the etching rates of the first spin coating 300 and the second spin coating 400 are similar, allowing for the removal of material of the same thickness. Based on the flat surface of the second spin coating 400, the same thickness of material is removed by etching at different locations on the substrate 100, thus resulting in a flat surface for the first spin coating 300.
[0078] In one embodiment, the etching selection ratio of the second spin coating 400 and the first spin coating 300 is 1:3 to 1:1. Considering that the second spin coating 400 has a certain viscosity, the surface of the second spin coating 400 is not completely flat. For areas with large height differences in the first spin coating 300, there may still be unevenness on the surface of the second spin coating 400. Therefore, the etching rate of the second spin coating 400 is slightly lower than that of the first spin coating 300 to further optimize the surface of the first spin coating 300 through the etching process and eliminate the influence of the unevenness of the second spin coating 400 on the surface of the first spin coating 300.
[0079] In one embodiment, the process parameters for etching the first and second swirl coatings include a plasma source power of 12000W to 22000W and a radio frequency of 400kHz.
[0080] In one embodiment, the process parameters for etching the first and second swirl coatings include a bias power of 4100W to 5700W and a radio frequency of 400MHz.
[0081] In one embodiment, the process parameters for etching the first and second swirl coatings include a chamber pressure of 10 mtorr to 30 mtorr.
[0082] In one embodiment, the process parameters for etching the first and second swirl coatings include a process time of 30s to 120s to avoid excessive consumption of the first swirl coating.
[0083] In one embodiment, the etching gases used to etch the first and second swirl coatings include C4F8, C4F6, and O2, with flow rates of C4F8: 15 sccm–45 sccm, C4F6: 20 sccm–50 sccm, and O2: 40 sccm–65 sccm, respectively. It is important to note that the selection of the etching gases and their flow rates allows for a relatively narrow selection of etching between the first and second swirl coatings, thereby optimizing the surface flatness of the first swirl coating.
[0084] Figure 5 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure is shown. Figure 3 Based on the previous embodiment, a buffer layer is added between the first and second swirl coatings, and etching back is performed to obtain a smooth first swirl coating. The semiconductor device fabrication method of this embodiment includes steps S302-S304 and S502-S506, specifically as follows... Figure 5 As shown, the method includes:
[0085] S502, A buffer layer is formed on the first spin coating layer;
[0086] S504. A second swirl coating is formed on the buffer layer;
[0087] S506. Etch the first swirl coating, the buffer layer, and the second swirl coating, control the etching selectivity ratio of the second swirl coating, the buffer layer, and the first swirl coating, and etch away the second swirl coating, the buffer layer, and part of the first swirl coating.
[0088] It should be noted that steps S302 and S304 are implemented in the same way as in the above embodiments, and will not be described again here.
[0089] In one embodiment, the buffer layer is an inorganic BARC material layer. For example, the inorganic BARC material can be SiON.
[0090] For example, the first spin coating is a SOC coating, on which a SiON material layer is prepared by chemical vapor deposition (CVD). CVD includes low-pressure CVD, atmospheric pressure CVD, sub-atmospheric pressure CVD, ultra-high vacuum CVD, plasma-enhanced CVD, high-density plasma CVD, and rapid thermal CVD. Two or more gaseous raw materials are introduced into the reaction chamber, and through a series of chemical reactions, a new material is formed and deposited onto the substrate surface. For the SiON material layer, high-purity silane (SiH4), ammonia (NH3), and water vapor (H2O) can be used as reactant gases, and high-purity nitrogen (N2) can be used as a protective gas under vacuum. The SiON material layer can then be obtained through atmospheric pressure chemical vapor deposition.
[0091] It should be noted that the SiON material layer formed by CVD process is conformally grown on the surface of the SOC coating. The two surfaces have the same shape. Since the inorganic BARC material layer is easy to etch, during the etching process, for the first spin coating, the thinner end first contacts the inorganic BARC material layer and the first spin coating. The thinner end preferentially enters the etching stage of the inorganic BARC material layer and the first spin coating, thereby compensating for the etching difference caused by the uneven thickness of the first spin coating, improving the etching effect, improving the flatness of the first spin coating, and enhancing the performance of the semiconductor device.
[0092] The following is combined with Figures 6a-6e The present disclosure describes in detail the process steps of the method for fabricating a semiconductor device according to embodiments of the present disclosure.
[0093] like Figure 6a As shown, a substrate 100 is provided, and a patterned pattern structure 200 is formed on the substrate 100. The pattern structure 200 includes a patterned dense region 203 and a patterned sparse region 204.
[0094] like Figure 6b As shown, a first spin coating 300 is formed on a substrate 100 by a spin coating process, covering the dense pattern region 203 and the sparse pattern region 204. The first spin coating 300 covers the entire surface of the substrate 100, and the top surface of the first spin coating 300 is a non-flat surface.
[0095] like Figure 6c As shown, after the first spin coating 300 is spin coated, a buffer layer 500 is formed on the first spin coating 300 by a CVD process. It should be noted that the buffer layer 500 has the same surface shape as the first spin coating 300.
[0096] In one embodiment, the thickness of the buffer layer 500 is between 10 nm and 50 nm.
[0097] The buffer layer 500 can be an inorganic BARC material layer, specifically, the inorganic BARC material can be SiON.
[0098] like Figure 6d As shown, a second spin coating layer 400 is formed on the buffer layer 500 by a spin coating process. It should be noted that the viscosity of the second spin coating layer 400 is lower than that of the first spin coating layer 300, so that the second spin coating layer 400 has a relatively flat surface.
[0099] like Figure 6eAs shown, the first swirl coating 300, buffer layer 500, and second swirl coating 400 are etched. The etching selectivity ratio of the second swirl coating 400, buffer layer 500, and the first swirl coating 300 is controlled. The second swirl coating 400, buffer layer 500, and part of the first swirl coating 300 are etched away to obtain a smooth surface on the first swirl coating 300. It should be noted that in the etching process, the etching rates of the first swirl coating 300 and buffer layer 500 are close, and the etching rates of the buffer layer 500 and the second swirl coating 400 are also close, thus removing material of the same thickness through etching.
[0100] In one embodiment, the etching selectivity ratio for the buffer layer and the second swirl coating is between 5:1 and 10:1.
[0101] In one embodiment, the etching process parameters for the first swirl coating, the buffer layer, and the second swirl coating include: a plasma source power of 12000W to 22000W and a radio frequency of 400kHz.
[0102] In one embodiment, the process parameters for etching the first spin coating layer, the buffer layer, and the second spin coating layer include: a bias power of 4100W to 5700W and a radio frequency of 400MHz.
[0103] In one embodiment, the process parameters for etching the first spin coating layer, the buffer layer, and the second spin coating layer include: a chamber pressure of 10 mtorr to 30 mtorr.
[0104] In one embodiment, the process parameters for etching the first spin coating, the buffer layer, and the second spin coating include a process time of 30s to 120s to avoid excessive consumption of the first spin coating.
[0105] In one embodiment of this disclosure, the etching gas used to etch the first and second swirl coatings includes C4F8, C4F6 and O2, with the etching gas flow rates being C4F8: 15 sccm to 45 sccm, C4F6: 20 sccm to 50 sccm, and O2: 40 sccm to 65 sccm.
[0106] In summary, the semiconductor device fabrication method of this disclosure involves forming a first spin coating layer on a substrate using a spin coating process, followed by forming a second spin coating layer or a buffer layer or a composite layer of the second spin coating layer on the first spin coating layer. By selecting a suitable material for the second spin coating layer or the buffer layer and an etching selectivity ratio, each material layer is etched back to obtain a first spin coating layer with a smooth surface, ultimately resulting in a semiconductor device with better product performance.
[0107] To verify the effectiveness of the embodiments of this disclosure, the following description uses a scheme of forming a second spin coating (organic BARC coating) on a first spin coating (SOC coating) as an example.
[0108] First, select organic BARC materials with good planarization and low viscosity, with priority given to KrF-type planarization BARC materials. As shown in Table 1, six combinations of organic BARCs with different thicknesses, different viscosities, and different etching rates are presented.
[0109] Then, the etching rates of the SOC coating and the organic BARC coating were tested separately. Table 1 shows the process parameters of the organic BARC coating.
[0110] Secondly, a SOC coating is formed on the substrate by spin coating, and the morphology of the substrate at a fixed position is measured by atomic force microscopy (AFM). For example, the morphology of the center-edge of the array region, the morphology of the peripheral circuit region, and the morphology of the OVL region are measured.
[0111] Next, an organic BARC coating was formed on the SOC coating by spin coating, and the morphology at the same location as the SOC coating was measured using AFM.
[0112] Finally, the organic BARC coating and the SOC coating are etched back.
[0113] Table 1. Process parameters for spin coating of organic BARC coatings.
[0114]
[0115] After the experiment was completed, AFM measurements were performed on different regions of the AR2 experimental group. The measurement results are shown in Figures 7 to 9.
[0116] Figure 7a and Figure 7b The AFM measurement results for the substrate surface from the center to the edge of the array region are shown after spin-coating with SOC and organic BARC coatings. Figure 7a It can be observed that the surface of the transition region D between the center and edge of the array region has protrusions, indicating that the coating surface is uneven after spin-coating the SOC. This is addressed by spin-coating an organic BARC coating onto the SOC material surface. Figure 7b As shown, the unevenness in transition region D is improved, and the organic BARC coating forms a relatively smooth surface, effectively improving the planarization of the array pattern. This lays the foundation for etching back to form a flat SOC coating. It should be noted that... Figure 7a and Figure 7b The x and y coordinates in the figure are relative coordinates.
[0117] Figures 8a-8bThe AFM test results on the substrate surface of the peripheral circuit region are shown after spin-coating a SOC coating and spin-coating an organic BARC coating. The comparison reveals that spin-coating an organic BARC coating over the SOC coating effectively improves the flatness of the pattern in the peripheral circuit region.
[0118] Figures 9a-9b The AFM test results on the OVL region substrate surface are shown after spin-coating a SOC coating and spin-coating an organic BARC coating. The comparison reveals that spin-coating an organic BARC coating over the SOC coating effectively improves the flatness of the OVL region pattern.
[0119] For the scheme of adding a buffer layer between the first and second swirl coatings and forming a smooth surface of the first swirl coating through etching back etching, the experimental results are the same as those of the scheme without adding a buffer layer, and will not be repeated here.
[0120] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.
[0121] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0122] The above provides a detailed description of a method for fabricating a semiconductor device provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
[0123] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided having densely patterned regions and sparsely patterned regions; A first spin coating is formed on the substrate, covering the densely patterned region and the sparsely patterned region; A second spool coating is formed on the first spool coating, wherein the viscosity of the second spool coating is less than the viscosity of the first spool coating. The first spin coating and the second spin coating are etched, and the etching selectivity ratio of the second spin coating to the first spin coating is controlled within a preset range. The second spin coating and part of the first spin coating are etched away to form a first spin coating with a flat surface. The first spin coating is SOC, and the second spin coating is an organic BARC material layer; The viscosity of the second spin coating is between 2 cps and 14 cps; the viscosity of the first spin coating is between 20 cps and 50 cps. The etching selectivity ratio for the second spin coating and the first spin coating is 1:3 to 1:
1.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the first swirl coating above the dense pattern region is less than the thickness of the first swirl coating above the sparse pattern region, and the thickness difference between the two ranges from 5nm to 20nm.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the first spin coating is between 100nm and 500nm, and the thickness of the second spin coating is between 50nm and 200nm.
4. The method for fabricating a semiconductor device according to any one of claims 1 to 3, characterized in that, The method further includes: A buffer layer is formed between the first spin coating layer and the second spin coating layer; The first spin coating layer, the buffer layer, and the second spin coating layer are etched, and the etching selectivity ratio of the second spin coating layer, the buffer layer, and the first spin coating layer is controlled to etch away the second spin coating layer, the buffer layer, and part of the first spin coating layer.
5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The buffer layer is an inorganic BARC material layer.
6. The method for fabricating a semiconductor device according to claim 4, characterized in that, The thickness of the buffer layer is between 10 nm and 50 nm.
7. The method for fabricating a semiconductor device according to claim 4, characterized in that, The etching process has an etching selectivity ratio between the buffer layer and the second spin coating layer of 5:1 to 10:
1.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching process parameters include: The plasma source power is 12000W~22000W, and the radio frequency is 400kHz; The bias power is 4100W to 5700W, and the radio frequency is 400MHz. The chamber pressure is 10 mtorr to 30 mtorr; The process time is 30s to 120s; The etching gas flow rates are: C4F8: 15 sccm to 45 sccm, C4F6: 20 sccm to 50 sccm, and O2: 40 sccm to 65 sccm.
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