Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a plurality of interlayer dielectric layers on the substrate, a method for forming one of the interlayer dielectric layers includes: forming an initial interlayer dielectric layer on the substrate, the initial interlayer dielectric layer having free radical fluorine therein; performing a defluorination treatment on the initial interlayer dielectric layer to form the interlayer dielectric layer, the method for performing the defluorination treatment includes: diffusing the free radical fluorine in the initial interlayer dielectric layer to a surface of the initial interlayer dielectric layer, wherein a concentration profile of the free radical fluorine in the initial interlayer dielectric layer is different before and after the diffusing of the free radical fluorine to the surface of the initial interlayer dielectric layer; and removing the free radical fluorine diffused to the surface of the initial interlayer dielectric layer. Thus, the performance and reliability of the semiconductor structure are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] As integrated circuit manufacturing progresses towards very large-scale integrated circuits, the density of internal circuits is increasing, the number of components is constantly increasing, and the size of devices is constantly shrinking.

[0003] The fabrication process of semiconductor integrated circuits is extremely complex. It requires creating various electronic components needed for a specific circuit on a small area of ​​silicon wafer, and then forming appropriate conductive structures between these components to establish electrical connections in order for them to perform their intended functions. Furthermore, to ensure that the electrical connections between conductive structures, the electrical insulation between conductive structures, or the electrical insulation between conductive structures and various electronic components meet the circuit design requirements, interlayer dielectric layers must be formed between the conductive structures or between the various electronic components.

[0004] However, the performance and reliability of semiconductor structures formed by existing technologies need to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve the performance and reliability of the semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of interlayer dielectric layers on the substrate; wherein forming one of the interlayer dielectric layers comprises: forming an initial interlayer dielectric layer on the substrate, the initial interlayer dielectric layer containing free radical fluorine; performing a defluorination treatment on the initial interlayer dielectric layer to form the interlayer dielectric layer, the defluorination treatment comprising: diffusing free radical fluorine in the initial interlayer dielectric layer to the surface of the initial interlayer dielectric layer, wherein the concentration distribution of free radical fluorine in the initial interlayer dielectric layer is different before and after the free radical fluorine diffuses to the surface of the initial interlayer dielectric layer; and removing the free radical fluorine diffused to the surface of the initial interlayer dielectric layer.

[0007] Optionally, the mass concentration percentage of free radical fluorine within the interlayer medium is below 0.02%.

[0008] Optionally, free radical fluorine in the initial interlayer dielectric layer can be diffused to the surface of the initial interlayer dielectric layer through one or more annealing processes.

[0009] Optionally, a method for removing free radical fluorine diffused to the surface of the initial interlayer dielectric layer includes: reacting a first gas with the free radical fluorine diffused to the surface of the initial interlayer dielectric layer to form a byproduct gas; and removing the byproduct gas.

[0010] Optionally, the first gas includes at least one of silane, hydrogen, and nitrogen; the byproduct gas includes at least one of silicon fluoride, hydrogen fluoride, and nitrogen fluoride.

[0011] Optionally, during the annealing process, the first gas reacts with free radical fluorine on the surface of the initial interlayer dielectric layer.

[0012] Optionally, the method for removing byproduct gases includes: during the annealing process, extracting the byproduct gases from the reaction chamber to the outside of the reaction chamber.

[0013] Optionally, the temperature range of the annealing process is 300 degrees Celsius to 500 degrees Celsius.

[0014] Optionally, the duration of the annealing process ranges from 10 seconds to 100 seconds.

[0015] Optionally, the method for forming the initial interlayer dielectric layer includes: depositing an interlayer dielectric material layer on the substrate; etching or planarizing the interlayer dielectric material layer to form the initial interlayer dielectric layer.

[0016] Optionally, the method of forming one of the interlayer dielectric layers further includes: etching or planarizing the interlayer dielectric layer after forming the interlayer dielectric layer.

[0017] Optionally, the material of the interlayer dielectric layer includes silicon-fluorine bonds.

[0018] Optionally, the material of the interlayer dielectric layer includes fluorine-doped silicon dioxide.

[0019] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0020] In the semiconductor structure formation method provided by the present invention, free radical fluorine in the initial interlayer dielectric layer diffuses to the surface of the initial interlayer dielectric layer, and the free radical fluorine diffused to the surface of the initial interlayer dielectric layer is removed. Therefore, after each initial interlayer dielectric layer is formed and before a new initial interlayer dielectric layer is formed, the free radical fluorine in the current initial interlayer dielectric layer can be reduced or removed, forming a corresponding interlayer dielectric layer with a low concentration of free radical fluorine. This reduces the free radical fluorine in each interlayer dielectric layer, thereby reducing the risk of bubble pit defects on the surface of the uppermost interlayer dielectric layer under subsequent high-temperature processes, and also reducing the risk of deformation or damage to the semiconductor structure after stress release. In this way, the performance and reliability of the semiconductor structure are improved. Attached Figure Description

[0021] Figures 1 to 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0022] Figure 3 yes Figure 2 A schematic diagram of bubble pit defects on the surface of the interlayer dielectric layer along the X direction;

[0023] Figures 4 to 10 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0024] As described in the background section, the performance and reliability of semiconductor structures formed by existing technologies need to be improved.

[0025] The following detailed explanation, with reference to the accompanying diagrams, explains the reasons for the poor performance and reliability of semiconductor structures. Figures 1 to 2 This is a schematic diagram of the steps involved in forming a semiconductor structure. Figure 3 yes Figure 2 A schematic diagram of bubble pit defects on the surface of the interlayer dielectric layer along the X direction.

[0026] It should be noted that the term "surface" in this specification is used to describe the relative spatial relationship and is not limited to whether there is direct contact.

[0027] Please refer to Figure 1 Provides a base of 100.

[0028] Please refer to Figure 2 A multilayer interlayer dielectric layer 110 is formed on the substrate 100 using a chemical vapor deposition process.

[0029] It should be noted that, for ease of understanding, Figure 2 The semiconductor structure shown does not include the conductive structures and electronic components that are insulated from each other by the interlayer dielectric layers 110.

[0030] In the above method, during the formation of the interlayer dielectric layer 110 by chemical vapor deposition, fluorine is doped in situ to create silicon-fluorine bonds in each interlayer dielectric layer 110, thereby reducing the dielectric constant of the interlayer dielectric layer 110.

[0031] However, while in-situ fluorine doping creates silicon-fluorine bonds within the interlayer dielectric layer 110, it also easily introduces a certain amount of free radical fluorine 111 (e.g., ...) within the interlayer dielectric layer 110. Figure 2 As shown), therefore, the free radical fluorine 111 in each interlayer dielectric layer 110, after being subjected to subsequent high-temperature processes, will diffuse and accumulate to the uppermost surface of the multilayer interlayer dielectric layer 110, and eventually release stress to the semiconductor structure, thereby causing the formation of bubble pit defects (such as...) in the uppermost layer of the multilayer interlayer dielectric layer 110. Figure 3 (as shown in region A), or it may cause the semiconductor structure to bend, deform, or be damaged, resulting in poor performance and reliability of the semiconductor structure.

[0032] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure. By performing a fluorine removal treatment on the initial interlayer dielectric layer during the formation of an interlayer dielectric layer, the performance and reliability of the semiconductor structure are improved.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 4 to 10 This is a cross-sectional structural schematic diagram of each step in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0035] Please refer to Figure 4 Provides a base of 200.

[0036] The substrate 200 is made of semiconductor materials.

[0037] In this embodiment, the substrate 200 is made of silicon.

[0038] In other embodiments, the substrate material includes silicon carbide, silicon-germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0039] In this embodiment, the substrate 200 has a device layer (not shown). The device layer may include device structures, such as PMOS transistors or NMOS transistors. The device layer may also include interconnect structures electrically connected to the device structures, and an insulating layer surrounding the device structures and the interconnect structures.

[0040] Next, several interlayer dielectric layers are formed on the substrate 200. For detailed steps on forming these interlayer dielectric layers, please refer to [link to documentation]. Figures 5 to 9 It should be noted that, for ease of understanding, Figures 5 to 8 These are the detailed steps of a method for forming one of the aforementioned interlayer dielectric layers. Figure 9 This is a schematic cross-sectional view of a semiconductor structure that forms several interlayer dielectric layers.

[0041] Please refer to Figure 5 An interlayer dielectric material layer 210 is formed on the substrate 200.

[0042] The interlayer dielectric material layer 210 provides material for forming the initial interlayer dielectric layer.

[0043] In this embodiment, the process for forming the interlayer dielectric material layer 210 includes a deposition process. The deposition process may be, for example, chemical vapor deposition (CVD) or flow-through chemical vapor deposition (FCVD).

[0044] In this embodiment, during the formation of the interlayer dielectric material layer 210, fluorine is doped into the material of the interlayer dielectric material layer 210 by in-situ doping.

[0045] In this embodiment, the material of the interlayer dielectric material layer 210 includes fluorine-doped silicon dioxide. The material of the interlayer dielectric material layer 210 includes silicon-fluorine bonds (not shown) and free radical fluorine 211.

[0046] Specifically, because fluorine is doped into silicon dioxide through in-situ doping, silicon-fluorine bonds are formed, meaning that the material of the interlayer dielectric layer 210 includes silicon-fluorine bonds. This is beneficial for reducing the subsequent formation of the interlayer dielectric layer 230 (such as...). Figure 8 The dielectric constant (as shown) improves the performance of the semiconductor structure.

[0047] In this embodiment, the interlayer dielectric layer 230 (e.g. Figure 8 The percentage of non-radical fluorine concentration in the interlayer medium layer 230 (as shown) ranges from 2% to 7%. Figure 8 The dielectric constant of the sample (as shown) is below 4.

[0048] In this embodiment, since fluorine is doped into silicon dioxide through in-situ doping, a certain amount of free radical fluorine 211 is also present in the material of the interlayer dielectric material layer 210 while silicon-fluorine bonds are formed.

[0049] Please refer to Figure 6 The interlayer dielectric material layer 210 is etched or planarized to form an initial interlayer dielectric layer 220 on the substrate 200, the initial interlayer dielectric layer 220 containing free radical fluorine 221.

[0050] Since the initial interlayer dielectric layer 220 is formed by etching or planarizing the interlayer dielectric material layer 210 before subsequent fluorine treatment, a portion of the free radical fluorine 211 within the interlayer dielectric material layer 210 is removed along with part of the interlayer dielectric material layer 210 during the etching or planarization process. This reduces the amount of free radical fluorine 211 that needs to be removed in the subsequent defluorination process, thereby improving the process efficiency of forming the semiconductor structure.

[0051] Furthermore, when there is a risk of free radical fluoride forming in the material of the interlayer dielectric material layer 210 during the etching or planarization process, the risk of free radical fluoride in the formed interlayer dielectric layer can be better reduced by performing a defluorination treatment on the initial interlayer dielectric layer 220 after the etching or planarization process.

[0052] It should be noted that, for ease of understanding, Figure 6 The diagram illustrates an example of a planarization process for the interlayer dielectric material layer 210. In actual semiconductor structure formation, the etching or planarization process is selected based on the desired structure or process.

[0053] Similarly, the material of the initial interlayer dielectric layer 220 includes fluorine-doped silicon dioxide, and the material of the initial interlayer dielectric layer 220 includes silicon-fluorine bonds, and the material of the initial interlayer dielectric layer 220 contains a certain number of free radical fluorine 211.

[0054] In another embodiment, an initial interlayer dielectric layer is formed directly on the substrate by a deposition process, and fluorine is doped into the material of the initial interlayer dielectric layer by in-situ doping. Similarly, the material of the initial interlayer dielectric layer comprises fluorine-doped silicon dioxide, and the material of the initial interlayer dielectric layer includes silicon-fluorine bonds and contains a certain amount of free radical fluorine.

[0055] In this embodiment, the planarization process includes a chemical mechanical polishing process. The etching process includes at least one of a wet etching process and a dry etching process.

[0056] Please refer to Figure 7 and Figure 8 , Figure 7 This is a schematic cross-sectional view of a semiconductor structure during the defluorination process of an initial interlayer dielectric layer. Figure 8 This is a cross-sectional schematic diagram of a semiconductor structure after a fluorine removal treatment of an initial interlayer dielectric layer 220. The initial interlayer dielectric layer 220 is subjected to a fluorine removal treatment to form an interlayer dielectric layer 230. The fluorine removal treatment method includes: allowing free radical fluorine 221 in the initial interlayer dielectric layer 220 to diffuse to the surface of the initial interlayer dielectric layer 220; and removing the free radical fluorine 221 that has diffused to the surface of the initial interlayer dielectric layer 220.

[0057] The concentration distribution of free radical fluorine 221 within the initial interlayer dielectric layer 220 differs before and after the diffusion of free radical fluorine 221 to the surface of the initial interlayer dielectric layer 220.

[0058] In this embodiment, by allowing free radical fluorine 221 within the initial interlayer dielectric layer 220 to diffuse to the surface of the initial interlayer dielectric layer 220, and removing the free radical fluorine 221 diffused to the surface of the initial interlayer dielectric layer 220, it is possible to reduce or remove the free radical fluorine 221 within the currently formed initial interlayer dielectric layer 220 after each formation of the initial interlayer dielectric layer 220 and before the formation of a new initial interlayer dielectric layer 220, thereby forming a corresponding interlayer dielectric layer 230 with a low concentration of free radical fluorine 221. This reduces the free radical fluorine 221 within each interlayer dielectric layer 230, thereby reducing the risk of bubble pit defects on the surface of the uppermost interlayer dielectric layer 230 under subsequent high-temperature processes, and also reducing the risk of deformation or damage to the semiconductor structure after stress release, thus improving the performance and reliability of the semiconductor structure.

[0059] In this embodiment, through the defluorination treatment, the mass concentration percentage of free radical fluorine 221 in the interlayer dielectric layer 230 is less than 0.02%.

[0060] In this embodiment, free radical fluorine 221 in the initial interlayer dielectric layer 220 diffuses to the surface of the initial interlayer dielectric layer 220 through one or more annealing processes.

[0061] Specifically, depending on the actual defluorination effect of each defluorination treatment, different numbers of annealing processes can be used to improve the defluorination effect.

[0062] Furthermore, the number of annealing processes used in the defluorination treatment can be selected based on the concentration of free radical fluorine 211 within the initial interlayer dielectric layer 220. This balances the defluorination effect with the efficiency of the semiconductor structure formation process. In this embodiment, the initial interlayer dielectric layer 220 is defluorinated using a seven-stage high-temperature process.

[0063] In this embodiment, the method for removing free radical fluorine 221 diffused to the surface of the initial interlayer dielectric layer 220 includes: reacting a first gas with the free radical fluorine 221 diffused to the surface of the initial interlayer dielectric layer 220 to form a byproduct gas 231; and removing the byproduct gas 231.

[0064] Specifically, by reacting the first gas with the free radical fluorine 221 that diffuses to the surface of the initial interlayer medium layer 220, a byproduct gas 231 is formed. Thus, by removing the byproduct gas 231, the free radical fluorine 221 that diffuses to the surface of the initial interlayer medium layer 220 is removed.

[0065] In this embodiment, the first gas includes silane; the byproduct gas includes at least one of silicon fluoride gas, hydrogen fluoride gas, and nitrogen fluoride gas.

[0066] In this embodiment, during the annealing process, the first gas reacts with free radical fluorine 221 on the surface of the initial interlayer dielectric layer 220.

[0067] Specifically, during the annealing process, on the one hand, the free radical fluorine 221 in the initial interlayer dielectric layer 220 diffuses toward the surface of the initial interlayer dielectric layer 220; on the other hand, the first gas reacts with the free radical fluorine 221 that diffuses to the surface of the initial interlayer dielectric layer 220 to form the byproduct gas 231.

[0068] In this embodiment, the reaction process between the first gas and the free radical fluorine 221 is as follows:

[0069] F + SiH4 (heated) → SiF4 + other gases.

[0070] The SiF4 and the other gases are byproduct gases 231 in this embodiment.

[0071] In one other embodiment, the first gas further includes at least one of hydrogen and nitrogen. In yet another embodiment, the first gas includes at least one of hydrogen and nitrogen. Wherein, when the first gas includes hydrogen, the formed byproduct gas includes hydrogen fluoride gas, and when the first gas includes nitrogen, the formed byproduct gas includes nitrogen fluoride gas.

[0072] In this embodiment, the temperature range of the annealing process is 300 degrees Celsius to 500 degrees Celsius.

[0073] If the annealing temperature is too high, it can easily affect the performance of semiconductor devices, leading to unreliable electrical characteristics and poor reliability. If the annealing temperature is too low, the free radical fluorine 211 within the initial interlayer dielectric layer 220 is difficult to diffuse to the surface of the initial interlayer dielectric layer 220, and the free radical fluorine 211 on the surface of the initial interlayer dielectric layer 220 is difficult to react with the first gas to form byproduct gas 231. Therefore, it is not conducive to achieving a good defluorination effect through the defluorination treatment. Therefore, keeping the annealing temperature within a suitable range, i.e., when the annealing temperature range is 300 degrees Celsius to 500 degrees Celsius, it is possible to reduce the adverse effects of excessively high temperatures on semiconductor devices while improving the defluorination effect of the defluorination treatment, thereby better improving the performance of the semiconductor structure.

[0074] In this embodiment, the duration of each annealing process ranges from 10 seconds to 100 seconds.

[0075] If the time range is too long, it reduces the efficiency of the semiconductor structure formation process. Furthermore, the accumulated heat within the semiconductor structure can negatively impact the electrical characteristics and reliability of the semiconductor device. If the time range is too short, a significant amount of free radical fluorine 211 remains unremoved within the initial interlayer dielectric layer 220, affecting the defluorination effect. Therefore, ensuring the high-temperature process duration is within a suitable range—specifically, 10 to 100 seconds—can reduce adverse effects on the semiconductor device while improving the defluorination effect, thereby enhancing the performance of the semiconductor structure.

[0076] In this embodiment, the method for removing byproduct gas 231 includes: during the annealing process, extracting the byproduct gas 231 from the reaction chamber to the outside of the reaction chamber. Since the reaction between the first gas and the free radical fluorine 211 on the surface of the initial interlayer medium layer 220 forms a gas (byproduct gas 231), by extracting the byproduct gas 231 from the reaction chamber to the outside of the reaction chamber during the annealing process, not only is the removal of byproduct gas 231 achieved, enabling the defluorination treatment to be realized, but also, compared to extracting the byproduct gas 231 separately, the time for removing the byproduct gas 231 is saved, thereby improving the efficiency of the defluorination treatment.

[0077] In other embodiments, after the high-temperature process, the byproduct gas in the reaction chamber is extracted to the outside of the reaction chamber.

[0078] In this embodiment, since the material of the initial interlayer dielectric layer 220 includes silicon-fluorine bonds, the material of the interlayer dielectric layer 230 also includes silicon-fluorine bonds.

[0079] In this embodiment, the material of the interlayer dielectric layer 230 includes fluorine-doped silicon dioxide.

[0080] In another embodiment, the method of forming one of the interlayer dielectric layers further includes: etching or planarizing the interlayer dielectric layer after forming the interlayer dielectric layer.

[0081] Please refer to Figure 9 ,according to Figures 5 to 8 The method shown forms a plurality of interlayer dielectric layers 230 on the substrate 200.

[0082] It should be noted that, in this embodiment, for ease of understanding, Figures 5 to 9 The conductive structure in the semiconductor structure is not illustrated in the diagram. According to design requirements, in the method for forming the semiconductor structure, a conductive structure is formed within or between the plurality of interlayer dielectric layers 230.

[0083] Please refer to Figure 10 After forming several interlayer dielectric layers 230, the semiconductor structure undergoes an overall high-temperature process (alloy process) to release the stress of the semiconductor structure after the entire semiconductor structure formation process.

[0084] In this embodiment, the temperature of the overall high-temperature step is below 500 degrees Celsius. Preferably, the overall high-temperature step is at 400 degrees Celsius.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A plurality of interlayer dielectric layers are formed on the substrate. After each layer of the interlayer dielectric layer is formed and before the formation of a new layer, the free radical fluorine within the interlayer dielectric layer is immediately subjected to a defluorination treatment before the deposition of the next layer. The defluorination treatment method includes: The free radical fluorine in the initial interlayer dielectric layer is diffused to the surface of the initial interlayer dielectric layer through an annealing process, wherein the concentration of free radical fluorine in the initial interlayer dielectric layer decreases before and after the free radical fluorine diffuses to the surface of the initial interlayer dielectric layer. During the annealing process, on the one hand, the free radical fluorine on the surface of the initial interlayer dielectric layer diffuses toward the surface of the initial interlayer dielectric layer; on the other hand, the first gas reacts with the free radical fluorine diffused to the surface of the initial interlayer dielectric layer to form a byproduct gas. The byproduct gas is removed to remove the free radical fluorine diffused to the surface of the initial interlayer dielectric layer. The method for removing byproduct gases includes: during the annealing process, extracting the byproduct gases from the reaction chamber to the outside of the reaction chamber.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The mass concentration percentage of free radical fluorine within the interlayer medium is below 0.02%.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first gas includes at least one of silane, hydrogen, and nitrogen; the byproduct gas includes at least one of silicon fluoride, hydrogen fluoride, and nitrogen fluoride.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The annealing process has a temperature range of 300 degrees Celsius to 500 degrees Celsius.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The duration of the annealing process ranges from 10 seconds to 100 seconds.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming an initial interlayer dielectric layer includes: depositing an interlayer dielectric material layer on the substrate; etching or planarizing the interlayer dielectric material layer to form the initial interlayer dielectric layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming one of the interlayer dielectric layers further includes: etching or planarizing the interlayer dielectric layer after forming the interlayer dielectric layer.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the interlayer dielectric layer includes silicon-fluorine bonds.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The material of the interlayer dielectric layer includes fluorine-doped silicon dioxide.

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