Interconnect structures containing graphite and their formation methods

Abstract

This disclosure relates to interconnect structures comprising graphite and methods for forming the same. One method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form the graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is above and electrically connected to the graphite conductive feature.

Description

Technical Field

[0001] This disclosure generally relates to interconnect structures comprising graphite and methods for forming the same. Background Technology

[0002] Interconnect structures are used in integrated circuits to interconnect devices such as transistors, diodes, and capacitors to form functional circuits. Traditional interconnect structures can include damascene structures. Damascene structures typically include a barrier layer and copper regions on the barrier layer, with the barrier layer formed on the opposite side of the copper regions.

[0003] As the width of interconnect structures continues to decrease, the thickness of the barrier layer is becoming an increasingly larger part of the interconnect structure. For example, when the width of the metal line is less than 10 nm, the thickness of the barrier layer / pad layer still needs to be approximately [missing information]. This is used as a barrier layer to effectively prevent copper diffusion through. This means the barrier layer uses approximately... Because the barrier / pad layer extends on the opposite side of the copper area. This leaves less than Copper regions are formed using this method. However, when the copper size is smaller than 10 nm, the resistivity of copper increases significantly. Therefore, the resistance value of the metal lines may not meet the requirements of the interconnect structure. Summary of the Invention

[0004] According to one aspect of this disclosure, a method of manufacturing an interconnect structure is provided, comprising: forming a first conductive feature; depositing a graphite layer over the first conductive feature; patterning the graphite layer to form a graphite conductive feature; depositing a dielectric spacer layer on the graphite layer; depositing a first dielectric layer over the dielectric spacer layer; planarizing the first dielectric layer; forming a second dielectric layer over the first dielectric layer; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature is over the graphite conductive feature and electrically connected to the graphite conductive feature.

[0005] According to another aspect of this disclosure, an interconnect structure is provided, comprising: a first conductive feature; a graphite conductive feature above and electrically coupled to the first conductive feature; a dielectric spacer layer including a sidewall portion on a sidewall of the graphite conductive feature; a first dielectric layer surrounding the sidewall portion of the dielectric spacer layer; an etch stop layer above the first dielectric layer and the graphite conductive feature; a second dielectric layer above the etch stop layer; and a second conductive feature passing through the second dielectric layer, wherein the second conductive feature is above and electrically connected to the graphite conductive feature.

[0006] According to another aspect of this disclosure, an interconnect structure is provided, comprising: an integrated circuit; a dual damascene structure including: a metal line and a via, wherein the dual damascene structure includes a barrier layer and a copper region above the barrier layer; a graphite line electrically coupled between the via and the integrated circuit; and a dielectric spacer layer surrounding the graphite line. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figures 1-12 A cross-sectional view is shown of an intermediate stage in the formation of a graphite-containing interconnect structure according to some embodiments.

[0009] Figure 13 A top view of a portion of a graphite-containing interconnect structure according to some embodiments is shown.

[0010] Figures 14-16 A cross-sectional view is shown of an intermediate stage in the formation of a graphite-containing interconnect structure according to some embodiments.

[0011] Figure 17 , Figure 18 and Figure 19 Cross-sectional views of interconnect structures according to some embodiments are shown, wherein each interconnect structure includes a layer of graphite-containing features in one of a fin field-effect transistor (FinFET), a nanosheet transistor, or a nanowire transistor.

[0012] Figure 20 , Figure 21 and Figure 22 Cross-sectional views of interconnect structures according to some embodiments are shown, wherein each interconnect structure includes two layers of graphite-containing features in a fin field-effect transistor (FinFET), a nanosheet transistor, or a nanowire transistor.

[0013] Figure 23 A process flow for forming an interconnect structure containing graphite, according to some embodiments, is shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In addition, for ease of description, spatially related terms (e.g., "below," "below," "lower than," "above," "upper") may be used herein to describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0016] An interconnect structure incorporating graphite conductive features and a method for forming the same are provided. According to some embodiments of this disclosure, a graphite layer is deposited. The graphite layer is patterned to form conductive features, such as conductive lines, conductive vias, conductive plugs, etc. A spacer layer may be deposited on the graphite conductive features to prevent peeling. By using graphite as the conductive material for forming the interconnect structure, a diffusion barrier layer is not required. Therefore, the lateral dimensions (e.g., width) of the resulting conductive features can be reduced. The graphite-incorporating interconnect structure according to embodiments of this disclosure is well-suited for first back-end process (BEOL) layers due to the material of its underlying features. The embodiments discussed herein will provide examples to enable the manufacture or use of the subject matter of this disclosure, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0017] Figures 1 to 12 A cross-sectional view is shown illustrating an intermediate stage in the formation of a graphite-containing interconnect structure according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in... Figure 23 The process flow shown is as follows.

[0018] Figure 1A cross-sectional view of package assembly 20 is shown. According to some embodiments of this disclosure, package assembly 20 is a device wafer including active devices and possibly passive devices (represented by the illustrated integrated circuit device 26). Device wafer 20 may include a plurality of dies 22, one of which is shown. According to alternative embodiments of this disclosure, package assembly 20 is an interposer wafer, which may or may not include active devices and / or passive devices. In the following discussion, device wafers are discussed as examples of package assembly 20. Embodiments of this disclosure can also be applied to other types of package assemblies, such as interposer wafers, package substrates, packages, etc.

[0019] According to some embodiments of this disclosure, wafer 20 includes a semiconductor substrate 24 and features formed at the top surface of the semiconductor substrate 24. The semiconductor substrate 24 may be formed of crystalline silicon, crystalline germanium, silicon-germanium, or a III-V compound semiconductor (e.g., GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc.). The semiconductor substrate 24 may also be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 24 to isolate active regions in the semiconductor substrate 24. Although not shown, vias may (or may not) be formed to extend into the semiconductor substrate 24, wherein the vias are used to electrically couple features on opposite sides of wafer 20 to each other.

[0020] According to some embodiments of this disclosure, integrated circuit device 26 is formed on the top surface of semiconductor substrate 24. According to some embodiments, integrated circuit device 26 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Figure 1 Details of the integrated circuit device 26 are not shown in the figure. Figures 17 to 22 Schematic diagrams of some example transistors according to some embodiments are shown, including fin field-effect transistors (FinFETs), nanosheet transistors, and nanowire transistors, etc. According to an alternative embodiment, wafer 20 is used to form an interposer layer, and substrate 24 may be a semiconductor substrate or a dielectric substrate.

[0021] A dielectric layer 28 is formed above the integrated circuit device 26. According to some embodiments, the dielectric layer 28 is an interlayer dielectric (ILD) in which contact plugs are formed. The corresponding materials can be or may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. According to alternative embodiments, the dielectric layer 28 is an intermetallic dielectric (IMD) in which metal lines (which may include vias) are formed. The corresponding dielectric materials may include carbon-containing low-k dielectric materials, HSQ, MSQ, etc. The dielectric layer 28 can be formed using spin coating, flow chemical vapor deposition (FCVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0022] Conductive features 30 are formed in the dielectric layer 28 and are used to electrically connect the integrated circuit device 26 to the overlying metal lines and vias. The corresponding processes are as follows: Figure 23 The process flow 200 shown is illustrated as process 202. According to some embodiments where the dielectric layer 28 is an IMD, the conductive feature 30 is a contact plug, and therefore may be referred to hereinafter as contact plug 30. According to an alternative embodiment, the dielectric layer 28 may be an IMD, and the conductive feature 30 may be a via, conductive line, etc. According to another alternative embodiment, the conductive feature 30 is the gate electrode of a transistor.

[0023] According to some embodiments, each conductive feature 30 includes a barrier 30A and a conductive material 30B on the barrier 30A. The barrier 30A may be formed of a conductive material selected from titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multiple layers thereof. The conductive material may include copper, cobalt, tungsten, ruthenium, etc., or alloys thereof. According to alternative embodiments, the conductive feature 30 is unbarrier-free and formed of a homogeneous material, which may include cobalt, tungsten, ruthenium, etc., or alloys thereof. The lateral dimension of the conductive feature 30 may be less than about 20 nm and may be in the range of about 6 nm to about 15 nm.

[0024] The formation of conductive feature 30 may include forming a contact opening in dielectric layer 28, filling the contact opening with one or more conductive materials, and performing a planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical polishing process, to make the top surface of conductive feature 30 flush with the top surface of dielectric layer 28.

[0025] According to an alternative embodiment, the conductive feature 30 is formed of graphite, and therefore has the following properties: Figure 12 and Figure 16 The structure of the graphite conductive feature 32A' is shown. The formation process of the conductive feature 30 and the corresponding dielectric layer 28 can be compared with that of... Figures 2 to 9 ,or Figures 2 to 8and Figure 14 The basic structure is the same as shown. The corresponding dielectric layer 28 may therefore include a dielectric spacer layer and an etch stop layer, as will be discussed in subsequent paragraphs.

[0026] refer to Figure 2 A 32-layer graphite layer was deposited. The corresponding process is as follows: Figure 23 The process flow 200 is shown as process 204. According to some embodiments, the deposition of graphite layer 32 is performed by plasma-enhanced chemical vapor deposition (PECVD); however, other methods such as CVD, ALD, pyrolysis, etc., can also be used. Precursors may include carbon-containing gases (e.g., CH4, C2H2, etc.), hydrocarbons, or combinations thereof. Other gases, such as H2, Ar, etc., may also be added. During the deposition process, the temperature of wafer 20 can be in the range of approximately 200°C to approximately 600°C. The flow rate of the carbon-containing gas during the deposition process can be in the range of approximately 100 sccm to approximately 500 sccm. The flow rate of hydrogen (H2, if used) can be in the range of approximately 1000 sccm to approximately 6000 sccm. The thickness T1 of graphite layer 32 can be in the range of approximately 15 nm to approximately 30 nm. As a result of the deposition process, multiple graphene layers are formed, each being a layer of carbon atoms arranged in a hexagonal or honeycomb lattice. Multiple graphene layers together form graphite layer 32.

[0027] refer to Figure 3 A hard mask 34 is deposited on the graphite layer 32. The corresponding process is as follows: Figure 23 The process flow 200 is shown as process 206. According to some embodiments, the hard mask 34 includes silicon nitride, silicon oxide, silicon oxynitride, etc., or combinations thereof. Next, an etch mask 36 is formed over the hard mask 34 and is patterned. The corresponding process is as follows: Figure 23 The process flow 200 is shown as process 208. Therefore, an opening 38 is formed in the etching mask 36. According to some embodiments, the etching mask 36 includes a single photoresist layer. According to alternative embodiments, the etching mask 36 may have a two-layer structure, a three-layer structure, etc.

[0028] Next, refer to Figure 4 An etching process 40 is performed to pattern the hard mask 34. The corresponding process is as follows: Figure 23The process flow 200 is shown as process 210. The opening 38 thus extends into the hard mask 34, and the graphite layer 32 is exposed. The etching process 40 is anisotropic. The etching gas is selected based on the materials of the hard mask 36, the etching mask 34, and the graphite layer 32. For example, etch photoresist and oxygen (O2) from graphite are not used. When the hard mask 34 comprises silicon nitride, the etching gas may include fluorine-containing gases such as CF4, NF3, SF6, CHF3, or combinations thereof. Other gases may also be added, such as N2, H2, Ar, etc. When the hard mask 34 comprises silicon oxide, the etching gas may include a mixture of NF3 and NH3, or a mixture of HF and NH3.

[0029] Next, refer to Figure 5 An etching process 42 is performed to etch the graphite layer 32, thereby forming multiple graphite features 32'. The corresponding process is as follows: Figure 23 The process flow 200 is shown as process 212. Graphite feature 32' may include graphite conductive feature 32A' for electrical connection and graphite sealing ring 32B'. For example, graphite conductive feature 32A' may be electrically connected to integrated circuit device 26 via conductive feature 30. Etching may be performed by reactive ion etching (RIE). Graphite sealing ring 32B' is formed near the periphery of device die 22. For example, after a subsequent separation process for cutting die 22 from wafer 20, graphite sealing ring 32B' may include four portions, each parallel to and adjacent to a corresponding adjacent edge of the respective die 22. The portions of graphite sealing ring 32B' adjacent to the edge of the respective die 22 are interconnected to form a complete ring. The sealing ring functions to prevent harmful substances such as moisture from penetrating from the external environment into the internal region of die 22. Sealing ring 32B' may be electrically grounded or electrically floated in the final structure, for example, after device die separation and when device die is powered on. The graphite conductive feature 32A' can be an elongated conductive wire. Alternatively, the graphite conductive feature 32A' can be formed into a conductive pad, via, contact plug, etc., which can be elongated or non-elongated.

[0030] Etching process 42 is anisotropic, in which plasma is generated from an etching gas to etch graphite layer 32. According to some embodiments, the etching gas has the function of consuming etching mask 36 and simultaneously etching graphite layer 32. For example, the etching gas may include oxygen (O2), which can ashing photoresist and simultaneously etching graphite layer 32. Other carbon-etchable gases, such as Ar, CO2, etc., may also be used. During etching process 42, etching mask 36 may be completely consumed, and the underlying hard mask 34 begins to function as the etching mask. The exposed graphite layer 32 is etched, and an opening 38 extends into the underlying dielectric layer 28. The opening 38 separates the remaining portion of graphite layer 32 into discrete features, such as conductive feature 32A' and graphite sealing ring 32B'. According to an alternative embodiment, etching mask 36 is first removed without etching graphite layer 32, and then hard mask 34 is used as the etching mask to etch graphite layer 32. After etching graphite layer 32, hard mask 34 is removed.

[0031] Figure 6 The structure after removing the hard mask 34 is shown. According to some embodiments, the spacing P1 of the graphite conductive features 32A' can be less than approximately 25 nm. The top width TCD-A of the graphite conductive features 32A' can be less than approximately 15 nm or less than approximately 12 nm. The top width TCD-A can also be in the range of approximately 8 nm to approximately 11 nm. The bottom width BCD-A of the graphite conductive features 32A' is greater than the corresponding top width TCD-A and can be less than approximately 16 nm or less than approximately 13 nm. The bottom width BCD-A can also be in the range of approximately 8.5 nm to approximately 12 nm. The top width TCD-B of the graphite sealing ring 32B' can be less than approximately 200 nm or less than approximately 180 nm. The top width TCD-B can also be in the range of approximately 100 nm to approximately 180 nm. The bottom width BCD-B of the graphite sealing ring 32B' is greater than the corresponding top width TCD-B and can be less than approximately 200 nm or less than approximately 180 nm. The bottom width BCD-B can also be in the range of approximately 100 nm to approximately 180 nm, where the bottom width BCD-B is slightly larger than the top width TCD-B, for example, the difference (BCD-B-TCD-B) is in the range of approximately 0.5 nm to approximately 2 nm.

[0032] Because the graphene layers in graphite layer 32 can peel off from each other, the dielectric spacer layer 44 can be deposited on each of the graphite conductive feature 32A' and the graphite sealing ring 32B', and surround each of the graphite conductive feature 32A' and the graphite sealing ring 32B', as shown. Figure 7 As shown. The corresponding process is as follows: Figure 23The process flow 200 is shown as process 214. The dielectric spacer layer 44 can be a conformal layer, which can be deposited using conformal deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. The material of the dielectric spacer layer 44 can include silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, etc., combinations thereof, and / or multiple layers thereof. The thickness T2 of the dielectric spacer layer 44 is selected to be neither too thin nor too thick. If the dielectric spacer layer 44 is too thin, it may not be able to adequately prevent delamination between graphene layers. Conversely, if the dielectric spacer layer 44 is too thick, the spacing between adjacent graphite conductive features 32A' may have to be disadvantageously increased to accommodate the thick spacer layer 44. According to some embodiments, the thickness T2 of the dielectric spacer layer 44 can be approximately With approximately Within the range between.

[0033] In the processes discussed above, the graphite conductive features 32A' and graphite sealing ring 32B' may be exposed to various adverse environments, such as chemicals and plasmas used in previous etching processes, and plasmas used in the deposition of the dielectric spacer layer 44. As a result, the surface layer 32” of the graphite conductive features 32A' and graphite sealing ring 32B' may change in structure and composition. For example, the original crystalline surface layer may be transformed into an amorphous carbon layer. In addition, impurities such as oxygen and fluorine may be doped into the surface layer 32”. The surface layer 32” may also include some oxides. On the other hand, the internal portions of the graphite conductive features 32A' and graphite sealing ring 32B' remain unchanged. According to some embodiments, an amorphous surface layer is formed due to the loss of the crystalline structure in the graphite, and therefore the resulting amorphous layer is mainly carbon, for example, having a carbon percentage greater than about 80% and about 95%.

[0034] According to some embodiments, the surface layer 32” forms an interface layer with the dielectric spacer layer 44, and an interface layer (not shown) is formed therebetween. The interface layer includes the material of the dielectric spacer layer 44 and may further include carbon and oxygen, and may or may not include fluorine. Depending on the composition and structure, the surface layer 32” may be conductive or electrically insulating. The surface layer 32” may also be conductive, but its conductivity value is lower than that of the internal crystalline portion. In the following discussion, the surface layer 32” may be considered as a conversion portion of the graphite layer or as a separate layer on the graphite layer.

[0035] In comparison, the internal portions of the graphite conductive feature 32A' and the graphite sealing ring 32B' have a crystalline structure and are free of impurities. For example, the impurity concentration in the internal portions (e.g., the centers of the corresponding graphite conductive feature 32A' and graphite sealing ring 32B') may be equal to 0, or alternatively not equal to 0, but less than 10% or 1% of the impurity concentration in the surface layer 32". According to some embodiments, the thickness T3 of the surface layer 32" can be approximately With approximately Within the range between.

[0036] According to an alternative embodiment, the dielectric spacer layer 44 is not formed. Therefore, the dielectric layer 48 formed subsequently ( Figure 8 The surface layer 32" will contact the top surface and sidewalls of the graphite conductive feature 32A' and the graphite sealing ring 32B'. According to some embodiments, the surface layer 32" forms an interface layer with the dielectric layer 48, and an interface layer is formed therebetween. The interface layer accordingly comprises the material of the dielectric layer 48, carbon, and oxygen, and may or may not include fluorine.

[0037] According to some embodiments, the amorphous surface layer 32” is not removed, such as... Figure 8 As shown. According to an alternative embodiment, the amorphous surface layer 32” is removed by plasma treatment, wherein hydrogen (H2) can be used in this process. As a result, the crystalline interior portions of the graphite conductive features 32A' and the graphite sealing ring 32B' come into contact with the dielectric spacer layer 44, or with the dielectric layer 48 ( Figure 8 Contact (if no dielectric spacer layer 44 is formed).

[0038] refer to Figure 8 Dielectric layer 48 is deposited above dielectric spacer layer 44. The corresponding process is as follows: Figure 23 The process flow 200 shown is illustrated as process 216. According to some embodiments, the dielectric layer 48 is also an ILD layer. Therefore, the dielectric layer 48 may include PSG, BSG, BPSG, FSG, silicon oxide, etc. The dielectric layer 48 can be formed using spin coating, flow chemical vapor deposition (FCVD), PECVD, low-pressure chemical vapor deposition (LPCVD), etc.

[0039] According to alternative embodiments, dielectric layer 48 is an IMD layer for forming metal lines and / or vias. According to some embodiments of this disclosure, dielectric layer 48 is formed of, or comprises, a low-k dielectric material having a dielectric constant (k value) below 3.8, and the dielectric constant may also be below about 3.0, for example, between about 2.5 and 3.0. Dielectric layer 48 may include carbon-containing low-k dielectric materials, HSQ, MSQ, etc. According to some embodiments, the formation of dielectric layer 48 includes depositing a dielectric material containing a pore-forming agent, followed by a curing process to remove the pore-forming agent, thus leaving dielectric layer 48 porous.

[0040] refer to Figure 9 This involves performing planarization processes such as chemical mechanical polishing (CMP) or mechanical grinding. The corresponding processes are as follows: Figure 23 The process flow 200 is shown as process 218. The planarization process can be performed using the dielectric spacer layer 44 as a polishing stop layer. Therefore, the top surface of the horizontal portion of the dielectric spacer layer 44 is exposed, and the top surface of the dielectric spacer layer 44 is coplanar with the top surface of the dielectric layer 48.

[0041] Figure 10 The deposition of etch stop layer 50 is shown. The corresponding process is as follows: Figure 23 The process flow 200 is shown as process 220. According to some embodiments, the etch stop layer 50 is formed of a material selected from SiN, SiC, SiON, SiOC, SiCN, or combinations thereof. The etch stop layer 50 may also include metal oxides, metal nitrides, etc. The etch stop layer 50 may be a single layer formed of a homogeneous material, or it may be a composite layer including multiple dielectric sublayers. According to some embodiments of this disclosure, the etch stop layer 50 includes an aluminum nitride layer, a SiOC layer above the aluminum nitride layer, and an aluminum oxide layer above the SiOC layer.

[0042] Further reference Figure 10 A dielectric layer 52 is deposited. The corresponding process is as follows: Figure 23 The process flow 200 shown is illustrated as process 222. According to some embodiments, the dielectric layer 52 may be an ILD layer or an IMD layer, and therefore may be formed from or include the following: silicon oxide, PSG, BSG, BPSG, FSG, carbon-containing low-k dielectric materials, HSQ, MSQ, etc. According to some embodiments of this disclosure, the dielectric layer 52 may be formed from, or include, a low-k dielectric material having a dielectric constant below 3.8, and the dielectric constant may be below approximately 3.0. The dielectric layer 52 may also be porous.

[0043] refer to Figure 11 Trench 56 and via opening 54 are formed in dielectric layer 52. The corresponding process is as follows: Figure 23 The process flow 200 is shown as process 224. According to some embodiments of this disclosure, a hard metal mask (not shown) is formed and patterned to define a pattern for trench 56. A photolithography process is performed to etch a dielectric layer 52 to form a via opening 54. The via opening extends from the top surface of the dielectric layer 52 to an intermediate level between the top and bottom surfaces of the dielectric layer 52. An anisotropic etching process is then performed using the hard metal mask as an etching mask to etch the dielectric layer 52 and form trench 56. While forming trench 56, the via opening extends downward, thus forming via opening 54. A time-mode can be used to perform the etching for forming trench 56. According to an alternative embodiment, via opening 54 and trench 56 are formed in separate photolithography processes. For example, in a first photolithography process, via opening 54 is formed extending downward to reach etch stop layer 50. In a second photolithography process, trench 56 is formed.

[0044] Next, the etch stop layer 50 is etched. Etching can be performed using either a dry etching process or a wet etching process. Next, the etching passes through the dielectric spacer layer 44, exposing the underlying surface layer 32” or graphite conductive feature 32A’ and graphite sealing ring 32B’. According to some embodiments, when the surface layer 32” is conductive, the via opening 54 stops on the top surface of the surface layer 32”. According to alternative embodiments (when the surface layer 32” is conductive or electrically insulating), the via opening 54 can pass through the surface layer 32”, exposing the internal portions of the graphite conductive feature 32A’ and graphite sealing ring 32B’, which are crystalline graphene layers.

[0045] refer to Figure 12 A barrier layer 58 is deposited. According to some embodiments, the barrier layer 58 is formed of or includes titanium, titanium nitride, tantalum, tantalum nitride, etc. The barrier layer 58 can be formed as a conformal layer, which can be formed using CVD, ALD, PVD, etc. After forming the barrier layer 58, a metal seed layer (not shown) is formed. The metal seed layer can be formed of or include copper, and can be formed, for example, using PVD.

[0046] Figure 12Further illustration shows the deposition of conductive material 60. According to some embodiments, conductive material 60 includes copper or copper alloys, cobalt, tungsten, aluminum, etc., or alloys thereof. Deposition processes may include electrochemical plating (ECP), electroless plating, CVD, etc. The conductive material 60 completely fills the via openings 54 and trenches 56. Next, a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove excess portions of the conductive material 60 and the barrier layer 58. The planarization process may stop at the top surface of the dielectric layer 52. The remaining portions of the conductive material 60 and the barrier layer 58 form vias 62 and metal lines 64. Corresponding processes are described in... Figure 23 The process flow 200 shown is illustrated as process 226. Metal line 64 includes metal line 64A and sealing ring 64B. Via 62 includes metal via 62A and sealing ring 62B. Via 62, metal line 64, graphite conductive feature 32A', and conductive feature 30 form part of interconnect structure 66.

[0047] In such Figure 11 and Figure 12 In the example embodiment shown, a dual-damascene structure is formed. According to an alternative embodiment, a single-damascene process can be performed, and metal vias, metal wires, or metal contact plugs are formed above and in contact with the graphite conductive feature 32A' and the graphite sealing ring 32B'. According to these embodiments, the top width of the graphite conductive feature 32A' can be greater than the bottom width of the corresponding overlying single-damascene structure. According to another alternative embodiment, graphite can be used to form additional conductive features above the graphite conductive feature 32A' and the graphite sealing ring 32B', and these additional conductive features are in contact with the graphite conductive feature 32A' and the graphite sealing ring 32B'. The materials and forming processes can be substantially the same as those provided above.

[0048] In subsequent processes, more conductive features are formed above the metal wire 64 to form more layers for the interconnect structure 66. Since the upper conductive layer can have a larger spacing and width than the lower layer, graphite can be used to form the lower layer of the interconnect structure, while the upper layer can be formed using a mosaic process. Separator layers, such as layers M0, M1, or M2, can be present, and the layers above and including these separator layers are graphite-free, with all graphite-containing layers located below the separator layers. As more layers are formed for the interconnect structure 66, sealing rings are also formed above and electrically connected to the lower sealing rings 64B and 62B, and connected to the sealing rings including the graphite sealing ring 32B' and the surrounding portion of the dielectric spacer layer 44.

[0049] Figure 13A top view is shown of a portion of a graphite conductive feature 32A' (or graphite sealing ring 32B') and a corresponding surface layer 32” according to some embodiments. A via 62 may pass through the surface layer 32”. Furthermore, the surface layer 32” may form a ring surrounding the inner portion of the corresponding graphite conductive feature 32A' and graphite sealing ring 32B'.

[0050] Figures 14 to 16 A cross-sectional view is shown of an intermediate stage in the formation of a graphite-containing interconnect structure according to an alternative embodiment of the present disclosure. These embodiments are similar to... Figures 1 to 12 The embodiment shown differs in that, during the planarization of dielectric layer 48, a portion of the top surface of dielectric spacer layer 44 is also removed. Unless otherwise stated, the materials and fabrication processes of the components in these embodiments are the same as those in the previous embodiments. Figures 1 to 12 The same components, indicated by the same reference numerals, shown in the foregoing embodiments are substantially the same. Therefore, with Figures 14 to 16 Details regarding the forming process and materials of the components shown can be found in the discussion of the foregoing embodiments.

[0051] The initial process of these embodiments and Figures 1 to 8 The following is essentially the same as shown, wherein a dielectric spacer layer 44 is formed to cover the sidewalls and top surface of the graphite conductive feature 32A' and the graphite sealing ring 32B'. The surface layer 32" may not be removed, or may be removed using plasma treatment. A dielectric layer 48 is also deposited. Next, as shown... Figure 14 As shown, a planarization process is performed. The planarization process is performed until the horizontal portion of the dielectric spacer layer 44 on top of the graphite conductive feature 32A' and the graphite sealing ring 32B' is removed. According to some embodiments, the horizontal portion of the surface layer 32” on top of the graphite conductive feature 32A' and the graphite sealing ring 32B' is also removed. Therefore, the top surface of the inner crystalline graphite portion is exposed. According to an alternative embodiment, the horizontal portion of the surface layer 32” on top of the graphite conductive feature 32A' and the graphite sealing ring 32B' is retained after the planarization process.

[0052] Figure 15 The deposition of etch stop layer 50 and dielectric layer 52 is shown. Etch stop layer 50 may contact the horizontal portion of surface layer 32” on top of graphite conductive feature 32A' and graphite sealing ring 32B'. Alternatively, if the horizontal portion of surface layer 32” has been removed in a planarization process, etch stop layer 50 may contact the top surface of the inner crystal portion.

[0053] Figure 16The formation of via 62 and metal line 64 is shown. According to some embodiments in which surface layer 32” has a horizontal portion, via 62 may fall on the top surface of surface layer 32”, or alternatively, pass through the horizontal portion of surface layer 32”. According to some embodiments in which surface layer 32” does not have a horizontal portion or is absent, via 62 falls directly on the top surface of the inner crystalline portion of graphite conductive feature 32A' and graphite sealing ring 32B'.

[0054] Figures 17 to 19 The use of graphite conductive feature 32A' in various types of transistors is illustrated. Although not shown, graphite sealing ring 32B' can also be formed in these structures. These figures are schematic and show portions of the channel and gate stack forming the transistor, while some other portions are not shown. Furthermore, several layers of the interconnect structure are shown.

[0055] Figure 17 An interconnect structure connected to a FinFET 70 is shown. The FinFET 70 includes a semiconductor fin 72 and a gate stack 74 on the top surface and sidewalls of the semiconductor fin 72. According to some embodiments, a graphite conductive feature 32A' is above and in direct contact with the gate stack 74. According to alternative embodiments, the graphite conductive feature 32A' may be above and in contact with contact plugs, vias, metal lines, etc. Figure 18 A nanosheet transistor 70' is shown, which includes a nanosheet 82 and a gate stack 84 surrounding the nanosheet 82. Figure 19 A nanowire transistor 70" is shown, which includes nanowires 82' and a gate stack 84' surrounding the nanowires 82'. The gate stack 74 ( Figure 17 ), 84 Figure 18 ) and 84'( Figure 19 This may include a high-k gate dielectric. In Figure 18 and Figure 19 In this context, the graphite conductive feature 32A' can also be located above the corresponding gate stacks 84 and 84' and in direct contact with the corresponding gate stacks 84 and 84', or it can be located above the gate stacks, vias, metal lines, etc. and in contact with the gate stacks, vias, metal lines, etc.

[0056] Figure 20 , Figure 21 and Figure 22 The use of graphite conductive feature 32A' in various types of transistors is illustrated. These embodiments are respectively similar to Figure 17 , Figure 18 and Figure 19 The embodiment shown differs in that it illustrates two layers of graphite conductive feature 32A' instead of a single layer. The remaining features are the same as... Figure 17, Figure 18 and Figure 19 The basic principles shown are the same, and will not be repeated here. These embodiments can be used when the upper layer of the interconnect structure does not have sufficient width to allow for a barrier layer, and therefore graphite is used to form the conductive features therein.

[0057] like Figures 17 to 22 As shown, the lower layer of contact plugs, metal lines, vias, etc., can use graphite, allowing the width of the corresponding conductive features to be smaller. Since the upper metal layer can have a larger width and greater spacing than the corresponding lower layer, metal lines (e.g., including barrier layers and copper) can be used from certain layers of the interconnect structure upwards, and no graphite features may be present in the upper layer.

[0058] The embodiments disclosed have several advantageous features. When the corresponding width is less than 10 nm, the resistivity of conventional conductive materials such as copper and aluminum can increase significantly. However, graphite is not affected by this effect. Therefore, graphite is used to form narrow conductive features. Furthermore, graphite does not require a diffusion barrier layer. The scaling of integrated circuits can thus be advanced to even smaller dimensions.

[0059] According to some embodiments of this disclosure, a method includes: forming a first conductive feature; depositing a graphite layer over the first conductive feature; patterning the graphite layer to form a graphite conductive feature; depositing a dielectric spacer layer on the graphite layer; depositing a first dielectric layer over the dielectric spacer layer; planarizing the first dielectric layer; forming a second dielectric layer over the first dielectric layer; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature is over the graphite conductive feature and electrically connected to the graphite conductive feature. In one embodiment, the planarization of the first dielectric layer stops at the top surface of a horizontal portion of the dielectric spacer layer, wherein the horizontal portion overlaps with the graphite conductive feature, and wherein the second conductive feature passes through the horizontal portion of the dielectric spacer layer. In one embodiment, during planarization, the horizontal portion of the dielectric spacer layer is removed, and wherein the horizontal portion overlaps with the graphite conductive feature. In one embodiment, after forming the dielectric spacer layer, a surface portion of the graphite conductive feature has been converted into an amorphous layer, and the dielectric spacer layer is deposited on the amorphous layer. In one embodiment, the planarization of the first dielectric layer stops at the top surface of a horizontal portion of the amorphous layer, wherein the horizontal portion overlaps with the graphite conductive feature. In one embodiment, during planarization, a horizontal portion of the amorphous layer is removed, wherein the horizontal portion overlaps with the graphite conductive feature. In one embodiment, the patterned graphite layer further forms a graphite sealing ring. In one embodiment, the method further includes forming a conductive ring in a second dielectric layer, wherein the conductive ring is above and electrically connected to the graphite sealing ring. In one embodiment, plasma-enhanced chemical vapor deposition is used to perform the deposition of the graphite layer. In one embodiment, a damascene process is used to form the second conductive feature, and the second conductive feature comprises copper. In one embodiment, the method further includes depositing an etch stop layer over the first dielectric layer and the graphite conductive feature, wherein a second dielectric layer is deposited over the etch stop layer.

[0060] According to some embodiments of this disclosure, a structure includes: a first conductive feature; a graphite conductive feature above and electrically coupled to the first conductive feature; a dielectric spacer layer including a sidewall portion on a sidewall of the graphite conductive feature; a first dielectric layer surrounding the sidewall portion of the dielectric spacer layer; an etch stop layer above the first dielectric layer and the graphite conductive feature; a second dielectric layer above the etch stop layer; and a second conductive feature passing through the second dielectric layer, wherein the second conductive feature is above and electrically connected to the graphite conductive feature. In one embodiment, the graphite conductive feature has a lateral dimension of less than about 12 nm. In one embodiment, the dielectric spacer layer further includes a horizontal portion overlapping the graphite conductive feature, and wherein the second conductive feature also passes through the horizontal portion of the dielectric spacer layer. In one embodiment, the structure further includes an amorphous carbon layer above and in contact with the graphite conductive feature, wherein the second conductive feature is above and in contact with the top surface of the amorphous carbon layer. In one embodiment, the structure further includes an amorphous carbon layer, wherein the second conductive feature extends through the amorphous carbon layer to contact the crystalline interior portion of the graphite conductive feature. In one embodiment, the amorphous carbon layer also contains fluorine.

[0061] According to some embodiments of this disclosure, a structure includes: an integrated circuit; a dual damascene structure including a metal line and a via, wherein the dual damascene structure includes a barrier layer and a copper region above the barrier layer; a graphite line electrically coupled between the via and the integrated circuit; and a dielectric spacer layer surrounding the graphite line. In one embodiment, the graphite line has a top width and a bottom width greater than the top width. In one embodiment, the structure further includes an amorphous carbon layer above and in contact with the graphite line.

[0062] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0063] Example 1. A method of manufacturing an interconnect structure, comprising: forming a first conductive feature; depositing a graphite layer over the first conductive feature; patterning the graphite layer to form a graphite conductive feature; depositing a dielectric spacer layer on the graphite layer; depositing a first dielectric layer over the dielectric spacer layer; planarizing the first dielectric layer; forming a second dielectric layer over the first dielectric layer; and forming a second conductive feature in the second dielectric layer, wherein the second conductive feature is over the graphite conductive feature and electrically connected to the graphite conductive feature.

[0064] Example 2. According to the method of Example 1, the planarization of the first dielectric layer stops on the top surface of a horizontal portion of the dielectric spacer layer, wherein the horizontal portion overlaps with the graphite conductive feature, and wherein the second conductive feature passes through the horizontal portion of the dielectric spacer layer.

[0065] Example 3. The method according to Example 1, wherein in the planarization, the horizontal portion of the dielectric spacer layer is removed, and wherein the horizontal portion overlaps with the graphite conductive feature.

[0066] Example 4. The method according to Example 1, wherein after the formation of the dielectric spacer layer, the surface portion of the graphite conductive feature has been transformed into an amorphous layer, and the dielectric spacer layer is deposited on the amorphous layer.

[0067] Example 5. The method according to Example 4, wherein the planarization of the first dielectric layer stops on the top surface of the horizontal portion of the amorphous layer, wherein the horizontal portion overlaps with the graphite conductive feature.

[0068] Example 6. The method according to Example 4, wherein in the planarization, the horizontal portion of the amorphous layer is removed, wherein the horizontal portion overlaps with the graphite conductive feature.

[0069] Example 7. The method according to Example 1, wherein patterning the graphite layer further forms a graphite sealing ring.

[0070] Example 8. The method according to Example 7 further includes forming a conductive ring in the second dielectric layer, wherein the conductive ring is above the graphite sealing ring and electrically connected to the graphite sealing ring.

[0071] Example 9. The method according to Example 1, wherein the deposition of the graphite layer is performed using plasma-enhanced chemical vapor deposition.

[0072] Example 10. The method according to Example 1, wherein the second conductive feature is formed using an inlay process, and the second conductive feature comprises copper.

[0073] Example 11. The method according to Example 1 further includes depositing an etch stop layer over the first dielectric layer and the graphite conductive feature, wherein the second dielectric layer is deposited over the etch stop layer.

[0074] Example 12. An interconnect structure comprising: a first conductive feature; a graphite conductive feature above and electrically coupled to the first conductive feature; a dielectric spacer layer including a sidewall portion on a sidewall of the graphite conductive feature; a first dielectric layer surrounding the sidewall portion of the dielectric spacer layer; an etch stop layer above the first dielectric layer and the graphite conductive feature; a second dielectric layer above the etch stop layer; and a second conductive feature passing through the second dielectric layer, wherein the second conductive feature is above and electrically connected to the graphite conductive feature.

[0075] Example 13. The structure according to Example 12, wherein the graphite conductive feature has a lateral dimension of less than 12 nm.

[0076] Example 14. According to the structure described in Example 12, wherein the dielectric spacer layer further includes a horizontal portion overlapping the graphite conductive feature, and wherein the second conductive feature also extends through the horizontal portion of the dielectric spacer layer.

[0077] Example 15. The structure according to Example 12 further includes an amorphous carbon layer above and in contact with the graphite conductive feature, wherein the second conductive feature is above and in contact with the top surface of the amorphous carbon layer.

[0078] Example 16. The structure according to Example 12 further includes an amorphous carbon layer, wherein the second conductive feature passes through the amorphous carbon layer to contact the crystalline interior portion of the graphite conductive feature.

[0079] Example 17. The structure according to Example 16, wherein the amorphous carbon layer further comprises fluorine.

[0080] Example 18. An interconnect structure comprising: an integrated circuit; a dual damascene structure including: a metal line and a via, wherein the dual damascene structure includes a barrier layer and a copper region above the barrier layer; a graphite line electrically coupled between the via and the integrated circuit; and a dielectric spacer layer surrounding the graphite line.

[0081] Example 19. The structure according to Example 18, wherein the graphite line has a top width and a bottom width greater than the top width.

[0082] Example 20. The structure according to Example 18 further includes an amorphous carbon layer above and in contact with the graphite line.

Claims

1. A method for manufacturing an interconnect structure, comprising: Forming the first conductive characteristic; A graphite layer is deposited over the first conductive feature; The graphite layer is patterned to form graphite conductive features; A dielectric spacer layer is deposited on the graphite layer; A first dielectric layer is deposited over the dielectric spacer layer; The first dielectric layer is planarized, wherein the planarization of the first dielectric layer stops on the top surface of the horizontal portion of the dielectric spacer layer, wherein the horizontal portion overlaps with the graphite conductive feature. A second dielectric layer is formed above the first dielectric layer; as well as A second conductive feature is formed in the second dielectric layer, wherein the second conductive feature is electrically connected to the graphite conductive feature above the graphite conductive feature and through the horizontal portion of the dielectric spacer layer.

2. The method of claim 1, wherein after the formation of the dielectric spacer layer, the surface portion of the graphite conductive feature has been transformed into an amorphous layer, and the dielectric spacer layer is deposited on the amorphous layer.

3. The method of claim 2, wherein planarizing the first dielectric layer stops on the top surface of the horizontal portion of the amorphous layer, wherein the horizontal portion overlaps with the graphite conductive feature.

4. The method of claim 2, wherein in the planarization, the horizontal portion of the amorphous layer is removed, wherein the horizontal portion overlaps with the graphite conductive feature.

5. The method of claim 1, wherein patterning the graphite layer further forms a graphite sealing ring.

6. The method of claim 5, further comprising forming a conductive ring in the second dielectric layer, wherein the conductive ring is above the graphite sealing ring and electrically connected to the graphite sealing ring.

7. The method of claim 1, wherein the deposition of the graphite layer is performed using plasma-enhanced chemical vapor deposition.

8. The method of claim 1, wherein the second conductive feature is formed using an inlay process, and the second conductive feature comprises copper.

9. The method of claim 1, further comprising depositing an etch stop layer over the first dielectric layer and the graphite conductive feature, wherein the second dielectric layer is deposited over the etch stop layer.

10. An interconnection structure, comprising: First electrical conductivity characteristic; A graphite conductive feature is located above and electrically coupled to the first conductive feature; A dielectric spacer layer includes a sidewall portion on the sidewall of the graphite conductive feature and a horizontal portion overlapping the graphite conductive feature; A first dielectric layer surrounds the sidewall portion of the dielectric spacer layer; An etch stop layer is formed above the first dielectric layer and the graphite conductive feature; A second dielectric layer is located above the etch stop layer; as well as A second conductive feature passes through the horizontal portion of the second dielectric layer and the dielectric spacer layer, wherein the second conductive feature is above and electrically connected to the graphite conductive feature.

11. The structure according to claim 10, wherein the graphite conductive feature has a lateral dimension of less than 12 nm.

12. The structure of claim 10 further includes an amorphous carbon layer above and in contact with the graphite conductive feature, wherein the second conductive feature is above and in contact with the top surface of the amorphous carbon layer.

13. The structure of claim 10 further includes an amorphous carbon layer, wherein the second conductive feature penetrates the amorphous carbon layer to contact the crystalline interior portion of the graphite conductive feature.

14. The structure according to claim 13, wherein the amorphous carbon layer further comprises fluorine.

15. An interconnection structure, comprising: integrated circuit; Dual damascene structure, including: Metal lines and vias, wherein the dual damascene structure includes a barrier layer and a copper region above the barrier layer; Graphite wires, electrically coupled between the via and the integrated circuit; and A dielectric spacer layer surrounds the graphite wires. The dielectric spacer layer includes a horizontal portion that overlaps with the graphite wire, and the dual damascene structure passes through the horizontal portion of the dielectric spacer layer and is electrically connected to the graphite wire.

16. The structure of claim 15, wherein the graphite line has a top width and a bottom width greater than the top width.

17. The structure of claim 15 further includes an amorphous carbon layer above and in contact with the graphite line.

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