Three-dimensional memory and methods of making the same, memory systems

Abstract

The present disclosure relates to a three-dimensional memory, a manufacturing method thereof, and a storage system. The manufacturing method of the three-dimensional memory comprises: forming a fin field effect transistor in a first semiconductor layer, comprising: forming a fin structure, the fin structure comprising a sacrificial portion and a channel portion alternately stacked in a direction away from the first semiconductor layer, the fin structure comprising a first active region, a second active region, and a gate region in a vertical plane of the direction away from the first semiconductor layer; forming a gate structure in the gate region; forming a first active structure and a second active structure in the first active region and the second active region, respectively, at least one of the first active structure and the second active structure comprising a first doped layer and a second doped layer alternately stacked in the direction away from the first semiconductor layer; forming a first bonding layer electrically connected with the fin field effect transistor; forming a three-dimensional storage structure in a second semiconductor layer, and forming a second bonding layer electrically connected with the three-dimensional storage structure; and bonding the first bonding layer with the second bonding layer.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to a three-dimensional memory and its manufacturing method and storage system. Background Technology

[0002] As the number of stacked layers of storage cells in 3D memory increases, the number of components in the peripheral circuitry also increases, resulting in a larger area occupied by the peripheral circuitry. Reducing the area occupied by the peripheral circuitry has become an urgent problem to be solved, especially in 3D memory with more than two hundred stacked layers of storage cells. Summary of the Invention

[0003] The embodiments disclosed herein can at least solve one or more of the technical problems in the prior art described above, or can be used to solve some other technical problems in the prior art.

[0004] This disclosure provides a method for manufacturing a three-dimensional memory. The method includes: forming a fin field-effect transistor in a first semiconductor layer, wherein forming the fin field-effect transistor includes: forming a fin structure, the fin structure including sacrificial portions and channel portions alternately stacked in a direction away from the first semiconductor layer, wherein in a vertical plane away from the first semiconductor layer, the fin structure includes a first active region, a second active region, and a gate region located between the first active region and the second active region; forming a gate structure in the gate region; and forming a first active structure and a second active structure in the first active region and the second active region, respectively, wherein at least one of the first active structure and the second active structure includes a first doped layer and a second doped layer alternately stacked in a direction away from the first semiconductor layer; forming a first bonding layer electrically connected to the fin field-effect transistor; forming a three-dimensional memory structure in the second semiconductor layer and forming a second bonding layer electrically connected to the three-dimensional memory structure; and bonding the first bonding layer to the second bonding layer.

[0005] In some embodiments, the fin field-effect transistor is a high-voltage device, and the thickness of the first doped layer is within 100 to 200 nm along the direction away from the first semiconductor layer, and the thickness of the second doped layer is within 100 to 200 nm.

[0006] In some embodiments, the first active structure includes a first lightly doped region and a first heavily doped region, and the second active structure includes a second lightly doped region and a second heavily doped region. The step of forming the first active structure and the second active structure in the first active region and the second active region respectively includes: forming the first lightly doped region and the second lightly doped region in the first active region and the second lightly doped region respectively by a first ion implantation on the side of the fin structure away from the first semiconductor layer, wherein at least one of the first lightly doped region and the second lightly doped region includes a first doped layer and a second doped layer; and forming the first heavily doped region in a portion of the first lightly doped region and the second heavily doped region in a portion of the second lightly doped region by a second ion implantation.

[0007] For example, the fin field-effect transistor further includes: a multilayer channel structure connecting the first active structure and the second active structure, wherein the first heavily doped region and the multilayer channel structure are separated by a first lightly doped region, and the second heavily doped region and the multilayer channel structure are separated by a second lightly doped region.

[0008] In some embodiments, the first heavily doped region and the second heavily doped region are spaced 0.5 to 1 μm apart from the gate structure.

[0009] In some embodiments, at least one of the first heavily doped region and the second heavily doped region includes a third doped layer and a fourth doped layer that are alternately stacked in a direction away from the first semiconductor layer.

[0010] In some embodiments, the gate structure includes a first conductive portion, a second conductive portion, and a third conductive portion. The step of forming the gate structure in the gate region includes: removing a portion of the sacrificial portion located in the gate region, wherein there is a space between any two adjacent channel portions and between the channel portions and the first semiconductor layer; forming an insulating portion in the gate region, the insulating portion shielding the surface of the channel portions exposed in the gate region; forming the first conductive portion on the side of the fin structure away from the first semiconductor layer; forming the second conductive portion on the side of the fin structure adjacent to one side; and forming the third conductive portion in the space.

[0011] In some embodiments, the gate structure includes a first conductive portion and a second conductive portion, wherein the step of forming the gate structure in the gate region includes: removing a portion of the sacrificial portion located in the gate region, wherein there is a space between any two adjacent channel portions and between the channel portions and the first semiconductor layer; forming an insulating portion in the gate region, wherein the insulating portion shields the surface of the channel portions exposed in the gate region and fills the space; and forming the first conductive portion on the side of the fin structure away from the first semiconductor layer, and forming the second conductive portion on the side of the fin structure adjacent to one side.

[0012] In some embodiments, the step of forming the fin structure includes: forming a stacked structure by alternately stacking sacrificial layers and channel layers; forming a first shallow trench and a second shallow trench extending into a first semiconductor layer in the stacked structure, the directions of the first shallow trench and the second shallow trench intersecting to divide the stacked structure into fin structures.

[0013] For example, the method further includes: forming a first shallow trench isolation structure in the first shallow trench.

[0014] In some embodiments, a first planar transistor is formed on a first semiconductor layer; wherein the step of forming the first planar transistor includes: forming two third shallow trench isolation structures that extend along a direction close to the first semiconductor layer and are disposed opposite each other in the stacked structure to divide the planar structure, wherein the planar structure includes a third active region, a channel region and a fourth active region in a vertical plane away from the first semiconductor layer; forming a fourth conductive portion on the planar structure; and forming a third active structure and a fourth active structure in the third active region and the fourth active region, respectively.

[0015] For example, the planar structure is covered and the fin structure is exposed before the step of removing the portion of the sacrificial part located in the gate region, and the planar structure is exposed after the step of removing the portion of the sacrificial part located in the gate region.

[0016] In some embodiments, the steps of forming the third active structure and the fourth active structure include: forming a third lightly doped region in the third active region and a fourth lightly doped region in the fourth active region by a first ion implantation on the side of the planar structure away from the first semiconductor layer; and forming a third heavily doped region and a fourth heavily doped region in the third lightly doped region and the fourth lightly doped region by a second ion implantation, wherein the third heavily doped region is separated from the channel region by the third lightly doped region, and the fourth heavily doped region is separated from the channel region by the fourth lightly doped region.

[0017] In some implementations, the fin field-effect transistor is one of a high-voltage device and a low-voltage device, and the first planar transistor is the other.

[0018] In some embodiments, the method further includes forming a second planar transistor on a first semiconductor layer, which serves as a high-voltage device, wherein the fin field-effect transistor is a low-voltage device.

[0019] For example, along the direction away from the first semiconductor layer, the thickness of the first doped layer is within 10 to 50 nm, and the thickness of the second doped layer is within 10 to 50 nm.

[0020] In some embodiments, the method further includes: forming a well region in a first semiconductor layer; and forming a first drift region and a second drift region spaced apart from the first drift region in the well region; wherein forming a fin field-effect transistor in the first semiconductor layer includes: forming a fin field-effect transistor on the well region, the fin field-effect transistor including a first active structure and a second active structure formed on the side of the first drift region and the second drift region away from the first semiconductor layer, respectively.

[0021] In some embodiments, the method further includes: forming a first interconnect layer and a second interconnect layer in the first semiconductor layer and the second semiconductor layer, respectively; wherein the fin field-effect transistor is electrically connected to the three-dimensional memory structure through the first interconnect layer, the first bonding layer, the second bonding layer and the second interconnect layer.

[0022] Secondly, embodiments of this disclosure provide a three-dimensional memory, comprising: a first semiconductor layer; a fin field-effect transistor located on the first semiconductor layer, in a vertical plane away from the first semiconductor layer, the fin field-effect transistor including a first active structure, a second active structure, a multilayer channel structure connecting the first active structure and the second active structure, and a gate structure located between the first active structure and the second active structure, wherein at least one of the first active structure and the second active structure includes a first doped layer and a second doped layer alternately stacked along a direction away from the first semiconductor layer; a first bonding layer located on the side of the fin field-effect transistor away from the first semiconductor layer and electrically connected to the fin field-effect transistor; a second semiconductor layer; a second bonding layer located on the side of the second semiconductor layer close to the first bonding layer and bonded to the first bonding layer; and a three-dimensional memory structure located on the second semiconductor layer and electrically connected to the second bonding layer.

[0023] In some implementations, the fin field-effect transistors include at least one of high-voltage devices and low-voltage devices.

[0024] In some embodiments, in a fin field-effect transistor of the type of low-voltage device, the thickness of the first doped layer is within 10 to 50 nm in the direction away from the first semiconductor layer, and the thickness of the second doped layer is within 10 to 50 nm.

[0025] In some embodiments, in fin field-effect transistors of the type of high-voltage devices, the thickness of the first doped layer is within 100 to 200 nm in the direction away from the first semiconductor layer, and the thickness of the second doped layer is within 100 to 200 nm.

[0026] In some embodiments, the first active structure includes a first lightly doped region and a first heavily doped region, wherein the first heavily doped region is separated from the multilayer channel structure by the first lightly doped region; wherein the second active structure includes a second lightly doped region and a second heavily doped region, wherein the second heavily doped region is separated from the multilayer channel structure by the second lightly doped region, wherein at least one of the first lightly doped region and the second lightly doped region includes a first doped layer and a second doped layer.

[0027] In some embodiments, the first heavily doped region and the second heavily doped region are spaced 0.5 to 1 μm apart from the multilayer channel structure.

[0028] In some embodiments, at least one of the first heavily doped region and the second heavily doped region includes a third doped layer and a fourth doped layer that are alternately stacked in a direction away from the first semiconductor layer.

[0029] In some embodiments, the gate structure includes: a first conductive portion located on the side of the multilayer channel structure away from the first semiconductor layer; a second conductive portion located on the side of the multilayer channel structure adjacent to one side; and a third conductive portion located at least between the multilayer channel structure and the first semiconductor layer.

[0030] In some embodiments, the gate structure includes: a first conductive portion located on the side of the multilayer channel structure away from the first semiconductor layer; a second conductive portion located on the side of the multilayer channel structure adjacent to one side; and an insulating portion filling the space between the multilayer channel structure and the first semiconductor layer.

[0031] In some embodiments, the three-dimensional memory further includes a first planar transistor located in a first semiconductor layer. The first planar transistor includes a third active structure, a fourth active structure, and a channel region connecting the third active structure and the fourth active structure. The channel region includes alternately stacked second channel pillars and spacers, with the top layer being the second channel pillars.

[0032] In a third aspect, this disclosure also provides a storage system comprising: the aforementioned three-dimensional memory; and a controller electrically connected to the three-dimensional memory and controlling the three-dimensional memory.

[0033] The method for manufacturing a three-dimensional memory provided by embodiments of this disclosure manufactures at least a portion of the devices in the peripheral circuit as fin field-effect transistors. These fin field-effect transistors can adapt to the operating environment of the peripheral circuit, ensuring that the peripheral circuit maintains good performance to control the three-dimensional memory structure, and can reduce the overall size of the peripheral circuit.

[0034] The three-dimensional memory provided by the embodiments of this disclosure can provide a large storage capacity in a small volume. Attached Figure Description

[0035] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0036] Figure 1 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0037] Figure 2 This is a flowchart of a method for forming a fin field-effect transistor according to an embodiment of the present disclosure;

[0038] Figure 3 This is a schematic diagram of the structure of the first semiconductor layer according to an embodiment of the present disclosure;

[0039] Figure 4 This is a schematic diagram of the structure of the first semiconductor layer after forming the well region according to an embodiment of the present disclosure;

[0040] Figure 5 This is a schematic diagram of the structure of the first semiconductor layer after ion implantation in the trap region according to an embodiment of the present disclosure;

[0041] Figure 6 This is a schematic diagram of the semiconductor structure after forming a multilayer structure according to an embodiment of the present disclosure;

[0042] Figure 7 This is a schematic diagram of the semiconductor structure after forming the first shallow trench isolation structure according to an embodiment of the present disclosure;

[0043] Figure 8 This is a top view of the semiconductor structure after forming the first shallow trench isolation structure and the second shallow trench isolation structure according to the embodiments of this disclosure;

[0044] Figure 9 yes Figure 8 Cross-sectional view at point AA;

[0045] Figure 10 yes Figure 8 Cross-sectional view at point BB;

[0046] Figure 11 yes Figure 10 An enlarged schematic diagram of the structure at point A after the insulating part has been formed;

[0047] Figure 12 This is a cross-sectional view of the semiconductor structure after the formation of the third conductive portion according to an embodiment of the present disclosure in the XZ plane.

[0048] Figure 13 This is a cross-sectional view of the semiconductor structure after the formation of the third conductive portion according to an embodiment of the present disclosure in the YZ plane;

[0049] Figure 14 This is a schematic diagram of a semiconductor structure after the first ion implantation of a finned structure according to an embodiment of the present disclosure.

[0050] Figure 15 This is a schematic diagram of a semiconductor structure obtained by a second ion implantation of a fin structure according to an embodiment of the present disclosure.

[0051] Figure 16 This is a schematic diagram of the semiconductor structure after the insulating portion 23 fills the space 211-0 according to the embodiments of this disclosure;

[0052] Figure 17 yes Figure 16 A schematic diagram of the semiconductor structure after oxidation;

[0053] Figure 18 yes Figure 16 A schematic diagram of the semiconductor structure after oxidation in the YZ plane;

[0054] Figure 19 This is a schematic diagram of the semiconductor structure after forming the gate structure according to an embodiment of the present disclosure;

[0055] Figure 20 yes Figure 19 A schematic diagram of the semiconductor structure in the XZ plane;

[0056] Figure 21 This is a schematic diagram of a semiconductor structure after the first ion implantation of a fin structure according to another embodiment of the present disclosure.

[0057] Figure 22 This is a schematic diagram of a semiconductor structure obtained by a second ion implantation of a fin structure according to another embodiment of the present disclosure.

[0058] Figure 23 yes Figure 15 Enlarged view of point A in the middle;

[0059] Figure 24 This is a schematic diagram of a semiconductor structure having a fin field-effect transistor and a first planar transistor according to an embodiment of the present disclosure;

[0060] Figure 25 This is a schematic diagram of the structure of a three-dimensional memory according to an embodiment of the present disclosure;

[0061] Figure 26 This is a schematic diagram of the structure of a three-dimensional memory according to another embodiment of the present disclosure;

[0062] Figure 27 This is a schematic diagram of the structure of a storage system according to an embodiment of the present disclosure. Detailed Implementation

[0063] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0064] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features. Therefore, without departing from the teachings of this disclosure, the first active structure discussed below may also be referred to as the second active structure, and vice versa.

[0065] In the accompanying drawings, the thickness, dimensions, and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thicknesses of the first lightly doped region and the first heavily doped region are not proportional to actual production. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0066] It should also be understood that the terms "comprising," "including," "having," "containing," and / or "comprising," when used in this specification, indicate the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof. Furthermore, when a statement such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, not individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0067] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0068] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0069] Figure 1 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure. (See reference) Figure 1 The method 1000 for manufacturing a three-dimensional memory provided in this disclosure includes the following steps.

[0070] Step S101: A fin field-effect transistor is formed in the first semiconductor layer.

[0071] Step S102: A first bonding layer is formed that is electrically connected to the fin field-effect transistor.

[0072] In step S103, a three-dimensional memory structure is formed in the second semiconductor layer, and a second bonding layer electrically connected to the three-dimensional memory structure is formed.

[0073] Step S104: Bond the first bonding layer to the second bonding layer.

[0074] like Figure 2 The flowchart shown illustrates a method for forming a fin field-effect transistor, where step S101 includes the following steps.

[0075] Step S1011: Forming a fin structure. The fin structure includes sacrificial portions and channel portions alternately stacked along a direction away from the first semiconductor layer. In a vertical plane along the direction away from the first semiconductor layer, the fin structure includes a first active region, a second active region, and a gate region located between the first active region and the second active region. The vertical plane along the direction away from the first semiconductor layer can refer to a plane perpendicular to the direction away from the first semiconductor layer.

[0076] Step S1012: Form a gate structure in the gate region.

[0077] Step S1013: A first active structure is formed in the first active region, and a second active structure is formed in the second active region. At least one of the first and second active structures includes a first doped layer and a second doped layer alternately stacked along a direction away from the first semiconductor layer.

[0078] The method for manufacturing a three-dimensional memory provided in this disclosure can be fabricated into a fin field-effect transistor for controlling a three-dimensional memory structure. Fin field-effect transistors occupy a small area, which can reduce the size of the peripheral circuitry formed on the first semiconductor layer, enabling the peripheral circuitry to meet the control requirements of increasingly more layers in the three-dimensional memory structure. This increases the storage density of the three-dimensional memory.

[0079] The structures on the first and second semiconductor layers can be fabricated separately, and then the fin field-effect transistors can be electrically connected to the three-dimensional memory structure by bonding.

[0080] The following is in conjunction with the appendix Figures 3 to 27 The embodiments provided in this disclosure are illustrated by way of example.

[0081] Figure 3 A schematic diagram of the structure of the first semiconductor layer is shown. The first semiconductor layer 1 may have a certain thickness in the Z direction. The first semiconductor layer 1 may be a first substrate, and the material of the first substrate may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0082] In some embodiments of this disclosure, a well region 11 may be formed in the provided first semiconductor layer 1. For example, the well region 11 may be obtained by p-type doping the first semiconductor layer 1. Figure 4 A schematic diagram of the structure of the first semiconductor layer after the formation of the well region 11 is shown. The first semiconductor layer 1 may include the well region 11 obtained by ion implantation and the original substrate 10.

[0083] In some embodiments of this disclosure, after forming the well region 11, a first drift region 121 and a second drift region 122 spaced apart from the first drift region 121 can be formed in the well region 11. For example, along the X direction, the space can be divided into a first region N1, a second region P, and a third region N2. The surface of the well region 11 located in the second region P can be shielded, and then the well region 11 can be N-type doped in the first region N1 and the third region N2. Figure 5 A schematic diagram of the structure of the first semiconductor layer 1 after ion implantation into the well region 11 is shown. Figure 5As shown, after N-type doping, a first drift region 121 is formed at the first region N1, and a second drift region 122 is formed at the third region N3. The remaining portion of the well region 11 is still referred to as the well region 11 below. The first drift region 121 and the second drift region 122 are separated by the portion of the well region 11 located at the second region P. Exemplarily, the first drift region 121 and the second drift region 122 may not penetrate the well region 11 in the Z direction.

[0084] In some embodiments of this disclosure, a fin field-effect transistor can be formed on the well region 11 after the first drift region 121 and the second drift region 122 are formed. Exemplarily, the steps for forming the fin field-effect transistor may be as follows: Figure 2 As shown. For ease of understanding, the following is an explanation. Figure 2 The various sub-steps are illustrated by way of example.

[0085] In some embodiments of this disclosure, the fin field-effect transistor includes a fin structure, and the step of forming the fin structure may include: forming a stacked structure by alternately stacking a sacrificial layer and a channel layer, forming a first shallow trench and a second shallow trench extending into a first semiconductor layer 1 in the stacked structure, wherein the directions of the first shallow trench and the second shallow trench intersect, thereby dividing the stacked structure into a fin structure.

[0086] Exemplarily, different stacking orders can be used when the sacrificial layer 21 and the channel layer 22 are alternately stacked on the first semiconductor layer 1. For example, the bottom layer may be the sacrificial layer 21, while in other embodiments the bottom layer may be the channel layer 22. Exemplarily, the top layer formed in this step is the channel layer 22.

[0087] Figure 6 This is a schematic diagram of the semiconductor structure after forming a multilayer structure according to an embodiment of the present disclosure. Figure 7 This is a schematic diagram of the semiconductor structure after forming the first shallow trench isolation structure according to an embodiment of the present disclosure. Figure 8 This is a top view schematic diagram of the semiconductor structure after forming the first shallow trench isolation structure and the second shallow trench isolation structure according to the embodiments of this disclosure.

[0088] like Figure 6 As shown, a stacked structure 2 is formed on the first semiconductor layer 1. The stacked structure 2 is formed by alternately stacking a sacrificial layer 21 and a channel layer 22. Both the first semiconductor layer 1 and the stacked structure 2 can be extended to a large area. Multiple well regions 11 can be fabricated in the first semiconductor layer 1, and the stacked structure 2 can simultaneously cover these well regions 11. Specifically, the sacrificial layer 21 and the channel layer 22 can be formed using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0089] For example, there may be etching selectivity between the materials of the sacrificial layer 21 and the channel layer 22. For instance, the material of the sacrificial layer 21 may include silicon germanium, and the material of the channel layer 22 may include silicon.

[0090] For example, such as Figure 7 and Figure 8 As shown, the stacked structure 2 in this embodiment can be formed as a single unit, and the fin structure 20 on each well region 11 and the surrounding structure can also be integral. Exemplarily, a first shallow trench and a second shallow trench with intersecting extending directions can be formed in the stacked structure 2, for example, along the first direction (e.g.,...). Figure 8 The first shallow trenches are spaced apart in the X direction (as shown), and a second trench is formed along the second direction (e.g., Figure 8 The second shallow trench is spaced at intervals in the Y direction (as shown). In the XY plane ( Figure 8 Within the first semiconductor layer 1, the first shallow trench and the second shallow trench separate the portion of the first active region 121, the second active region 122, and the well region 11 located between them from the rest of the first semiconductor layer 1. Alternatively, the fin structure 20 is obtained by forming a first shallow trench extending into the first semiconductor layer 1 on both sides of the stacked structure 2 along the X direction (i.e., the first direction), and a second shallow trench extending into the first semiconductor layer 1 on both sides of the stacked structure 2 along the second direction. The first and second shallow trenches divide the stacked structure 2 into the fin structure 20.

[0091] like Figure 7 As shown, the fin structure 20 includes stacked sacrificial portions 211 and channel portions 221. The sacrificial portion 211 is part of the original integral sacrificial layer 21, and the channel portion 221 is part of the original integral channel layer 22. It should be understood that in the fin structure 20, the sacrificial portion 211 and the channel portion 221 can each be an integral structure.

[0092] For example, the fin structure 20 can be divided into three parts along the X direction: a first active region, a gate region, and a second active region. Specifically, the portion of the fin structure 20 located in the first region N1 can be considered as the first active region, the portion located in the second region P can be considered as the gate region, and the portion located in the third region N2 can be considered as the second active region.

[0093] In some embodiments of this disclosure, such as Figure 7 and Figure 8As shown, after forming the first shallow trench and the second shallow trench, a first shallow trench isolation structure 31 can be formed in the first shallow trench, and a second shallow trench isolation structure 32 can be formed in the second shallow trench. Along the XY plane, the portions of the fin structure 20 corresponding to the first region N1 and the third region N2 are fittedly covered, and the portion of the fin structure 20 corresponding to the second region P is exposed by the slot 320. The slot 320 can be formed after the second shallow trench isolation structure 32 is formed. The materials of the first shallow trench isolation structure 31 and the second shallow trench isolation structure 32 can include oxides, such as silicon oxide, so that the fin structure 20 is electrically isolated from the rest of the first semiconductor layer 1.

[0094] In some embodiments of this disclosure, such as Figure 8 As shown, three fin structures 20 can be formed on the first semiconductor layer 1, and the three fin structures 20 are arranged along the Y direction. It should be understood that the number of fin structures 20 provided on the first semiconductor layer 1 can be determined according to requirements, and the arrangement can also be adjusted. The first directions of different fin structures 20 may not be parallel. In this embodiment, the X direction is the first direction; however, it is understood that the X direction is not a limitation on the direction of the fin structures 20 of this disclosure.

[0095] In some embodiments of this disclosure, during the formation of the gate structure in the gate region, for example... Figure 8 The slit 320 shown removes the portion of the sacrificial portion 211 in the gate region of the fin structure 20, leaving the active sacrificial portion located in the first active region / second active region. The channel portion 221 can still maintain its overall shape. Figure 9 yes Figure 8 Cross-sectional view at point AA. After removing the portion of the sacrificial portion 211 located in the gate region through the gap 320, the spacer space 211-0 is formed, thereby exposing more surface area of ​​the channel portion 221 located in the gate region. Figure 10 yes Figure 8 The cross-sectional view at point BB shows the semiconductor structure after the active sacrificial portion 211-1 is formed. It can be seen that a spacer space 211-0 is formed between two adjacent channel portions 221 and between the channel portion 221 and the first semiconductor layer 1. The spacer space 211-0 is located in the second region P, which is also the gate region of the fin structure 20.

[0096] It should be understood that, Figure 9 The fin structure 20 may include three channel portions 221 as an example for illustrative purposes. Without departing from the teachings of this application, the fin structure 20 may also be configured to include other numbers of channel portions 221. The dimensions of the channel portions 221 in the Z direction can be designed as needed, and the dimensions of the spacing space 221-0, i.e., the dimensions of the previous sacrificial portion 211, can also be designed.

[0097] In some embodiments, the dimension of the spacer 211-0 along the Z direction is large, and the step of forming the gate structure may further include forming an insulating portion 23 in the gate region. Figure 11 yes Figure 10 An enlarged schematic diagram of the structure at point A after the formation of insulating part 23. (See diagram below.) Figure 11 As shown, the insulating portion 23 shields the surface of the channel portion 222 exposed in the gate region. Exemplarily, the insulating portion 23 can be formed on the surface of the channel portion 221 by oxidation.

[0098] It should be understood that there may still be a spacing space 211-0 between any two adjacent channel portions 221 and between the channel portion 221 and the well region 11 of the first semiconductor layer, for example... Figure 11 As shown, the space 211-0 can also be filled by the insulating part 23, for example... Figure 16 This application does not impose any restrictions on this.

[0099] Because the filling form of the insulating portion 23 is different, the final structure of the fin field-effect transistor may be different. For ease of understanding, the subsequent processes for forming the fin field-effect transistor will be described by way of example below, taking into account the filling form of the insulating portion 23.

[0100] The following example describes the subsequent process of forming a fin field-effect transistor when the insulating portion 23 is not completely filled with the spacing space 211-0, that is, when there is still a spacing space 211-0 between any two adjacent channel portions 221 and between the channel portion 221 and the well region 11 of the first semiconductor layer.

[0101] In some embodiments, the step of forming the gate structure 4 of the fin field-effect transistor may include: forming a first conductive portion 41 located on the side of the fin structure 20 away from the first semiconductor layer 1, forming a second conductive portion 42 located on at least one side of the two sides of the fin structure 20 along a second direction, and forming a third conductive portion 43 located in the spacer space. Exemplarily, the third conductive portion 43 is at least located between the first semiconductor layer 1 and the plurality of channel portions 221, and may also be located between the plurality of channel portions 221. For example, Figure 12 This is a cross-sectional view of the XZ plane of the semiconductor structure after the formation of the third conductive portion 43 according to an embodiment of the present disclosure. Figure 13 This is a cross-sectional view of the YZ plane of the semiconductor structure after the formation of the third conductive portion 43 according to an embodiment of this disclosure. Figure 12 and Figure 13 The gate structure 4 is located in the second region P and completely surrounds each channel portion 221 in the XY plane. The gate structure 4 and the channel portion 221 are isolated by an insulating portion 23. It should be understood that... Figure 12 and Figure 13The fact that the insulating part 23 is omitted in the enlarged view does not mean that the insulating part 23 is not present.

[0102] In some embodiments of this application, after forming the gate structure 4, a first active structure and a second active structure are formed in the first active region and the second active region, respectively, to process the fin structure 20 into a fin field-effect transistor. For example, on the side of the fin structure 20 away from the first semiconductor layer 1, the fin structure 20 undergoes a first ion implantation in the first region N1 and the third region N2. Figure 14 A schematic diagram of the semiconductor structure after the first ion implantation is shown. The original fin structure 20 located in the first region N1, i.e., the first active region becomes the first lightly doped region 241; the original fin structure 20 located in the third region N2, i.e., the second active region becomes the second lightly doped region 242.

[0103] Specifically, on the side of the fin structure 20 away from the first semiconductor layer 1, the portion of the channel portion 221 located in the first region N1 / second region N2 and the active sacrificial portion 211-1 are transformed into components of the first lightly doped region 241 / second lightly doped region 242 through ion implantation. The portion of the channel portion 221 located in the second region P is the first channel crossbeam 221-1, and the two ends of the first channel crossbeam 221-1 in the X direction connect the first lightly doped region 241 and the second lightly doped region 242. Multiple first channel crossbeams 221-1 are used to form a multilayer channel structure.

[0104] In some embodiments of this application, after the formation of the first lightly doped region 241 and the second lightly doped region 242, a first heavily doped region 251 can be formed in a portion of the first lightly doped region 241 and a second heavily doped region 252 can be formed in a portion of the second lightly doped region 242 by a second ion implantation. Figure 15 A schematic diagram of the semiconductor structure obtained after a second ion implantation is shown. Figure 15 As shown, the portions of the original first lightly doped region 241 / second lightly doped region 242 that have not been transformed into the first heavily doped region 251 / second heavily doped region 252 will still be referred to as the first lightly doped region 241 / second lightly doped region 242 in the following text. The first heavily doped region 251, the first lightly doped region 241, the multilayer channel structure, the second lightly doped region 242, and the second heavily doped region 252 can be used to construct a fin field-effect transistor.

[0105] Optionally, during the second ion implantation, the implantation area can be controlled using a mask, and then the first heavily doped region 251 and the multilayer channel structure and gate structure 4 located in the second region P are separated by the first lightly doped region 241, and the second heavily doped region 252 and the multilayer channel structure and gate structure 4 located in the second region P are separated by the second lightly doped region 242.

[0106] Alternatively, the first heavily doped region 251 and the second heavily doped region 252 are spaced 0.5 to 1 μm apart from the gate structure 4.

[0107] For example, the first heavily doped region 251 and the first drift region 121 are separated by a first lightly doped region 241 in the Z direction, and the second heavily doped region 252 and the second drift region 122 are separated by a second lightly doped region 242. The first heavily doped region 251 and the first lightly doped region 241 can be used to form a first active structure, which is located on the first drift region 121. The second heavily doped region 252 and the second lightly doped region 242 can be used to form a second active structure, which is located on the second drift region 122.

[0108] Figure 15 When the semiconductor structure shown is used in a circuit, the first heavily doped region 251, the second heavily doped region 252, and the gate structure 4 are respectively connected to the circuit. The first heavily doped region 251 and the second heavily doped region 252 can be used as the source and drain, respectively. The gate structure 4 can controllably apply a voltage to each first channel pillar 221-1 in the multilayer channel structure through the insulating portion 23, so that the first channel pillar 221-1 forms a channel under the action of the voltage, thereby electrically connecting the first heavily doped region 251 to the second heavily doped region 252 through the first lightly doped region 241, the multilayer channel structure, and the second lightly doped region 242.

[0109] The actual structure of the fin field-effect transistor can be adjusted according to actual needs. For example, in some embodiments, the distance between two adjacent first channel pillars 221-1 is closer, or the first channel pillars 221-1 are thinner in the Z direction, in which case the manufacturing process can be adjusted.

[0110] The above is an exemplary description of the subsequent process of forming a fin field-effect transistor when the insulating portion 23 does not fill the space 211-0. The following is an exemplary description of the subsequent process of forming a fin field-effect transistor when the insulating portion 23 fills the space 211-0.

[0111] Figure 16 This shows a cross-sectional view of the semiconductor structure in the XZ plane after the insulating portion 23 fills the space 211-0. The preceding fabrication process can be found by referring to... Figures 3 to 10 And the process steps shown above. However, when forming the insulating portion 23, the first oxide portion 23-1 can be formed first by deposition. The first oxide portion 23-1 can fill the space 211-0, that is, the space between two adjacent channel portions 221 and the space between the channel portion 221 and the first substrate 1 is filled by the first oxide portion 23-1.

[0112] A second oxide section 23-2 can then be formed on the top surface of the uppermost channel section 221 by oxidation. Figure 17 It shows Figure 16 A schematic diagram of the semiconductor structure after oxidation. (See attached diagram.) Figure 17 As shown, the uppermost channel portion 221 located in the second region P has a second oxide portion 23-2, while the uppermost channel portion 221 located in the first region N1 / third region N2 is protected from oxidation.

[0113] Figure 18 yes Figure 16 This is a schematic diagram of the semiconductor structure after oxidation in the YZ plane. The insulating portion 23 blocks the surface of the channel portion 221 exposed in the gate region. A gap 320 remains between the second shallow trench isolation structure 32 and the channel portion 221.

[0114] The step of forming the gate structure further includes: forming a first conductive portion 41 located on the side of the fin structure 20 away from the first substrate 1, and forming a second conductive portion 42 located on at least one side of the two sides of the fin structure 20 along the second direction (Y direction). Figure 19 A schematic diagram of the semiconductor structure after the gate structure is formed is shown. (Example) Figure 19 As shown, although the multiple channel portions 221 are surrounded by the gate structure 4 above in the Y and Z directions, the opposing surfaces between the channel portions 221 do not approach the gate structure 4. Figure 20 It shows Figure 19 The diagram shows the semiconductor structure in the XZ plane. When used in the circuit, the voltage applied to the gate structure 4 mainly acts on the portion of the uppermost channel 221 away from the first substrate 1 and at both ends of each channel 221 in the Y direction.

[0115] The fin structure 20 can then be fabricated into a fin field-effect transistor. Specifically, the fin structure 20 undergoes a first ion implantation in the first region N1 and the third region N2. Figure 21 A schematic diagram of the semiconductor structure after the first ion implantation is shown. The original fin structure 20 located in the first region N1, i.e., the first active region becomes the first lightly doped region 241; the original fin structure 20 located in the third region N2, i.e., the second active region becomes the second lightly doped region 242.

[0116] Specifically, the portion of the channel portion 221 located in the first region N1 / second region N2 and the active sacrificial portion 211-1 are transformed into components of the first lightly doped region 241 / second lightly doped region 242 through ion implantation. The portion of the channel portion 221 located in the second region P is the first channel crossbeam 221-1, which connects the first lightly doped region 241 and the second lightly doped region 242 at both ends in the X direction. Multiple first channel crossbeams 221-1 are used to form a multilayer channel structure.

[0117] Then, a first heavily doped region 251 can be formed in a portion of the first lightly doped region 241 and a second heavily doped region 252 can be formed in a portion of the second lightly doped region 242 by a second ion implantation. Figure 22 A schematic diagram of the semiconductor structure obtained after a second ion implantation is shown. Figure 22 As shown, the portions of the original first lightly doped region 241 / second lightly doped region 242 that have not been transformed into the first heavily doped region 251 / second heavily doped region 252 will still be referred to as the first lightly doped region 241 / second lightly doped region 242 in the following text. The first heavily doped region 251, the first lightly doped region 241, the multilayer channel structure, the second lightly doped region 242, and the second heavily doped region 252 can be used to construct a fin field-effect transistor.

[0118] Optionally, during the second ion implantation, the implanted region can be controlled using a mask, and the first heavily doped region 251 is separated from the multilayer channel structure and gate structure 4 located in the second region P by a first lightly doped region 241, and the second heavily doped region 252 is separated from the multilayer channel structure and gate structure 4 located in the second region P by a second lightly doped region 242. Alternatively, the first heavily doped region 251 and the second heavily doped region 252 are spaced 0.5–1 μm apart from the gate structure 4.

[0119] For example, the first heavily doped region 251 and the first drift region 121 are separated by a first lightly doped region 241 in the Z direction, and the second heavily doped region 252 and the second drift region 122 are separated by a second lightly doped region 242. The first heavily doped region 251 and the first lightly doped region 241 can be used to form a first active structure, which is located on the first drift region 121. The second heavily doped region 252 and the second lightly doped region 242 can be used to form a second active structure, which is located on the second drift region 122.

[0120] In some embodiments of this application, in Figure 15 and Figure 22 In the semiconductor structure shown, at least one of the first active structure and the second active structure includes a first doped layer and a second doped layer that are alternately stacked in a direction away from the first semiconductor layer.

[0121] As an example, at least one of the first lightly doped region 241 and the second lightly doped region 242 includes a direction away from the first semiconductor layer (e.g., Figure 15 and Figure 22 The first and second doped layers are shown in the Z-direction. Figure 15 Taking the second lightly doped region 242 as an example, Figure 23 It shows Figure 15The enlarged view at point A shows that the second lightly doped region 242 comprises alternating stacked first doped layers 242-1 and second doped layers 242-2. For example, the second doped layer and at least one channel structure are integrally formed. Since the first doped layer 241-1 is... Figure 8 The second doped layer 242-2 is formed after the active sacrificial portion remaining in the first active region / second active region is the result of the first ion implantation. Figure 8 The channel portion 221 remaining in the first active region / second active region is formed after the first ion implantation. The channel portion of the first active region, the channel portion of the gate region, and the channel portion of the second active region are integrally formed. Therefore, the second doped layer 242-2 formed in the channel portion and the channel structure are integrally formed.

[0122] In some embodiments of this application, at least one of the first heavily doped region 251 and the second heavily doped region 252 includes a direction away from the first semiconductor layer 1 (e.g., Figure 15 The third and fourth doped layers are alternately stacked (shown in the Z direction). Taking the second heavily doped region 252 as an example, Figure 23 It shows Figure 15 The enlarged view at point A shows that the second heavily doped region 252 includes alternately stacked third doped layers 252-1 and fourth doped layers 252-2. For example, the fourth doped layer and at least one channel structure are integrally formed. Since the third doped layer 252-1 is... Figure 8 The fourth doped layer 252-2 is formed after the active sacrificial portion remaining in the first / second active region undergoes a second ion implantation. Figure 8 The channel portion 221 remaining in the first active region / second active region is formed after the second ion implantation. The channel portion of the first active region, the channel portion of the gate region, and the channel portion of the second active region are integrally formed. Therefore, the fourth doped layer 252-2 formed by the channel portion and the channel structure are integrally formed.

[0123] In some embodiments of this application, Figure 22 In the semiconductor structure shown, the fin field-effect transistor can be used as a low-voltage device, while Figure 15 The fin field-effect transistor in the semiconductor structure shown can be used as a high-voltage device when applied to circuits.

[0124] Optional, in Figure 22 In the semiconductor structure shown, when the fin field-effect transistor is used as a low-voltage device, along the direction away from the first semiconductor layer (e.g.) Figure 15 (As shown in the Z direction), the thickness of the first doped layer is within 10 to 50 nm, and the thickness of the second doped layer is within 10 to 50 nm.

[0125] Optional, in Figure 15In the semiconductor structure shown, when the fin field-effect transistor is used as a low-voltage device, along the direction away from the first semiconductor layer (e.g.) Figure 15 (As shown in the Z direction), the thickness of the first doped layer 242-1 is within 100-200 nm, and the thickness of the second doped layer 242-2 is within 100-200 nm. Because multiple channel structures are connected in parallel in a fin field-effect transistor, manufacturing high-voltage devices in the peripheral circuit as fin field-effect transistors can greatly reduce the area occupied by the devices.

[0126] In some embodiments, in addition to forming fin field-effect transistors, a first planar transistor 5 is also formed on the first semiconductor layer 1. Figure 24 A schematic diagram of a semiconductor structure having a finned field-effect transistor and a first planar transistor is shown. The finned field-effect transistor can be used as at least one of a high-voltage device (HV), a low-voltage device (LV), and an ultra-low-voltage device (LLV), and the first planar transistor 5 can also be at least one of a high-voltage device, a low-voltage device, and an ultra-low-voltage device. Exemplarily, the finned field-effect transistor can be used as a high-voltage device, and the first planar transistor 5 can be used as a low-voltage device. Exemplarily, the finned field-effect transistor can be used as a low-voltage device, and the first planar transistor 5 can be used as a high-voltage device.

[0127] In some embodiments, the step of forming the first planar transistor 5, in conjunction with the step of forming a fin field-effect transistor in the first semiconductor layer 1, includes the following steps.

[0128] Two third shallow trench isolation structures, extending along a direction close to the first semiconductor layer 1 and disposed opposite to each other, are formed in the stacked structure 2 to separate the planar structure. In a vertical plane away from the first semiconductor layer 1 (e.g., the X direction), the planar structure includes a third active region, a channel region, and a fourth active region. The outermost layer of the stacked structure 2 is the channel layer 22 (see [link to documentation]). Figure 6 This makes the top of the channel region part of the original channel layer 22. Figure 24 The third shallow trench isolation structure 33 on the right side of the middle section is also used as the first shallow trench isolation structure.

[0129] Before the step of removing the portion of the sacrificial portion 211 located in the gate region, the planar structure is covered and the fin structure 20 is exposed. Exemplarily, a nitride can be used to cover the planar structure. Then, after the step of removing the portion of the sacrificial portion 211 located in the gate region, the planar structure is exposed. A planar insulating portion 53 can then be formed on the planar structure, and a fourth conductive portion 54 can be formed on the planar insulating portion 53.

[0130] When forming the planar insulating portion 53 and the fourth conductive portion 54, a mask can be used to cover the third active region and the fourth active region. Then the mask can be removed and a third active structure can be formed in the third active region, and a fourth active structure can also be formed simultaneously in the fourth active region. The steps of forming the third active structure and forming the fourth active structure may include: forming a third lightly doped region 511 in the third active region and a fourth lightly doped region 512 in the fourth active region by a first ion implantation on the side of the planar structure away from the first semiconductor layer 1; then forming a third heavily doped region 521 in the third lightly doped region 511 and a fourth heavily doped region 522 in the fourth lightly doped region 512 by a second ion implantation.

[0131] like Figure 24 As shown, the third heavily doped region 521 is separated from the channel region by the third lightly doped region 511, and the fourth heavily doped region 522 is separated from the channel region by the fourth lightly doped region 512. The third heavily doped region 521, the third lightly doped region 511, the channel region, the fourth lightly doped region 512, and the fourth heavily doped region 522 on the first semiconductor layer 1 can be used to form a first planar transistor. The top of the channel region is a part of the original channel layer 22, namely the second channel pillar. The second channel pillar and the spacer are stacked alternately, and the spacer is a part of the original sacrificial layer 21.

[0132] Figure 25 A schematic diagram of a three-dimensional memory structure is shown. Exemplarily, the method for manufacturing a three-dimensional memory provided in this application can form... Figure 25 The three-dimensional memory shown. The peripheral wafer 6 and the storage wafer 7 of this three-dimensional memory can be manufactured separately.

[0133] The steps of forming the peripheral wafer 6 may include the aforementioned steps of forming a fin field-effect transistor on the first semiconductor layer 1, and may also include the steps of forming a first planar transistor on the first semiconductor layer 1, and may further include forming a second planar transistor 8 on the first semiconductor layer. Exemplarily, the second planar transistor 8 may be an N-type MOS transistor or a P-type MOS transistor. In some embodiments, the second planar transistor may be used as a high-voltage device, and the fin field-effect transistor as a low-voltage device. It should be understood that the various transistors provided in this disclosure are not limited to this in their application in circuits.

[0134] The step of forming the peripheral wafer 6 further includes: forming a dielectric layer 61 covering the fin field-effect transistor, and then forming a plurality of conductive channels 62 that penetrate the dielectric layer 61 and are electrically connected to the fin field-effect transistor. The conductive channels 62 can be correspondingly connected to the gate structure 4, the first heavily doped region 251, the second heavily doped region 252, and the source, drain, or gate of the second planar transistor 8.

[0135] A first interconnect layer 63 electrically connected to the conductive channel 62 can then be formed, and a first bonding layer 64 electrically connected to the first interconnect layer 63 can also be formed. The first bonding layer 64 can be located on the side of the first interconnect layer 63 away from the first semiconductor layer 1.

[0136] The step of forming the memory wafer 7 may include forming a three-dimensional memory structure 72 on one side of the second semiconductor layer 71. The second semiconductor layer 71 may be a second substrate, and the material of the second substrate may include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0137] For example, the step of forming the memory wafer 7 further includes: forming a second interconnect layer 73 on the side of the three-dimensional memory structure 72 away from the second semiconductor layer 71, and then forming a second bonding layer 74 on the side of the second interconnect layer 73 away from the three-dimensional memory structure 72.

[0138] like Figure 25 As shown, after the first bonding layer 64 and the second bonding layer 74 are bonded together, the fin field-effect transistor is electrically connected to the three-dimensional memory structure 72 through the first interconnect layer 63, the first bonding layer 64, the second bonding layer 74 and the second interconnect layer 73.

[0139] Figure 26 This is a schematic diagram of another type of three-dimensional memory. Figure 26 In this three-dimensional memory, high-voltage and low-voltage devices can be disposed at the first semiconductor layer 1 of the peripheral wafer 6. The high-voltage device is a fin field-effect transistor, and the low-voltage device is also a fin field-effect transistor. The fin field-effect transistor in the three-dimensional memory provided in this disclosure can adapt to the complex usage environment requirements of the peripheral circuit, while having a small size, improving the utilization efficiency of the peripheral wafer 6, reducing the size of the first semiconductor layer 1, and thus reducing the size of the peripheral wafer 6.

[0140] refer to Figure 15 and Figures 22 to 26 The present disclosure provides a three-dimensional memory, which includes: a first semiconductor layer 1, a fin field-effect transistor, a first bonding layer 64, a second bonding layer 74, a second semiconductor layer 71, and a three-dimensional memory structure 72.

[0141] Exemplarily, the first semiconductor layer 1, the fin field-effect transistor, and the first bonding layer 64 can be fabricated on a peripheral wafer 6. The fin field-effect transistor is disposed on the first semiconductor layer 1 and includes: a first active structure, a second active structure, a multilayer channel structure connecting the first active structure and the second active structure, and a gate structure 4 located between the first active structure and the second active structure. At least one of the first active structure and the second active structure includes alternating stacked first and second doped layers along a direction away from the first semiconductor layer 1. The first bonding layer 64 is disposed on the side of the fin field-effect transistor away from the first semiconductor layer 1. The first bonding layer 64 is electrically connected to the fin field-effect transistor.

[0142] Exemplarily, a second semiconductor layer 71, a second bonding layer 74, and a three-dimensional memory structure 72 may be fabricated on a memory wafer 7. The second bonding layer 74 is located on the side of the second semiconductor layer 71 closest to the first bonding layer 64 and is bonded to the first bonding layer 64. The three-dimensional memory structure 72 is disposed on the side of the second bonding layer 74 away from the first bonding layer 64. Exemplarily, the second semiconductor layer 71 is disposed on the side of the three-dimensional memory structure 72 away from the second bonding layer 74. For memory wafers in other embodiments, the second semiconductor layer 71 may be disposed between the second bonding layer 74 and the three-dimensional memory structure 72.

[0143] It should be understood that, without departing from the teachings of this application, the second semiconductor layer 71 in the three-dimensional memory can be a second substrate used to prepare the three-dimensional memory structure 72, or it can be a semiconductor layer formed on one side of the three-dimensional memory structure 72 by removing the second substrate after completing part or all of the process of the three-dimensional memory structure 72, using semiconductor materials such as polysilicon. This application does not limit this.

[0144] Exemplarily, both the first active structure and the second active structure are used for electrical connection with the conductive channel 62. The first active structure and the second active structure may be disposed opposite each other on both sides of the multilayer channel structure along a first direction parallel to the first semiconductor layer. The multilayer channel structure is controlled by the gate structure 4, which enables the first active structure and the second active structure to be electrically connected. Exemplarily, the first active structure includes a first lightly doped region 241 and a first heavily doped region 251, with the first heavily doped region 251 spaced from the multilayer channel structure by the first lightly doped region 241; the second active structure includes a second lightly doped region 242 and a second heavily doped region 252, with the second heavily doped region 252 spaced from the multilayer channel structure by the second lightly doped region 242.

[0145] Alternatively, the first heavily doped region 251 and the second heavily doped region 252 are spaced 0.5 to 1 μm apart from the multilayer channel structure and the gate structure 4 located in the second region P, respectively.

[0146] In some embodiments, at least one of the first lightly doped region and the second lightly doped region includes a first doped layer and a second doped layer. Figure 15 Taking the second lightly doped region 242 as an example, Figure 23 It shows Figure 15 The enlarged view at point A shows that the second lightly doped region 242 includes alternating stacked first doped layer 242-1 and second doped layer 242-2.

[0147] Alternatively, at least one of the first heavily doped region 251 and the second heavily doped region 252 includes a direction away from the first semiconductor layer 1 (e.g., Figure 15 The third and fourth doped layers are alternately stacked (shown in the Z direction). Taking the second heavily doped region 252 as an example, Figure 23 It shows Figure 15 The enlarged view at point A shows that the second doped region 252 includes alternating stacked third doped layer 252-1 and fourth doped layer 252-2.

[0148] In some embodiments of this application, Figure 22 In the semiconductor structure shown, the fin field-effect transistor can be used as a low-voltage device, while Figure 15 The fin field-effect transistor in the semiconductor structure shown can be used as a high-voltage device when applied to circuits.

[0149] Optional, in Figure 22 In the semiconductor structure shown, when the fin field-effect transistor is used as a low-voltage device, along the direction away from the first semiconductor layer (e.g.) Figure 15 (As shown in the Z direction), the thickness of the first doped layer is within 10 to 50 nm, and the thickness of the second doped layer is within 10 to 50 nm.

[0150] Optional, in Figure 15 In the semiconductor structure shown, when the fin field-effect transistor is used as a low-voltage device, along the direction away from the first semiconductor layer (e.g.) Figure 15 (As shown in the Z direction), the thickness of the first doped layer 242-1 is within 100-200 nm, and the thickness of the second doped layer 242-2 is within 100-200 nm. Because multiple channel structures are connected in parallel in a fin field-effect transistor, manufacturing high-voltage devices in the peripheral circuit as fin field-effect transistors can greatly reduce the area occupied by the devices.

[0151] In some implementations, see Figure 14 and Figure 21 The multi-channel structure of the fin field-effect transistor may include a plurality of spaced-apart first channel pillars 221-1. Each first channel pillar 221-1 electrically connects a first active structure to a second active structure.

[0152] In some embodiments, the gate structure 4 surrounds the first channel pillar 221-1 in the YZ cross section. The gate structure 4 and the first channel pillar 221-1 are electrically isolated by an insulating portion. For example, see... Figure 13 and Figure 14 The gate structure 4 may include a first conductive portion 41, a second conductive portion 42, and a third conductive portion 43. The first conductive portion 41 is located on the side of the multilayer channel structure away from the first semiconductor layer 1. The second conductive portion 42 is disposed on at least one side of the multilayer channel structure along a second direction parallel to the first semiconductor layer and perpendicular to the first direction. The third conductive portion 43 is located between two adjacent channel pillars. The third conductive portion 43 is electrically connected to the first conductive portion 41 through the second conductive portion 42. The three conductive portions cooperate to apply an electric field to the first channel pillar 221-1 when energized.

[0153] In other embodiments, the gate structure 4 partially surrounds the first channel transverse pillar 221-1 in the YZ cross section. See, for example, [link to example]. Figure 19 and Figure 20 In a fin field-effect transistor, the first channel pillar 221-1 is relatively thin or has a narrow spacing. The gate structure 4 may include a first conductive portion 41 and a second conductive portion 42. The first conductive portion 41 is located on the multilayer channel structure. The second conductive portion 42 is disposed on at least one side of the multilayer channel structure. The space between two adjacent channel pillars is filled with an insulating portion.

[0154] In some implementations, the three-dimensional memory also includes a first planar transistor. See also Figure 24 The first planar transistor includes a third active structure, a fourth active structure, and a channel region. The channel region connects the third active structure and the fourth active structure and includes alternately stacked second channel pillars and spacers. The end of the channel region away from the first semiconductor layer is the second channel pillar. The three-dimensional memory also includes a fourth conductive portion 54, which is disposed on the side of the channel region away from the first semiconductor layer and is electrically isolated from the channel region by a planar insulating portion 53.

[0155] In some implementations, the three-dimensional memory further includes a second planar transistor, which may be an N-type MOS transistor or a P-type MOS transistor.

[0156] For example, the devices in the peripheral circuit of the three-dimensional memory can be classified into high-voltage devices, low-voltage devices, and ultra-low-voltage devices according to their voltage withstand capabilities. High-voltage devices can be configured as second planar transistors and / or first planar transistors including multi-layer channels, while low-voltage and ultra-low-voltage devices can be configured as fin field-effect transistors. For example, high-voltage, low-voltage, and ultra-low-voltage devices can all be configured as fin field-effect transistors.

[0157] In this disclosure, the peripheral wafer 6 and the memory wafer 7 are manufactured separately, so that the process of the memory wafer 7 has almost no impact on the manufacturing of the peripheral wafer 6, giving the peripheral wafer 6 a greater degree of freedom in its process, and enabling the overall process of the peripheral wafer 6 to realize fin field-effect transistors.

[0158] like Figure 27 As shown, this disclosure also provides a storage system 8, including at least one three-dimensional memory 81, a controller 82, and a connector 83. The connector 83 is used to couple the storage system 8 to an external device.

[0159] The present disclosure provides a three-dimensional memory 81, in which peripheral circuitry disposed on a peripheral wafer may include, for example, page buffers / sensor amplifiers, column decoders / bit line (BL) drivers, row decoders / word line (WL) drivers, voltage generators, control logic units, registers, interfaces, and data buses.

[0160] Exemplarily, the controller 82 and at least one three-dimensional memory 81 can be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. Exemplarily, the controller 62 and at least one three-dimensional memory 81 can be integrated into a solid-state drive (SSD).

[0161] The three-dimensional memory or storage system disclosed herein is relatively easy to manufacture, and the three-dimensional memory is small in size and has high storage density. The storage system has relatively stable operating performance.

[0162] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this disclosure.

Claims

1. A method of fabricating a three-dimensional memory, comprising: include: A finned field-effect transistor is formed in the first semiconductor layer, wherein the step of forming the finned field-effect transistor includes: A fin structure is formed, the fin structure including sacrificial portions and channel portions alternately stacked in a direction away from the first semiconductor layer, wherein, in a vertical plane away from the first semiconductor layer, the fin structure includes a first active region, a second active region, and a gate region located between the first active region and the second active region. A gate structure is formed in the gate region; and A first active structure and a second active structure are formed in the first active region and the second active region, respectively, wherein at least one of the first active structure and the second active structure includes a first doped layer and a second doped layer that are alternately stacked along a direction away from the first semiconductor layer. A first planar transistor is formed on the first semiconductor layer, wherein the first planar transistor includes a third active structure, a fourth active structure, and a channel region connecting the third active structure and the fourth active structure; A first bonding layer is formed that is electrically connected to the fin field-effect transistor; A three-dimensional memory structure is formed in the second semiconductor layer, and a second bonding layer electrically connected to the three-dimensional memory structure is formed; and Bond the first bonding layer to the second bonding layer; The fin field-effect transistors include low-voltage devices, and the first planar transistors include high-voltage devices.

2. The method of claim 1, wherein, The fin field-effect transistor is a high-voltage device. Along the direction away from the first semiconductor layer, the thickness of the first doped layer is within 100~200nm, and the thickness of the second doped layer is within 100~200nm.

3. The method of claim 1, wherein, The first active structure includes a first lightly doped region and a first heavily doped region, and the second active structure includes a second lightly doped region and a second heavily doped region. The steps of forming the first active structure and the second active structure in the first active region and the second active region, respectively, include: On the side of the fin structure away from the first semiconductor layer, a first lightly doped region and a second lightly doped region are formed in the first active region and the second active region respectively by a first ion implantation, wherein at least one of the first lightly doped region and the second lightly doped region includes the first doped layer and the second doped layer. A second ion implantation is performed to form a first heavily doped region in a portion of the first lightly doped region and a second heavily doped region in a portion of the second lightly doped region.

4. The method according to claim 3, wherein, At least one of the first heavily doped region and the second heavily doped region includes a third doped layer and a fourth doped layer that are alternately stacked in a direction away from the first semiconductor layer.

5. The method according to claim 1, wherein, The gate structure includes a first conductive portion, a second conductive portion, and a third conductive portion, wherein the step of forming the gate structure in the gate region includes: Remove the portion of the sacrificial portion located in the gate region, wherein there is a spacing space between any two adjacent channel portions and between the channel portion and the first semiconductor layer; An insulating portion is formed in the gate region, the insulating portion shielding the surface of the channel portion exposed in the gate region; The first conductive portion is formed on the side of the fin structure away from the first semiconductor layer, the second conductive portion is formed on the side of the fin structure adjacent to the first side, and the third conductive portion is formed in the space. or, The gate structure includes a first conductive portion and a second conductive portion, wherein the step of forming the gate structure in the gate region includes: Remove the portion of the sacrificial portion located in the gate region, wherein there is a spacing between any two adjacent channel portions and between the channel portion and the first semiconductor layer; and An insulating portion is formed in the gate region, wherein the insulating portion shields the surface of the channel portion exposed in the gate region and fills the spacer space; and A first conductive portion is formed on the side of the fin structure away from the first semiconductor layer, and a second conductive portion is formed on the side of the fin structure adjacent to the first semiconductor layer.

6. The method according to claim 5, wherein, The steps for forming the fin structure include: A laminated structure is formed by alternately stacking sacrificial layers and channel layers; A first shallow trench and a second shallow trench are formed in the stacked structure extending into the first semiconductor layer. The directions of the first shallow trench and the second shallow trench intersect, dividing the stacked structure into the fin structure.

7. The method according to claim 6, wherein, The steps for forming the first planar transistor include: Two third shallow trench isolation structures are formed in the stacked structure and are arranged opposite each other along the direction close to the first semiconductor layer to divide the planar structure, wherein the planar structure includes a third active region, a channel region and a fourth active region in the vertical plane away from the first semiconductor layer. A fourth conductive portion is formed on the planar structure; A third active structure and a fourth active structure are formed in the third active region and the fourth active region, respectively.

8. The method according to claim 7, wherein, The steps for forming the third active structure and the fourth active structure include: On the side of the planar structure away from the first semiconductor layer, a third lightly doped region is formed in the third active region by a first ion implantation, and a fourth lightly doped region is formed in the fourth active region; A third heavily doped region and a fourth heavily doped region are formed in the third lightly doped region and the fourth lightly doped region, respectively, wherein the third heavily doped region is separated from the channel region by the third lightly doped region, and the fourth heavily doped region is separated from the channel region by the fourth lightly doped region.

9. The method according to claim 1, wherein, The method further includes: A well region is formed in the first semiconductor layer; and A first drift region and a second drift region spaced apart from the first drift region are formed in the trap region; The formation of the fin field-effect transistor in the first semiconductor layer includes: The fin field-effect transistor is formed on the well region, and the fin field-effect transistor includes a first active structure and a second active structure formed on the side of the first drift region and the second drift region away from the first semiconductor layer, respectively.

10. The method according to claim 1, wherein, The method further includes: A first interconnect layer and a second interconnect layer are formed in the first semiconductor layer and the second semiconductor layer, respectively; The fin field-effect transistor is electrically connected to the three-dimensional memory structure through the first interconnect layer, the first bonding layer, the second bonding layer, and the second interconnect layer.

11. A three-dimensional memory, characterized in that, include: First semiconductor layer; A fin field-effect transistor is located in the first semiconductor layer in a vertical plane away from the first semiconductor layer. The fin field-effect transistor includes a first active structure, a second active structure, a multilayer channel structure connecting the first active structure and the second active structure, and a gate structure located between the first active structure and the second active structure. At least one of the first active structure and the second active structure includes a first doped layer and a second doped layer that are alternately stacked along the direction away from the first semiconductor layer. A first planar transistor, the first planar transistor including a third active structure, a fourth active structure, and a channel region connecting the third active structure and the fourth active structure; The first bonding layer is located on the side of the fin field-effect transistor away from the first semiconductor layer and is electrically connected to the fin field-effect transistor. Second semiconductor layer, The second bonding layer is located on the side of the second semiconductor layer close to the first bonding layer and is bonded to the first bonding layer; A three-dimensional storage structure is located in the second semiconductor layer and electrically connected to the second bonding layer; and The types of fin field-effect transistors include low-voltage devices, and the types of the first planar transistors include high-voltage devices.

12. The three-dimensional memory according to claim 11, wherein, The second doped layer and at least one of the channel structures are integrally formed.

13. The three-dimensional memory according to claim 11, wherein, The first active structure includes a first lightly doped region and a first heavily doped region, wherein the first heavily doped region is separated from the multilayer channel structure by the first lightly doped region. The second active structure includes a second lightly doped region and a second heavily doped region, wherein the second heavily doped region is separated from the multilayer channel structure by the second lightly doped region; Wherein, at least one of the first lightly doped region and the second lightly doped region includes the first doped layer and the second doped layer.

14. The three-dimensional memory according to claim 13, wherein, At least one of the first heavily doped region and the second heavily doped region includes a third doped layer and a fourth doped layer that are alternately stacked in a direction away from the first semiconductor layer.

15. The three-dimensional memory according to claim 14, wherein, The fourth doped layer and at least one of the channel structures are integrally formed.

16. The three-dimensional memory according to claim 11, wherein, The gate structure includes: The first conductive portion is located on the side of the multilayer channel structure away from the first semiconductor layer; The second conductive part is located on the side of the multilayer channel structure adjacent to one side; The third conductive portion is located at least between the multilayer channel structure and the first semiconductor layer; or, The gate structure includes: The first conductive portion is located on the side of the multilayer channel structure away from the first semiconductor layer; The second conductive part is located on the side of the multilayer channel structure adjacent to one side; The space between the multilayer channel structure and the first semiconductor layer is filled with an insulating portion.

17. The three-dimensional memory according to claim 11, wherein, The first planar transistor is located on the first semiconductor layer, and the channel region includes alternately stacked second channel pillars and spacers, with the top layer being the second channel pillars.

18. A storage system, characterized in that, include: The three-dimensional memory as described in any one of claims 11 to 17; and The controller is electrically connected to the three-dimensional memory and controls the three-dimensional memory.

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