Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor structure and a method for fabricating the same. The method includes: providing a first substrate and forming driving pads on the first substrate; providing a second substrate and sequentially forming active pillars and bit lines on one side of the second substrate; wherein one side of the bit lines is connected to the active pillars, and the surface of the bit lines facing away from the active pillars is exposed on the surface of the second substrate; bonding the bit lines to the corresponding driving pads; thinning the second substrate from the side facing away from the first substrate until the active pillars are exposed; forming a storage capacitor on the side of the active pillars facing away from the driving pads, and connecting the storage capacitor to the active pillars. This disclosure can effectively improve storage density and simplify the manufacturing process, thereby improving the production yield and electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source of the transistor is electrically connected to the bit line, and the drain of the transistor is electrically connected to the capacitor. The word line voltage controls the switching on and off of the transistor, thereby enabling the reading of data stored in the capacitor via the bit line, or the writing of data to the capacitor.

[0003] However, with the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. Especially after semiconductor processes entered the deep submicron stage, the size of devices in DRAM has also been reduced to its limit. On this basis, it has become very difficult to further reduce the size of devices in DRAM, and further miniaturization of device size will also cause a significant deterioration in the electrical performance of DRAM.

[0004] Therefore, how to further improve the storage density of semiconductor structures has become a pressing problem to be solved in related technologies. Summary of the Invention

[0005] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can effectively improve storage density and simplify the manufacturing process, thereby improving the production yield and electrical performance of the semiconductor structure.

[0006] On one hand, some embodiments of this disclosure provide a method for fabricating a semiconductor structure. This method for fabricating a semiconductor structure includes the following steps.

[0007] A first substrate is provided, and driving pads are formed on the first substrate.

[0008] A second substrate is provided, on one side of which an active pillar and a bit line are sequentially formed; wherein, one side of the bit line is connected to the active pillar, and the surface of the bit line facing away from the active pillar is exposed on the surface of the second substrate.

[0009] The bit lines are bonded to the corresponding drive pads.

[0010] The second substrate is thinned from the side opposite to the first substrate until the active pillar is exposed.

[0011] A storage capacitor is formed on the side of the active post away from the drive pad, and the storage capacitor is connected to the active post.

[0012] In some embodiments, after forming the active pillar and before forming the bit line, the fabrication method further includes forming a word line material layer on the sidewall of the active pillar.

[0013] After thinning the second substrate to expose the active pillars, and before forming storage capacitors on the side of the active pillars away from the drive pads, the fabrication method further includes etching the word line material layer to form word lines.

[0014] The bit line extends along a first direction, the word line extends along a second direction, and the first direction and the second direction intersect.

[0015] In some embodiments, forming the active pillars on one side of the second substrate includes: patterning the second substrate to form a plurality of active pillars arranged in an array. The distance between adjacent active pillars in the first direction is a first dimension, and the distance between adjacent active pillars in the second direction is a second dimension; the first dimension is greater than three times the second dimension, and the second dimension is less than or equal to two or three times the thickness of the word line in the first direction.

[0016] In some embodiments, before forming a word line material layer on the sidewall of the active pillar, the fabrication method further includes: forming a sacrificial layer on the surface of the second substrate, the sacrificial layer covering a portion of the sidewall of the active pillar and the surface of the second substrate between adjacent active pillars.

[0017] Forming a word line material layer on the sidewall of the active post includes: sequentially forming a gate dielectric material layer and a conductive material layer on the exposed surface of the active post; wherein the gate dielectric material layer covers the exposed sidewall of the active post, and the conductive material layer covers the gate dielectric material layer and the sacrificial layer; the gate dielectric material layer and the conductive material layer together constitute the word line material layer.

[0018] After forming a word line material layer on the sidewall of the active pillar, the preparation method further includes: forming an isolation material layer that covers the conductive material layer and fills the groove between adjacent active pillars.

[0019] In some embodiments, before forming the bit line, the fabrication method further includes the following steps.

[0020] The isolation material layer and the word line material layer are etched along a direction perpendicular to the second substrate to form an isolation structure and a word line intermediate structure, and to expose part of the sidewall of the active pillar.

[0021] A first dielectric layer is formed, which covers the isolation structure, the word line intermediate structure, and part of the sidewall of the active pillar.

[0022] A second dielectric layer extending along the first direction is formed between adjacent active pillars arranged in the second direction, and the second dielectric layer covers a portion of the first dielectric layer and a portion of the sidewall of the active pillar.

[0023] In some embodiments, forming the bit line includes the following steps.

[0024] A metal layer is formed on the surface of a groove between adjacent active posts arranged in a first direction, the metal layer covering the active posts and the sidewalls of the second dielectric layer exposed within the groove.

[0025] Heat treatment is performed on the metal layer and the active pillars covered by the metal layer to form the bit line connected to the active pillars.

[0026] In some embodiments, thinning the second substrate from the side of the second substrate away from the first substrate to expose the active pillar further includes exposing the surface of the sacrificial layer away from the word line intermediate structure.

[0027] The preparation method further includes: removing the sacrificial layer and part of the word line intermediate structure to form the word line and the isolation portion located between adjacent word lines.

[0028] In some embodiments, removing a portion of the word line intermediate structure includes: etching the word line intermediate structure along a direction perpendicular to the first substrate to disconnect the conductive material layer between adjacent active pillars in the first direction, and to allow the conductive material layers connected in the second direction to form the word line.

[0029] In some embodiments, after the word line is formed and before the storage capacitor is formed on the side of the active pillar away from the drive pad, the fabrication method further includes: forming a third dielectric layer that covers the word line and a portion of the sidewall of the active pillar; and forming a fourth dielectric layer that covers the third dielectric layer and the remaining sidewall of the active pillar, wherein the surface of the fourth dielectric layer away from the first substrate is flush with the surface of the active pillar away from the first substrate.

[0030] In some embodiments, forming a storage capacitor on the side of the active pillar away from the drive pad further includes: grinding the surfaces of the active pillar and the fourth dielectric layer away from the first substrate; and forming the storage capacitor on the surface of the active pillar.

[0031] In another aspect, some embodiments of this disclosure provide a semiconductor structure obtained using the semiconductor structure fabrication method described in the above embodiments. The semiconductor structure includes: a first substrate having driving pads on it; and a memory device bonded to the side of the driving pads facing away from the first substrate. The memory device includes: an active pillar, and bit lines and storage capacitors located at opposite ends of the active pillars. The surface of the bit line facing away from the first substrate is connected to the end of the active pillar closest to the first substrate, the storage capacitor is connected to the end of the active pillar facing away from the bit line, and the surface of the bit line close to the first substrate is bonded to the driving pads.

[0032] In some embodiments, the storage device further includes: word lines disposed on the sidewalls of the active pillars. The bit lines extend along a first direction, and the word lines extend along a second direction, the first and second directions intersecting; the word lines are formed after the bit lines are bonded to the drive pads and before the storage capacitor is formed.

[0033] In some embodiments, the storage device further includes an isolation structure located between adjacent word lines.

[0034] In some embodiments, the number of active pillars is multiple, and the multiple active pillars are arranged in an array. The distance between adjacent active pillars in the first direction is a first dimension, and the distance between adjacent active pillars in the second direction is a second dimension; the first dimension is greater than three times the second dimension, and the second dimension is less than or equal to two or three times the thickness of the word line in the first direction.

[0035] In some embodiments, the word line includes a gate dielectric layer and a conductive layer disposed on the sidewall of the active post along a direction away from the active post; wherein the second dimension is less than or equal to three times the thickness of the conductive layer in the first direction.

[0036] In this embodiment, a first substrate is used to form driving pads, and a second substrate is used to form active pillars and bit lines. The first substrate supports the devices on the second substrate by bonding the driving pads and bit lines to each other. Then, the second substrate is thinned until the ends of the active pillars facing away from the first substrate are exposed. Storage capacitors corresponding to and connected to the active pillars can be fabricated on the side of the active pillars facing away from the first substrate. Thus, the aforementioned fabrication method provided by this embodiment is simple, allowing for the formation of vertical transistors based on active pillars, the fabrication of bit lines on one side of the second substrate, and the self-alignment of the storage capacitors on the other side of the second substrate. This not only greatly simplifies the semiconductor structure fabrication process to improve production yield but also significantly reduces the horizontal dimensions of the vertical transistors and storage capacitors, further increasing storage density and effectively ensuring the electrical performance of each device structure within the semiconductor structure.

[0037] Furthermore, the method of bonding the driving pads on the first substrate to the upper lines on the second substrate in the embodiments of this disclosure to prepare the semiconductor structure is also beneficial to reduce the planar area of ​​the semiconductor structure, thereby increasing the number of storage capacitors per unit area and thus improving the area utilization of the wafer. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure as provided in one embodiment;

[0040] Figure 2 A flowchart illustrating a method for fabricating a semiconductor structure as provided in another embodiment;

[0041] Figure 3 This is a flowchart of a method for fabricating a semiconductor structure provided in another embodiment;

[0042] Figure 4 This is a schematic diagram of the structure of a first substrate provided in one embodiment;

[0043] Figure 5 This is a schematic diagram of a structure obtained after forming an active column, as provided in one embodiment;

[0044] Figure 6 This is a schematic diagram of the location distribution of an active column provided in one embodiment;

[0045] Figure 7 This is a schematic diagram of a structure obtained after forming a sacrificial layer in one embodiment;

[0046] Figure 8 This is a schematic diagram of a structure obtained after forming a word line material layer and an isolation material layer in one embodiment;

[0047] Figure 9 This is a schematic diagram of the structure obtained after removing part of the word line material layer and part of the isolation material layer in one embodiment;

[0048] Figure 10 This is a schematic diagram of a structure obtained after forming a word line intermediate structure and an isolation structure in one embodiment;

[0049] Figure 11 This is a schematic diagram of a structure obtained after forming a first dielectric layer in one embodiment;

[0050] Figure 12 This is a schematic diagram of a structure obtained after forming a second dielectric layer in one embodiment;

[0051] Figure 13 This is a top view schematic diagram of a structure obtained after forming bit lines in one embodiment;

[0052] Figure 14 This is a schematic diagram of a structure obtained after forming a bit line, as provided in one embodiment;

[0053] Figure 15 This is a schematic diagram of a word line intermediate structure provided in one embodiment in the second direction;

[0054] Figure 16 This is a schematic diagram of a structure obtained by bonding bit lines to drive pads in one embodiment;

[0055] Figure 17 This is a schematic diagram of a structure obtained by thinning a second substrate to expose an active pillar, as provided in one embodiment.

[0056] Figure 18 This is a schematic diagram of the structure obtained after forming word lines and isolation portions in one embodiment;

[0057] Figure 19 This is a schematic diagram of a structure obtained after forming a third dielectric layer and a fourth dielectric layer in one embodiment;

[0058] Figure 20 This is a schematic diagram of a semiconductor structure provided in one embodiment;

[0059] Figure 21 This is a top view schematic diagram of a semiconductor structure provided in one embodiment.

[0060] Explanation of reference numerals in the attached figures:

[0061] 1-First substrate, 11-Drive pad, 12-Circuit layer, 2-Second substrate, 21-Active pillar, L1-First dimension

[0062] L2 - Second dimension, 3 - Sacrificial layer, 220A - Word line material layer, 221A - Gate dielectric material layer, 222A - Conductive material layer.

[0063] 230A - Isolation material layer, 221B - Gate dielectric polished layer, 222B - Conductive material polished layer, 230B - Isolation material polished layer.

[0064] 221C - Gate dielectric intermediate structure, 222C - Conductive material intermediate structure, 221 - Gate dielectric layer, 222 - Conductive layer.

[0065] 22 - Middle structure of the word line, 23A - Isolation structure, 23 - Isolation part, 24 - First dielectric layer, 25 - Second dielectric layer.

[0066] 26 - Third dielectric layer, 27 - Fourth dielectric layer, G - Groove, M - Metal layer, BL - Bit line, WL - Word line, C - Storage capacitor

[0067] B - thickness of the letter line in the first direction, T - thickness of the conductive layer in the first direction, N - storage device. Detailed Implementation

[0068] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0070] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0071] It should be understood that although the terms first, second, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0072] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0073] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0074] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures), thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the invention.

[0075] Currently, with the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. Especially after semiconductor processes entered the deep submicron stage, the dimensions of devices in DRAM have also been reduced to their limits. For example, DRAM can achieve a maximum planar area size of 6F for memory cells. 2 The arrangement of the word lines and the fabrication method using embedded word lines; where F is the minimum process size, which refers to the smallest size that the process can process, also known as the critical size, and can be used as a standard to define the level of manufacturing process. On this basis, it has become very difficult to further reduce the device size in DRAM, and further miniaturization of the device size will also cause a significant deterioration in the electrical performance of DRAM.

[0076] In some examples, new materials can be used to fabricate DRAM to improve its electrical performance, but this requires higher production costs and more complex fabrication processes.

[0077] Based on this, the present disclosure provides a semiconductor structure and its fabrication method to effectively improve storage density, for example, it can be used to achieve a storage cell with a maximum planar area size of 4F. 2 The arrangement of semiconductor structures and the simplification of manufacturing processes are used to improve the production yield and electrical performance of semiconductor structures.

[0078] Please see Figure 1 This disclosure provides a method for fabricating a semiconductor structure, comprising the following steps.

[0079] S100 provides a first substrate on which drive pads are formed.

[0080] S200, a second substrate is provided, on one side of which an active pillar and a bit line are sequentially formed; wherein, one side of the bit line is connected to the active pillar, and the surface of the bit line facing away from the active pillar is exposed on the surface of the second substrate.

[0081] S300, which bonds the bit lines to the corresponding drive pads.

[0082] S400, the second substrate is thinned from the side of the second substrate away from the first substrate until the active pillar is exposed.

[0083] In S500, a storage capacitor is formed on the side of the active post away from the drive pad, and the storage capacitor is connected to the active post.

[0084] In this embodiment, a first substrate is used to form driving pads, and a second substrate is used to form active pillars and bit lines. The first substrate supports the devices on the second substrate by bonding the driving pads and bit lines to each other. Then, the second substrate is thinned until the ends of the active pillars facing away from the first substrate are exposed. Storage capacitors corresponding to and connected to the active pillars can be fabricated on the side of the active pillars facing away from the first substrate. Thus, the aforementioned fabrication method provided by this embodiment is simple, allowing for the formation of vertical transistors based on active pillars, the fabrication of bit lines on one side of the second substrate, and the fabrication of storage capacitors on the other side of the second substrate. This not only greatly simplifies the semiconductor structure fabrication process to improve production yield but also significantly reduces the horizontal dimensions of the vertical transistors and storage capacitors, further increasing storage density and effectively ensuring the electrical performance of each device structure within the semiconductor structure.

[0085] Furthermore, the method of bonding the driving pads on the first substrate to the upper lines on the second substrate in the embodiments of this disclosure to prepare the semiconductor structure is also beneficial to reduce the planar area of ​​the semiconductor structure, thereby increasing the number of storage capacitors per unit area and thus improving the area utilization of the wafer.

[0086] In some embodiments, it can be understood that in step S200, the active pillar and the bit line are sequentially formed on one side of the second substrate, that is, the active pillar and the bit line are formed independently. Thus, after forming the active pillar and before forming the bit line, the fabrication method further includes forming a word line material layer on the sidewall of the active pillar.

[0087] For example, please refer to Figure 2 Step S200 may include the following steps.

[0088] S210 provides a second substrate, on one side of which an active pillar is formed.

[0089] S220, a layer of letter line material is formed on the side wall of the active column.

[0090] S230, forming a bit line, one side of which is connected to an active pillar, and the surface of the bit line facing away from the active pillar is exposed on the surface of the second substrate.

[0091] Accordingly, please continue reading Figure 2 After performing step S400 to thin the second substrate to expose the active pillar, and before performing step S500 to form a storage capacitor on the side of the active pillar away from the driving pad, the fabrication method further includes:

[0092] S450, etching the letter line material layer to form the letter lines.

[0093] For example, bit lines extend along a first direction, and word lines extend along a second direction. The first and second directions intersect, for example, perpendicularly.

[0094] In some embodiments, forming an active pillar on one side of the second substrate in step S210 includes: patterning the second substrate to form a plurality of active pillars arranged in an array.

[0095] Here, multiple active pillar arrays are arranged in rows along a first direction and in columns along a second direction. Optionally, the spacing between the active pillars arranged in rows in the first direction may be different from the spacing between the active pillars arranged in columns in the second direction.

[0096] For example, the distance between adjacent active posts in a first direction is a first dimension, and the distance between adjacent active posts in a second direction is a second dimension. The first dimension is greater than three times the second dimension, and the second dimension is less than or equal to two or three times the thickness of the word line in the first direction.

[0097] As a further example, the word line includes a gate dielectric layer and a conductive layer disposed on the sidewall of the active post along a direction away from the active post; wherein the second dimension is less than or equal to three times the thickness of the conductive layer in the first direction.

[0098] In some embodiments, please refer to Figure 3 Before performing step S220 to form a word line material layer on the sidewall of the active pillar, the preparation method further includes:

[0099] S215, a sacrificial layer is formed on the surface of the second substrate, the sacrificial layer covering part of the sidewall of the active pillar and the surface of the second substrate between adjacent active pillars.

[0100] Accordingly, step S220, forming a word line material layer on the sidewall of the active pillar, includes: sequentially forming a gate dielectric material layer and a conductive material layer on the exposed surface of the active pillar; wherein the gate dielectric material layer covers the exposed sidewall of the active pillar, and the conductive material layer covers the gate dielectric material layer and the sacrificial layer. Thus, the gate dielectric material layer and the conductive material layer together constitute the word line material layer.

[0101] Accordingly, after performing step S220 to form a word line material layer on the sidewall of the active pillar, the preparation method further includes:

[0102] S221, forming an isolation material layer, the isolation material layer covering the conductive material layer and filling the groove between adjacent active pillars.

[0103] Based on this, please continue reading Figure 3In some embodiments, before performing step S230 to form the bit line, the preparation method further includes the following steps.

[0104] S222, etching the isolation material layer and word line material layer along a direction perpendicular to the second substrate to form the isolation structure and word line intermediate structure, and exposing part of the sidewall of the active pillar.

[0105] S223, forming a first dielectric layer, the first dielectric layer covering the isolation structure, the word line intermediate structure and part of the sidewall of the active column.

[0106] S224, a second dielectric layer extending in the first direction is formed between adjacent active columns arranged in the second direction, the second dielectric layer covering the first dielectric layer and part of the sidewall of the active column.

[0107] Accordingly, in some embodiments, please continue to refer to Figure 3 Step S230 involves forming a bit line, which includes the following steps.

[0108] S231, a metal layer is formed on the surface of the groove between adjacent active pillars arranged in the first direction, the metal layer covering the active pillars and the second dielectric layer exposed on the sidewalls within the groove.

[0109] S232, a heat-treated metal layer and an active pillar covered by the metal layer, forming a bit line connected to the active pillar.

[0110] Optionally, after heat-treating the metal layer and the active pillar covered by the metal layer, a metal silicide can be formed on the portion of the active pillar covered by the metal layer. Then, the residual metal layer can be cleaned to remove it, allowing for a second metal layer deposition within the aforementioned groove to form a bit line. Thus, the bit line can be formed by both the metal layer and the metal silicide at the bottom of the active pillar. Furthermore, in this embodiment, forming the bit line by cleaning away the residual metal layer after forming the metal silicide and then depositing a new metal layer not only avoids the problem of short circuits between different rows of metal layers caused by heat treatment, but also effectively reduces the contact resistance between the metal layer and the active pillar using the metal silicide, thereby improving the electrical performance of the semiconductor structure.

[0111] In some embodiments, please continue reading Figure 3 In step S400, the second substrate is thinned from the side of the second substrate away from the first substrate until the active pillar is exposed, and the process also includes exposing the surface of the sacrificial layer away from the middle structure of the word line.

[0112] Accordingly, step S450 can be manifested as: removing the sacrificial layer and part of the word line intermediate structure to form word lines and isolation portions located between adjacent word lines.

[0113] Based on this, in some embodiments, removing the word line intermediate structure includes: forming an etching opening on the sacrificial layer, etching the word line intermediate structure along a direction perpendicular to the first substrate according to the etching opening, so as to disconnect the conductive material layer between adjacent active pillars in a first direction, and make the conductive material layers connected in a second direction used to form the word line.

[0114] It is worth mentioning that the word lines extend along the second direction. In the aforementioned example where the first dimension is more than three times the second dimension, and the second dimension is less than or equal to two or three times the thickness of the word line in the first direction, or where the second dimension is less than or equal to three times the thickness of the conductive layer in the first direction, when a conductive material layer is deposited between adjacent active pillars arranged in the second direction, the conductive material layers located on the sidewalls of these adjacent active pillars can be directly connected; that is, after depositing the conductive material layer, there is no longer a recessed space between adjacent active pillars along the second direction for depositing an isolation material layer. Based on this, after thinning the second substrate, etching away part of the word line intermediate structure along a direction perpendicular to the first substrate yields the word lines and the isolation portion located between adjacent word lines, ensuring that adjacent word lines are not connected to each other. This facilitates the use of wet etching processes to simplify the semiconductor structure fabrication process.

[0115] In addition, in some other examples, an isolation structure is formed within the interval between adjacent active pillars along the second direction, so that the removal of the middle structure of the character line can also be achieved by the following steps.

[0116] A mask layer is formed on the surface of the sacrificial layer and the surface of the active pillar, the mask layer covering the surface of the active pillar extending in a second direction to expose the sacrificial layer located between adjacent active pillars in a first direction.

[0117] The exposed sacrificial layer is etched to expose the word line intermediate structure located between adjacent active pillars in the first direction.

[0118] The exposed word line intermediate structure is etched to expose the isolation structure, thereby breaking the conductive material layer between adjacent active pillars in a first direction.

[0119] Remove the mask layer and the remaining sacrificial layer so that the remaining word line middle structure located on the active pillar sidewall forms a word line, and the remaining isolation structure forms an isolation section.

[0120] In some embodiments, after performing step S450 to form word lines and before performing step S500 to form storage capacitors on the side of the active pillar away from the drive pad, the fabrication method further includes: forming a third dielectric layer, the third dielectric layer covering the word lines and a portion of the sidewalls of the active pillars; forming a fourth dielectric layer, the fourth dielectric layer covering the third dielectric layer and the remaining sidewalls of the active pillars, the surface of the fourth dielectric layer away from the first substrate being flush with the surface of the active pillars away from the first substrate.

[0121] In some embodiments, step S500, which forms a storage capacitor on the side of the active pillar away from the driving pad, further includes: grinding the surface of the active pillar and the fourth dielectric layer away from the first substrate; and forming a storage capacitor on the surface of the active pillar.

[0122] To more clearly illustrate the method for fabricating the semiconductor structure provided in the embodiments of this disclosure, the following is combined with... Figures 4 to 21 The preparation method provided in the embodiments of this disclosure is described in detail.

[0123] In step S100, please refer to Figure 4 A first substrate 1 is provided, and a driving pad 11 is formed on the first substrate 1.

[0124] Here, the first substrate 1 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The first substrate 1 can be a single-layer structure or a multi-layer structure. For example, the first substrate 1 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the first substrate 1 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0125] In addition, please continue to refer to Figure 4 A circuit layer 12 may be provided on the first substrate 1, and the circuit layer 12 includes a driving circuit corresponding to and connected to the driving pad 11. Figure 4 (Not shown in the diagram). The drive pad 11 can be formed of metal, such as tungsten or copper. The drive circuits in the circuit layer 12 can be formed using complementary metal-oxide-semiconductor (CMOS) devices.

[0126] In step S200, please refer to Figures 5 to 14 A second substrate 2 is provided, on one side of which an active pillar 21 and a bit line BL are sequentially formed.

[0127] Here, the second substrate 2 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The first substrate 2 can be a single-layer structure or a multi-layer structure. For example, the first substrate 2 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the second substrate 2 can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0128] For example, step S200 may include steps S210 to S230.

[0129] In step S210, as Figure 5 As shown, an active pillar 21 is formed on one side of the second substrate 2.

[0130] Here, the active pillars 21 can be formed by patterning the second substrate 2, that is, forming a matrix of mask patterns on the surface of the second substrate 2, and etching the second substrate 2 that is not covered by the mask patterns. Furthermore, the multiple active pillars 21 are arranged in an array, for example, they can be arranged in columns at equal intervals along a first direction, or in rows at equal intervals along a second direction.

[0131] For example, please refer to Figure 6 The distance between adjacent active posts 21 in the first direction (e.g., the X direction) is defined as the first dimension L1, and the distance between adjacent active posts 21 in the second direction (e.g., the Y direction) is defined as the second dimension L2. The first dimension L1 is greater than three times the second dimension L2; that is, L1 > 3L2. Furthermore, the second dimension L2 can be less than or equal to two or three times the thickness B of the subsequently formed word lines in the first direction; that is, L2 < 2B or L2 < 3B.

[0132] In step S215, as Figure 7 As shown, a sacrificial layer 3 is formed on the surface of the second substrate 2, and the sacrificial layer 3 covers part of the sidewall of the active pillar 21 and the surface of the second substrate 2 between adjacent active pillars 21.

[0133] Here, the sacrificial layer 3 can be formed using a deposition process, and the deposition thickness of the sacrificial layer 3 can be selected and set according to requirements, for example, less than or equal to one-third of the height of the active column 21. Alternatively, the sacrificial layer 3 can also be deposited first and then etched back to obtain a preset thickness.

[0134] For example, the sacrificial layer 3 is formed using an oxide, such as silicon oxide.

[0135] In step S220, please refer to Figure 8 A word line material layer 220A is formed on the side wall of the active column 21.

[0136] For example, the word line material layer 220A includes a gate dielectric material layer 221A and a conductive material layer 222A stacked together. The gate dielectric material layer 221A covers the exposed sidewalls of the source pillar 21, and the conductive material layer 222A covers the gate dielectric material layer 221A and the sacrificial layer 3; the gate dielectric material layer 221A and the conductive material layer 222A together constitute the word line material layer 220A.

[0137] Here, the gate dielectric material layer 221A can be formed by deposition process, or it can be formed directly by oxidizing the surface of the active pillar 21.

[0138] For example, the gate dielectric material layer 221A can be formed by deposition of a high-k dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or aluminum silicate (HfSiO).

[0139] For example, the conductive material layer 222A may comprise a metal or metal compound, such as titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al). The conductive material layer 222A may be formed using a deposition process, such as physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), etc.

[0140] For example, the gate dielectric material layer 221A and the sacrificial layer 3 are made of the same material, such as silicon oxide. Thus, they can be formed using the same deposition process.

[0141] In step S221, please refer to... Figure 8 An isolation material layer 230A is formed, which covers the conductive material layer 222A and fills the groove between adjacent active pillars 21.

[0142] For example, the insulating material layer 230A may be formed using a nitride, such as silicon nitride.

[0143] It is understandable that, in examples where the second dimension L2 between adjacent active pillars 21 in the second direction can be less than or equal to two or three times the thickness B of the word line in the first direction, after forming the gate dielectric material layer 221A and the conductive material layer 222A, the groove between adjacent active pillars 21 in the second direction can be filled by the gate dielectric material layer 221A and the conductive material layer 222A. Thus, an isolation material layer 230A may not be formed between adjacent active pillars 21 in the second direction.

[0144] In step S222, please refer to Figure 8 , Figure 9 and Figure 10 The isolation material layer 230A and the word line material layer 220A are etched along a direction perpendicular to the second substrate 2 to form the isolation structure 23 and the word line intermediate structure 22, and to expose part of the sidewall of the active pillar 21.

[0145] For example, such as Figure 9 As shown, after forming the isolation material layer 230A, a portion of the isolation material layer 230A and a portion of the word line material layer 220A can be removed using a chemical mechanical polishing (CMP) process until the active pillar 21 is exposed, thereby forming an isolation material polished layer 230B, a conductive material polished layer 222B, and a gate dielectric material polished layer 221B. Then, as... Figure 10 As shown, by continuing to etch the isolation material polished layer 230B, the conductive material polished layer 222B, and the gate dielectric material polished layer 221B using dry etching or wet etching, an isolation structure 23A and a word line intermediate structure 22 can be formed accordingly. The word line intermediate structure 22 includes a gate dielectric intermediate structure 221C and a conductive material intermediate structure 222C.

[0146] In step S223, please refer to Figure 11 A first dielectric layer 24 is formed, which covers part of the sidewalls of the isolation structure 23A, the word line intermediate structure 22, and the active pillar 21.

[0147] For example, the first dielectric layer 24 may be formed using a nitride, such as silicon nitride.

[0148] In step S224, please refer to Figure 12 A second dielectric layer 25 extending in a first direction (e.g., the X direction) is formed between adjacent active pillars 21 arranged in a second direction (e.g., the Y direction). The second dielectric layer 25 covers the first dielectric layer 24 extending in the first direction (e.g., the X direction) and part of the sidewalls of the active pillars 21. Thus, a groove G can be provided between adjacent active pillars 21 arranged in the first direction (e.g., the X direction).

[0149] For example, the second dielectric layer 25 may be formed of an oxide, such as silicon oxide.

[0150] Optionally, the second dielectric layer 25 can be formed after depositing the second dielectric material layer by patterning the second dielectric material layer and removing the unmasked second dielectric material layer. Alternatively, the second dielectric layer 25 can also be formed by setting a mask pattern in the groove G and depositing it directly on the first dielectric layer 24 that is not covered by the mask pattern, and then removing the mask pattern.

[0151] In step S230, please refer to Figure 13 and Figure 14This forms a bit line BL. One side of the bit line BL is connected to the active pillar 21, and the surface of the bit line BL facing away from the active pillar 21 is exposed on the surface of the second substrate 2.

[0152] For example, step S230 may include steps S231 to S233.

[0153] In step S231, please refer to Figure 13 A metal layer M is formed on the surface of the groove G between adjacent active posts 21 along a first direction (e.g., the X direction). The metal layer M covers the active posts 21 and the sidewalls of the second dielectric layer 24 exposed in the groove G.

[0154] In step S232, please refer to Figure 13 and Figure 14 A heat-treated metal layer M and an active pillar 21 covered by the metal layer M form a bit line BL connected to the active pillar 21.

[0155] Optionally, after heat-treating the metal layer M and the active pillar 21 covered by the metal layer M, a metal silicide can be formed on the surface of the active pillar 21. Then, the residual metal layer can be cleaned to remove it, so as to deposit a metal layer a second time in the aforementioned groove G to form the bit line BL. Thus, the bit line BL can be composed of both the metal layer and the metal silicide. Furthermore, in this embodiment of the present disclosure, the bit line BL is formed by cleaning and removing the residual metal layer after forming the metal silicide and then depositing a metal layer again. This not only avoids the problem of short circuits between different rows of metal layers caused by heat treatment, but also effectively reduces the contact resistance between the metal layer and the active pillar by utilizing the metal silicide, thereby improving the electrical performance of the semiconductor structure.

[0156] Optionally, the metal layer M can be made of metals such as tungsten (W), cobalt (Co), or aluminum (Al).

[0157] Please refer to the following for further information. Figure 14 and Figure 15 In some examples, the second dimension L2, used to characterize the distance between adjacent active pillars 21 in the second direction (e.g., the Y direction), is, for example, less than or equal to twice the thickness of the word line material layer 220A in the first direction (i.e., the width B of the word line intermediate structure 22 in the first direction at this moment); or, the second dimension L2 is less than or equal to three times the thickness T of the conductive material intermediate structure 222C in the first direction. Thus, after the gate dielectric intermediate structure 221C and the conductive material intermediate structure 222C are formed, the groove between adjacent active pillars 21 in the second direction can be filled by the gate dielectric intermediate structure 221C and the conductive material intermediate structure 222C. In this way, an isolation structure 23A may not be formed between adjacent active pillars 21 in the second direction (e.g., the Y direction), for example... Figure 15 As shown in the image.

[0158] In step S300, please refer to Figure 16 The bit line BL is bonded to the corresponding drive pad 11.

[0159] Here, it can be understood that aligning and fastening the side of the second substrate 2 where the bit line BL is formed with the side of the first substrate 1 where the drive pad 11 is formed can achieve alignment and bonding between the bit line BL and the drive pad 11. This disclosure does not limit the number or position of the drive pads 11 bonded to the same bit line BL. Figure 16 The bonding shown is only used to express that there is a bonding relationship between the bit line BL and the drive pad 11, and is not a limitation on the bonding position between the bit line BL and the drive pad 11.

[0160] In step S400, please refer to Figure 16 and Figure 17 The second substrate 2 is thinned from the side of the second substrate 2 away from the first substrate 1 until the active pillar 21 is exposed.

[0161] Optionally, a chemical mechanical polishing (CMP) process can be used to polish the surface of the second substrate 2 away from the first substrate 1 until the surface of the sacrificial layer 3 away from the word line intermediate structure 22 is exposed, for example... Figure 17 As shown in the diagram, the sacrificial layer 3 can serve as a polishing barrier layer for thinning the second substrate 2.

[0162] In step S450, please refer to Figure 17 and Figure 18 Remove the sacrificial layer 3 and part of the word line intermediate structure 22 to form word lines WL and isolation parts 23 located between adjacent word lines WL.

[0163] In some examples, the removal of the sacrificial layer 3 and part of the word line intermediate structure 22 can be achieved using either wet etching or dry etching processes.

[0164] In some embodiments, the removed portion of the word line intermediate structure 22 is the word line intermediate structure 22 located between the sacrificial layer 3 and the isolation structure 23A in a first direction (e.g., the X direction). Removing the portion of the word line intermediate structure 22 includes: etching the word line intermediate structure 22 along a direction perpendicular to the first substrate 1 (e.g., the Z direction) to disconnect the conductive material layer (i.e., the partial conductive material intermediate structure 222C) between adjacent active pillars 21 in the first direction (e.g., the X direction), and allowing the conductive material layer (i.e., the conductive layer 222 formed after patterning the conductive material intermediate structure 222C) connected in a second direction (e.g., the Y direction) to be used to form the word line WL.

[0165] Here, the word line WL also includes the gate dielectric layer 221 formed after the patterned gate dielectric intermediate structure 221C.

[0166] Furthermore, in some examples, an isolation structure 23A is also formed in the interval between adjacent active pillars 21 along the second direction (e.g., the Y direction), so that the removal of the word line intermediate structure 22 can also be achieved by the following steps.

[0167] A mask layer is formed on the surface of the sacrificial layer 3 and the active pillar 21. Figure 17 (Not shown in the image), the mask layer extends along a second direction (e.g., the Y direction) to expose the sacrificial layer 3 located between adjacent active pillars 21 in a first direction (e.g., the X direction).

[0168] The exposed sacrificial layer 3 is etched to expose the word line intermediate structure 22 located between adjacent active pillars 21 in a first direction (e.g., the X direction).

[0169] The exposed word line intermediate structure 22 is etched to expose the isolation structure 23A, thereby breaking the conductive material layer (i.e., the partially conductive material intermediate structure 222C) between adjacent active pillars 21 in a first direction (e.g., the X direction).

[0170] To ensure that the conductive material layer between adjacent active pillars 21 is completely disconnected in the first direction (e.g., the X direction), after etching the word line intermediate structure 22 in contact with the isolation structure 23A, the remaining isolation structure 23A and the remaining word line intermediate structure 22 located on the sidewall of the active pillar 21 can be etched downwards to achieve complete removal of the word line intermediate structure 22 located between the sacrificial layer 3 and the isolation structure 23A in the first direction (e.g., the X direction).

[0171] Remove the mask layer and the remaining sacrificial layer 3 so that the remaining word line intermediate structure on the side wall of the active pillar 21 forms the word line WL, and the remaining isolation structure forms the isolation part 23.

[0172] Please see Figure 19 After performing step S450 to form the word line WL, and before performing step S500 to form the storage capacitor C on the side of the active pillar 21 away from the driving pad 11, the fabrication method further includes: forming a third dielectric layer 26, the third dielectric layer 26 covering the word line WL and part of the sidewall of the active pillar 21; forming a fourth dielectric layer 27, the fourth dielectric layer 27 covering the third dielectric layer 26 and the remaining sidewall of the active pillar 21, the surface of the fourth dielectric layer 27 away from the first substrate 1 being flush with the surface of the active pillar 21 away from the first substrate 1.

[0173] For example, the third dielectric layer 26 may be formed using a nitride, such as silicon nitride.

[0174] For example, the fourth dielectric layer 27 can be formed of an oxide, such as silicon oxide.

[0175] In step S500, please refer to Figure 20 A storage capacitor C is formed on the side of the active post 21 that is away from the drive pad 11.

[0176] The present disclosure does not limit the structure of the storage capacitor C. For example, the storage capacitor C can be a columnar capacitor, a cup-shaped capacitor, or other capacitors that can be stacked in a direction perpendicular to the first substrate 1.

[0177] For example, before forming the storage capacitor C, the surfaces of the active pillar 21 and the fourth dielectric layer 27 facing away from the first substrate 1 can be ground to ensure that the storage capacitor C can have a good contact interface with the active pillar 21, thereby ensuring the electrical performance of the semiconductor structure. That is, the storage capacitor C can be formed directly on the surface of the active pillar 21 to achieve the connection between the storage capacitor C and the active pillar 21.

[0178] Alternatively, a storage node contact structure may be provided between the active post 21 and the storage capacitor C.

[0179] In another aspect, some embodiments of this disclosure provide a semiconductor structure obtained by the semiconductor structure preparation method described in the above embodiments.

[0180] Please see Figure 20 and Figure 21 The semiconductor structure includes a first substrate 1 and a memory device N. A drive pad 11 is provided on the first substrate 1, and the memory device N is bonded to the side of the drive pad 11 facing away from the first substrate 1. The memory device N includes an active pillar 21, and bit lines BL and storage capacitors C located at opposite ends of the active pillar 21. The surface of the bit line BL facing away from the first substrate 1 is connected to the end of the active pillar 21 closest to the first substrate 1, the storage capacitor C is connected to the end of the active pillar 21 facing away from the bit line BL, and the surface of the bit line BL closest to the first substrate 1 is bonded to the drive pad 11.

[0181] Here, in conjunction with the preparation methods in some of the foregoing embodiments, it can be seen that the active pillar 21 can be formed on the second substrate 2 first, and then bonded to the bit line BL and the driving pad 11. The second substrate 2 is thinned to remove other parts of the second substrate 2 except for the active pillar 21. This also facilitates the etching process of the word line WL and the preparation process of the storage capacitor C from the side of the second substrate 2 away from the first substrate 1.

[0182] In some embodiments, please continue reading Figure 20 and Figure 21The storage device N further includes a word line WL disposed on the sidewall of the active pillar 21. The bit line BL extends along a first direction (e.g., the X direction), and the word line WL extends along a second direction (e.g., the Y direction), the first and second directions intersecting, for example, perpendicularly. Furthermore, the word line WL is formed after the bit line BL is bonded to the drive pad 11 and before the storage capacitor C is formed.

[0183] In some embodiments, such as Figure 20 As shown, the storage device N also includes an isolation section 23 located between adjacent word lines WL.

[0184] The manufacturing process of the word line WL and the isolation part 23 can be referred to in some of the aforementioned embodiments, and will not be described in detail here.

[0185] In addition, for example, please continue to refer to Figure 20 The memory device N also includes a first dielectric layer 24 disposed between the bit line BL and the word line WL for isolating the bit line BL and the word line WL. The first dielectric layer 24 is, for example, a nitride layer, such as a silicon nitride layer.

[0186] For example, the memory device N further includes a second dielectric layer (not shown) disposed between adjacent bit lines BL to isolate adjacent bit lines BL. The second dielectric layer is, for example, an oxide layer, such as a silicon oxide layer.

[0187] For example, please continue reading Figure 20 The memory device N further includes a third dielectric layer 26 and a fourth dielectric layer 27 stacked on the side of the word line WL opposite to the first substrate 1. The third dielectric layer 26 is, for example, a nitride layer, such as a silicon nitride layer. The fourth dielectric layer 27 is, for example, an oxide layer, such as a silicon oxide layer.

[0188] Optionally, the surface of the fourth dielectric layer 27 facing away from the first substrate 1 is flush with the surface of the active pillar 21 facing away from the first substrate 1. This can be formed by a polishing process to ensure that the storage capacitor C formed subsequently can have a good contact interface with the active pillar 21.

[0189] In some embodiments, please continue reading Figure 20 and Figure 21 There are multiple active pillars 21, and the multiple active pillars 21 are arranged in an array.

[0190] Here, multiple active columns 21 are arranged in an array, arranged in rows along a first direction (e.g., the X direction) and in columns along a second direction (e.g., the Y direction). Optionally, the spacing between the active columns 21 arranged in rows in the first direction (e.g., the X direction) may be different from the spacing between the active columns 21 arranged in columns in the second direction (e.g., the Y direction).

[0191] For example, the dimension of the distance between adjacent active posts 21 in the first direction (e.g., the X direction) is the first dimension L1, and the dimension of the distance between adjacent active posts 21 in the second direction (e.g., the Y direction) is the second dimension L2; the first dimension L1 is greater than three times the second dimension L2, and the second dimension L2 is less than or equal to two or three times the thickness B of the word line WL in the first direction.

[0192] Furthermore, in some embodiments, the word line WL includes a gate dielectric layer 221 and a conductive layer 222 disposed on the sidewall of the active post 21 in a direction away from the active post 21; wherein the second dimension L2 is less than or equal to three times the thickness T of the conductive layer 222 in the first direction (e.g., the X direction).

[0193] It is understood that the word line WL extends along the second direction (e.g., the Y direction). In the aforementioned example where the first dimension L1 is greater than three times the second dimension L2, and the second dimension L2 is less than or equal to two or three times the thickness B of the word line WL in the first direction (e.g., the X direction), or the second dimension L2 is less than or equal to three times the thickness T of the conductive layer 222 in the first direction (e.g., the X direction), when a conductive material layer is deposited between adjacent active pillars 21 along the second direction (e.g., the Y direction), the conductive material layers located on the sidewalls of the adjacent active pillars 21 can be directly connected to simplify the formation process of the word line WL.

[0194] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0195] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0196] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first substrate is provided, and driving pads are formed on the first substrate; A second substrate is provided, on one side of which an active pillar and a bit line are sequentially formed; wherein, one side of the bit line is connected to the active pillar, and the surface of the bit line facing away from the active pillar is exposed on the surface of the second substrate; Bond the bit lines to the corresponding drive pads; The second substrate is thinned from the side opposite to the first substrate until the active pillar is exposed; A storage capacitor is formed on the side of the active post away from the drive pad, and the storage capacitor is connected to the active post. After forming the active pillar and before forming the bit line, the fabrication method further includes: forming a word line material layer on the sidewall of the active pillar; After thinning the second substrate to expose the active pillar, and before forming a storage capacitor on the side of the active pillar away from the drive pad, the fabrication method further includes: etching the word line material layer to form word lines; The bit line extends along a first direction, the word line extends along a second direction, and the first direction and the second direction intersect.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the active pillars on one side of the second substrate includes: patterning the second substrate to form a plurality of the active pillars arranged in an array; Wherein, the distance between adjacent active columns in the first direction is a first dimension, and the distance between adjacent active columns in the second direction is a second dimension; the first dimension is greater than three times the second dimension, and the second dimension is less than or equal to two or three times the thickness of the word line in the first direction.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming a word line material layer on the sidewall of the active pillar, the fabrication method further includes: forming a sacrificial layer on the surface of the second substrate, the sacrificial layer covering a portion of the sidewall of the active pillar and the surface of the second substrate between adjacent active pillars; Forming a word line material layer on the sidewall of the active post includes: sequentially forming a gate dielectric material layer and a conductive material layer on the exposed surface of the active post; wherein the gate dielectric material layer covers the exposed sidewall of the active post, and the conductive material layer covers the gate dielectric material layer and the sacrificial layer; the gate dielectric material layer and the conductive material layer together constitute the word line material layer; After forming a word line material layer on the sidewall of the active pillar, the preparation method further includes: forming an isolation material layer that covers the conductive material layer and fills the groove between adjacent active pillars.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, Before forming the bit line, the fabrication method further includes: The isolation material layer and the word line material layer are etched along a direction perpendicular to the second substrate to form an isolation structure and a word line intermediate structure, and to expose part of the sidewall of the active pillar; A first dielectric layer is formed, which covers the isolation structure, the word line intermediate structure, and part of the sidewall of the active pillar. A second dielectric layer extending along the first direction is formed between adjacent active columns arranged in the second direction, the second dielectric layer covering a portion of the first dielectric layer and a portion of the sidewall of the active column.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, Forming the bit line includes: A metal layer is formed on the surface of a groove between adjacent active pillars arranged in the first direction, the metal layer covering the active pillars and the sidewalls of the second dielectric layer exposed in the groove; Heat treatment is performed on the metal layer and the active pillars covered by the metal layer to form the bit line connected to the active pillars.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that, Thinning the second substrate from the side of the second substrate away from the first substrate until the active pillar is exposed further includes: exposing the surface of the sacrificial layer away from the word line intermediate structure; The preparation method further includes: removing the sacrificial layer and part of the word line intermediate structure to form the word line and the isolation portion located between adjacent word lines.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, Removing part of the middle structure of the character lines, including: The word line intermediate structure is etched along a direction perpendicular to the first substrate to disconnect the conductive material layer between adjacent active pillars in the first direction, and to make the conductive material layers connected in the second direction constitute the word line.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the word line is formed, and before the storage capacitor is formed on the side of the active pillar opposite to the drive pad, the fabrication method further includes: A third dielectric layer is formed, which covers the word line and part of the sidewall of the active pillar; A fourth dielectric layer is formed, which covers the third dielectric layer and the remaining sidewalls of the active pillar, and the surface of the fourth dielectric layer facing away from the first substrate is flush with the surface of the active pillar facing away from the first substrate.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, A storage capacitor is formed on the side of the active pillar opposite to the drive pad, and the method further includes: Grind the surfaces of the active pillar and the fourth dielectric layer that are away from the first substrate. The storage capacitor is formed on the surface of the active post.

10. A semiconductor structure, said semiconductor structure being prepared by the preparation method according to any one of claims 1-9, characterized in that, include: A first substrate, wherein a driving pad is provided on the first substrate; A storage device is bonded to the side of the drive pad opposite to the first substrate; The storage device includes: an active column, and bit lines and storage capacitors located at both ends of the active column; The surface of the bit line away from the first substrate is connected to the end of the active pillar near the first substrate, the storage capacitor is connected to the end of the active pillar away from the bit line, and the surface of the bit line near the first substrate is bonded to the drive pad. The storage device further includes: word lines disposed on the sidewall of the active column; The bit line extends along a first direction, and the word line extends along a second direction, the first direction and the second direction intersect; the word line is formed after the bit line is bonded to the drive pad and before the storage capacitor is formed.

11. The semiconductor structure according to claim 10, characterized in that, The storage device further includes an isolation portion located between adjacent word lines.

12. The semiconductor structure according to claim 10, characterized in that, The number of active pillars is multiple, and the multiple active pillars are arranged in an array; Wherein, the distance between adjacent active columns in the first direction is a first dimension, and the distance between adjacent active columns in the second direction is a second dimension; the first dimension is greater than three times the second dimension, and the second dimension is less than or equal to two or three times the thickness of the word line in the first direction.

13. The semiconductor structure according to claim 12, characterized in that, The word line includes a gate dielectric layer and a conductive layer disposed on the sidewall of the active post along a direction away from the active post; Wherein, the second dimension is less than or equal to three times the thickness of the conductive layer in the first direction.

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