Semiconductor structure and method of forming the same

Abstract

The semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, wherein the package includes: an interposer, wherein a first side of the interposer is bonded to the first surface of the substrate via a first conductive bump; a die attached to a second side of the interposer opposite to the first side; and a molding material located on the second side of the interposer surrounding the die; a plurality of thermal interface material (TIM) films located on the first surface of the package remote from the substrate, wherein each of the TIM films is directly disposed above at least one corresponding die in the die; and a heat sink attached to the first surface of the substrate, wherein the package and the plurality of TIM films are disposed in an enclosed space between the heat sink and the substrate, wherein the heat sink contacts the plurality of TIM films. Embodiments of this application also relate to methods of forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this increase in integration density comes from the repeated reduction in the size of the smallest component, which allows more components to be integrated into a given area.

[0003] With the growing demand for miniaturized electronic devices, there is a need for smaller and more innovative packaging technologies for semiconductor dies. One example of such a packaging system is the PoP (PoS) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is the chip-on-wafer (CoWoS) structure, where a semiconductor chip is attached to a wafer (e.g., an interposer) to form a chip-on-wafer (CoW) structure. The CoW structure is then attached to a substrate (e.g., a printed circuit board) to form a CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with enhanced functionality and small coverage areas. Summary of the Invention

[0004] Some embodiments of this application provide a semiconductor structure including: a substrate; a package attached to a first surface of the substrate, wherein the package includes: an interposer, wherein a first side of the interposer is bonded to the first surface of the substrate via a first conductive bump; a plurality of dies attached to a second side of the interposer opposite to the first side; and a molding material located on the second side of the interposer surrounding the plurality of dies; a plurality of thermal interface material (TIM) films located on a first surface of the package remote from the substrate, wherein each of the thermal interface material films is directly disposed above at least one corresponding die among the plurality of dies; and a heat sink attached to the first surface of the substrate, wherein the package and the plurality of thermal interface material films are disposed in an enclosed gap between the heat sink and the substrate, wherein the heat sink contacts the plurality of thermal interface material films.

[0005] Other embodiments of this application provide a semiconductor structure including: a substrate; a first die, a second die, and a third die attached to a first side of the substrate, wherein the second die and the third die are laterally disposed on opposite sides of the first die; a molding material located on the first side of the substrate, wherein the first die, the second die, and the third die are embedded in the molding material; a heat sink attached to the first side of the substrate, wherein the first die, the second die, and the third die are located in a closed gap between the heat sink and the substrate; and a thermal interface material (TIM) film located between the heat sink and the first die, the second die, and the third die, wherein the thermal interface material film includes a first thermal interface material film, a second thermal interface material film, and a third thermal interface material film respectively disposed above the first die, the second die, and the third die, wherein the thermal interface material films are laterally spaced apart from each other.

[0006] Some embodiments of this application provide a method for forming a semiconductor structure, the method comprising: attaching a first die, a second die, and a third die to a first surface of a substrate, wherein the second die and the third die are located on opposite sides of the first die; forming a molding material around the first die, the second die, and the third die; forming a first thermal interface material (TIM) film, a second thermal interface material film, and a third thermal interface material film on the first die, the second die, and the third die, respectively, wherein the first thermal interface material film, the second thermal interface material film, and the third thermal interface material film are spaced apart from each other; and attaching a heat sink to the first surface of the substrate to form a closed gap between the heat sink and the substrate, wherein the first die, the second die, the third die, the first thermal interface material film, the second thermal interface material film, and the third thermal interface material film are disposed in the closed gap, wherein the first thermal interface material film, the second thermal interface material film, and the third thermal interface material film are in contact with the heat sink. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment is shown.

[0009] Figure 1B An example is shown. Figure 1A A top view of a semiconductor device.

[0010] Figure 2 , Figure 3A , Figure 3B and Figures 4 to 6 Various views of a semiconductor device at different stages of manufacturing according to an embodiment are shown.

[0011] Figures 7 to 10 Various exemplary top views of semiconductor devices according to some embodiments are shown.

[0012] Figures 11 to 14 Various exemplary top views of semiconductor devices according to some embodiments are shown.

[0013] Figure 15 A flowchart of a method for forming a semiconductor structure is shown in some embodiments. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. Throughout the specification, unless otherwise stated, the same reference numerals in different figures indicate the same or similar components formed using the same or similar materials and by the same or similar methods. Furthermore, figures with the same reference numerals but different letters (e.g., Figure 3A and Figure 3B The diagram shows various views (e.g., cross-sectional views, top views) of the same structure at the same stage of the manufacturing process.

[0015] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] This paper discusses embodiments of the invention in the context of forming a chip-on-wafer (CoWoS) structure on a substrate having a thermal interface material (TIM) film. The principles of the invention can be applied to other structures or devices, such as integrated fan-out (InFO) packages or system-on-integrated circuit (SoIC) packages.

[0017] In some embodiments, a wafer-on-wafer (CoW) structure (which includes a plurality of dies bonded to an interposer and molding material around the dies) is attached to a substrate to form a substrate-on-wafer-on-slab (CoWoS) structure. Next, a plurality of pre-fabricated, sheet-type TIM films are laminated onto the dies, wherein each TIM film is directly above at least one of the dies, and the TIM films are laterally spaced from each other. Next, a heat sink is attached to the substrate above the CoW structure and the TIM films, wherein the TIM films contact the sink and the dies. By using multiple, smaller TIM films over the dies instead of a single, larger TIM film over all the dies, the likelihood of TIM film delamination in the peripheral regions of the CoW structure is avoided or reduced, which improves heat dissipation efficiency, reduces stress in the package, and improves the structural integrity of the formed device.

[0018] Figure 1A A cross-sectional view of a semiconductor device 100 according to an embodiment is shown. The semiconductor device 100 has a wafer-on-wafer (CoW) structure. Figure 1A As shown, semiconductor device 100 includes a wafer 150 (e.g., an interposer), one or more dies 111 (e.g., 111A and 111B) attached to the wafer 150, an underfill material 133 between the dies 111 and the wafer 150, and a molding material 135 above the wafer 150 and around the dies 111. Semiconductor device 100 is then attached to a substrate to form semiconductor device 200 having a chip-on-wafer (CoWoS) structure, details of which are described below.

[0019] To form the semiconductor device 100, one or more dies 111 (also referred to as semiconductor dies, chips, or integrated circuit (IC) dies) are attached to the upper surface of the wafer 150. In the illustrated embodiment, the wafer 150 is an interposer, and therefore, in the discussion herein, the wafer 150 may also be referred to as an interposer. It should be understood that other suitable types of wafers may also be used as wafer 150. In some embodiments, dies 111 (e.g., 111A and 111B) are dies of the same type (e.g., memory dies or logic dies). In other embodiments, dies 111 are of different types; for example, die 111A may be a logic die and die 111B may be a memory die. Figure 1AThe number and relative positions of the dies 111 are merely examples; other numbers and positions of dies are possible and are fully intended to be included within the scope of this invention.

[0020] In some embodiments, die 111A includes a substrate 111AS, electrical components (e.g., transistors, resistors, capacitors, diodes, etc.) formed in / on the substrate 111AS, and interconnect structures 112 above the substrate 111AS to form the functional circuitry of die 111A. Die 111A also includes conductive pads 102 and conductive posts 117 (also referred to as die connectors) formed on the conductive pads 102. The conductive posts 117 provide electrical connections to the circuitry of die 111A.

[0021] The substrate 111AS of die 111A can be an active layer of a semiconductor substrate (doped or undoped) or a silicon-on-insulator (SOI) substrate. Typically, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is provided on a substrate that is typically a silicon or glass substrate. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates. In some embodiments, the semiconductor material of the substrate may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0022] The electrical components of die 111A include a wide variety of active components (e.g., transistors) and passive components (e.g., capacitors, resistors, inductors), etc. The electrical components of die 111A can be formed within or on the substrate 111AS of die 111A using any suitable method. The interconnect structure 112 of die 111A includes one or more metallization layers (e.g., copper layers) formed in one or more dielectric layers and is used to connect the various electrical components to form a functional circuit. In embodiments, the interconnect structure is formed from alternating layers of dielectric and conductive materials (e.g., copper) and can be formed by any suitable process (e.g., deposition, damascene, double damascene).

[0023] One or more passivation layers (not shown) may be formed over the interconnect structure 112 of die 111A to provide a degree of protection for the structure beneath die 111A. The passivation layers may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silicon dioxide), combinations thereof, etc. The passivation layers may be formed using processes such as chemical vapor deposition (CVD), but any suitable process may be used.

[0024] Conductive pads 102 may be formed above the passivation layer, extending through the passivation layer to make electrical contact with the interconnect structure 112 of the die 111A. The conductive pads 102 may include aluminum, but other materials such as copper may be used.

[0025] Conductive posts 117 of die 111A are formed on conductive pad 102 to provide conductive areas for circuitry electrically connected to die 111A. Conductive posts 117 may be copper posts, contact bumps such as microbumps, and may include materials such as copper, tin, silver, combinations thereof, or other suitable materials.

[0026] Die 111B is formed using the same or similar processing steps, but different electrical components and different electrical connections can be formed, thus creating circuits with different functions for different dies. Details will not be repeated here.

[0027] Observe wafer 150, which includes substrate 123, via 121 (also known as substrate via (TSV)), redistribution structure 131, conductive pad 132 located on the upper surface of wafer 150, and external connector 125 (also known as conductive bump) located on the lower surface of wafer 150. Figure 1A The structure of wafer 150 shown is merely a non-limiting example. Other structures are possible and are fully intended to be included within the scope of this invention.

[0028] Substrate 123 may be, for example, an active layer of a silicon substrate (doped or undoped) or a silicon-on-insulator (SOI) substrate. However, substrate 123 may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnect functions.

[0029] In some embodiments, substrate 123 may include electrical components such as resistors, capacitors, signal distribution circuitry, combinations thereof, etc. These electrical components may be active, passive, or combinations thereof. In other embodiments, substrate 123 contains neither active nor passive electrical components. All such combinations are intended to be included within the scope of this invention.

[0030] A via 121 is formed in substrate 123, extending from the upper surface 123U to the lower surface 123L of substrate 123. The via 121 provides an electrical connection between conductive pad 132 and external connector 125. The via 121 can be formed of a suitable conductive material, such as copper, tungsten, aluminum, alloys, doped polysilicon, combinations thereof, etc. A barrier layer can be formed between the via 121 and substrate 123. The barrier layer can include suitable materials such as titanium nitride, but other materials such as tantalum nitride, titanium, etc., can also be used.

[0031] Once the via 121 has been formed, a redistribution structure 131 can be formed on the upper surface 123U of the substrate 123 to provide interconnectivity between the via 121, the external connector 125, and the dies 111A and 111B. The redistribution structure 131 includes conductive components (wires and / or vias) disposed in one or more dielectric layers within the redistribution structure 131. In some embodiments, the one or more dielectric layers are formed of polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layers are formed of: nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The one or more dielectric layers of the redistribution structure 131 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, combinations thereof, etc.

[0032] In some embodiments, the conductive components of the redistribution structure 131 include wires and / or conductive vias formed of suitable conductive materials such as copper, titanium, tungsten, aluminum, etc. The conductive components can be formed, for example, by forming openings in the dielectric layer of the redistribution structure to expose the underlying conductive components; forming a seed layer over the dielectric layer and in the openings; forming a patterned photoresist with a designed pattern over the seed layer; plating (e.g., electroplating or electroless plating) a conductive material in the designed pattern and over the seed layer; and removing portions of the photoresist and seed layer where no conductive material is formed. After the redistribution structure 131 is formed, conductive pads 132 can be formed over the redistribution structure 131 and electrically coupled to the redistribution structure 131 using any suitable material such as copper, aluminum, gold, tungsten, combinations thereof, etc.

[0033] Next, an external connector 125 is formed on the lower surface 123L of the substrate 123. The external connector 125 can be any suitable type of external contact, such as microbumps, copper pillars, copper layers, nickel layers, lead-free (LF) layers, electroless nickel plating, electroless palladium plating (ENEPIG) layers, Cu / LF layers, Sn / Ag layers, Sn / Pb layers, combinations thereof, etc.

[0034] like Figure 1A As shown, the conductive posts 117 of die 111 are bonded to the conductive pads 132 of wafer 150 via, for example, solder regions. A reflow process can be performed to bond die 111 to wafer 150.

[0035] After die 111 is bonded to wafer 150, an underfill material 133 is formed between die 111 and wafer 150. The underfill material 133 may, for example, comprise liquid epoxy resin, which is dispensed into the gap between die 111 and wafer 150, for example using a dispensing needle or other suitable dispensing tool, and then cured to harden. Figure 1A As shown, the bottom filler material 133 fills the gap between the die 111 and the wafer 150, and can also fill the gap between the sidewalls of the die 111.

[0036] Next, a molding material 135 is formed over wafer 150 and around die 111. The molding material 135 also surrounds underfill material 133. As an example, molding material 135 may include epoxy resin, organic polymer, polymer with or without added silica-based filler or glass filler, or other materials. In some embodiments, molding material 135 includes a liquid molding compound (LMC) that is a gel-like liquid when applied. Molding material 135 may also include liquid or solid components when applied. In some embodiments, molding material 135 may include other insulating and / or sealing materials. In some embodiments, molding material 135 is applied using a wafer-level molding process. Molding material 135 may be molded using, for example, compression molding, transfer molding, molded underfill (MUF), or other methods.

[0037] Next, in some embodiments, the molding material 135 is cured using a curing process. The curing process may include heating the molding material 135 to a predetermined temperature for a predetermined time period using an annealing process or other heating processes. The curing process may also include ultraviolet (UV) light exposure, infrared (IR) energy exposure, combinations thereof, or combinations thereof with heating processes. In some embodiments, the molding material 135 may be cured using other methods. In some embodiments, a curing process is not included.

[0038] After the molding material 135 is formed, planarization processes, such as chemical and mechanical planarization (CMP), can be performed to remove excess portions of the molding material 135 from above the die 111, thereby ensuring that the molding material 135 and the die 111 have coplanar upper surfaces. Figure 1A As shown, the molding material 135 is connected to the substrate 123 of the wafer 150, such that the sidewalls of the molding material 135 are perpendicularly aligned with the corresponding sidewalls of the wafer 150.

[0039] Figure 1B Examples are shown Figure 1A A top view of the semiconductor device 100. Figure 1A It shows along Figure 1B The image shows a cross-sectional view of semiconductor device 100 at section AA. For simplicity, Figure 1B Not all components are shown. For example, Figure 1B The bottom filler material 133 is not shown in the diagram. (Example) Figure 1B As shown in the top view, die 111A is located in the central region of semiconductor device 100. A plurality of dies 111B smaller than die 111A are located in the peripheral region of semiconductor device 100 on the opposite side of die 111A. Figure 1B The molding material 135 surrounding the dies 111A and 111B is also shown.

[0040] Figure 2 , Figure 3A , Figure 3B and Figures 4 to 6 Various views of a semiconductor device 200 at different stages of manufacturing according to an embodiment are shown. Figure 2 As shown, Figure 1A The semiconductor device 100 is bonded to the upper surface of the substrate 209 (e.g., a printed circuit board) to form a semiconductor device 200 having a chip-on-wafer (CoWoS) structure. Figure 2 A passive component 211 attached to the upper surface of substrate 209 is also shown.

[0041] In some embodiments, substrate 209 is a multilayer circuit board, such as a printed circuit board (PCB). For example, substrate 209 may include one or more dielectric layers 201 formed of bismaleimide triazine (BT) resin, FR-4 (a composite material composed of glass fiber woven fabric and flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other support materials. Substrate 209 may include conductive components (e.g., wires 202 and vias 204) formed in / on substrate 209. Figure 2 As shown, solder resist layers 208 are formed on the upper and lower surfaces of substrate 209. In addition, substrate 209 has conductive pads 203 formed on the upper surface of substrate 209 and conductive pads 205 formed on the lower surface of substrate 209, which are electrically coupled to conductive components of substrate 209.

[0042] exist Figure 2 In this process, semiconductor device 100 is bonded to conductive pads 203 of substrate 209. A reflow process can be performed to electrically and mechanically couple external connectors 125 of semiconductor device 100 to conductive pads 203 of substrate 209. Underfill material 137 is formed to fill the gap between semiconductor device 100 and substrate 209. Underfill material 137 may be the same as or similar to underfill material 133, so details are not repeated here.

[0043] Figure 2A passive component 211, attached to the upper surface of the substrate 209 adjacent to the semiconductor device 100, is also shown. The passive component 211 may be, for example, a discrete component, such as a capacitor, inductor, resistor, etc. The contact terminals of the passive component 211 are bonded to conductive pads 203. In some embodiments, the passive component 211 is attached to the substrate 209 before the semiconductor device 100 is attached to the substrate 209. In other embodiments, the passive component 211 is attached to the substrate 209 after the semiconductor device 100 is attached to the substrate 209.

[0044] Next step, refer to Figure 3A Multiple thermal interface material (TIM) films 141 are placed (e.g., laminated) on the upper surface of the die 111. The TIM films 141 are pre-formed before being placed on the die 111. For example, each of the TIM films 141 is pre-formed into a sheet (e.g., in the form of a sheet of paper) before being placed on the die 111. Therefore, the TIM film 141 is also referred to as a sheet-type TIM film.

[0045] The TIM film 141 is formed from a suitable material with high thermal conductivity. For example, the TIM film 141 may be a graphene film. As an example, the thickness of the TIM film 141 may be in the range of about 0.1 mm and about 0.2 mm. In some embodiments, the thermal conductivity of the TIM film 141 is between about 10 W / (m·K) and about 15 W / (m·K). It should be noted that although the TIM film 141 is shown as a single layer in the figure, the TIM film 141 may comprise multiple sublayers laminated together. In some embodiments, multiple TIM films 141 may be stacked together over the die 111 to achieve the desired total thickness.

[0046] In some embodiments, the TIM film 141 is formed of a dielectric material of a mixture of carbon and a polymer, wherein the polymer may be, for example, a resin-based polymer or an acrylic-based polymer. In some embodiments, the weight percentage of carbon in the material of the TIM film 141 is between about 40% and about 90%. In some embodiments, the thermal conductivity of the TIM film 141 comprising carbon and a polymer is between about 20 W / (m·K) and about 80 W / (m·K), such as 23 W / (m·K). The range of carbon weight percentages disclosed above can be adjusted according to the physical properties and performance requirements of the TIM film 141. For example, if the carbon percentage is below about 40%, the thermal conductivity of the TIM film 141 may be too low. Conversely, if the carbon percentage is above about 90%, the elasticity and / or tackiness of the TIM film 141 may be too low.

[0047] Still referencing Figure 3A After placing the TIM film 141 on the die 111, by, for example along Figure 3AArrow 149 indicates that the roller 147 rolls on the TIM film 141, pressing the TIM film 141 against the upper surface of the die 111. The compression by the roller 147 ensures close contact between the TIM film 141 and the upper surface of the die 111, eliminating gaps (e.g., air bubbles) between them. This maximizes the contact area between the TIM film 141 and the die 111, improving the efficiency of heat transfer (e.g., heat dissipation) from the die 111 to the TIM film 141. In some embodiments, the step of pressing the TIM film 141 using the roller 147 is omitted.

[0048] Figure 3B It shows Figure 3A A top view of the semiconductor device 200. It should be noted that, for simplicity, not all components of the semiconductor device 200 are shown. For example, the substrate 209 and passive component 211 are not shown. Figure 3B In the diagram, dies 111 (e.g., 111A and 111B) are shown in dashed lines, and molding material 135 surrounds dies 111. Figure 3B In this example, each TIM membrane 141 completely covers the upper surface of the underlying die 111 (e.g., 111A or 111B). In other words, in Figure 3B In this example, the number of TIM films 141 is equal to the number of dies 111, and each TIM film 141 is located directly above the corresponding die 111 (e.g., directly above and in physical contact).

[0049] exist Figure 3B In the illustrated example, each TIM membrane 141 has the same shape (e.g., rectangular or square) as the underlying core 111, and the dimensions (e.g., width and height) of each TIM membrane 141 are larger than the dimensions of the underlying core 111, such that the TIM membrane 141 extends beyond the boundary (e.g., sidewall) of the underlying core 111 and contacts the molding material 135 (and / or the bottom fill material 133). In other embodiments, the dimensions of each TIM membrane 141 are the same as the underlying core 111, such that in a top view, the boundary (e.g., sidewall) of the TIM membrane 141 completely overlaps (e.g., is the same as) the boundary of the underlying core 111. Therefore, in Figure 3BIn the examples, each of the TIM membranes 141 has a shape geometrically similar to the underlying die 111. It should be noted that the term "geometrically similar" is used to include embodiments in which the shape of the TIM membrane 141 is the same as and has the same dimensions as the underlying die 111, as well as embodiments in which the shape of the TIM membrane 141 is a scaled (e.g., enlarged) version of the shape of the underlying die 111. The drawings for the various embodiments of the invention show each of the TIM membranes 141 as having a larger dimension than the underlying die 111; it should be understood that in some embodiments, the TIM membrane 141 may have the same dimensions as the underlying die 111.

[0050] Still referencing Figure 3B The TIM films 141 are separated from each other (e.g., spaced apart). For example, Figure 3B It is shown that there is a gap of size d2 or d3 between adjacent TIM films 141, where d2 and d3 are greater than zero. Figure 3B The distance d1 between the boundary (e.g., sidewall) of the molding material 135 and the corresponding boundary (e.g., sidewall) of the mandrel 111 is also shown, where d1 is greater than zero. In other words, in Figure 3B In the top view, the TIM film 141 is disposed within and spaced apart from the boundary of the molding material 135. In the exemplary embodiment, all TIM films 141 have the same thickness. Figure 3B The shape and number of TIM films 141 shown are merely non-limiting examples. Other shapes and / or numbers are possible and are fully intended to be included within the scope of this invention. For example, those discussed below... Figures 7 to 10 Additional embodiments are shown.

[0051] Using multiple pre-formed sheet-type TIM films on die 111 offers advantages over the reference method of depositing gel-type TIM material on die 111 or placing a single pre-formed TIM film on all dies 111. Details are discussed below.

[0052] Compared to reference methods that deposit gel-type TIM material on the upper surface of die 111, the method of the present invention offers several advantages. For example, gel-type TIM materials typically have low thermal conductivity, such as below 3 W / (m·K). In contrast, TIM film 141 has a much higher thermal conductivity (e.g., greater than 20 W / (m·K)) to improve heat dissipation. Gel-type TIM materials typically need to be stored at lower temperatures (e.g., -40°C), while sheet-type TIM film 141 can be stored at room temperature. To reduce voids (e.g., bubbles) between the cured gel-type TIM material and die 111, the gel-type TIM material may have to be deposited in a special pattern. Even with a special pattern, voids can still form in the cured gel-type TIM material. Conversely, no special pattern needs to be designed for sheet-type TIM film 141, and voids (e.g., bubbles) are formed using the embodiments disclosed herein.

[0053] Furthermore, the shape and size of the deposited gel-type TIM material are difficult to control, often resulting in low coverage of the die 111 (e.g., the ratio between the area of ​​the upper surface of the die 111 covered by TIM material and the area of ​​the upper surface of the die 111 without TIM material), because some areas of the upper surface of the die 111 may not have gel-type TIM material deposited. Therefore, after curing, the coverage using gel-type TIM material is relatively low, such as around 83%. In contrast, the TIM film 141 is pre-formed (e.g., in sheet form) and can be cut into any suitable shape and / or size and is easily laminated onto the upper surface of the die 111. Therefore, after curing, the TIM film 141 achieves a high coverage of greater than 90% for all dies 111, which in turn leads to improved heat dissipation of the die 111. Because the sheet-type TIM film is easily laminated onto the die 111, the manufacturing process yields significantly higher throughput than the process of depositing gel-type TIM material on the die 111.

[0054] The currently disclosed method offers additional advantages compared to the reference method, which laminates a single sheet-type TIM film on top of all dies 111. Semiconductor devices 100 (e.g., CoW structures) may warp during thermal cycling due to the different materials of the CoW structure with varying coefficients of thermal expansion (CTE). Warpage is generally worse for larger semiconductor packages and is exacerbated near the periphery of the semiconductor package (e.g., near the sidewalls). It has been observed that when a single, large sheet-type TIM film 141 is laminated on all dies 111, the peripheral portion of the single TIM film 141 experiences significant stress and may delaminate (e.g., separate from the upper surface of the die 111 below the peripheral portion), reducing the coverage of the die 111 and resulting in reduced heat dissipation efficiency. In contrast, the currently disclosed method uses multiple, smaller sheet-type TIM films 141 to be laminated onto the die 111. Due to the smaller size of each TIM film 141, the variation in the amount of warpage experienced across each TIM film 141 is smaller, and therefore, the smaller TIM film 141 is less likely to delaminate from the underlying die 111, thereby improving the coverage and heat dissipation efficiency of the die 111. Tests show that, with the use of multiple, smaller TIM films 141, 93% or better coverage of all dies 111 can be achieved after the TIM films 141 have cured. Furthermore, the smaller TIM films 141 do not increase the stress level in the semiconductor device 100 and do not increase the warpage of the semiconductor device 100.

[0055] Next step, in Figure 4 In this configuration, a heat dissipation cap 151 (also called a cover) is attached to the upper surface of the substrate 209 to form a closed gap between the heat dissipation cap 151 and the substrate 209. The cover 151 can be formed of a material suitable for heat dissipation, such as copper, aluminum, or steel. Figure 4 In this embodiment, the cover 151 has a top 151T and a sidewall portion 151S. The sidewall portion 151S is attached to the upper surface of the substrate 209 by, for example, adhesive 153. In one embodiment, the cover 151 is formed of a metallic material and is electrically isolated. In another embodiment, the cover 151 is formed of a metallic material and is electrically coupled to a conductive pad 203 configured to be connected to an electrically grounded location (e.g., via a solder area), in which case the cover 151 also serves as an electromagnetic interference (EMI) shield for the semiconductor device 100.

[0056] like Figure 4As shown, the semiconductor device 100, the TIM film 141, and the passive component 211 are disposed in an enclosed space between the cover 151 and the substrate 209. The TIM film 141 is disposed between the top 151T of the cover 151 and the upper surface of the die 111. Specifically, the upper surface of each TIM film 141 contacts (e.g., physically contacts) the top 151T, and the lower surface of each TIM film 141 contacts (e.g., physically contacts) the upper surface of the semiconductor device 100 (e.g., the upper surface of the die 111, the upper surface of the molding material 135, and / or the upper surface of the underfill material 133).

[0057] Next step, in Figure 5 In this process, the semiconductor device 200 is clamped between the top clamp 157 and the bottom clamp 159 of the clamp. A rubber pad 155 can be placed between the top clamp 157 and the cover 151 to prevent damage to the semiconductor device 200. Next, while clamped between the top clamp 157 and the bottom clamp 159, the semiconductor device 200 is heated to a predetermined temperature (e.g., between 25°C and 150°C) for a predetermined time period (e.g., less than 1000 hours). The heating process cures the TIM film 141.

[0058] Next step, in Figure 6 In the process, the semiconductor device 200 is removed from the fixture, and conductive bumps 207 are formed on the conductive pads 205 on the lower surface of the substrate 209. The conductive bumps 207 can be solder balls, copper pillars, combinations thereof, etc. Thus, the semiconductor device 100, the passive component 211, and the conductive bumps 207 are electrically interconnected through conductive parts (e.g., wires or vias) of the substrate 209.

[0059] Figure 7 A top view of a semiconductor device 200A according to an embodiment is shown. Semiconductor device 200A is similar to semiconductor device 200, but the number and shape of the TIM films 141 differ. For example, with Figure 3B Compared to the top view, Figure 7 A subset of the dies 111 of the semiconductor device 200A (e.g., dies 111A in the central region) is covered by a larger TIM film 141 (labeled 141A), and other subsets of the dies 111 of the semiconductor device 200 (e.g., every two adjacent dies 111B in the peripheral region) are covered by a smaller TIM film 141 (labeled 141B).

[0060] It should be pointed out that, in Figure 7In this design, dies 111 (e.g., 111A and 111B) are grouped into different subsets of dies, and each subset of dies 111 is covered by a corresponding TIM film 141 (e.g., 141A or 141B). The shape of each TIM film 141 (e.g., 141A or 141B) follows the contour of the corresponding subset of dies 111. Here, the term "contour" is used to describe the shape defined by the outer boundaries of the subset of dies 111. For example, the contour of the subset of dies 111A is a rectangular shape, wherein the four sides of the rectangular shape are defined by the outer walls of the subset of dies 111A that are away from the center of dies 111A. Figure 7 In one example, the size of each TIM membrane 141 is larger than the outline of the subset below the die 111, and therefore, the shape of each TIM membrane 141 is a scaled (e.g., enlarged) version of the outline of the subset below the die 111. In other embodiments, the size of each TIM membrane 141 is the same as the outline of the subset below the die 111, such that in a top view, the TIM membrane 141 completely overlaps with the outline of the subset below the die 111. Therefore, the shape of each TIM membrane 141 is a geometrically similar shape to the outline of the subset below the die 111.

[0061] Figure 7 The TIM films 141A and 141B are sheet-type TIM films and are formed of the same material as the TIM film 141 of the semiconductor device 200. Figure 7 The dimensions of TIM films 141A and 141B are larger than Figure 3B The size of the TIM film 141 is smaller than that of a single, large TIM film covering all the dies 111. Therefore, the advantages of lower stress, less delamination, and improved coverage of the dies 111 remain. Furthermore, due to… Figure 7 The reduced amount of TIM film 141 used can reduce the manufacturing time for laminating TIM film 141 onto die 111.

[0062] exist Figure 7In this embodiment, TIM films 141A and 141B have different shapes but are formed from the same material. In some embodiments, TIM films 141A and 141B have the same thickness, for example, because TIM films 141A and 141B are formed by cutting identical large, sheet-type TIM films into sheets having the shapes / sizes of TIM films 141A and 141B. In other embodiments, TIM films 141A and 141B have different thicknesses. In particular, TIM film 141B, located along the peripheral region of semiconductor device 200A, has a greater thickness than TIM film 141A located in the central region of semiconductor device 200A. For example, TIM film 141B may be 10% to 20% thicker than TIM film 141A. Because the warpage in the peripheral region of semiconductor device 200A is typically large, and because TIM film 141B is located in the peripheral region, its thickness is increased compared to TIM film 141A to compensate for the increased warpage in the peripheral region of the device. The thicker TIM film 141B can advantageously reduce TIM film delamination in the peripheral region and decrease stress on the package, thereby improving heat dissipation efficiency and the structural integrity of the formed device.

[0063] Figure 8 A top view of a semiconductor device 200B according to an embodiment is shown. Semiconductor device 200B is similar to semiconductor device 200A, but each subset of dies 111B includes four dies instead of... Figure 7 The two dies in the tube. It should be noted that, similar to... Figure 7 The TIM film 141A above the central region of the semiconductor device 200B may be thinner than the TIM film 141B above the peripheral region of the semiconductor device 200B. In some embodiments, the TIM films 141A and 141B have the same thickness.

[0064] Figure 9 A top view of a semiconductor device 200C according to an embodiment is shown. Semiconductor device 200C is similar to semiconductor device 200A, but some subsets of die 111B include two dies, while other subsets of die 111B may include only one die. It should be noted that, similar to... Figure 7 The TIM film 141A above the central region of the semiconductor device 200C may be thinner than the TIM film 141B above the peripheral region of the semiconductor device 200C. In some embodiments, the TIM films 141A and 141B have the same thickness.

[0065] Figure 10A top view of a semiconductor device 200D according to an embodiment is shown. Semiconductor device 200D is similar to semiconductor device 200, but may have only two subsets of dies, wherein each subset of dies includes dies 111 (e.g., 111A and 111B) located in half of the upper surface region of semiconductor device 200D. In some embodiments, Figure 10 The TIM film 141 has the same thickness.

[0066] Figure 11 A top view of a semiconductor device 200E according to an embodiment is shown. Semiconductor device 200E is similar to semiconductor device 200 (see...). Figure 3B However, each die 111B is covered by a TIM film 143, wherein the TIM film 143 is formed of a different material than the TIM film 141 disposed above the die 111A. In other words, the die 111A located in the central region of the semiconductor device 200E is covered by the TIM film 141, and the die 111B located in the peripheral region of the semiconductor device 200E is covered by the TIM film 143.

[0067] In an exemplary embodiment, the TIM film 141 and Figure 3B The TIM film 141 is the same as that in the die 111B, such as a pre-formed sheet-type TIM film, which is then laminated onto the die 111A. However, the TIM film 143 is formed by applying a gel-type TIM material onto the die 111B and then curing the gel-type TIM material. The gel-type TIM material can be, for example, an adhesive with a metal filler, such as a silicone gel with aluminum or zinc as a filler. In some embodiments, the TIM film 143 is thicker than the TIM film 141 to compensate for increased warpage in the peripheral region of the semiconductor package. The semiconductor device 200E may be referred to as a semiconductor package with a hybrid TIM film. The use of a gel-type TIM material in the peripheral region of the semiconductor package may be suitable for packages with greater warpage that cannot be well compensated for by using a sheet-type TIM film.

[0068] Figure 12 A top view of a semiconductor device 200F according to an embodiment is shown. The semiconductor device 200F is similar to... Figure 11 The semiconductor device 200E has different subsets of dies 111. Specifically, four dies 111A in the central region of the semiconductor device 200F are covered by a wafer-type TIM film 141. Each subset of dies 111B includes two dies 111B in the peripheral region, and the dies 111B in each subset are covered by a corresponding TIM film 143.

[0069] Figure 13 A top view of a semiconductor device 200G according to an embodiment is shown. The semiconductor device 200G is similar to... Figure 12 The semiconductor device 200F has a different number of dies 111. Specifically, four dies 111A in the central region of the semiconductor device 200G are covered by a wafer-type TIM film 141. Each subset of dies 111B includes four dies 111B in the peripheral region, and the dies 111B in each subset are covered by a corresponding TIM film 143.

[0070] Figure 14 A top view of a semiconductor device 200H according to an embodiment is shown. The semiconductor device 200H is similar to... Figure 12 The semiconductor device 200F has different numbers of dies 111 in subsets. Specifically, the four dies 111A in the central region of the semiconductor device 200H are covered by a wafer-type TIM film 141. The dies 111B in the peripheral region are grouped into different subsets, some of which include two dies 111B, while other subsets may include only one die 111B. The dies 111B in each subset are covered by a corresponding TIM film 143.

[0071] The embodiments offer advantages. Compared to gel-type TIM materials, using a sheet-type TIM film 141 allows for higher thermal conductivity, resulting in more efficient heat dissipation. The shape and thickness of the TIM film 141 can be easily controlled to achieve good coverage of more than 93% of the die 111 after the TIM film 141 has cured. Because the TIM film 141 is prefabricated, it is easily used in the manufacturing process to achieve higher yields than gel-type TIM materials. Compared to a single TIM film covering all dies 111, the disclosed method uses multiple TIM films covering a subset of each die, which allows for reduced stress in the package. Little or no TIM film delamination is observed, thereby increasing die coverage and improving heat dissipation efficiency. Furthermore, TIM film delamination is further reduced and device integrity is improved by using a thicker TIM film above the die in the peripheral region of the semiconductor package and / or using a different material for the TIM film.

[0072] Figure 15 A flowchart of a method 1000 for forming a semiconductor structure in some embodiments is shown. It should be understood that... Figure 15 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and alterations. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 15 The steps shown are as follows.

[0073] refer to Figure 15In frame 1010, a first die, a second die, and a third die are attached to a first surface of a substrate, wherein the second die and the third die are located on opposite sides of the first die. In frame 1020, a molding material is formed around the first die, the second die, and the third die. In frame 1030, a first thermal interface material (TIM) film, a second TIM film, and a third TIM film are formed on the first die, the second die, and the third die, respectively, wherein the first TIM film, the second TIM film, and the third TIM film are spaced apart from each other. In frame 1040, a heat sink is attached to the first surface of the substrate to form a closed gap between the heat sink and the substrate, wherein the first die, the second die, the third die, the first TIM film, the second TIM film, and the third TIM film are disposed in the closed gap, and wherein the first TIM film, the second TIM film, and the third TIM film are in contact with the heat sink.

[0074] According to an embodiment, the semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, wherein the package includes: an interposer, wherein a first side of the interposer is bonded to the first surface of the substrate via a first conductive bump; a plurality of dies attached to a second side of the interposer opposite to the first side; and a molding material located on the second side of the interposer surrounding the plurality of dies; a plurality of thermal interface material (TIM) films located on a first surface of the package remote from the substrate, wherein each of the TIM films is directly disposed over at least one corresponding die among the plurality of dies; and a heat sink attached to the first surface of the substrate, wherein the package and the plurality of TIM films are disposed in a closed gap between the heat sink and the substrate, wherein the heat sink contacts the plurality of TIM films. In an embodiment, the plurality of TIM films are laterally spaced from each other. In an embodiment, in a plan view, the molding material surrounds the plurality of dies, and the plurality of TIM films are disposed within and spaced from the boundary of the molding material. In an embodiment, the plurality of TIM films are graphene films. In an embodiment, each of the plurality of TIM films is disposed over a corresponding die among the plurality of dies and has a shape similar to the geometry of the corresponding die. In one embodiment, the plurality of dies includes a first subset of dies and a second subset of dies, wherein the plurality of TIM films include: a first TIM film disposed directly over the first subset of dies, wherein the first TIM film has a shape with a contour geometry similar to that of the first subset of dies; and a second TIM film disposed directly over the second subset of dies, wherein the second TIM film has a shape with a contour geometry similar to that of the second subset of dies. In another embodiment, in a top view, the plurality of dies includes: a first die located in a central region of a first surface of the package; and a second die located in a first peripheral region of the first surface of the package, wherein the plurality of TIM films includes a first TIM film disposed directly over the first die and a second TIM film disposed directly over the second die, wherein a first thickness of the first TIM film is less than a second thickness of the second TIM film. In another embodiment, the first TIM film and the second TIM film comprise different materials. In another embodiment, the first TIM film is a graphene film, and the second TIM film is an adhesive with a metal filler. In one embodiment, the plurality of dies further includes a third die located in a second peripheral region of a first surface of the package. The second and third dies are laterally disposed on opposite sides of the first die. The TIM film further includes a third TIM film located directly above the third die, wherein the third TIM film has a third thickness greater than the first TIM film. In another embodiment, the first and second TIM films are made of different materials, while the second and third TIM films are made of the same material.

[0075] According to an embodiment, the semiconductor structure includes: a substrate; a first die, a second die, and a third die attached to a first side of the substrate, wherein the second die and the third die are laterally disposed on opposite sides of the first die; a molding material located on the first side of the substrate, wherein the first die, the second die, and the third die are embedded in the molding material; a heat sink attached to the first side of the substrate, wherein the first die, the second die, and the third die are located in a closed gap between the heat sink and the substrate; and a thermal interface material (TIM) film located between the heat sink and the first die, the second die, and the third die, wherein the TIM film includes a first TIM film, a second TIM film, and a third TIM film respectively disposed above the first die, the second die, and the third die, wherein the TIM films are laterally spaced from each other. In an embodiment, each TIM film has a shape similar to the geometry of the die below. In one embodiment, the semiconductor structure further includes a fourth die attached to a first side of the substrate, wherein the second die and the fourth die are located on the same side of the first die, wherein a first TIM film covers the first die and has a first geometry similar to the first die, and wherein a second TIM film covers the second die and the fourth die and has a second geometry similar to the outlines of the second die and the fourth die. In one embodiment, the first thickness of the first TIM film is less than the second thickness of the second TIM film and less than the third thickness of the third TIM film. In one embodiment, the second thickness and the third thickness are the same. In one embodiment, the first TIM film is formed of a first material, wherein the second TIM film and the third TIM film are formed of a second material different from the first material.

[0076] According to an embodiment, a method for forming a semiconductor structure includes: attaching a first die, a second die, and a third die to a first surface of a substrate, wherein the second die and the third die are located on opposite sides of the first die; forming a molding material around the first die, the second die, and the third die; forming a first thermal interface material (TIM) film, a second TIM film, and a third TIM film on the first die, the second die, and the third die, respectively, wherein the first TIM film, the second TIM film, and the third TIM film are spaced apart from each other; and attaching a heat sink to the first surface of the substrate to form a closed gap between the heat sink and the substrate, wherein the first die, the second die, the third die, the first TIM film, the second TIM film, and the third TIM film are disposed in the closed gap, and wherein the first TIM film, the second TIM film, and the third TIM film are in contact with the heat sink. In one embodiment, forming the first TIM film, the second TIM film, and the third TIM film includes placing a first pre-formed TIM sheet, a second pre-formed TIM sheet, and a third pre-formed TIM sheet onto a first die, a second die, and a third die, respectively, wherein the second and third pre-formed TIM sheets are thicker than the first pre-formed TIM sheet. In another embodiment, forming the first, second, and third TIM films includes: placing pre-formed sheet-type TIM onto the first die; and dispensing gel-type TIM onto the second and third dies, wherein the pre-formed sheet-type TIM and the gel-type TIM comprise different materials.

Claims

1. A semiconductor structure, comprising: Substrate; A package, attached to a first surface of the substrate, wherein the package includes: An interposer layer, wherein a first side of the interposer layer is bonded to the first surface of the substrate via a first conductive bump; A plurality of dies are attached to a second side of the interposer opposite to the first side, wherein, in a top view, the plurality of dies includes a first die located in a central region of the first surface of the package and a second die located in a first peripheral region of the first surface of the package; and Molding material is located on the second side of the intermediate layer surrounding the plurality of dies; Multiple thermal interface material (TIM) films are located on a first surface of the package remote from the substrate, wherein each of the TIM films is directly disposed above at least one of the plurality of dies, wherein the plurality of TIM films includes a first TIM film directly above the first die and a second TIM film directly above a second die, the first TIM film being formed of a pre-formed sheet-type TIM material, the second TIM film being formed of a gel-type TIM material, the first thickness of the pre-formed sheet-type TIM material being less than the second thickness of the gel-type TIM material, and wherein the pre-formed sheet-type TIM material is graphene, and the gel-type TIM material is an adhesive having a metal filler; and A heat sink is attached to the first surface of the substrate, wherein the package and the plurality of thermal interface material films are disposed in a closed gap between the heat sink and the substrate, wherein the heat sink contacts the plurality of thermal interface material films.

2. The semiconductor structure of claim 1, wherein, The plurality of thermal interface material films are spaced laterally apart from each other.

3. The semiconductor structure of claim 2, wherein, In the plan view, the molding material surrounds the plurality of dies, and the plurality of thermal interface material films are disposed within the boundary of the molding material and spaced apart from the boundary of the molding material.

4. The semiconductor structure according to claim 1, wherein, In the top view, the area of ​​the first thermal interface material film is larger than the area of ​​the second thermal interface material film.

5. The semiconductor structure according to claim 1, wherein, Each of the plurality of thermal interface material films is disposed above a corresponding die in the plurality of dies and has a shape similar to the geometry of the corresponding die.

6. The semiconductor structure according to claim 1, wherein, The plurality of dies includes a first subset of dies and a second subset of dies, wherein the plurality of thermal interface material films include: A first thermal interface material film is disposed directly above the first subset of the die, wherein the first thermal interface material film has a shape geometrically similar to the contour of the first subset of the die; and A second thermal interface material film is disposed directly above the second subset of the die, wherein the second thermal interface material film has a shape that is geometrically similar to the profile of the second subset of the die.

7. The semiconductor structure according to claim 1, wherein, In the top view, both the first die and the first thermal interface material film are rectangular in shape.

8. The semiconductor structure according to claim 1, wherein, The heat sink is made of metal.

9. The semiconductor structure according to claim 7, wherein, The plurality of dies includes logic dies and memory dies.

10. The semiconductor structure according to claim 1, wherein, The plurality of dies also includes a third die located in a second peripheral region of the first surface of the package, the second die and the third die being laterally disposed on opposite sides of the first die, wherein the thermal interface material film also includes a third thermal interface material film located directly above the third die, wherein the third thickness of the third thermal interface material film is greater than the first thickness of the first thermal interface material film.

11. The semiconductor structure according to claim 10, wherein, The second thermal interface material film and the third thermal interface material film are made of the same material.

12. A semiconductor structure, comprising: Substrate; A first die, a second die, and a third die are attached to a first side of the substrate, wherein the second die and the third die are laterally disposed on opposite sides of the first die; A molding material is located on the first side of the substrate, wherein the first die, the second die, and the third die are embedded in the molding material; A heat sink is attached to the first side of the substrate, wherein the first die, the second die, and the third die are located in a closed gap between the heat sink and the substrate; and A thermal interface material (TIM) film is located between the heat sink and the first die, the second die, and the third die. The TIM film includes a first TIM film, a second TIM film, and a third TIM film respectively disposed above the first die, the second die, and the third die. The TIM films are laterally spaced from each other. The first TIM film is formed of a pre-formed sheet-type thermal interface material, and the second and third TIM films are respectively formed of a gel-type thermal interface material. The first thickness of the pre-formed sheet-type thermal interface material is less than the second thickness of the gel-type thermal interface material. The pre-formed sheet-type thermal interface material is graphene, and the gel-type thermal interface material is an adhesive with metal fillers.

13. The semiconductor structure according to claim 12, wherein, Each of the thermal interface material films has a shape similar to the underlying die geometry.

14. The semiconductor structure of claim 12, further comprising a fourth die attached to the first side of the substrate, wherein, The second die and the fourth die are located on the same side of the first die, wherein the first thermal interface material film covers the first die and has a first geometry similar to the first die, and wherein the second thermal interface material film covers the second die and the fourth die and has a second geometry similar to the outline of the second die and the fourth die.

15. The semiconductor structure according to claim 12, wherein, In the top view, both the first die and the first thermal interface material film are rectangular in shape.

16. The semiconductor structure according to claim 12, wherein, The heat sink is made of metal.

17. The semiconductor structure according to claim 12, wherein, The first die is a logic die or a memory die.

18. A method for forming a semiconductor structure, the method comprising: A first die, a second die, and a third die are attached to a first surface of a substrate, wherein the second die and the third die are located on opposite sides of the first die; A molding material is formed around the first die, the second die, and the third die; A first thermal interface material (TIM) film, a second thermal interface material film, and a third thermal interface material film are formed on the first die, the second die, and the third die, respectively. The first, second, and third thermal interface material films are spaced apart from each other. The first thermal interface material film is formed of a pre-formed sheet-type thermal interface material, and the second and third thermal interface material films are each formed of a gel-type thermal interface material. The first thickness of the pre-formed sheet-type thermal interface material is less than the second thickness of the gel-type thermal interface material. The pre-formed sheet-type thermal interface material is graphene, and the gel-type thermal interface material is an adhesive with metal fillers. A heat sink is attached to the first surface of the substrate to form a closed gap between the heat sink and the substrate, wherein the first die, the second die, the third die, the first thermal interface material film, the second thermal interface material film and the third thermal interface material film are disposed in the closed gap, wherein the first thermal interface material film, the second thermal interface material film and the third thermal interface material film are in contact with the heat sink.

19. The method according to claim 18, wherein, The heat sink is formed of a metallic material.

20. The method of claim 18, wherein, Forming the first thermal interface material film, the second thermal interface material film, and the third thermal interface material film includes: The pre-formed sheet-like thermal interface material is placed on the first die; and The gel-type thermal interface material is distributed on the second and third dies.

Images