Semiconductor structure

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure, which comprises: a substrate, wherein the substrate has array-arranged structure units; the structure unit comprises a plurality of transistor groups arranged in a first direction, the transistor group comprises a plurality of layers of transistors, and the transistors extend in a second direction; the first direction is perpendicular to the second direction, and both are parallel to the substrate surface; the structure unit further comprises a plurality of bit lines extending in a third direction, the bit line is electrically connected with the plurality of layers of transistors of the same transistor group; the third direction is perpendicular to the substrate surface; and a plurality of connection lines, wherein the plurality of connection lines are connected with the plurality of bit lines in the structure unit one by one, and one bit line in the array-arranged structure unit is connected by the same connection line. The embodiment of the present disclosure can at least reduce the number of connection lines.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, specifically relating to a semiconductor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that primarily works by using the amount of charge stored in a capacitor to represent whether a stored binary bit is 1 or 0.

[0003] 3D stacked DRAM is a structure in which multiple layers of transistors are stacked on a substrate. It has a high integration density, which helps to reduce the cost per unit area. However, the number of transistors and capacitors corresponding to a single bit line in 3D stacked DRAM is relatively small. Summary of the Invention

[0004] This disclosure provides a semiconductor structure that at least facilitates increasing the number of transistors and capacitors corresponding to a single bit line.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having an array of structural units arranged on the substrate; each structural unit includes a plurality of transistor groups arranged in a first direction, each transistor group including multiple layers of transistors, the transistors extending in a second direction; the first direction and the second direction are perpendicular and parallel to the surface of the substrate; each structural unit further includes a plurality of bit lines extending in a third direction, the bit lines being electrically connected to the multiple layers of transistors in the same transistor group; the third direction is perpendicular to the surface of the substrate; a plurality of connecting lines, the plurality of connecting lines being connected one-to-one with the plurality of bit lines in the structural unit, and one bit line in the array of structural units being connected by the same connecting line.

[0006] The technical solutions provided in this disclosure have at least the following advantages:

[0007] Multiple connection lines are connected one-to-one with multiple bit lines in the structural unit, and one bit line in the arrayed structural unit is connected by the same connection line. That is, bit lines connected by the same connection line have the same potential, and these connected bit lines can be regarded as the same bit line, which is beneficial to increasing the number of transistors and capacitors corresponding to each bit line. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0009] Figure 1 A top view of a structural unit provided in an embodiment of this disclosure is shown;

[0010] Figure 2 It shows Figure 1 Cross-sectional view along the A-A1 direction;

[0011] Figure 3 A top view of a semiconductor structure provided in an embodiment of this disclosure is shown;

[0012] Figure 4 A top view of another semiconductor structure provided in one embodiment of the present disclosure is shown;

[0013] Figure 5 A top view of yet another semiconductor structure provided in an embodiment of this disclosure is shown;

[0014] Figures 6-7 Two cross-sectional views of a semiconductor structure provided in an embodiment of the present disclosure are shown in a second direction;

[0015] Figures 8-9 Two partial cross-sectional views of a semiconductor structure provided in an embodiment of the present disclosure are shown in a first direction. Detailed Implementation

[0016] As the background technology indicates, 3D stacked DRAM has a large number of interconnects, thus increasing the complexity of the manufacturing process. Analysis reveals that the main reason is that in a 3D stacked DRAM structure, the number of transistors and capacitors corresponding to bit lines depends primarily on the number of stacked transistor and capacitor layers. However, due to process limitations, increasing the number of stacked layers is quite difficult. Furthermore, 3D stacked DRAM typically has multiple structural units, each with multiple bit lines, which need to be connected to external circuits via interconnects. The large number of interconnects further increases the complexity of the process for connecting these interconnects to the external circuits.

[0017] This disclosure provides a semiconductor structure including multiple interconnect lines, each interconnect line corresponding one-to-one with a plurality of bit lines in a structural unit, and a bit line within an array of structural units is connected by the same interconnect line. In other words, one interconnect line can connect multiple bit lines in multiple structural units, and interconnected bit lines can be considered as a single bit line, thereby increasing the number of transistors and capacitors connected to a single bit line. Furthermore, since each bit line does not need to be led out through a separate interconnect line, the number of interconnect lines is reduced, thus simplifying the connection process between the interconnect lines and peripheral circuits.

[0018] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0019] like Figures 1-9 As shown, an embodiment of this disclosure provides a semiconductor structure. First, it should be noted that the semiconductor structure has a first direction X, a second direction Y, and a third direction Z. The first direction X is the arrangement direction of multiple transistor groups, the second direction Y is the extension direction of transistor 23, the first direction X is perpendicular to the second direction Y, and both are parallel to the surface of the substrate 10; the third direction Z is the stacking direction of the multilayer transistors 23, and the third direction Z is perpendicular to the surface of the substrate 10.

[0020] The semiconductor structure includes: a substrate 10, on which structural units 20 are arranged in an array; the structural unit 20 includes a plurality of transistor groups arranged in a first direction X, the transistor groups including multilayer transistors 23, the transistors 23 extending in a second direction Y; the first direction X and the second direction Y are perpendicular and parallel to the surface of the substrate 10; the structural unit 20 also includes a plurality of bit lines 21 extending in a third direction Z, the bit lines 21 being electrically connected to the multilayer transistors 23 of the same transistor group; the third direction Z is perpendicular to the surface of the substrate 10; a plurality of connecting lines 30, the plurality of connecting lines 30 being connected one-to-one with the plurality of bit lines 21 in the structural unit 20, and one bit line 21 in the array-arranged structural unit 20 being connected by the same connecting line 30.

[0021] That is, bit lines 21 of different structural units 20 can be connected to the same connection line 30. Since the interconnected bit lines 21 have the same potential, these bit lines 21 can be regarded as the same bit line 21. Accordingly, the number of transistors 23 and capacitors 24 connected to a single bit line 21 increases. In addition, since multiple bit lines 21 can be led out through the same connection line 30, instead of a single bit line 21 being led out through a separate connection line 30, it is beneficial to reduce the number of connection lines 30. The fewer the number of connection lines 30, the fewer the connection contacts between the connection lines 30 and the peripheral circuit, which helps to simplify the formation process of the connection contacts and also helps to reduce the size of the semiconductor structure.

[0022] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0023] Figure 1 This is a top view of structural unit 20. Figure 2 for Figure 1 Cross-sectional view along the A-A1 direction. Figure 2 A group of transistors in structural unit 20 is shown. (Reference) Figures 1-2 The structural unit 20 may include a transistor region 23 and a capacitor region C arranged in the second direction Y. The transistor region includes a word line region WL and a bit line region BL. The word line region WL is provided with multiple spaced word lines (not shown in the figure), which are connected to the transistors 23 on the same layer, i.e., the extension direction of the word lines is the first direction X. The bit line 21 is located in the bit line region BL and extends in the third direction Y. The capacitor region C has multiple capacitors 24, which are arranged one-to-one with the transistors 23. Specifically, the transistor 23 includes a first source-drain, a channel region, and a second source-drain arranged in the second direction Y, wherein the first source-drain is electrically connected to the capacitors 24, the channel region is electrically connected to the word lines, and the second source-drain is electrically connected to the bit lines 21.

[0024] refer to Figure 1 The structural unit 20 may also include a word line step 22, which is directly opposite the word line area WL. The word line step 22 can lead out word lines, that is, the word lines originally extend in the first direction X, but in order to facilitate subsequent connection with external circuits, the word line step 22 can lead out word lines from the third direction Z.

[0025] Continue to refer to Figure 1 The bit lines 21 of the structural unit 20 include the first to Nth bit lines arranged sequentially in the first direction X, where N is a positive integer greater than 1. For example, the bit lines 21 of all structural units 20 are arranged in the same way.

[0026] refer to Figure 2In this transistor array, each layer of transistor 23 contains two transistors 23, each connected to one capacitor 24. The two transistors 23 are connected to the same bit line 21, allowing for the connection of more transistors 23 and capacitors 24 along a single bit line 21. The more capacitors 24 present, the stronger the storage capacity of the semiconductor structure. For example, when the number of transistor layers 23 is K and the number of structural units 20 is Q, the number of capacitors on each connection line 30 is 2KQ. For instance, when K = 64 and Q = 8, the number of capacitors 24 on each connection line 30 is 1024. In other embodiments, each layer of transistor 23 contains only one transistor 23.

[0027] It should be noted that, in this embodiment of the present disclosure, although the bit lines 21 of different structural units 20 are connected together by the connecting line 30, each structural unit 20 can still work normally. The following will explain this in detail with reference to the working principle of DRAM memory.

[0028] For DRAM memory, each memory cell consists of a capacitor 24 and a transistor 23. The capacitor 24 stores charge, and the transistor 23 accesses the capacitor 24, allowing the reading of the stored charge and the storage of new charge. A word line is always connected to the gate of the transistor 23, controlling access to the capacitor 24. A bit line is connected to the source of the transistor 23, allowing the reading of the charge stored in the capacitor 24 or providing voltage when a new value is written to it. Word lines and bit lines 21 intersect each other, and a memory cell exists at each intersection. Although multiple bit lines 21 can be connected by the connection line 30, the memory cells corresponding to these bit lines 21 are controlled by different word lines without mutual interference. Therefore, the structural unit 20 can still function normally.

[0029] It is worth noting that in this embodiment, bit lines 21 within the same structural unit 20 are connected to different connection lines 30. Therefore, within the structural unit 20, there is still one bit line 21 intersecting with one word line. If the connection line 30 connects two bit lines 21 within the same structural unit 20, then the potentials of these two bit lines 21 are equal, and they are actually the same bit line 21. This can result in a situation where one bit line 21 intersects with one word line multiple times.

[0030] In some embodiments, a bit line 21 within all structural units 20 can be connected by the same connection line 30. In other embodiments, a bit line 21 within some structural units 20 can be connected by the same connection line 30. This is acceptable as long as the connection line 30 can connect the bit lines 21 of multiple structural units 20.

[0031] The specific connection method of the connecting cable 30 will be explained in detail below.

[0032] refer to Figures 3-5 Two adjacent structural units 20 arranged in the first direction X are used to form a structural module 20a. For example, the two structural units 20 of the same structural module 20a are a first structural unit 201 and a second structural unit 202. The two word line steps 23 in the same structural module 20a are arranged back to back, that is, the word line step 23 of the first structural unit 201 is located on the side away from the second structural unit 202, and the word line step 23 of the second structural unit 202 is located on the side away from the first structural unit 201.

[0033] Two structural modules 20a arranged in the second direction Y constitute a module group 20b; multiple module groups 20b are arranged in the first direction X. Figures 3-5 The diagram shows two module groups 20b.

[0034] In some embodiments, two first structural units 201 within module group 20b are directly opposite each other in the second direction Y, and two second structural units 202 within module group 20b are directly opposite each other in the second direction Y. That is, the first structural units 201 and second structural units 202 within different structural modules 20a are arranged in the same way.

[0035] Continue to refer to Figures 3-5 The connecting line 30 includes a first connecting segment 31; the first connecting segment 31 connects two bit lines 21, and the two bit lines 21 are located in two structural units 20 of the same structural module 20a, and the sum of the serial numbers of the two bit lines 21 is N+1.

[0036] That is, the first bit line 21 of one structural module 20a is connected to the last bit line 21 of another structural module 20a; the second first bit line 21 of one module 20a is connected to the second last bit line 21 of another structural module 20a. And so on, without further elaboration. Correspondingly, within the same structural module 20a, the two bit lines 21 connected by different first connecting segments 31 have different spacings. For example, the spacing between the first bit line of the first structural unit 201 and the Nth bit line of the second structural unit 202 is the largest; the spacing between the Nth bit line of the first structural unit 201 and the first bit line of the second structural unit 202 is the smallest.

[0037] The purpose of the aforementioned arrangement of the first connecting segments 31 is to avoid the first connecting segments 31 of the same structural unit 20 from intersecting, thereby preventing multiple first connecting segments 31 from being electrically connected. In addition, connecting the bit lines 21 according to the serial number correspondence also helps to standardize the positional relationship of multiple first connecting segments 31, thereby shortening the length of the first connecting segments 31.

[0038] In other embodiments, the sum of the serial numbers of the two bit lines 21 connected by the first connecting segment 31 may not be N+1. Accordingly, different first connecting segments 31 can be set at different height positions to avoid electrical connection between the first connecting segments 31.

[0039] It should be noted that the numbering of bit lines 21 from 1 to N in this embodiment is for ease of understanding, but this embodiment does not limit the numerical value of the bit line 21, as long as the corresponding positional relationship can be satisfied.

[0040] In some embodiments, multiple first connecting segments 31 are arranged in parallel. This arrangement helps to avoid the first connecting segments 31 from crossing each other. It also helps to ensure that there is a uniform spacing between adjacent first connecting segments 31, which facilitates manufacturing and reduces parasitic capacitance.

[0041] Continue to refer to Figures 3-5 The connecting line 30 also includes a second connecting segment 32; the second connecting segment 32 connects two bit lines 21 located in different structural modules 20a, and the different structural modules 20a are arranged in the first direction X. For example, the two bit lines 21 connected by the second connecting segment 32 are respectively located in two structural units 20 of adjacent structural modules 20a, and the two structural units 20 are arranged opposite each other. For instance, the second connecting segment 32 connects a second structural unit 202 of one structural module 20a and a first structural unit 201 of another structural module 20a. This connection method helps to shorten the length of the second connecting segment 32, thereby reducing the resistance of the second connecting segment 32 and thus reducing the power consumption of the semiconductor structure.

[0042] In some embodiments, the sum of the sequence numbers of the two bit lines 21 connected by the second connecting segment 32 is N+1. That is, the connection method of the second connecting segment 32 is similar to that of the first connecting segment 31, both in order to avoid the connecting segments from crossing. In addition, connecting the bit lines 21 according to the sequence number correspondence also helps to standardize the positional relationship of multiple second connecting segments 32, thereby shortening the length of the second connecting segment 32.

[0043] In other embodiments, the sum of the serial numbers of the two bit lines 21 connected by the second connection segment 32 may not be N+1. Accordingly, different second connection segments 32 can be set at different height positions to avoid electrical connection.

[0044] In some embodiments, multiple second connecting segments 32 are arranged in parallel. This arrangement helps to avoid the second connecting segments 32 from crossing each other. It also helps to ensure that there is a uniform spacing between adjacent second connecting segments 32, which facilitates the manufacturing process and also helps to reduce parasitic capacitance.

[0045] Continue to refer to Figures 3-5The connecting line 30 also includes a third connecting segment 33. The third connecting segment 33 connects two bit lines 21 located in different structural modules 20a, and the different structural modules 20a are arranged in the second direction Y. For example, the third connecting segment 33 connects two bit lines 21 of the first structural unit 201 facing each other in the second direction Y; or, the third connecting segment 33 connects two bit lines 21 of the second structural unit 202 facing each other in the second direction Y. This shortens the length of the third connecting segment 33, thereby reducing its resistance and consequently reducing the power consumption of the semiconductor structure. In other embodiments, the third connecting segment 33 may also connect one bit line 21 of the first structural unit 201 and one bit line 21 of the second structural unit 202.

[0046] In some embodiments, the sum of the sequence numbers of the two bit lines 21 connected by the third connecting segment 33 is N+1, or the sequence numbers of the two bit lines 21 are the same. This helps to avoid the third connecting segments 33 from crossing. In addition, connecting the bit lines 21 according to the sequence number correspondence also helps to standardize the positional relationship of multiple third connecting segments 33, thereby shortening the length of the third connecting segments 33.

[0047] In some embodiments, multiple third connecting segments 33 are arranged in parallel. This arrangement helps to avoid the third connecting segments 33 from crossing each other. It also helps to ensure that there is a uniform spacing between adjacent third connecting segments 33, which facilitates the manufacturing process and also helps to reduce parasitic capacitance.

[0048] To make it easier to understand, examples will be provided below.

[0049] Example 1, for reference Figure 3 Each module group 20b has two third connection segments 30, one third connection segment 33 connects the bit lines 21 of two first structural units 201, and the other third connection segment 33 connects the bit lines 21 of two second structural units 202, and the two bit lines 21 connected by the third connection segment 33 have the same sequence number; the connection segments 30 of two adjacent module groups 20b have one second connection segment 32.

[0050] For example, if the semiconductor structure has two module groups 20b, then each connection line 30 has one second connection segment 32 and four third connection segments 33. In other words, each connection line 30 has an "S" shaped orientation and connects to the bit lines 21 of multiple structural units 20 in sequence.

[0051] Example 2, see reference Figure 4 One of the multiple module groups 20b has a third connection segment 33 for its corresponding connection line 30, and the sum of the serial numbers of the two bit lines 21 connected by the third connection segment 33 is N+1; the connection lines 30 of two adjacent module groups 20b have two second connection segments 32.

[0052] For example, if the semiconductor structure has four module groups 20b, then each connection line 30 has one third connection segment 33 and six second connection segments 32. That is to say, multiple module groups 20b can be regarded as memory regions, and the connection lines 30 connect the bit lines 21 of each structural unit 20 around the memory regions.

[0053] Example 3, for reference Figure 5 One of the multiple module groups 20b has a third connection segment 33 for its corresponding connection line 30, and the two bit lines 21 connected by the third connection segment 33 have the same sequence number; the connection lines 30 of two adjacent module groups 20b have two second connection segments 32.

[0054] For example, if the semiconductor structure has three module groups 20b, then each connection line 30 has one third connection segment 33 and four second connection segments 32. That is, multiple module groups 20b can be considered as memory regions, and the connection lines 30 connect the bit lines of each structural unit 20 circumferentially around the memory regions. The routing of the connection lines 30 in Examples 2 and 3 is roughly the same; the main difference lies in the connection method of the third connection segments 33. In Example 2, the third connection segment 33 can bend between two structural units 20, while in Example 3, the third connection segment 33 needs to bend outside the two structural units 20. Therefore, the total length of the third connection segment 33 in Example 2 is smaller.

[0055] In other embodiments, the connection methods in the three examples can be combined. For example, [the following can be done:] Figure 3 The structural unit 20 shown is... Figure 4 The structural units 20 shown are combined. Figure 3 The structural unit 20 arranged in the middle array and Figure 4 The structural units arranged in the array are arranged in the second direction Y. Only a third connecting segment 33 needs to be added between them, so that a connecting line 30 can connect the sixteen bit lines 21 of the sixteen structural units 20.

[0056] In other words, the connection method of the connecting line 30 can be adjusted and combined according to different semiconductor structures, thereby improving the space utilization rate within the semiconductor structure.

[0057] Figures 6-7 Two cross-sectional views of the semiconductor structure in the second direction Y are shown respectively, for reference. Figures 6-7 The connecting line 30 includes a vertical connecting line 3a and a parallel connecting line 3b connected together; the vertical connecting line 3a is perpendicular to the surface of the substrate 10 and is connected to the position line 21, while the parallel connecting line 3b is parallel to the surface of the substrate 10. The vertical connecting line 3a is mainly used to lead out the position line 21 to ensure that the parallel connecting line 3a can cross multiple structural units 20.

[0058] In some embodiments, two adjacent parallel connecting lines 3b have different heights relative to the surface of the substrate 10, and correspondingly, two adjacent vertical connecting lines 3a have different lengths in the third direction Z. For example, Figure 6 The connecting line 30 in the middle and Figure 7 The connecting lines 30 are set adjacent to each other. Figure 6 The height ratio of the parallel connecting line 3b in the middle Figure 7 The height of the parallel connecting line 3b is low, and correspondingly, Figure 6 The length of the vertical connecting line 3a in the middle is compared to Figure 7 The length of the vertical connecting line 3a is small.

[0059] It is worth noting that the parasitic capacitance between adjacent parallel connection lines 3b is related to the distance between them and the area of ​​their opposing surfaces; the greater the distance and the smaller the area of ​​their opposing surfaces, the smaller the parasitic capacitance becomes. If the heights of adjacent parallel connection lines 3b are different, that is, if they are staggered, it is beneficial to reduce the parasitic capacitance between adjacent parallel connection lines 3b, thereby improving the operating speed of the semiconductor structure.

[0060] Figures 8-9 Two partial cross-sectional views of the semiconductor structure in the first direction X are shown, with reference to... Figures 8-9 In some embodiments, at least two parallel connecting lines 3b are used to form a group of parallel connecting lines. The parallel connecting lines 3b in a group of parallel connecting lines include parallel connecting lines from the first to the Mth, where M is a positive integer greater than 1. The parallel connecting lines from the first to the Mth have different heights, and parallel connecting lines 3b with the same index in different groups of parallel connecting lines have the same height. For example, refer to... Figure 8 A set of parallel connecting lines 3b includes a first parallel connecting line and a second parallel connecting line. The first parallel connecting line has a first height, and the second parallel connecting line has a second height, wherein the first height is greater than the second height. (Reference) Figure 9 A set of parallel connecting lines 3b includes the first to the fourth parallel connecting lines, which have the first to the fourth heights respectively, with the first to the fourth heights decreasing sequentially.

[0061] It is worth noting that the numbering of the parallel connecting lines 3b from 1 to M in this embodiment is for ease of understanding, but this embodiment does not limit the numerical value of the serial number of the parallel connecting lines 3b, as long as the corresponding positional relationship can be satisfied.

[0062] It should be noted that if each parallel interconnect 3b has a different height, it will increase the thickness of the semiconductor structure in the third direction Y, which is not conducive to the miniaturization of the semiconductor structure and will also increase the number of photomasks required. By grouping the interconnects 30, the interconnects 30 in different groups can have the same height. In this way, the parasitic capacitance 24 of adjacent interconnects 30 can be reduced without significantly affecting the thickness of the semiconductor structure, and it is also beneficial to simplify the manufacturing process.

[0063] In some embodiments, the parallel connecting lines 3b of each parallel connecting line group are arranged sequentially according to numbers 1 to M. For example, the parallel connecting lines 3b of each parallel connecting line group can be arranged in an increasing or decreasing height manner. This ensures that parallel connecting lines 3b with the same number have the same uniform distance, thereby facilitating manufacturing and reducing parasitic capacitance.

[0064] In other embodiments, all parallel connecting lines 3b can also be at the same height, so only one photomask is needed to form all parallel connecting lines 3b, which helps to save production costs.

[0065] In summary, bit lines 21 of different structural units 20 can be connected to the same connection line 30. Multiple bit lines 21 connected to the same connection line 30 can be considered as a single bit line 21. Therefore, the number of transistors 23 and capacitors connected to a single bit line 21 increases. Furthermore, since multiple bit lines 21 can be led out through the same connection line 30, the number of connection lines 30 can be reduced. This reduces the difficulty of connecting the connection lines 30 to external circuits and also helps to fully utilize the internal space of the semiconductor structure.

[0066] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and description of the present disclosure should fall within the scope of the patent coverage of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having structural units arranged in an array on the substrate; The structural unit includes a transistor region and a capacitor region arranged along the second direction; The transistor region includes multiple transistors and the capacitor region includes multiple capacitors, and the multiple transistors and the multiple capacitors are arranged in a one-to-one correspondence. The structural unit includes a plurality of transistor groups arranged in a first direction, the transistor groups including multilayer transistors, the transistors extending in a second direction; the first direction and the second direction are perpendicular and parallel to the substrate surface; The structural unit also includes multiple bit lines extending upward in a third direction, the bit lines being electrically connected to multiple layers of transistors in the same transistor group; the third direction is perpendicular to the substrate surface; Multiple connecting lines are connected one-to-one with multiple bit lines in the structural unit, and one bit line in the arrayed structural unit is connected by the same connecting line.

2. The semiconductor structure according to claim 1, characterized in that, Two adjacent structural units arranged in the first direction are used to form a structural module; The bit lines of the same structural unit include the first to Nth bit lines arranged sequentially in the first direction, where N is a positive integer greater than 1; The connecting line includes a first connecting segment; the first connecting segment connects two bit lines, and the two bit lines are respectively located in two structural units of the same structural module, and the sum of the serial numbers of the two bit lines is N+1.

3. The semiconductor structure according to claim 2, characterized in that, The connecting line further includes a second connecting segment and a third connecting segment; The second connection segment connects two bit lines located in different structural modules, and the different structural modules are arranged in the first direction; the sum of the sequence numbers of the two bit lines connected by the second connection segment is N+1; The third connection segment connects two bit lines located in different structural modules, and the different structural modules are arranged in the second direction; the sum of the sequence numbers of the two bit lines connected by the third connection segment is N+1, or the sequence numbers of the two bit lines are the same.

4. The semiconductor structure according to claim 3, characterized in that, The two bit lines connected by the second connection segment are respectively located in two structural units of adjacent structural modules, and the two structural units are arranged opposite to each other; Two structural modules arranged in the second direction constitute a module group; multiple module groups are arranged in the first direction; The two structural units of the same structural module are respectively a first structural unit and a second structural unit; the two first structural units in the module group are facing each other, and the two second structural units in the module group are facing each other; The third connection segment connects the bit lines of two opposing first structural units; or, the third connection segment connects the bit lines of two opposing second structural units.

5. The semiconductor structure according to claim 4, characterized in that, Each module group has two third connection segments in its corresponding connection line. One third connection segment connects two bit lines of the first structural unit, and the other third connection segment connects two bit lines of the second structural unit. The two bit lines connected by the third connection segment have the same sequence number. The connecting lines corresponding to two adjacent module groups have a second connecting segment.

6. The semiconductor structure according to claim 4, characterized in that, The connection line corresponding to one of the plurality of module groups has a third connection segment, and the sum of the sequence numbers of the two bit lines connected by the third connection segment is N+1; The connecting lines corresponding to two adjacent module groups have two second connecting segments.

7. The semiconductor structure according to claim 4, characterized in that, The connection line corresponding to one of the plurality of module groups has a third connection segment, and the two bit lines connected by the third connection segment have the same sequence number; The connecting lines corresponding to two adjacent module groups have two second connecting segments.

8. The semiconductor structure according to claim 2, characterized in that, Multiple first connection segments are arranged in parallel.

9. The semiconductor structure according to claim 3, characterized in that, Multiple second connection segments are arranged in parallel.

10. The semiconductor structure according to claim 3, characterized in that, Multiple third connecting segments are arranged in parallel.

11. The semiconductor structure according to claim 1, characterized in that, The connecting lines include connected vertical connecting lines and parallel connecting lines; the vertical connecting lines are perpendicular to the substrate surface and connected to the bit lines, and the parallel connecting lines are parallel to the substrate surface.

12. The semiconductor structure according to claim 11, characterized in that, The two adjacent parallel connecting lines have different heights relative to the substrate surface.

13. The semiconductor structure according to claim 12, characterized in that, At least two of the parallel connecting lines are used to form a group of parallel connecting lines, wherein the parallel connecting lines of the group of parallel connecting lines include the first to the Mth parallel connecting lines, where M is a positive integer greater than 1; The first to the Mth parallel connecting lines have different heights, and the parallel connecting lines with the same serial number in different groups of parallel connecting lines have the same height.

14. The semiconductor structure according to claim 13, characterized in that, The parallel connecting lines in the parallel connecting line group are arranged sequentially according to the numbers from 1 to M.

15. The semiconductor structure according to claim 1, characterized in that, The number of transistors in one layer of the transistor group is two.

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