Semiconductor device

Abstract

A semiconductor device (1) includes a trench gate structure (6) formed in a surface layer portion of a first main surface of a semiconductor layer. A source region (10) and a well region (11) are formed in the surface layer portion of the first main surface of the semiconductor layer laterally of the trench gate structure (6). The well region (11) is formed in a region of a second main surface side of the semiconductor layer with respect to the source region (10). In the well region (11), a channel is formed in a portion along the trench gate structure (6). A stacked region (22) is formed in a region between the trench gate structure (6) and the source region (10) in the semiconductor layer. The stacked region (22) has a p-type impurity region (20) formed in the surface layer portion of the first main surface of the semiconductor layer and an n-type impurity region (21) formed in the second main surface side of the semiconductor layer with respect to the second conductive type impurity region (20).

Description

[0001] This invention is a divisional application of the invention application with application number 201780007370.X (international application number PCT / JP2017 / 001245), titled "Semiconductor Device", and filed on January 16, 2017. Technical Field

[0002] This invention relates to semiconductor devices. Background Technology

[0003] MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are known as semiconductor elements that are connected to a load and provide a predetermined switching action to that load. Patent Document 1 discloses an example of a semiconductor device incorporating a MOSFET.

[0004] The semiconductor device of Patent Document 1 includes: an n-type semiconductor layer; a p-type well region formed on the surface portion of the semiconductor layer; an n-type source region formed on the surface portion of the well region at intervals from the periphery of the well region; and a gate electrode formed on the semiconductor layer in a manner opposite to the channel between the periphery of the well region and the periphery of the source region.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2011-159797 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] If a load is short-circuited while the semiconductor device is in the ON state, the voltage applied to the load may act as a short-circuit voltage to the semiconductor device. In this case, a relatively large short-circuit current flows into the semiconductor device. As a result, due to the Joule heating caused by the short-circuit voltage and short-circuit current, there is a possibility that the semiconductor device may be damaged within a short period of time, for example, from a few μs to tens of μs.

[0010] The short-circuit withstand capability is known as the time from the start of short-circuit current flow to the failure of the semiconductor device. Generally speaking, the longer the time before the semiconductor device fails, the better the short-circuit withstand capability.

[0011] Reducing the impurity concentration in the well region forming the channel can suppress short-circuit current. Therefore, it can be assumed that the short-circuit tolerance is improved due to the reduction in Joule heating. However, reducing the impurity concentration in the well region presents a trade-off between decreased carrier mobility and increased on-resistance.

[0012] Therefore, the object of the present invention is to provide a semiconductor device that can suppress the increase of on-resistance and achieve excellent short-circuit withstand capability.

[0013] Solution for solving the problem

[0014] The semiconductor device of the first aspect of the present invention includes: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; a trench gate structure including a gate trench formed on the surface portion of the first main surface of the semiconductor layer and a gate electrode buried in the gate trench through an insulating film; a source region of a first conductivity type formed on the surface portion of the first main surface of the semiconductor layer on the side of the trench gate structure; a well region of a second conductivity type formed on the side of the trench gate structure along the region of the trench gate structure relative to the source region on the second main surface side of the semiconductor layer and forming a channel on the portion along the trench gate structure; and a stacked region formed on the semiconductor layer in the region between the trench gate structure and the source region, and having a second conductivity type impurity region formed on the surface portion of the first main surface of the semiconductor layer and a first conductivity type impurity region formed on the second main surface side of the semiconductor layer relative to the second conductivity type impurity region.

[0015] The second aspect of the semiconductor device of the present invention includes: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; a trench gate structure including a gate trench formed on the surface portion of the first main surface of the semiconductor layer and a gate electrode buried in the gate trench through an insulating film; a source region of a first conductivity type formed on the surface portion of the first main surface of the semiconductor layer on the side of the trench gate structure; a well region of a second conductivity type formed on the side of the trench gate structure along the region of the trench gate structure relative to the source region on the second main surface side of the semiconductor layer and forming a channel along the portion of the trench gate structure; a first conductivity type impurity region formed on the semiconductor layer in a manner exposed from the first main surface of the semiconductor layer between the trench gate structure and the source region and electrically connected to the well region; and a source electrode formed on the first main surface of the semiconductor layer and electrically connected to the source region and the first conductivity type impurity region, and forming a Schottky junction with the first conductivity type impurity region.

[0016] The semiconductor device of the third aspect of the present invention includes: a semiconductor layer of a first conductivity type having a first main surface and a second main surface; a well region of a second conductivity type formed on the surface portion of the first main surface of the semiconductor layer; a source region of a first conductivity type formed on the surface portion of the well region at intervals from the periphery of the well region; a gate electrode formed on the first main surface of the semiconductor layer with an insulating film between it and a channel between the periphery of the well region and the periphery of the source region; and a stacked region formed on the surface portion of the well region in a region between the channel and the source region, and having a first conductivity type impurity region formed on the surface portion of the well region and a second conductivity type impurity region formed on the surface portion of the first conductivity type impurity region.

[0017] Invention Effects

[0018] In the semiconductor device of the first aspect of the present invention, a pn junction is formed between a second conductivity type impurity region and a first conductivity type impurity region. Additionally, a pn junction is formed between a second conductivity type well region and a first conductivity type impurity region.

[0019] When a short-circuit voltage is applied between the semiconductor layer and the source region, the depletion layer expands from the pn junction formed between the second conductivity type impurity region and the first conductivity type impurity region into the first conductivity type impurity region. Additionally, the depletion layer expands from the pn junction formed between the well region of the second conductivity type and the first conductivity type impurity region into the first conductivity type impurity region. Therefore, under short-circuit conditions, the current path within the first conductivity type impurity region can be shortened, thus hindering short-circuit current in the first conductivity type impurity region.

[0020] On the other hand, in the non-short-circuit state, the depletion layer hardly expands from the pn junction formed between the second conductivity type impurity region and the first conductivity type impurity region into the first conductivity type impurity region. Furthermore, in the non-short-circuit state, the depletion layer hardly expands from the pn junction formed between the well region of the second conductivity type and the first conductivity type impurity region into the first conductivity type impurity region. Therefore, in the non-short-circuit state, the current flowing in the first conductivity type impurity region is hardly hindered by the depletion layer.

[0021] Therefore, in the semiconductor device of the first embodiment, a current narrowing is formed in the region between the channel (well region) and the source region. Regarding the current narrowing, when it becomes a short-circuit state, the current path is narrowed, and when switching from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0022] Therefore, in the short-circuit state, the short-circuit current can be reduced, thereby reducing Joule heating caused by short-circuit voltage and short-circuit current. On the other hand, in the non-short-circuit state, the current path is hardly narrowed, thus suppressing the increase in on-resistance caused by current narrowing. Thus, a semiconductor device that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided.

[0023] In the semiconductor device of the second aspect of the present invention, a Schottky junction is formed between the source electrode and the first conductivity type impurity region. Additionally, a pn junction is formed between the second conductivity type well region and the first conductivity type impurity region.

[0024] When a short-circuit voltage is applied between the semiconductor layer and the source region, the depletion layer expands from the Schottky junction formed between the source electrode and the first conductivity type impurity region into the first conductivity type impurity region. Additionally, the depletion layer expands from the pn junction formed between the well region of the second conductivity type and the first conductivity type impurity region into the first conductivity type impurity region. Therefore, the current path within the first conductivity type impurity region can be shortened under short-circuit conditions, thus hindering short-circuit current in the first conductivity type impurity region.

[0025] On the other hand, in the non-short-circuit state, the depletion layer hardly expands from the Schottky junction formed between the source electrode and the first conductivity type impurity region into the first conductivity type impurity region. Furthermore, in the non-short-circuit state, the depletion layer hardly expands from the pn junction formed between the well region of the second conductivity type and the first conductivity type impurity region into the first conductivity type impurity region. Therefore, in the non-short-circuit state, the current flowing in the first conductivity type impurity region is hardly hindered by the depletion layer.

[0026] Therefore, in the semiconductor device of the second embodiment, a current narrowing is formed in the region between the channel (well region) and the source region. Regarding the current narrowing, when it becomes a short-circuit state, the current path is narrowed, and when switching from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0027] Therefore, in the short-circuit state, the short-circuit current can be reduced, thereby reducing Joule heating caused by short-circuit voltage and short-circuit current. On the other hand, in the non-short-circuit state, the current path is hardly narrowed, thus suppressing the increase in on-resistance caused by current narrowing. Thus, a semiconductor device that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided.

[0028] In the semiconductor device of the third aspect of the present invention, a pn junction is formed between a second conductivity type impurity region and a first conductivity type impurity region. Additionally, a pn junction is formed between a second conductivity type well region and a first conductivity type impurity region.

[0029] When a short-circuit voltage is applied between the semiconductor layer and the source region, the depletion layer expands from the pn junction formed between the second conductivity type impurity region and the first conductivity type impurity region into the first conductivity type impurity region. Additionally, the depletion layer expands from the pn junction formed between the well region of the second conductivity type and the first conductivity type impurity region into the first conductivity type impurity region. Therefore, under short-circuit conditions, the current path within the first conductivity type impurity region can be shortened, thus hindering short-circuit current in the first conductivity type impurity region.

[0030] On the other hand, in the non-short-circuit state, the depletion layer hardly expands from the pn junction formed between the second conductivity type impurity region and the first conductivity type impurity region into the first conductivity type impurity region. Furthermore, in the non-short-circuit state, the depletion layer hardly expands from the pn junction formed between the well region of the second conductivity type and the first conductivity type impurity region into the first conductivity type impurity region. Therefore, in the non-short-circuit state, the current flowing in the first conductivity type impurity region is hardly hindered by the depletion layer.

[0031] Therefore, in the semiconductor device of the third embodiment, a current narrowing is formed in the region between the channel (well region) and the source region. Regarding the current narrowing, when it becomes a short-circuit state, the current path is narrowed, and when switching from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0032] Therefore, in the short-circuit state, the short-circuit current can be reduced, thereby reducing Joule heating caused by short-circuit voltage and short-circuit current. On the other hand, in the non-short-circuit state, the current path is hardly narrowed, thus suppressing the increase in on-resistance caused by current narrowing. Thus, a semiconductor device that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided. Attached Figure Description

[0033] Figure 1 This is a top view of a semiconductor device according to the first embodiment of the present invention.

[0034] Figure 2A It is along Figure 1 The cross-sectional view of line IIA-IIA shown.

[0035] Figure 2B It is along Figure 1 The cross-sectional view of line IIB-IIB shown.

[0036] Figure 3 Is it by Figure 2A The enlarged view of the area enclosed by the dashed line III shows the non-short-circuit condition.

[0037] Figure 4 Is with Figure 3The enlarged view of the corresponding area represents the short-circuit condition.

[0038] Figure 5 This is a cross-sectional view of a semiconductor device for reference.

[0039] Figure 6 It is a graph representing the drain current-drain voltage characteristics.

[0040] Figure 7A It means Figure 1 A cross-sectional view of a method for manufacturing a semiconductor device.

[0041] Figure 7B It means Figure 7A A cross-sectional view of the subsequent processes.

[0042] Figure 7C It means Figure 7B A cross-sectional view of the subsequent processes.

[0043] Figure 7D It means Figure 7C A cross-sectional view of the subsequent processes.

[0044] Figure 7E It means Figure 7D A cross-sectional view of the subsequent processes.

[0045] Figure 7F It means Figure 7E A cross-sectional view of the subsequent processes.

[0046] Figure 8 This is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

[0047] Figure 9 It is a graph representing the drain current-drain voltage characteristics.

[0048] Figure 10 This is a top view of a semiconductor device according to a third embodiment of the present invention.

[0049] Figure 11A It is along Figure 10 The cross-sectional view of the XIA-XIA line shown.

[0050] Figure 11B It is along Figure 10 A cross-sectional view of the XIB-XIB line shown.

[0051] Figure 12 It is a graph representing the drain current-drain voltage characteristics.

[0052] Figure 13A It means Figure 10 A cross-sectional view of a method for manufacturing a semiconductor device.

[0053] Figure 13B It means Figure 13A A cross-sectional view of the subsequent processes.

[0054] Figure 13C It means Figure 13B A cross-sectional view of the subsequent processes.

[0055] Figure 13D It means Figure 13C A cross-sectional view of the subsequent processes.

[0056] Figure 13E It means Figure 13D A cross-sectional view of the subsequent processes.

[0057] Figure 13F It means Figure 13E A cross-sectional view of the subsequent processes.

[0058] Figure 14 This is a top view of a semiconductor device according to the fourth embodiment of the present invention.

[0059] Figure 15A It is along Figure 14 The cross-sectional view of the XVA-XVA line shown.

[0060] Figure 15B It is along Figure 14 The cross-sectional view of the XVB-XVB line shown.

[0061] Figure 16 Is it by Figure 15A The enlarged view of the area enclosed by the dashed line XVI shows the non-short-circuit condition.

[0062] Figure 17 Is with Figure 16 The enlarged view of the corresponding area represents the short-circuit condition.

[0063] Figure 18A It means Figure 14 A cross-sectional view of a method for manufacturing a semiconductor device.

[0064] Figure 18B It means Figure 18A A cross-sectional view of the subsequent processes.

[0065] Figure 18C It means Figure 18B A cross-sectional view of the subsequent processes.

[0066] Figure 18D It means Figure 18C A cross-sectional view of the subsequent processes.

[0067] Figure 18E It means Figure 18DA cross-sectional view of the subsequent processes.

[0068] Figure 18F It means Figure 18E A cross-sectional view of the subsequent processes.

[0069] Figure 19 This is a top view of a semiconductor device according to the fifth embodiment of the present invention.

[0070] Figure 20A It is along Figure 19 The sectional view of line XXA-XXA shown.

[0071] Figure 20B It is along Figure 19 The sectional view of the XXB-XXB line shown.

[0072] Figure 21 This is an enlarged view of the area enclosed by the dashed line XXI shown in Figure 20, representing the non-short-circuit state.

[0073] Figure 22 Is with Figure 21 The enlarged view of the corresponding area represents the short-circuit condition.

[0074] Figure 23 This is a cross-sectional view of a semiconductor device according to the sixth embodiment of the present invention.

[0075] Figure 24 This is a cross-sectional view of a semiconductor device according to the seventh embodiment of the present invention.

[0076] Figure 25 This is a cross-sectional view of a semiconductor device according to the eighth embodiment of the present invention.

[0077] Figure 26 This is a cross-sectional view of a semiconductor device according to the ninth embodiment of the present invention.

[0078] Figure 27 This is a cross-sectional view of a semiconductor device according to the tenth embodiment of the present invention.

[0079] Figure 28 This is a cross-sectional view of a semiconductor device according to the eleventh embodiment of the present invention.

[0080] Figure 29 This is a cross-sectional view of a semiconductor device according to the twelfth embodiment of the present invention.

[0081] Figure 30 It is a graph representing the drain current-drain voltage characteristics.

[0082] Figure 31 This is a cross-sectional view of a semiconductor device according to the thirteenth embodiment of the present invention.

[0083] Figure 32 This is a cross-sectional view of a semiconductor device according to the fourteenth embodiment of the present invention.

[0084] Figure 33 This is a cross-sectional view of a semiconductor device according to the fifteenth embodiment of the present invention. Detailed Implementation

[0085] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0086] Hereinafter, when referred to as n-type impurities or n-type, the type of impurity containing a pentavalent element as the main component will be described. Examples of pentavalent elements include boron (B), aluminum (Al), indium (In), and gallium (Ga). Conversely, when referred to as p-type impurities or p-type, the type of impurity containing a trivalent element as the main component will be described. Examples of trivalent elements include phosphorus (P) and arsenic (As).

[0087] <First Implementation>

[0088] Figure 1 This is a top view of the semiconductor device 1 according to the first embodiment of the present invention. Figure 2A It is along Figure 1 The cross-sectional view of line IIA-IIA shown. Figure 2B It is along Figure 1 The cross-sectional view of line IIB-IIB shown.

[0089] Semiconductor device 1 includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Semiconductor device 1 includes an n-type semiconductor layer having a surface (first main surface) and a back surface (second main surface) located opposite it. The semiconductor layer includes: an n-type semiconductor layer containing SiC. + Type 2 SiC semiconductor substrate; and n containing SiC － SiC epitaxial layer 3. The SiC epitaxial layer 3 is formed on the surface of the SiC semiconductor substrate 2.

[0090] A drain electrode 4 is connected to the back side of the semiconductor layer. The SiC semiconductor substrate 2 and the SiC epitaxial layer 3 are formed as the drain region 5. Hereinafter, the surface of the semiconductor layer will be referred to as the surface of the SiC epitaxial layer 3.

[0091] Reference Figure 1 , Figure 2A as well as Figure 2B Multiple trench gate structures 6 are formed on the surface portion of the SiC epitaxial layer 3. Figure 1 In the figure, the trench gate structure 6 is shown using cross-sectional lines.

[0092] Multiple trench gate structures 6 extend in a strip-like manner in the same direction when viewed from above, and are formed at intervals from each other. The trench gate structure 6 includes a gate electrode 9, which is buried through a gate insulating film 8 in a gate trench 7 formed by selectively drilling down the surface portion of the SiC epitaxial layer 3.

[0093] The gate insulating film 8 is formed on one surface of its SiC epitaxial layer 3 and the opposite surface along the inner wall of the gate trench 7. The inner wall of the gate trench 7 includes a side surface and a bottom surface. The gate insulating film 8 may also have approximately the same thickness.

[0094] Reference Figure 1 and Figure 2A n is formed on the surface of SiC epitaxial layer 3. + Type source region 10 and p － Type 11, well region. + Type source region 10 and p － The type of well region 11 is formed on the side of the trench gate structure 6 from the surface side of the semiconductor layer to the back side in this order.

[0095] The source region 10 extends in a strip shape along the trench gate structure 6 and is formed at intervals from the trench gate structure 6. In this embodiment, the source region 10 is formed in the central portion between adjacent trench gate structures 6. The source region 10 is exposed from the surface of the SiC epitaxial layer 3.

[0096] Reference Figure 2A and Figure 2B The source region 10 is connected to the well region 11 in the depth direction of the SiC epitaxial layer 3 (semiconductor layer). The depth direction of the SiC epitaxial layer 3 refers to the direction orthogonal to the surface of the SiC epitaxial layer 3. The n-type impurity concentration of the source region 10 is higher than that of the SiC epitaxial layer 3.

[0097] Reference Figure 2A and Figure 2B The well region 11 is formed relative to the source region 10 on the back side of the semiconductor layer in a manner that follows the trench gate structure 6. The well region 11 is formed to the depth at which its boundary with the SiC epitaxial layer 3 connects to the side surface of the trench gate structure 6.

[0098] A well region 11 is formed in the region between adjacent trench gate structures 6. The well region 11 is shared by the adjacent trench gate structures 6 on one side and the trench gate structures 6 on the other side. The portion of the well region 11 along the side of the trench gate structure 6 is a channel forming region 12. The formation of the channel in the channel forming region 12 is controlled by the trench gate structure 6 (gate electrode 9).

[0099] The values ​​for SiC epitaxial layer 3, trench gate structure 6, source region 10, and well region 11 are supplemented.

[0100] Regarding the depth direction of the SiC epitaxial layer 3, the depth D of the trench gate structure 6 GT For example, it is 0.5μm or more and 2.0μm or less (around 1.0μm in this embodiment).

[0101] Regarding the depth direction of SiC epitaxial layer 3, the thickness T of source region 10 S For example, it is 0.1 μm or more and 0.2 μm or less (around 0.15 μm in this embodiment).

[0102] Regarding the depth direction of the SiC epitaxial layer 3, the thickness T of the well region 11 W For example, it is 0.4 μm or more and 0.6 μm or less (around 0.5 μm in this embodiment).

[0103] The n-type impurity concentration of the SiC epitaxial layer 3 is, for example, 1.0 × 10⁻⁶. 14 cm -3 Above and 1.0×10 16 cm -3 The following (in this embodiment, 8.0×10) 15 cm -3 about).

[0104] The concentration of n-type impurities in source region 10 is, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 20 cm -3 The following (in this embodiment, 6.0 × 10) 19 cm -3 about).

[0105] The concentration of p-type impurities in well region 11 is, for example, 1.0 × 10⁻⁶. 17 cm -3 Above and 1.0×10 19 cm -3 The following (in this embodiment, 2.0 × 10) 18 cm -3 about).

[0106] The semiconductor device 1 of this embodiment includes a stacked region 22, which is formed in the surface portion of the SiC epitaxial layer 3 between the trench gate structure 6 and the source region 10.

[0107] The stacked region 22 includes a p-type impurity region 20 and an n-type impurity region 21 formed sequentially from the surface side to the back side of the semiconductor layer in the surface portion of the SiC epitaxial layer 3. By having the stacked region 22, the semiconductor device 1 achieves suppression of the increase in on-resistance and excellent short-circuit withstand capability.

[0108] Reference Figure 1 and Figure 2A The stacked region 22 is formed in a strip shape along the trench gate structure 6. The stacked region 22 is formed to a depth approximately equal to that of the source region 10. In the stacked region 22, the p-type impurity region 20 and the n-type impurity region 21 are formed to be connected to the side of the source region 10 and the trench gate structure 6 in a lateral direction parallel to the surface of the SiC epitaxial layer 3.

[0109] The transverse direction parallel to the surface of the SiC epitaxial layer 3 is also the direction that intersects with the strip-shaped trench gate structure 6. The direction that intersects with the strip-shaped trench gate structure 6 can also be the direction that is orthogonal to the strip-shaped trench gate structure 6.

[0110] The p-type impurity region 20 is formed on the surface portion of the SiC epitaxial layer 3, exposed from the surface of the SiC epitaxial layer 3. The p-type impurity region 20 is connected to the entire region of the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. A pn ​​junction is formed between the p-type impurity region 20 and the n-type impurity region 21. The p-type impurity concentration of the p-type impurity region 20 is higher than that of the well region 11.

[0111] The n-type impurity region 21 is formed on the back side of the semiconductor layer relative to the p-type impurity region 20 in the surface portion of the SiC epitaxial layer 3. The n-type impurity region 21 is connected to the well region 11 in the depth direction of the SiC epitaxial layer 3. A pn ​​junction is formed between the n-type impurity region 21 and the well region 11.

[0112] The n-type impurity region 21 has a width L in a transverse direction parallel to the surface of the SiC epitaxial layer 3 that is approximately equal to the width of the p-type impurity region 20. n The n-type impurity concentration in n-type impurity region 21 is higher than that in SiC epitaxial layer 3 but lower than that in source region 10. Regarding the depth direction of SiC epitaxial layer 3, the thickness T of n-type impurity region 21... n The preferred thickness T of the p-type impurity region 20 is... p The above (T) n ≥T p ).

[0113] The values ​​for p-type impurity region 20 and n-type impurity region 21 are supplemented.

[0114] Regarding the depth direction of SiC epitaxial layer 3, the thickness T of the p-type impurity region 20 p For example, it is 0.04 μm or more and 0.08 μm or less (around 0.06 μm in this embodiment).

[0115] Regarding the depth direction of the SiC epitaxial layer 3, the thickness T of the n-type impurity region 21 nFor example, it is 0.06 μm or more and 0.12 μm or less (around 0.09 μm in this embodiment).

[0116] Regarding the transverse direction parallel to the surface of the SiC epitaxial layer 3, the width L of the n-type impurity region 21 n For example, it is 0.1 μm or more and 0.8 μm or less (around 0.4 μm in this embodiment).

[0117] The p-type impurity concentration in p-type impurity region 20 is, for example, 1.0 × 10⁻⁶. 19 cm -3 Above and 1.0×10 21 cm -3 The following (in this embodiment, 4.0 × 10) 20 cm -3 about).

[0118] The n-type impurity concentration in n-type impurity region 21 is, for example, 1.0 × 10⁻⁶. 17 cm -3 Above and 1.0×10 19 cm -3 The following (in this embodiment, 1.0 × 10) 18 cm -3 about).

[0119] Reference Figure 1 and Figure 2B In the stacked region 22, a portion of the region 21 where no n-type impurities are present is selectively formed (refer to...). Figure 1 (The dashed line). The portion of the n-type impurity region 21 that does not exist is formed as the p-type contact region 23.

[0120] The stacked region 22 may also include a region 24 along the trench gate configuration 6 where portions of the region 21 containing n-type impurities and portions of the region 21 not containing n-type impurities are alternately formed.

[0121] The p-type impurity region 20 is electrically connected to the well region 11 in the contact region 23. Thus, the p-type impurity region 20 is set to have the same potential as the well region 11.

[0122] Reference Figure 2A and Figure 2B A surface insulating film 30 is formed on the surface of the SiC epitaxial layer 3. The surface insulating film 30 covers the trench gate structure 6. Contact holes 31 are formed in the surface insulating film 30 to selectively expose the source region 10 and the p-type impurity region 20.

[0123] An active electrode 32 is formed on the surface insulating film 30. The source electrode 32 enters the contact hole 31 from the surface insulating film 30. The source electrode 32 is electrically connected to the source region 10 and the p-type impurity region 20 within the contact hole 31. As a result, the source region 10 and the p-type impurity region 20 are short-circuited and have the same potential.

[0124] Alternatively, the source electrode 32 may form an ohmic junction with the source region 10 and also with the p-type impurity region 20. Another option is that the source electrode 32 may form an ohmic junction with the source region 10 and also with the p-type impurity region 20.

[0125] Next, refer to Figure 3 and Figure 4 The electrical structure of semiconductor device 1 will be explained. Figure 3 Is it by Figure 2A The enlarged view of the area enclosed by the dashed line III shows the non-short-circuit condition. Figure 4 Is with Figure 3 The enlarged view of the corresponding area represents the short-circuit condition.

[0126] The non-short-circuit state of semiconductor device 1 refers to the stable state in which a predetermined driving voltage is applied to the gate electrode 9. The short-circuit state of semiconductor device 1 refers to the state in which a predetermined short-circuit voltage (e.g., 200V to 1000V) is applied between the drain electrode 4 and the source electrode 32 while a predetermined driving voltage is applied to the gate electrode 9.

[0127] Reference Figure 3 and Figure 4 MISFET 40 and JFET (Junction Gate Field-Effect Transistor) 41 are formed on the side of the trench gate structure 6.

[0128] The MISFET40 is formed by a SiC epitaxial layer 3 (drain region 5), a trench gate structure 6 (gate electrode 9), and a source region 10 (specifically, an n-type impurity region 21 electrically connected to the source region 10).

[0129] exist Figure 3 and Figure 4 For ease of explanation, the gate terminal G of the MISFET 40 is shown in the SiC epitaxial layer 3 (drain region 5), the trench gate structure 6 (gate electrode 9), and the n-type impurity region 21, respectively. M Leakage extreme D M and source extreme sub-S M .

[0130] JFET41 consists of p －The pnp stack structure of the type 11 well region, n-type impurity region 21, and p-type impurity region 20 and n + A p-type source region 10 is formed. A well region 11 and a p-type impurity region 20 are formed at the same potential and constitute the gate of the JFET 41.

[0131] exist Figure 3 and Figure 4 For ease of explanation, the gate terminal G of JFET41 is shown in p-type impurity region 20, n-type impurity region 21, and source region 10, respectively. J Leakage extreme D J and source extreme sub-S J .

[0132] MISFET40 source extremum S M and the drain terminal D of JFET41 J They are electrically connected to each other. This forms a series circuit including MISFET40 and JFET41. The gate terminal G of JFET41... J and source extreme sub-S J Short-circuited through source electrode 32.

[0133] When a predetermined driving voltage is applied to the gate electrode 9, a channel is formed in the channel formation region 12. As a result, the semiconductor device 1 becomes conductive, and current I flows from the drain electrode 4 to the source electrode 32 via the SiC epitaxial layer 3, the well region 11 (channel formation region 12), the n-type impurity region 21, and the source region 10. D On the other hand, when the semiconductor device 1 is in the off state, no channel is formed in the channel formation region 12, therefore no current I flows between the drain electrode 4 and the source electrode 32. D .

[0134] Reference Figure 3 and Figure 4 A pn junction is formed between the p-type impurity region 20 and the n-type impurity region 21. Additionally, a pn junction is formed between the well region 11 and the n-type impurity region 21.

[0135] A first depletion layer DL1 is formed from the pn junction formed between the p-type impurity region 20 and the n-type impurity region 21. A second depletion layer DL2 is formed from the pn junction formed between the well region 11 and the n-type impurity region 21.

[0136] Reference Figure 3In the non-short-circuit state of semiconductor device 1, the first depletion layer DL1 and the second depletion layer DL2 hardly expand into the n-type impurity region 21. Therefore, a relatively wide current path is formed between the drain electrode 4 and the source electrode 32. Thus, in the non-short-circuit state, the current flowing through the n-type impurity region 21 is hardly hindered by the first depletion layer DL1 and the second depletion layer DL2.

[0137] On the other hand, refer to Figure 4 In the short-circuit state of semiconductor device 1, the first depletion layer DL1 expands from the pn junction formed between the p-type impurity region 20 and the n-type impurity region 21 into the n-type impurity region 21. Additionally, the second depletion layer DL2 expands from the pn junction formed between the well region 11 and the n-type impurity region 21 into the n-type impurity region 21.

[0138] The width W1 of the first depletion layer DL1 gradually increases from the source region 10 side toward the trench gate structure 6 side. Therefore, the width W1 of the first depletion layer DL1 on the trench gate structure 6 side is relatively larger than the width W1 of the first depletion layer DL1 on the source region 10 side.

[0139] Similarly, the width W2 of the second depletion layer DL2 gradually increases from the source region 10 side toward the trench gate structure 6 side. Therefore, the width W2 of the second depletion layer DL2 on the trench gate structure 6 side is relatively larger than the width W2 of the second depletion layer DL2 on the source region 10 side.

[0140] In the short-circuit state of semiconductor device 1, the area of ​​the current path formed in the n-type impurity region 21 is reduced due to the first depletion layer DL1 and the second depletion layer DL2. In this state, the area of ​​the current path formed on the channel formation region 12 side of the n-type impurity region 21 is narrower than the area of ​​the current path formed on the source region 10 side. Therefore, in the short-circuit state of semiconductor device 1, because the area of ​​the current path formed in the n-type impurity region 21 is reduced, the short-circuit current I... D The flow was obstructed.

[0141] As one option, the well region 11, the p-type impurity region 20, and the n-type impurity region 21 can be formed such that the thickness T of the n-type impurity region 21 is... n The width W1 of the first depletion layer DL1 and the width W2 of the second depletion layer DL2 satisfy T n >The formula of W1+W2.

[0142] Alternatively, the well region 11, the p-type impurity region 20, and the n-type impurity region 21 can also be formed such that the thickness T of the n-type impurity region 21 is... n The width W1 of the first depletion layer DL1 and the width W2 of the second depletion layer DL2 satisfy T n The mathematical expression ≤W1+W2.

[0143] In other schemes, the first depletion layer DL1 and the second depletion layer DL2 overlap within the n-type impurity region 21, thus effectively hindering the short-circuit current I. D The flow. It is also possible to combine one of the above schemes with the others to include the flow that satisfies T. n The partial sum of the expression > W1 + W2 satisfies T n The number of regions ≤W1+W2 forms the well region 11, the p-type impurity region 20, and the n-type impurity region 21.

[0144] To compare the drain current I caused by the presence or absence of JFET41 D - Drain voltage V D Due to differences in characteristics, additional preparations were made. Figure 5 The semiconductor device 101 shown has a drain current I. D - Drain voltage V D The characteristic is also the short-circuit current I. D - Short-circuit voltage V D Characteristics. In Figure 5 A cross-sectional view of a semiconductor device 101 of a reference example is shown in the figure.

[0145] The semiconductor device 101 of the reference example does not have the stacked region 22 and has a structure that does not include JFET 41. Figure 5 In the middle, regarding the above-mentioned Figure 2A Structures that are identical to those shown in the diagram are labeled with the same reference symbols, and their descriptions are omitted.

[0146] Figure 6 This indicates that the drain voltage V applied to drain electrode 4 from 0V to 1000V was determined through simulation. D The drain current I flowing between the drain electrode 4 and the source electrode 32 D The result.

[0147] Figure 6 In the middle, the vertical axis represents the drain current I. D [A / cm 2 The horizontal axis represents the drain voltage V. D [V].

[0148] Figure 6 Curves L1 and L2 are shown. Curve L1 represents the drain current I of the semiconductor device 101 in the reference example. D - Drain voltage V D Characteristics. Curve L2 represents the drain current I of the semiconductor device 1 in this embodiment. D - Drain voltage V D characteristic.

[0149] Referring to curve L1, in the semiconductor device 101 of the reference example, as the drain voltage V... D The increase in drain current I D It also increases when the drain voltage V D When the voltage exceeds 50V, the drain current I D Exceeding 10000 A / cm 2 .

[0150] On the other hand, referring to curve L2, in the semiconductor device 1 of this embodiment, when the drain voltage V D When the voltage exceeds 50V, the drain current I D At 5000 A / cm 2 Above but less than 10000 A / cm 2 Saturation within the range.

[0151] Drain voltage V D At 600V, the drain current I of the semiconductor device 1 in this embodiment is... D The drain current I of the semiconductor device 101 in the comparison example D It is reduced by about 70%. Moreover, in the semiconductor device 1 of this embodiment, the increase in on-resistance is basically not visible.

[0152] As described above, in the semiconductor device 1 of this embodiment, a current narrowing portion (i.e., JFET 41) is formed in the region between the channel forming region 12 (well region 11) and the source region 10. As for the current narrowing portion, when it is in a short-circuit state, the current path is narrowed, and when it switches from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0153] Therefore, it is possible to reduce the short-circuit current I under short-circuit conditions. D The voltage is reduced, thus reducing the short-circuit voltage V. D and short-circuit current I D This results in Joule heating. On the other hand, in the non-short-circuit state, the area of ​​the current path does not narrow significantly, thus suppressing the increase in on-resistance caused by the narrowing of the current path. Therefore, a semiconductor device 1 can be provided that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability.

[0154] Next, an example of a method for manufacturing semiconductor device 1 will be described. Figures 7A to 7F It means Figure 1 A cross-sectional view of the manufacturing method of the semiconductor device 1 shown. Figures 7A to 7F Is with Figure 2A A sectional view of the corresponding area.

[0155] Reference Figure 7AFirst, a SiC semiconductor substrate 2 is prepared. Then, SiC is epitaxially grown from the surface of the SiC semiconductor substrate 2. Thus, a SiC epitaxial layer 3 is formed on the SiC semiconductor substrate 2.

[0156] Then, p-type impurities are implanted into the surface portion of the SiC epitaxial layer 3. The implantation of p-type impurities is performed using an ion implantation mask (not shown), which selectively has openings in the region where the well region 11 is to be formed and is formed on the SiC epitaxial layer 3. Thus, the well region 11 is formed in the surface portion of the SiC epitaxial layer 3. After the well region 11 is formed, the ion implantation mask is removed.

[0157] Then, refer to Figure 7B A hard mask 50 is formed on the surface of the SiC epitaxial layer 3. The hard mask 50 selectively has openings 50a in the region where the gate trench 7 is to be formed. The hard mask 50 may also be an insulating film (e.g., a silicon oxide film).

[0158] Then, the surface portion of the SiC epitaxial layer 3 is selectively removed by etching using the hard mask 50. This forms a plurality of gate trenches 7. After the gate trenches 7 are formed, the hard mask 50 is removed.

[0159] Then, refer to Figure 7C For example, a gate insulating film 8 made of silicon oxide can be formed on the inner wall surface of the gate trench 7 by thermal oxidation. The gate insulating film 8 can also be formed by, for example, by depositing insulating material (e.g., silicon oxide and / or silicon nitride) on the inner wall surface of the gate trench 7 using a CVD method.

[0160] Then, electrode material (e.g., polysilicon) is deposited by, for example, CVD to fill the gate trench 7 and cover the SiC epitaxial layer 3. Thus, an electrode material layer covering the SiC epitaxial layer 3 is formed.

[0161] Then, the electrode material layer is selectively etched back. As a result, the gate electrode 9 is formed from the electrode material layer within the gate trench 7.

[0162] Then, refer to Figure 7D Source region 10, p-type impurity region 20 and n-type impurity region 21 are selectively formed on the surface of well region 11.

[0163] Source region 10 is formed by implanting an n-type impurity into the surface portion of well region 11. The implantation of the n-type impurity is performed, for example, by using an ion implantation mask (not shown) that selectively has openings in the region where source region 10 is to be formed.

[0164] The p-type impurity region 20 is formed by implanting p-type impurities into the surface portion of the well region 11. The implantation of p-type impurities is performed, for example, by selectively implanting an ion implantation mask (not shown) with an opening in the region where the p-type impurity region 20 is to be formed.

[0165] The n-type impurity region 21 is formed by implanting an n-type impurity into the surface portion of the well region 11. The implantation of the n-type impurity is performed, for example, by selectively implanting an ion implantation mask (not shown) with an opening in the region where the n-type impurity region 21 is to be formed.

[0166] Then, refer to Figure 7E For example, an insulating material (silicon oxide in this embodiment) is deposited on the SiC epitaxial layer 3 by CVD. As a result, a surface insulating film 30 is formed on the SiC epitaxial layer 3.

[0167] Then, the surface insulating film 30 is selectively removed, for example, by etching. As a result, contact holes 31 are formed in the surface insulating film 30, selectively exposing the source region 10 and the p-type impurity region 20.

[0168] Then, refer to Figure 7F Electrode material (e.g., copper, aluminum, and / or titanium) is deposited on the surface insulating film 30 by, for example, electroplating or sputtering. This forms the source electrode 32.

[0169] Additionally, electrode material (e.g., copper, aluminum, and / or titanium) is deposited on the back side of the SiC semiconductor substrate 2 using methods such as electroplating or sputtering to form a drain electrode 4. Through the above processes, the semiconductor device 1 is manufactured.

[0170] In the above Figure 7D In this paper, an example is described in which the stacked region 22 (p-type impurity region 20 and n-type impurity region 21) is formed after the formation process of the trench gate structure 6. However, these processes can also be changed so that the trench gate structure 6 is formed after the formation process of the stacked region 22 (p-type impurity region 20 and n-type impurity region 21).

[0171] <Second Implementation>

[0172] Figure 8 This is a cross-sectional view of the semiconductor device 51 according to the second embodiment of the present invention. Figure 8 In this document, structures identical to those shown in the first embodiment described above are marked with the same reference numerals, and descriptions are omitted.

[0173] The semiconductor device 51 of this embodiment includes a stacked region 22 in the same way as the first embodiment described above. In the stacked region 22, the n-type impurity region 21 has an epitaxial portion 21a extending below the source region 10.

[0174] The width L of the n-type impurity region 21 including the epitaxial portion 21a nSimilar to the first embodiment described above, the n-type impurity region 21 is formed in a transverse direction parallel to the surface of the SiC epitaxial layer 3, and is wider than the p-type impurity region 20.

[0175] The source region 10 has an epitaxial portion 21a of the n-type impurity region 21 that faces the well region 11. In this embodiment, the epitaxial portion 21a of the n-type impurity region 21 is formed in the entire region below the source region 10. Therefore, the entire region of the source region 10 faces the well region 11 through the epitaxial portion 21a of the n-type impurity region 21.

[0176] In this embodiment, the source region 10 has a thickness T equal to that of the p-type impurity region 20. p Approximately equal thickness T S Unlike the first embodiment described above, source region 10 is not connected to sink region 11.

[0177] Therefore, in this embodiment, in the lateral direction parallel to the surface of the SiC epitaxial layer 3, the p-type impurity region 20 is connected to the source region 10, while the n-type impurity region 21 is not connected to the source region 10.

[0178] The aforementioned MISFET 40 and JFET 41 are formed on the side of the trench gate structure 6. A pn ​​junction is formed between the p-type impurity region 20 and the n-type impurity region 21. Additionally, a pn junction is formed between the well region 11 and the n-type impurity region 21.

[0179] A first depletion layer DL1 is formed from the pn junction formed between the p-type impurity region 20 and the n-type impurity region 21. A second depletion layer DL2 is formed from the pn junction formed between the well region 11 and the n-type impurity region 21.

[0180] In the non-short-circuit state of semiconductor device 51, the first depletion layer DL1 and the second depletion layer DL2 hardly expand into the n-type impurity region 21. Therefore, a relatively wide current path is formed between the drain electrode 4 and the source electrode 32. Consequently, in the non-short-circuit state, the current flowing within the n-type impurity region 21 is hardly impeded by the first depletion layer DL1 and the second depletion layer DL2.

[0181] On the other hand, in the short-circuit state of the semiconductor device 51, the first depletion layer DL1 expands from the pn junction formed between the p-type impurity region 20 and the n-type impurity region 21 into the n-type impurity region 21. Additionally, the second depletion layer DL2 expands from the pn junction formed between the well region 11 and the n-type impurity region 21 into the n-type impurity region 21.

[0182] The first depletion layer DL1 and the second depletion layer DL2 expand into the n-type impurity region 21 in the same manner as the semiconductor device 1 described above. Therefore, in the short-circuit state of the semiconductor device 51, the area of ​​the current path within the n-type impurity region 21 is reduced due to the first depletion layer DL1 and the second depletion layer DL2. Consequently, in the short-circuit state, the short-circuit current I in the n-type impurity region 21... D The flow was obstructed.

[0183] Figure 9 The drain current I of the semiconductor device 51 in this embodiment is represented by... D - Drain voltage V D characteristic. Figure 9 The chart corresponds to the one mentioned above. Figure 6 The chart. Figure 9 Curve L3 and curve L1 described above are shown in the figure. Curve L3 represents the drain current I of the semiconductor device 51 in this embodiment. D - Drain voltage V D characteristic.

[0184] Reference Figure 9 From curve L3, it can be understood that the semiconductor device 51 of this embodiment has a drain current I that is approximately the same as that of the semiconductor device 1 described above. D - Drain voltage V D Features (also refer to) Figure 6 ).

[0185] Therefore, in the semiconductor device 51 of this embodiment, a current narrowing portion (i.e., JFET 41) is formed in the region between the channel formation region 12 (well region 11) and the source region 10. As for the current narrowing portion, when it becomes a short-circuit state, the current path is narrowed, and when it switches from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0186] Therefore, it is possible to reduce the short-circuit current I under short-circuit conditions. D The voltage is reduced, thus reducing the short-circuit voltage V. D and short-circuit current I D This results in Joule heating. On the other hand, in the non-short-circuit state, the area of ​​the current path remains essentially unchanged, thus suppressing the increase in on-resistance caused by the narrowing of the current path. Therefore, a semiconductor device 51 that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided.

[0187] The semiconductor device 51 of this embodiment is manufactured using the same manufacturing method as the semiconductor device 1 of the first embodiment described above. For example, in Figure 7D In the process, the implantation energy of the n-type impurity can be adjusted so that the source region 10 is formed in a shallower region on the surface of the SiC epitaxial layer 3.

[0188] <Third Implementation Method>

[0189] Figure 10 This is a top view of the semiconductor device 61 according to the third embodiment of the present invention. Figure 11A It is along Figure 10 The cross-sectional view of the XIA-XIA line shown. Figure 11B It is along Figure 10 A cross-sectional view of the XIB-XIB line shown. Figure 10 , Figure 11A as well as Figure 11B In this document, structures identical to those shown in the first embodiment described above are marked with the same reference numerals, and descriptions are omitted.

[0190] Reference Figure 10 , Figure 11A as well as Figure 11B In this embodiment, in the surface portion of the SiC epitaxial layer 3, in addition to the trench gate structure 6 described above, a plurality of trench source structures 62 are also formed. Figure 10 The trench gate structure 6 and the trench source structure 62 are shown in cross-section.

[0191] In top view, a trench source structure 62 is formed in the region between one trench gate structure 6 and the other trench gate structure 6. The trench source structure 62 extends in a strip shape along the trench gate structure 6.

[0192] The trench source structure 62 has a structure in which a portion 32a of the source electrode 32 is buried in a source trench 63 formed by selectively digging down into the surface portion of the SiC epitaxial layer 3. In this embodiment, the portion 32a of the source electrode 32 is buried in the source trench 63 through a source insulating film 64. The trench source structure 62 is formed at a depth D of the trench gate structure 6. GT Approximately equal depths D ST .

[0193] The aforementioned source region 10 is formed on the side of the trench gate structure 6 (in the region between the trench gate structure 6 and the trench source structure 62). Figure 10 (the dotted part) and the trap area 11.

[0194] The source region 10 extends in a strip shape along the same direction as the trench gate structure 6, and is formed at intervals from the trench gate structure 6. The source region 10 is connected to the side of the trench source structure 62 in a lateral direction parallel to the surface of the SiC epitaxial layer 3. The source region 10 is connected to the well region 11 in the depth direction of the SiC epitaxial layer 3.

[0195] The well region 11 is formed relative to the source region 10 on the back side of the semiconductor layer in a manner that follows the trench gate structure 6. The well region 11 is formed to the depth at which its boundary with the SiC epitaxial layer 3 connects to the side surface of the trench gate structure 6.

[0196] The well region 11 is formed in the region between adjacent trench gate structures 6 and trench source structures 62. The well region 11 is shared by adjacent trench gate structures 6 and trench source structures 62. The aforementioned channel forming region 12 is formed along the side of the trench gate structure 6.

[0197] In this embodiment, the well region 11 integrally has a source trench side region 65 formed along the side and bottom surfaces of the source trench 63 (trench source structure 62). The bottom of the source trench side region 65 is located in the region between the SiC semiconductor substrate 2 and the bottom surface of the trench source structure 62.

[0198] The source trench side region 65 may also have a p-type impurity concentration that is approximately equal to that of the well region 11. The p-type impurity concentration of the source trench side region 65 may be higher than or lower than that of the well region 11.

[0199] In the trench source configuration 62, the source insulating film 64 covers the SiC epitaxial layer 3 and the well region 11, and is formed in such a way that the source region 10 is exposed. A portion 32a of the source electrode 32 is directly electrically connected within the source trench 63 to the source region 10 exposed from the source trench 63.

[0200] Reference Figure 10 and Figure 11A In the surface portion of the SiC epitaxial layer 3, the aforementioned stacked region 22 is formed in the region between the trench gate structure 6 and the trench source structure 62.

[0201] More specifically, the stacked region 22 is formed in the region between the trench gate structure 6 and the source region 10. The stacked region 22 extends in a strip shape along the trench gate structure 6. The stacked region 22 has the p-type impurity region 20 and the n-type impurity region 21 described above.

[0202] The p-type impurity region 20 is formed on the surface portion of the SiC epitaxial layer 3, exposed from the surface of the SiC epitaxial layer 3. The p-type impurity region 20 is formed in a transverse direction parallel to the surface of the SiC epitaxial layer 3, and is wider than the n-type impurity region 21. The p-type impurity region 20 covers the source region 10 and the n-type impurity region 21.

[0203] More specifically, the p-type impurity region 20 is connected to the trench gate structure 6 and the trench source structure 62 in a lateral direction parallel to the surface of the SiC epitaxial layer 3. Therefore, the p-type impurity region 20 covers the entire region of the source region 10 and the entire region of the n-type impurity region 21.

[0204] The n-type impurity region 21 is formed on the back side of the semiconductor layer relative to the p-type impurity region 20 in the surface portion of the SiC epitaxial layer 3. The n-type impurity region 21 is connected to the well region 11 in the depth direction of the SiC epitaxial layer 3.

[0205] The n-type impurity region 21 is connected to the trench gate structure 6 and the source region 10 in a lateral direction parallel to the surface of the SiC epitaxial layer 3. The thickness T of the n-type impurity region 21 is [not specified in the original text]. n With the thickness T of source region 10 S Approximately equal. The width L of the n-type impurity region 21 n Same as described in the first embodiment above.

[0206] In the trench source configuration 62, the source insulating film 64 exposes not only the source region 10 but also the p-type impurity region 20. Therefore, a portion 32a of the source electrode 32 is directly electrically connected to the p-type impurity region 20 in addition to the source region 10 within the source trench 63.

[0207] Reference Figure 10 and Figure 11B The aforementioned contact region 23 is selectively formed in the stacked region 22 (refer to...). Figure 10 (The dotted line portion). The p-type impurity region 20 is electrically connected to the well region 11 in the contact region 23. Thus, the p-type impurity region 20 is set to have the same potential as the well region 11.

[0208] Reference Figure 11A and Figure 11B The aforementioned surface insulating film 30 is formed on the SiC epitaxial layer 3. The surface insulating film 30 has contact holes 31 that selectively expose the p-type impurity region 20. The aforementioned source electrode 32 is formed on the surface insulating film 30.

[0209] The aforementioned MISFET 40 and JFET 41 are formed on the side of the trench gate structure 6. A pn ​​junction is formed between the p-type impurity region 20 and the n-type impurity region 21. Additionally, a pn junction is formed between the well region 11 and the n-type impurity region 21.

[0210] A first depletion layer DL1 is formed from the pn junction formed between the p-type impurity region 20 and the n-type impurity region 21. A second depletion layer DL2 is formed from the pn junction formed between the well region 11 and the n-type impurity region 21.

[0211] In the non-short-circuit state of semiconductor device 61, the first depletion layer DL1 and the second depletion layer DL2 hardly expand into the n-type impurity region 21. As a result, a relatively wide current path is formed between the drain electrode 4 and the source electrode 32. Therefore, in the non-short-circuit state, the current flowing within the n-type impurity region 21 is hardly impeded by the first depletion layer DL1 and the second depletion layer DL2.

[0212] On the other hand, in the short-circuit state of the semiconductor device 61, the first depletion layer DL1 expands from the pn junction formed between the p-type impurity region 20 and the n-type impurity region 21 into the n-type impurity region 21. Additionally, the second depletion layer DL2 expands from the pn junction formed between the well region 11 and the n-type impurity region 21 into the n-type impurity region 21.

[0213] The first depletion layer DL1 and the second depletion layer DL2 expand into the n-type impurity region 21 in the same manner as the semiconductor device 1 described above. Therefore, in the short-circuit state of the semiconductor device 61, the area of ​​the current path within the n-type impurity region 21 is reduced due to the first depletion layer DL1 and the second depletion layer DL2. Consequently, in the short-circuit state, the short-circuit current I in the n-type impurity region 21... D The circulation of goods was hindered.

[0214] Figure 12 The drain current I of the semiconductor device 61 in this embodiment is represented by... D - Drain voltage V D characteristic. Figure 12 The chart corresponds to the one mentioned above. Figure 6 The chart. In Figure 12 Curve L4 and curve L1 described above are shown in the figure. Curve L4 is the drain current I of the semiconductor device 61 in this embodiment. D - Drain voltage V D characteristic.

[0215] Reference Figure 12 From curve L4, it can be understood that the semiconductor device 61 of this embodiment has a drain current I that is approximately the same as that of the semiconductor device 1 described above. D - Drain voltage V D Features (also refer to) Figure 6 ).

[0216] As described above, in the semiconductor device 61 of this embodiment, a current narrowing portion (i.e., JFET 41) is formed in the region between the channel forming region 12 (well region 11) and the source region 10. As for the current narrowing portion, when it is in a short-circuit state, the current path is narrowed, and when it switches from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0217] Therefore, it is possible to reduce the short-circuit current I under short-circuit conditions. D The voltage is reduced, thus reducing the short-circuit voltage V. D and short-circuit current I D This results in Joule heating. On the other hand, in the non-short-circuit state, the area of ​​the current path remains essentially unchanged, thus suppressing the increase in on-resistance caused by the narrowing of the current path. Therefore, a semiconductor device 51 that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided.

[0218] Next, an example of a method for manufacturing semiconductor device 61 will be described. Figures 13A to 13F It means Figure 10 A cross-sectional view of the manufacturing method of the semiconductor device 61 shown. Figures 13A to 13F Is with Figure 11A A sectional view of the corresponding area.

[0219] First, refer to Figure 13A Prepare a SiC semiconductor substrate 2. Then, grow SiC epitaxially from the surface of the SiC semiconductor substrate 2. Thus, a SiC epitaxial layer 3 is formed on the SiC semiconductor substrate 2.

[0220] Then, a well region 11, a p-type impurity region 20, and an n-type impurity region 21 are formed on the surface of the SiC epitaxial layer 3.

[0221] The well region 11 is formed by implanting an n-type impurity into the surface portion of the SiC epitaxial layer 3. The implantation of the n-type impurity is performed, for example, by selectively implanting an ion implantation mask (not shown) with an opening in the region where the well region 11 is to be formed.

[0222] The p-type impurity region 20 is formed by implanting p-type impurities into the surface portion of the SiC epitaxial layer 3. The implantation of p-type impurities is performed, for example, by using an ion implantation mask (not shown) that selectively has openings in the region where the p-type impurity region 20 is to be formed.

[0223] The n-type impurity region 21 is formed by implanting n-type impurities into the surface portion of the SiC epitaxial layer 3. The implantation of n-type impurities is performed, for example, by selectively using an ion implantation mask (not shown) with an opening in the region where the n-type impurity region 21 is to be formed.

[0224] Then, refer to Figure 13B A hard mask 50 is formed on the surface of the SiC epitaxial layer 3. The hard mask 50 has an opening 50a and an opening 50b. The opening 50a selectively exposes the region where the gate trench 7 is to be formed. The opening 50b selectively exposes the region where the source trench 63 is to be formed.

[0225] Then, the surface portion of the SiC epitaxial layer 3 is selectively removed by etching using the hard mask 50. This forms a plurality of gate trenches 7 and a plurality of source trenches 63. After forming the gate trenches 7 and source trenches 63, the hard mask 50 is removed.

[0226] Then, refer to Figure 13C p-type impurities are selectively implanted into the SiC epitaxial layer 3 exposed from the bottom of the source trench 63. This forms a source trench side region 65 as part of the well region 11. The source trench side region 65 is formed, for example, by implanting p-type impurities into an ion implantation mask (not shown) with an opening selectively in the region where the source trench side region 65 is to be formed.

[0227] Then, a gate insulating film 8 made of silicon oxide is formed on the inner wall surface of the gate trench 7 by, for example, thermal oxidation, and a source insulating film 64 made of silicon oxide is formed on the inner wall surface of the source trench 63. The gate insulating film 8 and the source insulating film 64 can also be formed by CVD. In this case, insulating material (e.g., silicon oxide and / or silicon nitride) is deposited on the inner wall surface of the gate trench 7 and the inner wall surface of the source trench 63.

[0228] Then, electrode material (e.g., polysilicon) is deposited by, for example, CVD to fill the gate trench 7 and cover it with the SiC epitaxial layer 3. Thus, an electrode material layer covering the SiC epitaxial layer 3 is formed.

[0229] Then, the electrode material layer is selectively etched back. As a result, the gate electrode 9 is formed through the electrode material layer within the gate trench 7.

[0230] Then, refer to Figure 13D A portion of the source insulating film 64 formed on the inner wall surface of the source trench 63 is selectively removed, for example, by back etching.

[0231] Then, an n-type impurity is implanted into the inner wall of the source trench 63 exposed from the source insulating film 64 by oblique irradiation. This forms a source region 10 exposed from the inner wall of the source trench 63. By oblique irradiation implantation of the n-type impurity, misalignment of the source region 10 relative to the source trench 63 can be effectively suppressed. This forms a MISFET 40 and a JFET 41 with good switching characteristics.

[0232] Then, refer to Figure 13E An insulating material (silicon oxide in this embodiment) is deposited on the SiC epitaxial layer 3 by, for example, CVD. As a result, a surface insulating film 30 is formed on the SiC epitaxial layer 3.

[0233] The surface insulating film 30 is then selectively removed, for example, by etching. This forms contact holes 31 in the surface insulating film 30, selectively exposing the p-type impurity regions 20.

[0234] Then, refer to Figure 13F Electrode material (e.g., copper, aluminum, and / or titanium) is deposited by means of, for example, electroplating or sputtering, to fill the source trench 63 and cover it with a surface insulating film 30. Thus, the source electrode 32 is formed.

[0235] Additionally, an electrode material (e.g., copper, aluminum, and / or titanium) is deposited on the back side of the SiC semiconductor substrate 2 by means of, for example, electroplating or sputtering, to form a drain electrode 4. Through the above processes, a semiconductor device 61 is manufactured.

[0236] <Fourth Implementation>

[0237] Figure 14 This is a top view of the semiconductor device 71 according to the fourth embodiment of the present invention. Figure 15A It is along Figure 14 The cross-sectional view of the XVA-XVA line shown. Figure 15B It is along Figure 14 The cross-sectional view of the XVB-XVB line shown. Figure 14 , Figure 15A as well as Figure 15B In this document, structures identical to those shown in the first embodiment described above are marked with the same reference numerals, and descriptions are omitted.

[0238] Reference Figure 14 and Figure 15A The semiconductor device 71 of this embodiment includes an n-type impurity region 72. The n-type impurity region 72 is formed on the surface portion of the well region 11 in such a way that it is exposed from the surface of the SiC epitaxial layer 3. A pn ​​junction is formed between the n-type impurity region 72 and the well region 11.

[0239] An n-type impurity region 72 is formed in the region between the trench gate structure 6 and the source region 10, and extends in a strip shape along the trench gate structure 6. The n-type impurity region 72 is connected to the side of the source region 10 and the trench gate structure 6 in a lateral direction parallel to the surface of the SiC epitaxial layer 3. The n-type impurity region 72 is connected to the well region 11 in the depth direction of the SiC epitaxial layer 3.

[0240] Regarding the depth direction of SiC epitaxial layer 3, the thickness T of the n-type impurity region 72 n With the thickness T of source region 10 S They are roughly equal. The n-type impurity concentration in the n-type impurity region 72 is higher than that in the SiC epitaxial layer 3 but lower than that in the source region 10.

[0241] The thickness T of the n-type impurity region 72 n For example, the width L is 0.1 μm or more and 0.2 μm or less (approximately 0.15 μm in this embodiment).n Same as described in the first embodiment above.

[0242] The n-type impurity concentration in n-type impurity region 72 is, for example, 1.0 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 The following (in this embodiment, 1.0 × 10) 18 cm -3 about).

[0243] Reference Figure 14 and Figure 15B The aforementioned contact region 23 is selectively formed in the stacked region 22. The p-type impurity region 20 is electrically connected to the well region 11 in the contact region 23. Thus, the p-type impurity region 20 is set to have the same potential as the well region 11.

[0244] Reference Figure 15A and Figure 15B The surface of the gate electrode 9 buried in the gate trench 7 is covered by a surface insulating film 73 formed within the gate trench 7. This embodiment shows an example where the surface of the surface insulating film 73 is formed as a single surface that is flat (more specifically, surface-uniform) with the surface of the SiC epitaxial layer 3. Alternatively, the surface insulating film 30 described above (see [reference]) can be used instead of the surface insulating film 73. Figure 2A wait).

[0245] Reference Figure 15A and Figure 15B The aforementioned source electrode 32 is formed on the surface of the SiC epitaxial layer 3 in such a way as to cover the surface insulating film 73.

[0246] The source electrode 32 is electrically connected to the source region 10 and the n-type impurity region 72. The source electrode 32 forms a Schottky junction with the n-type impurity region 72 and an ohmic junction with the source region 10.

[0247] Then, refer to Figure 16 and Figure 17 The electrical structure of the semiconductor device 71 will be explained. Figure 16 Is it by Figure 15A The enlarged view of the area enclosed by the dashed line XVI shows the non-short-circuit condition. Figure 17 Is with Figure 16 The enlarged view of the corresponding area represents the short-circuit condition.

[0248] Reference Figure 16 and Figure 17 MISFET40 and JFET41 are formed on the side of the trench gate structure 6. Figure 16 and Figure 17In the diagram, MISFET40 and JFET41 are represented by dashed lines.

[0249] The MISFET40 is formed by a SiC epitaxial layer 3 (drain region 5), a trench gate structure 6 (gate electrode 9), and a source region 10 (specifically, an n-type impurity region 72 electrically connected to the source region 10).

[0250] exist Figure 16 and Figure 17 For ease of explanation, the gate terminal G of the MISFET 40 is shown in the trench gate structure 6 (gate electrode 9), the SiC epitaxial layer 3 (drain region 5), and the n-type impurity region 72, respectively. M Leakage extreme D M and source extreme sub-S M .

[0251] In addition to the source electrode 32, which forms a Schottky junction with the n-type impurity region 72, the JFET41 is also formed by the source region 10, the well region 11, and the n-type impurity region 72. The source electrode 32 and the well region 11 are at the same potential and constitute the gate of the JFET41.

[0252] exist Figure 16 and Figure 17 For ease of explanation, the gate terminal G of JFET41 is shown in the source electrode 32, n-type impurity region 72, and source region 10, respectively. J Leakage extreme D J and source extreme sub-S J .

[0253] MISFET40 source extremum S M and the drain terminal D of JFET41 J They are electrically connected to each other. This forms a series circuit including MISFET40 and JFET41. The gate terminal G of JFET41... J and source extreme sub-S J Short-circuited through source electrode 32.

[0254] When a predetermined driving voltage is applied to the gate electrode 9, a channel is formed in the channel formation region 12. As a result, the semiconductor device 71 becomes conductive, and current I flows from the drain electrode 4 to the source electrode 32 via the SiC epitaxial layer 3, the well region 11 (channel formation region 12), the n-type impurity region 72, and the source region 10. D On the other hand, when the semiconductor device 71 is in the off state, no channel is formed in the channel formation region 12, therefore no current I flows between the drain electrode 4 and the source electrode 32. D .

[0255] Reference Figure 16 and Figure 17A Schottky junction is formed between the source electrode 32 and the n-type impurity region 72. The first depletion layer DL is formed by the Schottky junction formed between the source electrode 32 and the n-type impurity region 72. 11 .

[0256] Additionally, a pn junction is formed between the well region 11 and the n-type impurity region 72. A second depletion layer DL is formed from the pn junction formed between the well region 11 and the n-type impurity region 72. 12 .

[0257] Reference Figure 16 In the non-short-circuit state of semiconductor device 71, the first depletion layer DL 11 and the second depletion layer DL 12 The current hardly extends into the n-type impurity region 72. Therefore, a relatively wide current path is formed between the drain electrode 4 and the source electrode 32. Consequently, in the non-short-circuit state, the current flowing through the n-type impurity region 72 is hardly affected by the first depletion layer DL. 11 and the second depletion layer DL 12 Obstacles.

[0258] On the other hand, refer to Figure 17 In the short-circuit state of semiconductor device 71, the first depletion layer DL 11 It expands from the Schottky junction formed between the source electrode 32 and the n-type impurity region 21 into the n-type impurity region 21. Additionally, the second depletion layer DL... 12 It expands from the pn junction formed between the well region 11 and the n-type impurity region 72 into the n-type impurity region 72.

[0259] First depletion layer DL 11 Width W 11 The layer gradually increases from the source region 10 side towards the trench gate structure 6 side. Therefore, the first depletion layer DL on the trench gate structure 6 side... 11 Width W 11 The first depletion layer DL on the 10th side of the source region is relatively larger. 11 Width W 11 big.

[0260] Similarly, the second depleted layer DL 12 Width W 12 The layer gradually increases from the source region 10 side towards the trench gate structure 6 side. Therefore, the second depletion layer DL on the trench gate structure 6 side... 12 Width W 12 The second depletion layer DL on the 10th side of the source region is relatively larger. 12 Width W 12 big.

[0261] In the short-circuit state of semiconductor device 71, the area of ​​the current path formed in the n-type impurity region 72 is reduced due to the first depletion layer DL. 11 and the second depletion layer DL 12 The area of ​​the current path formed on the side of the channel formation region 12 in the n-type impurity region 72 is narrower than the area of ​​the current path formed on the source region 10. Therefore, in the short-circuit state of the semiconductor device 71, because the area of ​​the current path formed in the n-type impurity region 72 is smaller, the short-circuit current I... D The flow was obstructed.

[0262] As one option, the well region 11 and the n-type impurity region 72 can be formed such that the thickness T of the n-type impurity region 72 is... n First depletion layer DL 11 Width W 11 and the second depletion layer DL 12 Width W 12 Satisfy T n >W 11 +W 12 of numbers.

[0263] Alternatively, the well region 11 and the n-type impurity region 72 can also be formed such that the thickness T of the n-type impurity region 72 is... n First depletion layer DL 11 Width W 11 and the second depletion layer DL 12 Width W 12 Satisfy T n ≤W 11 +W 12 of numbers.

[0264] In other schemes, the first depletion layer DL 11 and the second depletion layer DL 12 They overlap within the n-type impurity region 72, thus effectively hindering the short-circuit current I. D The flow. It is also possible to combine one of the above schemes with the others to include the flow that satisfies T. n >W 11 +W 12 The partial sum of the numerical expression satisfies T n ≤W 11 +W 12 The number of parts forms the well region 11 and the n-type impurity region 72.

[0265] As described above, in the semiconductor device 71 of this embodiment, a current narrowing portion (i.e., JFET 41) is formed in the region between the channel formation region 12 (well region 11) and the source region 10. As for the current narrowing portion, when it is in a short-circuit state, the current path is narrowed, and when it switches from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0266] Therefore, it is possible to reduce the short-circuit current I under short-circuit conditions. D The voltage is reduced, thus reducing the short-circuit voltage V. D and short-circuit current I D This results in Joule heating. On the other hand, in the non-short-circuit state, the area of ​​the current path remains essentially unchanged, thus suppressing the increase in on-resistance caused by the narrowing of the current path. Therefore, a semiconductor device 71 that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided.

[0267] Furthermore, in the semiconductor device 71 of this embodiment, a first depletion layer DL is formed at the Schottky junction between the source electrode 32 and the n-type impurity region 72. 11 Therefore, unlike the embodiments described above, there is no need to form the p-type impurity region 20. This reduces labor time and allows for the provision of a low-cost semiconductor device 71.

[0268] Next, an example of a method for manufacturing semiconductor device 71 will be described. Figures 18A to 18F It means Figure 14 A cross-sectional view of the manufacturing method of the semiconductor device 71 shown. Figures 18A to 18F Is with Figure 15A A sectional view of the corresponding area.

[0269] First, refer to Figure 18A First, prepare a SiC semiconductor substrate 2. Then, grow SiC epitaxially from the surface of the SiC semiconductor substrate 2. Thus, a SiC epitaxial layer 3 is formed on the SiC semiconductor substrate 2.

[0270] Then, p-type impurities are implanted into the surface portion of the SiC epitaxial layer 3. The implantation of p-type impurities is performed by an ion implantation mask (not shown) that selectively has openings in the region where the well region 11 is to be formed and is formed on the surface of the SiC epitaxial layer 3. As a result, the well region 11 is formed in the surface portion of the SiC epitaxial layer 3. After the well region 11 is formed, the ion implantation mask is removed.

[0271] Then, refer to Figure 18B A hard mask 50 is formed on the surface of the SiC epitaxial layer 3. The hard mask 50 selectively has openings 50a in the region where the gate trench 7 is to be formed.

[0272] Then, the surface portion of the semiconductor layer is selectively removed by etching using the hard mask 50. This forms a plurality of gate trenches 7. After the gate trenches 7 are formed, the hard mask 50 is removed.

[0273] Then, refer to Figure 18C For example, a gate insulating film 8 made of silicon oxide can be formed on the inner wall surface of the gate trench 7 by thermal oxidation. The gate insulating film 8 can also be formed by, for example, by depositing insulating material (e.g., silicon oxide and / or silicon nitride) on the inner wall surface of the gate trench 7 using a CVD method.

[0274] Then, electrode material (e.g., polysilicon) is deposited by, for example, CVD to fill the gate trench 7 and cover the SiC epitaxial layer 3. Thus, an electrode material layer covering the SiC epitaxial layer 3 is formed.

[0275] Then, the electrode material layer is selectively etched back. As a result, the gate electrode 9 is formed from the electrode material layer within the gate trench 7.

[0276] Then, refer to Figure 18D The surface of the gate electrode 9 exposed from the gate trench 7 is selectively oxidized by, for example, thermal oxidation. This forms a surface insulating film 73.

[0277] Then, refer to Figure 18E Source region 10 and n-type impurity region 72 are selectively formed on the surface of well region 11.

[0278] Source region 10 is formed by implanting an n-type impurity into the surface portion of well region 11. The implantation of the n-type impurity is performed, for example, by using an ion implantation mask (not shown) that selectively has openings in the region where source region 10 is to be formed.

[0279] The n-type impurity region 72 is formed by implanting an n-type impurity into the surface portion of the well region 11. The implantation of the n-type impurity is performed, for example, by selectively implanting an ion implantation mask (not shown) with an opening in the region where the n-type impurity region 72 is to be formed.

[0280] Then, refer to Figure 18F Electrode materials (e.g., copper, aluminum, and / or titanium) are deposited by means of, for example, electroplating or sputtering, to cover the surface insulating film 73 and the SiC epitaxial layer 3. This forms the source electrode 32.

[0281] Additionally, electrode material (e.g., copper, aluminum, and / or titanium) is deposited on the back side of the SiC semiconductor substrate 2 using methods such as electroplating or sputtering. This forms the drain electrode 4. Through the above processes, the semiconductor device 71 is manufactured.

[0282] <Fifth Implementation>

[0283] Figure 19This is a top view of the semiconductor device 81 according to the fifth embodiment of the present invention. Figure 20A It is along Figure 19 The sectional view of line XXA-XXA shown. Figure 20B It is along Figure 19 The sectional view of the XXB-XXB line shown. Figure 19 , Figure 20A as well as Figure 20B In this document, structures identical to those shown in the first embodiment described above are marked with the same reference numerals, and descriptions are omitted.

[0284] Reference Figure 19 and Figure 20A In the semiconductor device 81 of this embodiment, a plurality of well regions 11 as described above are formed on the surface layer of the SiC epitaxial layer 3. In top view, the plurality of well regions 11 extend in a strip shape along the same direction and are spaced apart from each other. A source region 10 as described above is formed on the surface layer of each well region 11.

[0285] exist Figure 19 The diagram shows an example where the source region 10 is formed in the central part of the inner region of the well region 11 in a top view. The source region 10 extends in a strip along the well region 11 and is formed at intervals from the periphery of the well region 11 toward the inner region side. The source region 10 is exposed from the surface of the SiC epitaxial layer 3.

[0286] The semiconductor device 81 of this embodiment has a planar gate structure and includes a gate electrode 9 formed on the surface of the SiC epitaxial layer 3. The gate electrode 9 is positioned opposite the channel forming region 12 between the periphery of the well region 11 and the periphery of the source region 10, separated by a gate insulating film 8. Figure 19 In the diagram, the channel formation region 12 is represented by dotted cross-sectional lines. The formation of the channels in the channel formation region 12 is controlled by the gate electrode 9.

[0287] The semiconductor device 81 of this embodiment includes a stacked region 84, which is formed on the surface portion of the well region 11 between the channel formation region 12 and the source region 10. The stacked region 84 includes an n-type impurity region 82 formed on the surface portion of the well region 11 and a p-type impurity region 83 formed on the surface portion of the n-type impurity region 82. By providing the stacked region 84, the semiconductor device 81 can suppress the increase of on-resistance and achieve excellent short-circuit withstand capability.

[0288] Reference Figure 19 and Figure 20A The stacked region 84 is formed in a band along the well region 11. The stacked region 84 is formed to a depth approximately equal to that of the source region 10.

[0289] The n-type impurity region 82 is formed on the inner side of the source region 11 at intervals from the periphery of the well region 11 in the region between the periphery of the source region 10 and the periphery of the well region 11. The n-type impurity region 82 forms a pn junction with the well region 11. The channel forming region 12 is formed in the region between the periphery of the n-type impurity region 82 and the periphery of the well region 11.

[0290] The n-type impurity region 82 is connected to the source region 10 and the channel formation region 12 in a lateral direction parallel to the surface of the SiC epitaxial layer 3. The n-type impurity concentration of the n-type impurity region 82 is higher than that of the semiconductor layer and lower than that of the source region 10.

[0291] The gate electrode 9 is positioned opposite the periphery of the well region 11 and the periphery of the n-type impurity region 82 (i.e., the channel forming region 12) across the gate insulating film 8. Thus, a channel is formed in the region between the periphery of the well region 11 and the periphery of the n-type impurity region 82.

[0292] p-type impurity regions 83 are exposed from the surface of the SiC epitaxial layer 3. The p-type impurity regions 83 are formed at intervals from the periphery of the n-type impurity regions 82 in the region between the periphery of the source region 10 and the periphery of the n-type impurity regions 82. The p-type impurity regions 83 form pn junctions with the n-type impurity regions 82.

[0293] The p-type impurity region 83 is connected to the source region 10 in a transverse direction parallel to the surface of the SiC epitaxial layer 3. The p-type impurity concentration in the p-type impurity region 83 is higher than that in the well region 11.

[0294] The values ​​for n-type impurity region 82 and p-type impurity region 83 are supplemented.

[0295] The width W of the n-type impurity region 82 n For example, the width W is 0.06 μm or more and 0.12 μm or less (around 0.09 μm in this embodiment). n Defined as the distance between the periphery of the n-type impurity region 82 and the periphery of the p-type impurity region 83.

[0296] Regarding the depth direction of SiC epitaxial layer 3, the thickness T of the p-type impurity region 83 p For example, it is 0.04 μm or more and 0.08 μm or less (around 0.06 μm in this embodiment).

[0297] Regarding the transverse direction parallel to the surface of the SiC epitaxial layer 3, the width of the n-type impurity region 82 can also be greater than 0.1 μm and less than 0.8 μm.

[0298] The n-type impurity concentration in n-type impurity region 82 is, for example, 1.0 × 10⁻⁶.17 cm -3 Above and 1×10 19 cm -3 The following (in this embodiment, 1.0 × 10) 18 cm -3 about).

[0299] The p-type impurity concentration in region 83 is, for example, 1.0 × 10⁻⁶. 19 cm -3 Above and 1×10 21 cm -3 The following (in this embodiment, 4.0 × 10) 20 cm -3 about).

[0300] Reference Figure 19 and Figure 20B In the stacked region 84, a portion of the region 82 where no n-type impurities are present is selectively formed (refer to...). Figure 19 (The dashed line). The portion of region 82 where no n-type impurities exist is formed as contact region 23.

[0301] The stacked region 84 may also include a region 85 that alternately forms portions of n-type impurity regions 82 and portions of n-type impurity regions 82 along the direction extending from the well region 11.

[0302] The p-type impurity region 20 is electrically connected to the well region 11 in the contact region 23. Thus, the p-type impurity region 20 is set to have the same potential as the well region 11.

[0303] Reference Figure 20A and Figure 20B A surface insulating film 30 is formed on the surface of the SiC epitaxial layer 3. The surface insulating film 30 covers the gate electrode 9. Contact holes 31 are formed in the surface insulating film 30 to selectively expose the source region 10 and the p-type impurity region 83.

[0304] An active electrode 32 is formed on the surface insulating film 30. The source electrode 32 enters the contact hole 31 from the surface insulating film 30. The source electrode 32 is electrically connected to the source region 10 and the p-type impurity region 83 within the contact hole 31. As a result, the source region 10 and the p-type impurity region 83 are short-circuited and have the same potential.

[0305] Alternatively, the source electrode 32 may form an ohmic junction with the source region 10 and also with the p-type impurity region 83. Another option is that the source electrode 32 may form an ohmic junction with the source region 10 and also with the p-type impurity region 83.

[0306] Next, refer to Figure 21 and Figure 22 The electrical structure of the semiconductor device 81 will be explained. Figure 21 Is it by Figure 20A The enlarged view of the area enclosed by the dashed line XXI shows the non-short-circuit condition. Figure 22 Is with Figure 21 The enlarged view of the corresponding area represents the short-circuit condition.

[0307] The non-short-circuit state of semiconductor device 81 refers to the stable state in which a predetermined driving voltage is applied to the gate electrode 9. The short-circuit state of semiconductor device 1 refers to the state in which a predetermined short-circuit voltage (e.g., 200V to 1000V) is applied between the drain electrode 4 and the source electrode 32 while a predetermined driving voltage is applied to the gate electrode 9.

[0308] Reference Figure 21 and Figure 22 MISFET40 and JFET41 are formed in SiC epitaxial layer 3. Figure 21 and Figure 22 In the diagram, MISFET40 and JFET41 are shown with dashed lines.

[0309] The MISFET40 is formed from a SiC epitaxial layer 3 (drain region 5), a gate electrode 9, and a source region 10 (specifically, an n-type impurity region 82 electrically connected to the source region 10).

[0310] exist Figure 21 and Figure 22 For ease of explanation, the gate terminal G of the MISFET 40 is shown in the gate electrode 9, the SiC epitaxial layer 3 (drain region 5), and the n-type impurity region 82, respectively. M Leakage extreme D M and source extreme sub-S M .

[0311] JFET41 consists of p － The pnp stack structure of the type 11 well region, n-type impurity region 82, and p-type impurity region 83 and n + A p-type source region 10 is formed. A p-type impurity region 83 and a well region 11 are at the same potential and constitute the gate of the JFET 41.

[0312] exist Figure 21 and Figure 22 For ease of explanation, the gate terminal G of JFET41 is shown in the p-type impurity region 83, the n-type impurity region 82, and the source region 10, respectively. J Leakage extreme D J and source extreme sub-S J .

[0313] MISFET40 source extremum S Mand the drain terminal D of JFET41 J They are electrically connected to each other. This forms a series circuit including MISFET40 and JFET41. The gate terminal G of JFET41... J and source extreme sub-S J Short-circuited through source electrode 32.

[0314] When a predetermined driving voltage is applied to the gate electrode 9, a channel is formed in the channel formation region 12. As a result, the semiconductor device 81 becomes conductive, and current I flows from the drain electrode 4 to the source electrode 32 via the SiC epitaxial layer 3, the well region 11 (channel formation region 12), the n-type impurity region 82, and the source region 10. D On the other hand, when the semiconductor device 81 is in the off state, no channel is formed in the channel formation region 12, therefore no current I flows between the drain electrode 4 and the source electrode 32. D .

[0315] Reference Figure 21 and Figure 22 A pn junction is formed between the n-type impurity region 82 and the p-type impurity region 83. A first depletion layer DL is formed from the pn junction formed between the n-type impurity region 82 and the p-type impurity region 83. 21 .

[0316] Furthermore, a pn junction is formed between the well region 11 and the n-type impurity region 82. A second depletion layer DL is formed from the pn junction formed between the well region 11 and the n-type impurity region 82. 22 .

[0317] Reference Figure 21 In the non-short-circuit state of semiconductor device 81, the first depletion layer DL 21 and the second depletion layer DL 22 The current hardly extends into the n-type impurity region 82. Therefore, a relatively wide current path is formed between the drain electrode 4 and the source electrode 32. Consequently, in the non-short-circuit state, the current flowing through the n-type impurity region 82 is hardly affected by the first depletion layer DL. 21 and the second depletion layer DL 22 Obstacles.

[0318] On the other hand, refer to Figure 22 In the short-circuit state of semiconductor device 81, the first depletion layer DL 21 It expands from the pn junction formed between the n-type impurity region 82 and the p-type impurity region 83 into the n-type impurity region 21. Additionally, the second depletion layer DL... 22 It expands from the pn junction formed between the well region 11 and the n-type impurity region 82 into the n-type impurity region 21.

[0319] First depletion layer DL 21 Width W 21 The depletion layer gradually increases from the source region 10 towards the gate electrode 9. Therefore, the first depletion layer DL on the gate electrode 9 side... 21 Width W 21 The first depletion layer DL on the 10th side of the source region is relatively larger. 21 Width W 21 big.

[0320] Similarly, the second depleted layer DL 22 Width W 22 The depletion layer gradually increases from the source region 10 towards the gate electrode 9. Therefore, the second depletion layer DL on the gate electrode 9 side... 22 Width W 22 The second depletion layer DL on the 10th side of the source region is relatively larger. 22 Width W 22 big.

[0321] In the short-circuit state of semiconductor device 81, the area of ​​the current path formed in the n-type impurity region 82 is reduced due to the first depletion layer DL. 21 and the second depletion layer DL 22 The area of ​​the current path formed on the side of the channel formation region 12 in the n-type impurity region 82 is narrower than the area of ​​the current path formed on the source region 10. Therefore, in the short-circuit state of the semiconductor device 81, because the area of ​​the current path formed in the n-type impurity region 82 is smaller, the short-circuit current I... D The flow was obstructed.

[0322] As one option, the well region 11, the n-type impurity region 82, and the p-type impurity region 83 can be formed such that the width W of the n-type impurity region 82 is... n First depletion layer DL 21 Width W 21 and the second depletion layer DL 22 Width W 22 Satisfy W n >W 21 +W 22 of numbers.

[0323] Alternatively, the well region 11, the n-type impurity region 82, and the p-type impurity region 83 can also be formed such that the width W of the n-type impurity region 82 is... n First depletion layer DL 21 Width W 21 and the second depletion layer DL 22 Width W 22 Satisfy W n ≤W 21 +W 22 of numbers.

[0324] In other schemes, the first depletion layer DL 21 and the second depletion layer DL 22 They overlap within the n-type impurity region 82, thus effectively hindering the short-circuit current I. D The flow. It is also possible to combine one of the above schemes with the others to include the flow that satisfies W. n >W 21 +W 22 The partial sum of the expression satisfies W n ≤W 21 +W 22 The number of regions is used to form the well region 11, the n-type impurity region 82, and the p-type impurity region 83.

[0325] As described above, in the semiconductor device 81 of this embodiment, a current narrowing portion (i.e., JFET 41) is formed in the region between the channel formation region 12 (well region 11) and the source region 10. As for the current narrowing portion, when it is in a short-circuit state, the current path is narrowed, and when it switches from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0326] Therefore, it is possible to reduce the short-circuit current I under short-circuit conditions. D The voltage is reduced, thus reducing the short-circuit voltage V. D and short-circuit current I D This results in Joule heating. On the other hand, in the non-short-circuit state, the area of ​​the current path remains essentially unchanged, thus suppressing the increase in on-resistance caused by the narrowing of the current path. Therefore, a semiconductor device 81 can be provided that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability.

[0327] <Sixth Implementation Method>

[0328] Figure 23 This is a cross-sectional view of the semiconductor device 91 according to the sixth embodiment of the present invention. Figure 23 In this document, structures identical to those shown in the fifth embodiment described above are marked with the same reference numerals, and descriptions are omitted.

[0329] The semiconductor device 91 in this embodiment is similar to that in the fifth embodiment described above, a stacked region 84 is formed on the surface layer of the well region 11. The stacked region 84 is formed in the region between the channel formation region 12 and the source region 10, and includes the aforementioned n-type impurity region 82 and p-type impurity region 83.

[0330] In this embodiment, the n-type impurity region 82 has an epitaxial portion 82a extending below the source region 10. The source region 10 has a portion that faces the well region 11 across the epitaxial portion 82a of the n-type impurity region 82.

[0331] In this embodiment, the epitaxial portion 82a of the n-type impurity region 82 is formed over the entire region below the source region 10. Therefore, the entire region of the source region 10 is opposite to the well region 11 across the epitaxial portion 82a of the n-type impurity region 82. Unlike the semiconductor device 81 described above, the source region 10 and the well region 11 of the semiconductor device 91 in this embodiment are not connected.

[0332] Regarding the lateral direction parallel to the surface of the SiC epitaxial layer 3, the p-type impurity region 83 is connected to the source region 10, while the n-type impurity region 82 is not connected to the source region 10. Regarding the depth direction of the SiC epitaxial layer 3, the thickness T of the source region 10... S The thickness T of the p-type impurity region 83 p Roughly equal.

[0333] MISFET 40 and JFET 41 are formed in the SiC epitaxial layer 3 in the same manner as the semiconductor device 81 described above. A pn ​​junction is formed between the n-type impurity region 82 and the p-type impurity region 83. In addition, a pn junction is formed between the well region 11 and the n-type impurity region 82.

[0334] The first depletion layer DL is formed by the pn junction formed between the n-type impurity region 82 and the p-type impurity region 83. 21 Additionally, a second depletion layer DL is formed from the pn junction formed between the well region 11 and the n-type impurity region 82. 22 .

[0335] In the non-short-circuit state of semiconductor device 91, the first depletion layer DL 21 and the second depletion layer DL 22 It hardly expands into the n-type impurity region 82. Therefore, a relatively wide current path is formed between the drain electrode 4 and the source electrode 32. Consequently, in the non-short-circuit state, the current flowing within the n-type impurity region 82 is hardly affected by the first depletion layer DL. 21 and the second depletion layer DL 22 Obstacles.

[0336] On the other hand, in the short-circuit state of semiconductor device 91, the first depletion layer DL 21 and the second depletion layer DL 22 It expands into the n-type impurity region 82 in the same manner as the semiconductor device 81 described above. Therefore, in the short-circuit state of the semiconductor device 91, the area of ​​the current path formed in the n-type impurity region 82 is reduced due to the first depletion layer DL. 21 and the second depletion layer DL 22 Therefore, in the short-circuit state of semiconductor device 91, because the area of ​​the current path formed in the n-type impurity region 82 is reduced, the short-circuit current I... D The circulation of goods was hindered.

[0337] As described above, in the semiconductor device 91 of this embodiment, a current narrowing portion (i.e., JFET 41) is formed in the region between the channel formation region 12 (well region 11) and the source region 10. As for the current narrowing portion, when it is in a short-circuit state, the current path is narrowed, and when it switches from a short-circuit state to a non-short-circuit state, the current path is expanded.

[0338] Therefore, it is possible to reduce the short-circuit current I under short-circuit conditions. D The voltage is reduced, thus reducing the short-circuit voltage V. D and short-circuit current I D This results in Joule heating. On the other hand, in the non-short-circuit state, the area of ​​the current path remains essentially unchanged, thus suppressing the increase in on-resistance caused by the narrowing of the current path. Therefore, a semiconductor device 91 that can suppress the increase in on-resistance and achieve excellent short-circuit withstand capability can be provided.

[0339] <Seventh Implementation>

[0340] Figure 24 This is a cross-sectional view showing the semiconductor device 92 according to the seventh embodiment of the present invention. The semiconductor device 92 of this embodiment is the semiconductor device 1 of the first embodiment described above (see reference 1). Figure 2A Examples of variations of (etc.). Figure 24 In this document, structures identical to those described in the first embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0341] In the first embodiment described above, an example of forming a gate insulating film 8 along the inner wall surface of the gate trench 7 was explained. In contrast, in the semiconductor device 92 of this embodiment, as... Figure 24 As shown, the gate insulating film 8 includes a thick film portion 8A on the surface portion of the SiC epitaxial layer 3.

[0342] The thick portion 8A of the gate insulating film 8 is a portion obtained by thickening a part of the gate insulating film 8 laterally along the surface of the SiC epitaxial layer 3. More specifically, the thick portion 8A of the gate insulating film 8 is a portion formed by thickening a part of the gate insulating film 8 to a thickness greater than other portions in a manner that extends from the side of the trench gate structure 6 toward the p-type impurity region 20.

[0343] The thick portion 8A of the gate insulating film 8 has a thickness of, for example, more than 1.5 times that of other portions. The thick portion 8A of the gate insulating film 8 is connected to the p-type impurity region 20 in a transverse direction parallel to the surface of the SiC epitaxial layer 3.

[0344] The thick portion 8A of the gate insulating film 8 may also be connected to the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. Alternatively, the thick portion 8A of the gate insulating film 8 may be formed to transversely cut the boundary between the p-type impurity region 20 and the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. In this case, the thick portion 8A of the gate insulating film 8 may also be connected to the n-type impurity region 21 in a transverse direction parallel to the surface of the SiC epitaxial layer 3. The gate insulating film 8 may also contain silicon oxide.

[0345] In this way, the same effect as described in the first embodiment above can be achieved through this structure.

[0346] <Eighth Implementation Method>

[0347] Figure 25 This is a cross-sectional view showing the semiconductor device 93 according to the eighth embodiment of the present invention. The semiconductor device 93 of this embodiment is the semiconductor device 51 of the second embodiment described above (see reference). Figure 8 (Refer to) a variation of the example. Figure 25 In this document, structures identical to those described in the second embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0348] In the second embodiment described above, an example of forming a gate insulating film 8 along the inner wall surface of the gate trench 7 was given. In contrast, in the semiconductor device 93 of this embodiment, as... Figure 25 As shown, the gate insulating film 8 includes a thick film portion 8A on the surface portion of the SiC epitaxial layer 3.

[0349] The thick portion 8A of the gate insulating film 8 is a portion obtained by thickening a part of the gate insulating film 8 laterally along the surface of the SiC epitaxial layer 3. More specifically, the thick portion 8A of the gate insulating film 8 is a portion formed by thickening a part of the gate insulating film 8 to a thickness greater than other portions in a manner that extends from the side of the trench gate structure 6 toward the p-type impurity region 20.

[0350] The thick portion 8A of the gate insulating film 8 has a thickness of, for example, more than 1.5 times that of other portions. The thick portion 8A of the gate insulating film 8 is connected to the p-type impurity region 20 in a transverse direction parallel to the surface of the SiC epitaxial layer 3.

[0351] The thick portion 8A of the gate insulating film 8 may also be connected to the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. Alternatively, the thick portion 8A of the gate insulating film 8 may be formed to transversely cut the boundary between the p-type impurity region 20 and the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. In this case, the thick portion 8A of the gate insulating film 8 may also be connected to the n-type impurity region 21 in a transverse direction parallel to the surface of the SiC epitaxial layer 3. The gate insulating film 8 may also contain silicon oxide.

[0352] In this way, the same effect as described in the second embodiment above can be achieved through this structure.

[0353] <Ninth Implementation Method>

[0354] Figure 26 This is a cross-sectional view showing the semiconductor device 94 according to the ninth embodiment of the present invention. The semiconductor device 94 of this embodiment is the semiconductor device 61 of the third embodiment described above (see [reference]). Figure 11A Examples of variations of (etc.). Figure 26 In this document, structures identical to those described in the third embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0355] In the third embodiment described above, an example of forming a gate insulating film 8 along the inner wall surface of the gate trench 7 was explained. In contrast, in the semiconductor device 94 of this embodiment, as... Figure 26 As shown, the gate insulating film 8 includes a thick film portion 8A on the surface portion of the SiC epitaxial layer 3.

[0356] The thick portion 8A of the gate insulating film 8 is a portion obtained by thickening a part of the gate insulating film 8 laterally along the surface of the SiC epitaxial layer 3. More specifically, the thick portion 8A of the gate insulating film 8 is a portion formed by thickening a part of the gate insulating film 8 to a thickness greater than other portions in a manner that extends from the side of the trench gate structure 6 toward the p-type impurity region 20.

[0357] The thick portion 8A of the gate insulating film 8 has a thickness of, for example, more than 1.5 times that of other portions. The thick portion 8A of the gate insulating film 8 is connected to the p-type impurity region 20 in a transverse direction parallel to the surface of the SiC epitaxial layer 3.

[0358] The thick film portion 8A of the gate insulating film 8 may also be connected to the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. Alternatively, the thick film portion 8A of the gate insulating film 8 may be formed to transversely cut the boundary between the p-type impurity region 20 and the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. In this case, the thick film portion 8A of the gate insulating film 8 may also be connected to the n-type impurity region 21 in a transverse direction parallel to the surface of the SiC epitaxial layer 3. The gate insulating film 8 may also contain silicon oxide.

[0359] In this way, the same effect as described in the third embodiment above can be achieved.

[0360] <Tenth Implementation>

[0361] Figure 27 This is a cross-sectional view showing the semiconductor device 95 according to the tenth embodiment of the present invention. The semiconductor device 95 of this embodiment is the semiconductor device 61 of the third embodiment described above (see [reference]). Figure 11A Examples of variations of (etc.). Figure 27 In this document, structures identical to those described in the third embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0362] In the third embodiment described above, an example was given where the p-type impurity region 20 covers the entire source region 10. In contrast, in the semiconductor device 95 of this embodiment, as... Figure 27 As shown, a source region 10 is formed, which is exposed not only from the inner surface of the source trench 63 but also from the surface of the SiC epitaxial layer 3.

[0363] Source region 10 is connected to well region 11 along the depth direction of SiC epitaxial layer 3. Regarding the depth direction of SiC epitaxial layer 3, the thickness T of source region 10 is... S For example, it is above 0.1μm and below 0.2μm (in this example, around 0.15μm).

[0364] In addition to being connected to a portion 32a of the source electrode 32 buried in the source trench 63, the source region 10 is also electrically connected to the source electrode 32 formed on the surface of the SiC epitaxial layer 3.

[0365] The stacked regions 22 (p-type impurity region 20 and n-type impurity region 21) are connected to the source region 10 in a lateral direction parallel to the surface of the SiC epitaxial layer 3. The p-type impurity region 20 is exposed from the surface of the SiC epitaxial layer 3 and is connected to the entire region of the n-type impurity region 21 in the depth direction of the SiC epitaxial layer 3. The p-type impurity region 20 and the n-type impurity region 21 are formed with approximately equal widths L in a lateral direction parallel to the surface of the SiC epitaxial layer 3. n .

[0366] In this way, the same effect as described in the third embodiment above can be achieved.

[0367] Furthermore, this structure increases the contact area of ​​the source electrode 32 relative to the source region 10. Therefore, it improves the switching characteristics of both the MISFET 40 and the JFET 41. Needless to say, it also allows for… Figure 27 The structural combination shown Figure 26 The structure shown employs a gate insulating film 8 with a thick film portion 8A.

[0368] <Eleventh Implementation Method>

[0369] Figure 28 This is a cross-sectional view of a semiconductor device 96 according to the eleventh embodiment of the present invention. The semiconductor device 96 of this embodiment has the n-type impurity region 21 (see reference 21) of the semiconductor device 51 of the second embodiment described above. Figure 8 The semiconductor device 61 in the third embodiment described above (see reference) Figure 27 The resulting structure. Figure 28 In this document, structures that are identical to those described in the second and third embodiments above are marked with the same reference numerals, and descriptions are omitted.

[0370] like Figure 28 As shown, the n-type impurity region 21 has an epitaxial portion 21a extending below the source region 10. The source region 10 has a portion opposite the well region 11, separated by the epitaxial portion 21a of the n-type impurity region 21.

[0371] The epitaxial portion 21a of the n-type impurity region 21 can be formed over the entire region below the source region 10. That is, the entire region of the source region 10 can be opposed to the well region 11 through the epitaxial portion 21a of the n-type impurity region 21. The epitaxial portion 21a of the n-type impurity region 21 can also be connected to the trench source structure 62 (source trench 63).

[0372] The above structure can achieve the same effect as described in the second and third embodiments.

[0373] <Twelfth Implementation>

[0374] Figure 29 This is a cross-sectional view showing the semiconductor device 97 according to the twelfth embodiment of the present invention. The semiconductor device 97 of this embodiment is the semiconductor device 61 of the third embodiment described above (see [reference]). Figure 11A Examples of variations of (etc.). Figure 29 In this document, structures identical to those described in the third embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0375] In the third embodiment described above, the trench source structure 62 has a depth D that is the same as that of the trench gate structure 6. GT Equal depth D ST An example was provided. In contrast, in the semiconductor device 97 of this embodiment, the trench source structure 62 has a depth D greater than that of the trench gate structure 6. GT Large depth D ST .

[0376] In this embodiment, the well region 11 does not have the source trench side region 65 described above. However, the well region 11 may also have the source trench side region 65 described above.

[0377] Figure 30 This indicates that the result is obtained through simulation. Figure 29 In the semiconductor device 97 shown, a drain voltage V ranging from 0V to 1000V is applied to the drain electrode 4. D The drain current I flowing between drain electrode 4 and source electrode 32 D The result.

[0378] exist Figure 30 In the middle, the vertical axis represents the drain current I. D [A / cm 2 The horizontal axis represents the drain voltage V. D [V].

[0379] exist Figure 30 The curve L is shown in the figure. 11 And curve L 12 Curve L 11 It has the ability to... Figure 29 The drain current I of a semiconductor device (hereinafter referred to as "the semiconductor device of the reference example") with the structure of the stacked region 22 (p-type impurity region 20 and n-type impurity region 21) removed. D - Drain voltage V D Characteristics. Curve L 12 The drain current I of the semiconductor device 97 in this embodiment D - Drain voltage V D characteristic.

[0380] Reference curve L 11 In the semiconductor device of the reference example, as the drain voltage V... D The increase in drain current I D It also increases, and when the drain voltage V D When the voltage exceeds 100V, the drain current I D Exceeding 8000 A / cm 2 .

[0381] On the other hand, refer to curve L 12In the semiconductor device 97 of this embodiment, when the drain voltage V D When the voltage exceeds 100V, the drain current I D At 6000A / cm 2 Above but less than 7000 A / cm 2 Saturation within the range.

[0382] Drain voltage V D At 600V, the drain current I of the semiconductor device 97 in this embodiment is... D The drain current I of the semiconductor device compared to the reference example D It is reduced by about 45%. Moreover, in the semiconductor device 97 of this embodiment, the increase in on-resistance is almost invisible.

[0383] Based on this structure, the same effect as described in the third embodiment above can be achieved.

[0384] <Thirteenth Implementation Method>

[0385] Figure 31 This is a cross-sectional view showing the semiconductor device 98 according to the thirteenth embodiment of the present invention. The semiconductor device 98 of this embodiment is the semiconductor device 95 of the tenth embodiment described above (see [reference]). Figure 27 A variation of ). Figure 31 In this document, structures that are identical to those described in the tenth embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0386] In the tenth embodiment described above, the trench source structure 62 has a depth D that is the same as that of the trench gate structure 6. GT Equal depth D ST An example was provided. In contrast, in the semiconductor device 98 of this embodiment, the trench source structure 62 has a depth D greater than that of the trench gate structure 6. GT Large depth D ST .

[0387] In this embodiment, the well region 11 does not have the source trench side region 65 described above. However, the well region 11 may also have the source trench side region 65 described above.

[0388] Based on this structure, the same effect as described in the tenth embodiment above can be achieved.

[0389] <Fourteenth Implementation>

[0390] Figure 32 This is a cross-sectional view showing the semiconductor device 99 according to the fourteenth embodiment of the present invention. The semiconductor device 99 of this embodiment is the semiconductor device 96 of the eleventh embodiment described above (see [reference]). Figure 28 A variation of ). Figure 32 In this document, structures identical to those described in the eleventh embodiment above are marked with the same reference numerals, and descriptions are omitted.

[0391] In the eleventh embodiment described above, the trench source structure 62 has a depth D that is the same as that of the trench gate structure 6. GT Equal depth D ST An example was provided. In contrast, in the semiconductor device 98 of this embodiment, the trench source structure 62 has a depth D greater than that of the trench gate structure 6. GT Large depth D ST .

[0392] In this embodiment, the well region 11 does not have the source trench side region 65 described above. However, the well region 11 may also have the source trench side region 65 described above.

[0393] Based on this structure, the same effect as described in the eleventh embodiment above can be achieved.

[0394] <Fifteenth Implementation>

[0395] Figure 33 This is a cross-sectional view showing the semiconductor device 100 according to the fifteenth embodiment of the present invention. The semiconductor device 100 of this embodiment is based on the semiconductor device 71 of the fourth embodiment described above (see...). Figure 14 The trench source structure 62 of the semiconductor device 97 of the twelfth embodiment described above (see reference) combines the above-described trench source structure 62 of the semiconductor device 97. Figure 29 Examples of this. Figure 33 In this document, structures that are identical to those described in the fourth and twelfth embodiments above are marked with the same reference numerals and their descriptions are omitted.

[0396] In this embodiment, the trench source structure 62 has a depth D greater than that of the trench gate structure 6. GT Large depth D ST However, the trench source structure 62 can also have a depth D similar to that of the trench gate structure 6, as described in the third embodiment above. GT Equal depth D ST .

[0397] In this embodiment, the well region 11 does not have the source trench side region 65 described above. However, the well region 11 may also have the source trench side region 65 as described in the third embodiment above.

[0398] Based on this structure, the same effects as those described in the fourth and twelfth embodiments above can be achieved.

[0399] The embodiments of the present invention have been described above, but the present invention can also be implemented in other ways.

[0400] In embodiments containing the trench gate structure 6, the gate trench 7 may also be formed as having a cross-sectional quadrilateral shape that is substantially perpendicular to the surface of the SiC epitaxial layer 3.

[0401] In embodiments containing the trench gate configuration 6, the gate trench 7 may also be formed as a cross-sectional cone shape in which the opening width gradually narrows along its depth direction.

[0402] In embodiments containing the trench gate structure 6, the bottom of the gate trench 7 may also be formed parallel to the surface of the SiC epitaxial layer 3.

[0403] In embodiments containing the trench gate configuration 6, the bottom of the gate trench 7 may also be formed with rounded corners extending outward from its side.

[0404] In embodiments containing the trench gate structure 6, the trench gate structure 6 can be formed in a grid-like shape when viewed from above. In this case, it becomes a structure in which a plurality of trench gate structures 6 extending in a strip along a first direction and a plurality of trench gate structures 6 extending along a second direction intersecting the first direction are integrally formed.

[0405] In an embodiment containing the trench source structure 62, the source trench 63 may be formed as a cross-sectional quadrilateral shape that is substantially perpendicular to the surface of the SiC epitaxial layer 3.

[0406] In embodiments containing the trench source structure 62, the source trench 63 may also be formed as a cross-sectional cone shape in which the opening width gradually narrows along its depth direction.

[0407] In embodiments containing the trench source structure 62, the bottom of the source trench 63 may also be formed parallel to the surface of the SiC epitaxial layer 3.

[0408] In embodiments containing the trench source structure 62, the bottom of the source trench 63 may also be formed with rounded corners extending outward from its side.

[0409] In the above embodiments, the semiconductor layer may replace the SiC semiconductor substrate 2 and the SiC epitaxial layer 3 to include a Si semiconductor substrate containing Si and a Si epitaxial layer containing Si.

[0410] In the embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed can also be adopted. That is, the p-type portion can be made into n-type, and the n-type portion can be made into p-type.

[0411] In the above-described embodiments, n can be replaced+ The SiC semiconductor substrate 2 uses p + The SiC semiconductor substrate 2 is used to replace the MISFET40 to form an IGBT (Insulated Gate Bipolar Transistor).

[0412] In this case, the "source" of MISFET40 is read as the "emitter" of the IGBT. Additionally, the "drain" of MISFET40 is read as the "collector" of the IGBT. Therefore, the drain electrode 4 and drain region 5 of MISFET40 become the collector electrode and collector region of the IGBT. Furthermore, the source electrode 32 and source region 10 of MISFET40 become the emitter electrode and emitter region of the IGBT.

[0413] The structures of the above-described embodiments can also be selectively combined. As an example, the fourth embodiment described above illustrates an example in which a surface insulating film 73 covering the gate electrode 9 is formed. However, in the first to third embodiments described above, the surface insulating film 73 may be formed instead of the surface insulating film 30.

[0414] The semiconductor devices 1, 51, 61, 71, 81, 91, 92, 93, 94, 95, 96, 97, 98, 99, and 100 of the above embodiments can, for example, be fitted with power modules for inverter circuits that drive electric motors used as power sources for automobiles (including electric vehicles), electric trains, industrial robots, air conditioning units, air compressors, fans, vacuum cleaners, dehumidifiers, refrigerators, etc.

[0415] In addition, the semiconductor devices 1, 51, 61, 71, 81, 91, 92, 93, 94, 95, 96, 97, 98, 99, and 100 in the above embodiments can be equipped with power modules for inverter circuits used in solar cells, wind turbines, and other power generation devices, as well as circuit modules that constitute analog control power supplies, digital control power supplies, etc.

[0416] In addition, various design changes can be made within the scope of the claims.

[0417] This application corresponds to Japan Patent Application No. 2016-008834, filed with the Japan Patent Office on January 20, 2016, the entire disclosure of which is incorporated herein by reference.

[0418] The embodiments of the present invention have been described in detail, but these are merely specific examples used to clarify the technical content of the present invention. The present invention is not limited to these specific examples, but its scope is defined only by the claims.

[0419] Symbol Explanation

[0420] 1—Semiconductor device; 2—SiC semiconductor substrate; 3—SiC epitaxial layer; 6—Trench gate structure; 7—Gate trench; 8—Gate insulating film; 9—Gate electrode; 10—Source region; 11—Well region; 12—Channel formation region; 20—P-type impurity region; 21—N-type impurity region; 21a—Epochal portion; 22—Stacked region; 32—Source electrode; 40—MISFET; 41—JFET; 51—Semiconductor device; 61—Semiconductor device; 62—Trench source. Structure, 63—Source trench, 71—Semiconductor device, 72—n-type impurity region, 81—Semiconductor device, 82—n-type impurity region, 82a—Epidermal portion, 83—p-type impurity region, 84—Stacked region, 91—Semiconductor device, 92—Semiconductor device, 93—Semiconductor device, 94—Semiconductor device, 95—Semiconductor device, 96—Semiconductor device, 97—Semiconductor device, 98—Semiconductor device, 99—Semiconductor device, 100—Semiconductor device.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor layer of the first conductivity type, having a main surface as the drain region; A trench gate structure includes a trench formed on the main surface, an insulating film covering the wall of the trench, and a gate electrode embedded in the trench through the insulating film. The source region of the first conductivity type is formed on the side of the trench gate structure in the surface portion of the main surface. The first conductivity type of impurity region is formed in the surface portion of the main surface in the region between the trench gate structure and the source region, and has an impurity concentration lower than that of the source region. A second conductivity type well region, which is formed on the bottom wall side of the trench gate structure relative to the source region and the impurity region at the periphery of the trench gate structure; and A channel is formed in the vicinity of the aforementioned trench gate structure in a lateral direction perpendicular to the depth direction of the aforementioned trench gate structure. If a driving voltage is applied to the gate electrode, current flows through the channel to the current path connecting the semiconductor layer and the impurity region.

2. The semiconductor device according to claim 1, characterized in that, Also includes: A first current path is formed from the semiconductor layer in the longitudinal direction along the depth direction of the trench gate structure. as well as The second current path is formed from the first current path via the channel in the lateral direction perpendicular to the depth direction of the trench gate structure.

3. The semiconductor device according to claim 1, characterized in that, Multiple trench gate structures are spaced apart and formed on the main surface. The aforementioned well region includes a portion of the area between the plurality of aforementioned trench gate structures on the surface of the main surface. The aforementioned channel is formed in the region between the plurality of the aforementioned trench gate structures in the aforementioned lateral direction, which is perpendicular to the depth direction of the plurality of the aforementioned trench gate structures.

4. The semiconductor device according to claim 3, characterized in that, Multiple trench gate structures described above extend in a strip-like manner along the same direction when viewed from above.

5. The semiconductor device according to claim 1, characterized in that, The aforementioned groove, when viewed in cross-section, is a cone shape in which the opening width gradually narrows in the depth direction.

6. The semiconductor device according to claim 5, characterized in that, The aforementioned trench has a bottom wall that is parallel to the aforementioned main surface.

7. The semiconductor device according to claim 1, characterized in that, The aforementioned source region is exposed from the aforementioned main surface.

8. The semiconductor device according to claim 1, characterized in that, It is possible to apply a short-circuit voltage of 200V or more and 1000V or less to the semiconductor layer based on the aforementioned source region. Under the applied short-circuit voltage, short-circuit current flows from the semiconductor layer to the source region via the channel.

9. The semiconductor device according to claim 1, characterized in that, The aforementioned semiconductor layer contains SiC.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The surface portion of the main surface also includes a contact region of a second conductivity type formed on the side of the trench gate structure.

11. The semiconductor device according to claim 10, characterized in that, The contact area is formed on the side of the trench gate structure in such a way that it is opposite to the gate electrode through the insulating film.

12. The semiconductor device according to claim 10, characterized in that, The aforementioned contact area is exposed from the aforementioned main surface.

13. The semiconductor device according to claim 10, characterized in that, The aforementioned contact area is formed by a portion of the aforementioned trap area.

14. The semiconductor device according to any one of claims 1 to 9, characterized in that, It also includes a source electrode, which is formed on the main surface in a manner that is electrically connected to the source region.

15. The semiconductor device according to any one of claims 1 to 9, characterized in that, It also includes a drain electrode, which is connected to the opposite side of the main surface of the semiconductor layer.

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