Storage structure and method for manufacturing same, semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure, comprising a columnar epitaxial structure, a grounding structure, a bit line structure, a columnar capacitor structure and a word line structure, wherein the columnar epitaxial structure extends along a first direction; the grounding structure covers one end of the columnar epitaxial structure; the bit line structure covers the other end of the columnar epitaxial structure; the columnar capacitor structure surrounds the columnar epitaxial structure and is located between the grounding structure and the bit line structure; and the word line structure surrounds the columnar epitaxial structure and is located between the bit line structure and the columnar capacitor structure. By arranging the grounding structure on the columnar epitaxial structure, the electric charges in the columnar epitaxial structure flow away through the grounding structure, thereby avoiding the floating body effect and improving the performance of the semiconductor product.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design and manufacturing technology, and in particular to a memory structure and its fabrication method, and a semiconductor structure. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, the market has placed higher demands on the performance and reliability of semiconductor products. For semiconductor memory devices, the performance of their built-in transistors directly affects the product's storage performance and reliability.

[0003] However, in traditional semiconductor memory devices, the floating body effect of built-in transistors can cause warping, parasitic bipolar transistor effects, anomalous subthreshold slope, and device threshold voltage drift, among other things. These effects not only reduce device gain and lead to device instability, but also decrease leakage breakdown voltage and cause single-transistor latch-up, resulting in larger leakage currents and increased power consumption. Summary of the Invention

[0004] Based on this, this disclosure addresses the problems in the aforementioned background technology by providing a storage structure and its fabrication method, as well as a semiconductor structure, to solve the floating body effect problem of semiconductor transistors.

[0005] According to various embodiments of this disclosure, a first aspect of this disclosure provides a semiconductor structure including a columnar epitaxial structure, a ground structure, a bit line structure, a columnar capacitor structure, and a word line structure. The columnar epitaxial structure extends along a first direction; the ground structure covers one end of the columnar epitaxial structure; the bit line structure covers the other end of the columnar epitaxial structure; the columnar capacitor structure surrounds the columnar epitaxial structure and is located between the ground structure and the bit line structure; the word line structure surrounds the columnar epitaxial structure and is located between the bit line structure and the columnar capacitor structure. By providing a ground structure on the columnar epitaxial structure, the charge in the columnar epitaxial structure flows away through the ground structure, avoiding a floating body effect and improving the performance of the semiconductor product.

[0006] According to some embodiments, the semiconductor structure further includes a capacitor isolation structure surrounding the columnar epitaxial structure and located between the ground structure and the columnar capacitor structure; wherein a portion of the columnar epitaxial structure is covered by the capacitor isolation structure, and the cross-sectional area of ​​the end closer to the ground structure is smaller than the cross-sectional area of ​​the end farther from the ground structure.

[0007] According to some embodiments, the cross-sectional area of ​​the portion of the columnar epitaxial structure covered by the grounding structure is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure covered by the columnar capacitor structure; the grounding structure includes a conductive contact layer and a grounding electrode plate stacked sequentially from the inside to the outside; wherein, the conductive contact layer covers the end of the columnar epitaxial structure away from the bit line structure.

[0008] According to some embodiments, the sum of the lengths of the portions of the columnar epitaxial structure covered by the grounding structure and the capacitor isolation structure is [10nm, 100nm].

[0009] According to some embodiments, the cross-section of the portion of the columnar epitaxial structure covered by the grounding structure is square, and the side length is [1nm, 20nm].

[0010] According to some embodiments, the material of the conductive contact layer includes a metallic conductive material; the material of the grounding electrode includes a metallic conductive material and / or a non-metallic conductive material.

[0011] According to some embodiments, the word line structure includes a gate oxide layer and a gate metal layer stacked sequentially from the inside to the outside; the gate oxide layer surrounds the columnar epitaxial structure; the gate metal layer surrounds the gate oxide layer; wherein, the cross-section of the portion of the columnar epitaxial structure surrounded by the gate oxide layer is square, and the side length is [30nm, 100nm].

[0012] According to some embodiments, the outer boundary line of the gate oxide layer is square, and the thickness of the gate oxide layer is [4.5nm, 8nm].

[0013] According to some embodiments, the outer boundary line of the cross-section of the gate metal layer is square, and the thickness of the gate metal layer is [4nm, 10nm].

[0014] According to some embodiments, the columnar epitaxial structure includes a conductive pillar, a source conductive layer, a channel conductive layer, and a drain conductive layer. The conductive pillar extends along a first direction and is doped with a first type of doping. The source conductive layer covers one end of the conductive pillar and is located between the bit line structure and the conductive pillar, and is doped with a second type of doping. The channel conductive layer surrounds the conductive pillar and is located between the gate oxide layer and the conductive pillar, and is doped with a first type of doping. The drain conductive layer surrounds the conductive pillar and is located between the columnar capacitor structure and the conductive pillar, and is doped with a second type of doping.

[0015] According to some embodiments, a second aspect of this disclosure provides a memory structure, including a substrate and a plurality of target body structures formed on the substrate extending along a second direction and spaced apart along a third direction; the target body structures include a plurality of semiconductor structures spaced apart along the second direction, the semiconductor structures being any of the semiconductor structures in the embodiments of this disclosure; word line structures in adjacent semiconductor structures along the second direction are mutually insulated; bit line structures in adjacent target body structures along the third direction are mutually insulated; wherein, the first direction, the second direction and the third direction are perpendicular to each other.

[0016] According to some embodiments, a third aspect of this disclosure provides a method for fabricating a memory structure, comprising: providing a substrate; forming a plurality of target body structures extending along a second direction and spaced apart along a third direction on the substrate; the target body structures include a plurality of semiconductor structures spaced apart along the second direction, wherein the semiconductor structures are semiconductor structures in any embodiment of this disclosure; word line structures in adjacent semiconductor structures along the second direction are mutually insulated; bit line structures in adjacent target body structures along the third direction are mutually insulated; wherein the first direction, the second direction and the third direction are perpendicular to each other.

[0017] According to some embodiments, a plurality of target body structures extending along a second direction and spaced apart along a third direction are formed on a substrate, including: etching one end of the columnar epitaxial structure away from the bit line structure along a first direction to form an interconnect structure, wherein the cross-sectional area of ​​the interconnect structure is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure covered by the columnar capacitor structure; the cross-section is perpendicular to the first direction; and siliconizing one end of the interconnect structure away from the bit line structure along the first direction to form a conductive contact layer.

[0018] According to some embodiments, after forming the conductive contact layer, the method further includes: forming a capacitor isolation structure, the capacitor isolation structure surrounding the columnar epitaxial structure and located between the conductive contact layer and the columnar capacitor structure; forming a grounding electrode plate, the grounding electrode plate covering the conductive contact layer; wherein the conductive contact layer and the grounding electrode plate constitute a grounding structure; wherein adjacent grounding structures along the second direction are electrically connected; and adjacent grounding structures along the third direction are mutually insulated to form the target body structure.

[0019] According to some embodiments, a plurality of target body structures extending along a second direction and spaced apart along a third direction are formed on a substrate, further comprising: a gate oxide layer and a gate metal layer stacked sequentially from the inside to the outside on a columnar epitaxial structure; the gate oxide layer surrounds the columnar epitaxial structure; the gate metal layer surrounds the gate oxide layer; wherein the cross-section of the portion of the columnar epitaxial structure surrounded by the gate oxide layer is square and the side length is [30nm, 100nm]; the cross-section is perpendicular to the first direction; and / or the outer boundary line of the cross-section of the gate oxide layer is square and the thickness of the gate oxide layer is [4.5nm, 8nm]; and / or the outer boundary line of the cross-section of the gate metal layer is square and the thickness of the gate metal layer is [4nm, 10nm]. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0022] Figure 2a for Figure 1 A schematic diagram of the cross-sectional structure obtained along the AA' direction shown;

[0023] Figure 2b This is a schematic diagram of the cross-sectional structure obtained along the AA' direction in another embodiment of this disclosure;

[0024] Figure 3 This is a schematic flowchart illustrating a method for fabricating a storage structure according to an embodiment of the present disclosure;

[0025] Figures 4-7 This is a schematic diagram of the structure corresponding to different steps in the preparation method of the storage structure provided in one embodiment of the present disclosure, wherein, Figures 4-6 These are schematic diagrams of the 3D images obtained in different steps. Figure 7 for Figure 6 The left view is a schematic diagram; the ox direction is the first direction, the oz direction is the second direction, and the oy direction is the third direction.

[0026] Explanation of reference numerals in the attached figures:

[0027] 100. Substrate; 101. Columnar epitaxial structure; 1011. Conductive pillar; 1012. Source region conductive layer; 1013. Channel region conductive layer; 1014. Drain region conductive layer; 10. Target body structure; 11. Semiconductor structure; 111. Capacitor isolation structure; 112. Columnar capacitor structure; 113. Word line structure; 1131. Gate oxide layer; 1132. Gate metal layer; 20. Bit line structure; 30. Ground structure; 31. Interconnect structure; 32. Conductive contact layer; 33. Ground electrode. Detailed Implementation

[0028] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0032] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0033] Please note that the mutual insulation between the two in the embodiments of this disclosure includes, but is not limited to, the presence of one or more of the following: insulating material, insulating fumes, or gaps.

[0034] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Although the illustrations only show components related to this disclosure and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0035] Please note that in the embodiments of this disclosure, the “cross-sectional area” of the object refers to the area of ​​the cross section perpendicular to the direction of extension of the object.

[0036] A transistor forms a capacitor on the insulating layer, and the charge accumulated on this capacitor can have negative effects. In traditional semiconductor memory devices, the floating body effect of the built-in transistor can cause warping, parasitic bipolar transistor effects, anomalous subthreshold slope, and device threshold voltage drift, among other things. These effects not only reduce device gain and lead to device instability, but also decrease leakage breakdown voltage and cause single-transistor latch-up, resulting in larger leakage currents and increased power consumption.

[0037] This disclosure addresses the aforementioned technical problems by providing a storage structure and its fabrication method, as well as a semiconductor structure, to solve the floating body effect problem of semiconductor transistors.

[0038] In some embodiments of this disclosure, please refer to Figure 1 Figure 2 illustrates a semiconductor structure 10, including a columnar epitaxial structure 101, a ground structure 30, a bit line structure 20, a columnar capacitor structure 112, and a word line structure 113. The columnar epitaxial structure 101 extends along a first direction, such as the ox direction. The ground structure 30 covers one end of the columnar epitaxial structure 101. The bit line structure 20 covers the other end of the columnar epitaxial structure 101. The columnar capacitor structure 112 surrounds the columnar epitaxial structure 101 and is located between the ground structure 30 and the bit line structure 20. The word line structure 113 surrounds the columnar epitaxial structure 101 and is located between the bit line structure 20 and the columnar capacitor structure 112. By providing the ground structure 30 on the columnar epitaxial structure 101, the charge in the columnar epitaxial structure 101 flows away through the ground structure 30, avoiding the floating body effect and improving the performance of the semiconductor product.

[0039] In some embodiments, please continue reading Figure 1Figure 2 shows that the semiconductor structure 10 also includes a capacitor isolation structure 111, which surrounds the columnar epitaxial structure 101 and is located between the grounding structure 30 and the columnar capacitor structure 112. A portion of the columnar epitaxial structure 101 is covered by the capacitor isolation structure 111, and the cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the capacitor isolation structure 111 near the grounding structure 30 is smaller than the cross-sectional area of ​​the portion away from the grounding structure 30. By providing the capacitor isolation structure 111 on the columnar epitaxial structure 101, a sufficient distance is maintained between the columnar capacitor structure 112 and the grounding structure 30, thereby achieving good electrical isolation. Furthermore, the smaller cross-sectional area of ​​the columnar epitaxial structure 101 at the ground connection point compared to the portion away from the ground connection point effectively reduces parasitic capacitance effects.

[0040] In some embodiments, please continue reading Figure 1 - In Figure 2, the cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the grounding structure 30 is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the columnar capacitor structure 112. The grounding structure 30 includes a conductive contact layer 32 and a grounding electrode 33 stacked sequentially from the inside to the outside. The conductive contact layer 32 covers the end of the columnar epitaxial structure 101 away from the bit line structure 20. By setting the conductive contact layer 32 between the columnar epitaxial structure 101 and the grounding electrode 33, a good electrical contact is formed between the columnar epitaxial structure 101 and the grounding electrode 33, reducing the grounding resistance and better ensuring that the charge in the columnar epitaxial structure 101 flows away through the grounding structure 30, thereby improving the performance of the semiconductor product.

[0041] In some embodiments, please continue reading Figure 1 - As shown in Figure 2, the sum of the lengths of the portions of the columnar epitaxial structure 101 covered by the grounding structure 30 and the capacitor isolation structure 111 is [10nm, 100nm]. For example, the sum of the lengths of the portions of the columnar epitaxial structure 101 covered by the grounding structure 30 and the capacitor isolation structure 111 can be 10nm, 30nm, 50nm, 80nm, or 100nm, etc. When conditions permit, a relatively large value can be selected to make the electrical distance between the columnar capacitor structure 112 and the grounding structure 30 greater, so as to prevent mutual interference.

[0042] In some embodiments, please continue reading Figure 1- As shown in Figure 2, the cross-section of the portion of the columnar epitaxial structure 101 covered by the grounding structure 30 is square, and the side length can be [1nm, 20nm]. For example, the side length of the cross-section of the portion of the columnar epitaxial structure 101 covered by the grounding structure 30 can be 1nm, 5nm, 10nm, 15nm, or 20nm, etc. Under the premise of ensuring the structural strength of the columnar epitaxial structure 101, a relatively small value can be selected to reduce the interference between the columnar capacitor structure 112 and the grounding structure 30.

[0043] In some embodiments, please continue reading Figure 1 - As shown in Figure 2, the material of the conductive contact layer 32 may include, but is not limited to, metallic conductive materials; the material of the grounding electrode 33 includes metallic conductive materials and / or non-metallic conductive materials; the metallic conductive materials may include, but are not limited to, one or more of the following: cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), palladium (Pd), ruthenium (Ru), platinum (Pt), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). Non-metallic conductive materials include, but are not limited to, doped polycrystalline silicon.

[0044] In some embodiments, please continue reading Figure 1 - Figure 2 shows that the word line structure 113 includes a gate oxide layer 1131 and a gate metal layer 1132 stacked sequentially from the inside to the outside. The gate oxide layer 1131 surrounds the columnar epitaxial structure 101, and the gate metal layer 1132 surrounds the gate oxide layer 1131. The cross-section of the portion of the columnar epitaxial structure 101 surrounded by the gate oxide layer 1131 is square, and the side length is [30nm, 100nm]. The word line structure 113 is arranged symmetrically around the columnar epitaxial structure 101, which is beneficial to improving the stability of the word line structure 113. The side length of the cross-section of the portion of the columnar epitaxial structure 101 surrounded by the gate oxide layer 1131 can be 30nm, 50nm, 70nm, 90nm, or 100nm, etc. In this embodiment, while ensuring the electrical performance of the word line structure 113, it avoids contact between adjacent word line structures 113 in the stacking direction.

[0045] In some embodiments, please continue reading Figure 1- As shown in Figure 2, the outer boundary line of the cross-section of the gate oxide layer 1131 can be square, and the thickness of the gate oxide layer 1131 is [4.5 nm, 8 nm]. For example, the thickness of the gate oxide layer 1131 can be 4.5 nm, 5.5 nm, 6.5 nm, 7.5 nm, or 8 nm, etc., which ensures gate control on the one hand, reduces gate leakage current on the other hand, and improves gate breakdown voltage. The gate oxide layer 1131 can be formed using a material with a high k dielectric constant. For example, the material of the gate oxide layer 1131 can be one or more of the following, including but not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0046] In some embodiments, please continue reading Figure 1 - As shown in Figure 2, the outer boundary line of the cross-section of the gate metal layer 1132 can be square, and the thickness of the gate metal layer 1132 is [4nm, 10nm]. For example, the thickness of the gate metal layer 1132 can be 4nm, 5nm, 6nm, 8nm, 9nm, or 10nm, etc. This ensures the gate voltage balance of the semiconductor transistor and avoids word line coupling due to the close distance between the upper and lower gates. The gate metal layer 1132 can be any one or more of titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W), etc.

[0047] In some embodiments, please continue reading Figure 1Figure 2 shows a columnar epitaxial structure 101 comprising a conductive pillar 1011, a source conductive layer 1012, a channel conductive layer 1013, and a drain conductive layer 1014. The conductive pillar 1011 extends along a first direction, such as the ox direction, and can be doped using a first type of doping, such as light P-type doping. The source conductive layer 1012 covers one end of the conductive pillar 1011 and is located between the bit line structure 20 and the conductive pillar 1011. It can be doped using a second type of doping, such as heavy N-type doping, to form the source region of the transistor. The channel conductive layer 1013 surrounds the conductive pillar 1011 and is located between the gate oxide layer 1131 and the conductive pillar 1011. It can be doped using a first type of doping, such as heavy P-type doping, to form the channel region of the transistor. The drain conductive layer 1014 surrounds the conductive pillar 1011 and is located between the columnar capacitor structure 112 and the conductive pillar 1011. It can be doped using a second type of doping, such as heavy N-type doping, to form the drain region of the transistor. P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions; N-type impurity ions can include, but are not limited to, any one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions. The conductive post 1011 acts as a grounding wire, allowing the channel region to be directly connected to the ground, providing a release path for accumulated charge.

[0048] In some embodiments, please refer to Figures 3-7 This disclosure provides a method for fabricating a storage structure, comprising:

[0049] Step S22: Provide substrate 100;

[0050] Step S24: Form a plurality of target body structures 11 on the substrate 100 that extend along a second direction, such as the oz direction and are spaced apart along a third direction, such as the oy direction;

[0051] The target body structure 11 includes a plurality of semiconductor structures 10 arranged at intervals along the oz direction. Word line structures 113 in adjacent semiconductor structures 10 along the oz direction are insulated from each other. Bit line structures 20 in adjacent target body structures 11 along the oy direction are insulated from each other. The ox direction, oy direction and oz direction are perpendicular to each other.

[0052] In some embodiments, please continue reading Figure 4A substrate 100 is provided, which may be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the material type of the substrate 100 should not limit the scope of this disclosure. P-type ions can be implanted into the substrate 100 using an ion implantation process to form a first-type doped well region (not shown). The P-type ions can be any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF2) ions, and indium (In) ions. The doping concentration of the first-type doped well region in the substrate 100 can be [1E12cm-3, 1E18cm-3]. For example, the doping concentration of the first-type doped well region can be 1E12cm-3, 1E13cm-3, 1E14cm-3, 1E15cm-3, 1E16cm-3, 1E17cm-3, or 1E18cm-3, etc.

[0053] In some embodiments, please continue reading Figures 4-7 In step S24, a plurality of target body structures 11 extending along the oz direction and spaced apart along the oy direction are formed on the substrate 100, including:

[0054] Step S242: Etch one end of the columnar epitaxial structure 101 away from the bit line structure 20 along a first direction, such as the ox direction, to form an interconnect structure 31. The cross-sectional area of ​​the interconnect structure 31 is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the columnar capacitor structure 112; wherein the cross-section is perpendicular to the ox direction.

[0055] Step S244: Siliconize one end of the interconnect structure 31 away from the bit line structure 20 along a first direction, such as the ox direction, to form a conductive contact layer 32.

[0056] In some embodiments, please continue reading Figure 4In step S242, a wet etching process can be used to remove the end of the columnar epitaxial structure 101 away from the bit line structure 20 along the ox direction, forming the interconnect structure 31. The concentration, flow rate, or etching time of the etching solution can be adjusted. The etching solution includes, but is not limited to, a single solution or a mixture of multiple solutions of phosphoric acid, diluted hydrofluoric acid, diluted sulfuric acid, carbon tetrafluoride (CF4), or sulfur hexafluoride (SF6). The cross-sectional area of ​​the interconnect structure 31 is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the columnar capacitor structure 112. While ensuring structural strength, the cross-sectional area of ​​the interconnect structure 31 should be minimized as much as possible to reduce mutual interference between the columnar capacitor structure 112 and the grounding structure 30.

[0057] In some embodiments, please continue reading Figure 5 In step S244, a layer of conductive metal material is deposited by siliconizing the end of the interconnect structure 31 away from the bit line structure 20 along the ox direction to form a conductive contact layer 32. For example, the specific process can be as follows: First, an oxide layer is deposited on the surface of the columnar epitaxial structure 101 to protect the internal columnar capacitor structure 112 and expose the interconnect structure 31. Second, a conductive metal layer is deposited on both the oxide layer surface and the interconnect structure 31 by siliconization. The material of the conductive metal layer includes, but is not limited to, one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), palladium (Pd), ruthenium (Ru), platinum (Pt), tantalum titanate TaTi, tungsten nitride (WN), copper (Cu) and aluminum (Al). After annealing, the conductive metal layer and oxide layer covering the surface of the columnar capacitor structure 112 and the columnar capacitor structure 112 are etched away, while the conductive metal layer on the surface of the interconnect structure 31 is retained, thereby forming the conductive contact layer 32. Etching processes may include, but are not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP). Deposition processes may include, but are not limited to, one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0058] In some embodiments, please continue reading Figure 6 After forming the conductive contact layer 32 in step S244, the method further includes:

[0059] Step S246: Form a capacitor isolation structure 111, which surrounds the columnar epitaxial structure 101 and is located between the conductive contact layer 32 and the columnar capacitor structure 112.

[0060] Step S248: Form a grounding electrode plate 33, which covers a conductive contact layer 32; wherein the conductive contact layer 32 and the grounding electrode plate 33 constitute a grounding structure 30.

[0061] Figure 6 In the middle, adjacent grounding structures 30 along the second direction, such as the oz direction, are electrically connected; adjacent grounding structures 30 along the third direction, such as the oy direction, are insulated from each other.

[0062] In some embodiments, please continue reading Figure 6 In step S246, a deposition process can be used to form a capacitor isolation structure 111 on the columnar capacitor structure 112 located between the conductive contact layer 32 and the columnar capacitor structure 112. The longer the length of the capacitor isolation structure 111 along the ox direction, the better the isolation effect, and the better it can ensure that there is no electrical interference between the columnar capacitor structure 112 and the grounding structure 30. The capacitor isolation structure 111 can be formed using a material with a low K dielectric constant. For example, the material of the capacitor isolation structure 111 includes, but is not limited to, one or more of fluorine-doped silicon dioxide (SiOF), carbon-doped silicon dioxide (SiOC), organic polymers, or porous materials.

[0063] In some embodiments, please continue reading Figure 6 In step S248, a grounding electrode 33 can be deposited on the outer surface of the conductive contact layer 32 using a deposition process. The material of the grounding electrode 33 can include metallic conductive materials and / or non-metallic conductive materials. Metallic conductive materials include, but are not limited to, one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), palladium (Pd), ruthenium (Ru), platinum (Pt), tantalum titanide (TaTi), tungsten nitride (WN), titanium nitride (TiN), copper (Cu), and aluminum (Al). Non-metallic conductive materials include, but are not limited to, doped polycrystalline silicon. The conductive contact layer 32 and the grounding electrode 33 together constitute the grounding structure 30. Adjacent grounding structures 30 along the oz direction maintain an electrical connection, allowing the semiconductor transistors to form a common ground in the oz direction. This reduces interference between conductive structures in the oz direction, thereby improving the performance of the semiconductor transistors.

[0064] In some embodiments, please continue reading Figure 7 Step S24, which involves forming a plurality of target body structures 11 on the substrate 100 extending along a second direction, such as the oz direction, and spaced apart along a third direction, such as the oy direction, further includes:

[0065] Step S2410: A gate oxide layer 1131 and a gate metal layer 1132 are sequentially stacked from the inside to the outside on the columnar epitaxial structure 101.

[0066] As an example, please continue reading Figure 7 The gate oxide layer 1131 surrounds the columnar epitaxial structure 101; the gate metal layer 1132 surrounds the gate oxide layer 1131; the cross-section of the portion of the columnar epitaxial structure 101 surrounded by the gate oxide layer 1131 is square, and the side length is [30nm, 100nm]; the cross-section is perpendicular to the ox direction; and / or, the outer boundary line of the cross-section of the gate oxide layer 1131 is square, and the thickness of the gate oxide layer 1131 is [4.5nm, 8nm]; and / or, the outer boundary line of the cross-section of the gate metal layer 1132 is square, and the thickness of the gate metal layer 1132 is [4nm, 10nm].

[0067] In some embodiments, please continue reading Figure 7In step S2410, an atomic layer deposition process, a plasma vapor deposition process, or a rapid thermal oxidation (RTO) process can be used to form a gate oxide layer 1131 on the columnar epitaxial structure 101. Then, a gate metal layer 1132 is deposited on the outer surface of the gate oxide layer 1131 to form a word line structure 113. The gate oxide layer 1131 surrounds the columnar epitaxial structure 101, and the gate metal layer 1132 surrounds the gate oxide layer 1131. In the direction perpendicular to the upper surface of the substrate 100, for example, in the oz direction, adjacent word line structures 113 are insulated from each other to facilitate subsequent selection of the desired word line. In the oy direction, ohmic electrical contacts are formed between adjacent word line structures 113 or they are integrally formed. The gate oxide layer 1131 can be formed using a material with a high k dielectric constant. For example, the material of the gate oxide layer 1131 may be one or more of the following, including but not limited to aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The gate metal layer 1132 may be any one or more of the following, including but not limited to titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), and tungsten (W). In this design, the cross-section of the portion of the columnar capacitor structure 112 surrounded by the gate oxide layer 1131 is square, with a side length of [30nm, 100nm]. For example, the side length of the cross-section of the portion of the columnar epitaxial structure 101 surrounded by the gate oxide layer 1131 can be 30nm, 50nm, 70nm, 90nm, or 100nm, etc. To ensure gate control, reduce gate leakage, and increase gate breakdown voltage, the outer boundary line of the cross-section of the gate oxide layer 1131 is square, and the thickness of the gate oxide layer 1131 is [4.5nm, 8nm]. For example, the thickness of the gate oxide layer 1131 can be 4.5nm, 5.5nm, 6.5nm, 7.5nm or 8nm, etc. In order to ensure the gate voltage balance of the semiconductor transistor and avoid word line coupling caused by the close distance between the upper and lower gates, the outer boundary line of the cross section of the gate metal layer 1132 is square, and the thickness of the gate metal layer 1132 is [4nm, 10nm]. For example, the thickness of the gate metal layer 1132 can be 4nm, 5nm, 6nm, 8nm, 9nm or 10nm, etc.

[0068] It should be understood that, although Figure 3The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0069] Please refer to some embodiments of this disclosure. Figure 1 , Figures 6-7 A memory structure is provided, including a substrate 100 and a plurality of target body structures 11 formed on the substrate 100, extending along a second direction, such as the oz direction, and spaced apart along a third direction, such as the oy direction. Each target body structure 11 includes a plurality of semiconductor structures 10 spaced apart along the oz direction. Word line structures 113 in adjacent semiconductor structures 10 along the oz direction are mutually insulated; bit line structures 20 in adjacent target body structures 11 along the oy direction are mutually insulated. The ox direction, oy direction, and oz direction are mutually perpendicular. By providing a grounding structure 30 on the columnar epitaxial structure 101, the charge in the columnar epitaxial structure 101 flows away through the grounding structure 30, avoiding the floating body effect and improving the performance of the semiconductor product.

[0070] As an example, please continue reading Figures 6-7 The semiconductor structure 10 also includes a capacitor isolation structure 111, which surrounds the columnar epitaxial structure 101 and is located between the grounding structure 30 and the columnar capacitor structure 112. The cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the capacitor isolation structure 111 closer to the grounding structure 30 is smaller than the cross-sectional area of ​​the portion farther from the grounding structure 30. By providing the capacitor isolation structure 111 on the columnar epitaxial structure 101, sufficient electrical distance is maintained between the columnar capacitor structure 112 and the grounding structure 30, thereby achieving good electrical isolation. Furthermore, the smaller cross-sectional area of ​​the columnar epitaxial structure 101 at the ground connection point compared to the portion farther from the ground connection point effectively reduces parasitic capacitance effects.

[0071] As an example, please continue reading Figures 6-7The cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the grounding structure 30 is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure 101 covered by the columnar capacitor structure 112. The grounding structure 30 includes a conductive contact layer 32 and a grounding electrode 33 stacked sequentially from the inside to the outside. The conductive contact layer 32 covers the end of the columnar epitaxial structure 101 away from the bit line structure 20. By setting the conductive contact layer 32 between the columnar epitaxial structure 101 and the grounding electrode 33, a good electrical contact is formed between the columnar epitaxial structure 101 and the grounding electrode 33, reducing the grounding resistance and better ensuring that the charge in the columnar epitaxial structure 101 flows away through the grounding structure 30, thereby improving the performance of the semiconductor product.

[0072] In some embodiments, please continue reading Figure 7 The material of the conductive contact layer 32 may include, but is not limited to, metallic conductive materials; the material of the grounding electrode 33 includes metallic conductive materials and / or non-metallic conductive materials; the metallic conductive materials may include, but are not limited to, one or more of cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), palladium (Pd), ruthenium (Ru), platinum (Pt), tantalum titanide (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al). Non-metallic conductive materials include, but are not limited to, doped polycrystalline silicon.

[0073] In some embodiments, please continue reading Figure 7 The word line structure 113 includes a gate oxide layer 1131 and a gate metal layer 1132 stacked sequentially from the inside to the outside. The gate oxide layer 1131 surrounds the columnar epitaxial structure 101. The gate metal layer 1132 surrounds the gate oxide layer 1131. The cross-section of the portion of the columnar epitaxial structure 101 surrounded by the gate oxide layer 1131 is square, and the side length is [30nm, 100nm]. The word line structure 113 is arranged symmetrically around the columnar epitaxial structure 101, which is beneficial to improving the stability of the word line structure 113. The side length of the cross-section of the portion of the columnar epitaxial structure 101 surrounded by the gate oxide layer 1131 can be 30nm, 50nm, 70nm, 90nm, or 100nm, etc. In this embodiment, while ensuring the electrical performance of the word line structure 113, the contact between adjacent word line structures 113 in the stacking direction is avoided.

[0074] In some embodiments, please continue reading Figure 7The semiconductor structure 10 also includes a bit line isolation structure and a word line isolation structure. The bit line isolation structure is located between the bit line structure 20 and the word line structure 113, and surrounds the pillar-shaped epitaxial structure 101, so that the bit line structure 20 and the word line structure 113 are electrically isolated in the ox direction. The material of the bit line isolation structure can include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or silicon oxynitride (SiON). The bit line isolation structure can be formed by chemical vapor deposition. The chemical vapor deposition method can specifically include atomic layer deposition (ALD) and / or plasma enhanced vapor deposition (PECVD). The word line isolation structure is located between the word line structure 113 and the pillar-shaped capacitor structure 112, and surrounds the pillar-shaped epitaxial structure 101, so that the word line structure 113 and the pillar-shaped capacitor structure 112 are electrically isolated in the ox direction. The materials used for word line isolation structures can include, but are not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or silicon oxynitride (SiON). Word line isolation structures can be formed using chemical vapor deposition (CVD). Specific CVD methods can include ALD and / or PECVD.

[0075] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: A columnar extensional structure extending along a first direction; A grounding structure covers one end of the columnar extensional structure; The bitline structure covers the other end of the columnar extension structure; A columnar capacitor structure surrounds the columnar extension structure and is located between the ground structure and the bit line structure; as well as The bit line structure surrounds the columnar extension structure and is located between the bit line structure and the columnar capacitor structure; Also includes: A capacitor isolation structure surrounds the columnar extension structure and is located between the grounding structure and the columnar capacitor structure; In this embodiment, a portion of the columnar epitaxial structure is covered by the capacitor isolation structure, and the cross-sectional area of ​​the end closer to the grounding structure is smaller than the cross-sectional area of ​​the end farther from the grounding structure.

2. The semiconductor structure according to claim 1, characterized in that, The cross-sectional area of ​​the portion of the columnar epitaxial structure covered by the grounding structure is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure covered by the columnar capacitor structure. The grounding structure includes a conductive contact layer and a grounding electrode plate stacked sequentially from the inside to the outside; The conductive contact layer covers the end of the columnar epitaxial structure that is away from the bit line structure.

3. The semiconductor structure according to claim 2, characterized in that, The sum of the lengths of the portions of the columnar epitaxial structure covered by the grounding structure and the capacitor isolation structure is [10nm, 100nm].

4. The semiconductor structure according to claim 2, characterized in that, The cross-section of the portion of the columnar epitaxial structure covered by the grounding structure is square, and the side length is [1nm, 20nm].

5. The semiconductor structure according to claim 2, characterized in that, The material of the conductive contact layer includes a metallic conductive material; The grounding electrode plate is made of metallic conductive materials and / or non-metallic conductive materials.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The word line structure includes a gate oxide layer and a gate metal layer stacked sequentially from the inside out; The gate oxide layer surrounds the columnar epitaxial structure; the gate metal layer surrounds the gate oxide layer; The cross-section of the portion of the columnar epitaxial structure surrounded by the gate oxide layer is square, and the side length is [30nm, 100nm].

7. The semiconductor structure according to claim 6, characterized in that, The outer boundary line of the cross-section of the gate oxide layer is square, and the thickness of the gate oxide layer is [4.5nm, 8nm].

8. The semiconductor structure according to claim 6, characterized in that, The outer boundary line of the cross-section of the gate metal layer is square, and the thickness of the gate metal layer is [4nm, 10nm].

9. The semiconductor structure according to claim 6, characterized in that, The columnar epitaxial structure includes: The conductive pillar extends along the first direction and is doped with the first type of doping. A source region conductive layer, covering one end of the conductive pillar, is located between the bit line structure and the conductive pillar, and is doped with the second type of doping; A channel region conductive layer, surrounding the conductive pillar, is located between the gate oxide layer and the conductive pillar, and is doped using the first type of doping; A drain conductive layer, surrounding the conductive pillar, is located between the columnar capacitor structure and the conductive pillar, and employs the second type of doping.

10. A storage structure, characterized in that, Includes a substrate and a plurality of target body structures formed on the substrate that extend along a second direction and are spaced apart along a third direction; The target body structure includes a plurality of semiconductor structures spaced apart along the second direction, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1-9; word line structures in adjacent semiconductor structures along the second direction are mutually insulated; bit line structures in adjacent target body structures along the third direction are mutually insulated. Wherein, the first direction, the second direction, and the third direction are perpendicular to each other.

11. A method for fabricating a storage structure, characterized in that, include: Provide substrate; Multiple target body structures extending along a second direction and spaced apart along a third direction are formed on the substrate; The target body structure includes a plurality of semiconductor structures spaced apart along the second direction, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1-9; word line structures in adjacent semiconductor structures along the second direction are mutually insulated; bit line structures in adjacent target body structures along the third direction are mutually insulated. Wherein, the first direction, the second direction, and the third direction are perpendicular to each other.

12. The preparation method according to claim 11, characterized in that, Multiple target body structures extending along a second direction and spaced apart along a third direction are formed on the substrate, including: The columnar epitaxial structure is etched at one end away from the bit line structure along the first direction to form an interconnect structure. The cross-sectional area of ​​the interconnect structure is smaller than the cross-sectional area of ​​the portion of the columnar epitaxial structure covered by the columnar capacitor structure. The cross-section is perpendicular to the first direction. The end of the interconnect structure away from the bit line structure along the first direction is siliconized to form a conductive contact layer.

13. The preparation method according to claim 12, characterized in that, After forming the conductive contact layer, the method further includes: A capacitor isolation structure is formed, which surrounds the columnar epitaxial structure and is located between the conductive contact layer and the columnar capacitor structure. A grounding electrode is formed, and the grounding electrode covers the conductive contact layer; wherein, the conductive contact layer and the grounding electrode constitute a grounding structure; The adjacent grounding structures along the second direction are electrically connected; the adjacent grounding structures along the third direction are mutually insulated to form the target body structure.

14. The preparation method according to any one of claims 11-13, characterized in that, The substrate is formed with a plurality of target body structures extending along a second direction and spaced apart along a third direction, and further includes: A gate oxide layer and a gate metal layer are sequentially stacked from the inside to the outside on the columnar epitaxial structure; the gate oxide layer surrounds the columnar epitaxial structure; the gate metal layer surrounds the gate oxide layer. Wherein, the cross-section of the portion of the columnar epitaxial structure surrounded by the gate oxide layer is square, and the side length is [30nm, 100nm]; the cross-section is perpendicular to the first direction; and / or The outer boundary line of the cross-section of the gate oxide layer is square, and the thickness of the gate oxide layer is [4.5nm, 8nm]; and / or The outer boundary line of the cross-section of the gate metal layer is square, and the thickness of the gate metal layer is [4nm, 10nm].

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