Semiconductor memory device

Abstract

This invention provides a semiconductor memory device comprising: a plurality of memory cells arranged in a first direction; a plurality of semiconductor layers arranged in the first direction and electrically connected to the plurality of memory cells; a plurality of gate electrodes arranged in the first direction and facing each of the plurality of semiconductor layers; a gate insulating film disposed between the plurality of semiconductor layers and the plurality of gate electrodes; a first wiring extending in the first direction and connected to the plurality of gate electrodes; and a plurality of second wirings arranged in the first direction and connected to the plurality of semiconductor layers. The plurality of semiconductor layers face each other across the gate insulating film from one side and the other side of the plurality of gate electrodes in the first direction.

Description

[0001] This application is based on the priority interest of Japanese Patent Application No. 2021-049320, filed on March 23, 2021, and claims that interest, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This embodiment relates to a semiconductor memory device. Background Technology

[0003] With the increasing integration of semiconductor memory devices, research has been conducted on the three-dimensionalization of semiconductor memory devices. Summary of the Invention

[0004] One implementation provides a semiconductor memory device that operates appropriately.

[0005] One embodiment of a semiconductor memory device includes: a plurality of memory cells arranged in a first direction; a plurality of semiconductor layers arranged in the first direction and electrically connected to the plurality of memory cells; a plurality of gate electrodes arranged in the first direction and facing each of the plurality of semiconductor layers; a gate insulating film disposed between the plurality of semiconductor layers and the plurality of gate electrodes; a first wiring extending in the first direction and connected to the plurality of gate electrodes; and a plurality of second wirings arranged in the first direction and connected to the plurality of semiconductor layers. The plurality of semiconductor layers face each other across the gate insulating film from one side and the other side of the plurality of gate electrodes in the first direction.

[0006] Based on the above structure, a semiconductor memory device that can operate appropriately can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic circuit diagram showing a portion of the structure of the semiconductor memory device.

[0009] Figure 3 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0010] Figure 4 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0011] Figure 5 It is along line A-A′ Figure 3 and Figure 4 The structure shown is a schematic XZ sectional view observed along the direction of the arrow.

[0012] Figure 6 It is along line B-B' Figure 3 and Figure 4 The structure shown is a schematic YZ sectional view observed along the direction of the arrow.

[0013] Figure 7 It is along the C-C′ line Figure 3 and Figure 4 The structure shown is a schematic YZ sectional view observed along the direction of the arrow.

[0014] Figure 8 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment.

[0015] Figure 9 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0016] Figure 10 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0017] Figure 11 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0018] Figure 12 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0019] Figure 13 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0020] Figure 14 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0021] Figure 15 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0022] Figure 16 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0023] Figure 17 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0024] Figure 18 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0025] Figure 19 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0026] Figure 20It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0027] Figure 21 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0028] Figure 22 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0029] Figure 23 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0030] Figure 24 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0031] Figure 25 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0032] Figure 26 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0033] Figure 27 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0034] Figure 28 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0035] Figure 29 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0036] Figure 30 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0037] Figure 31 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0038] Figure 32 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0039] Figure 33 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0040] Figure 34 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0041] Figure 35 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0042] Figure 36 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0043] Figure 37 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0044] Figure 38 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0045] Figure 39 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0046] Figure 40 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0047] Figure 41 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0048] Figure 42 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0049] Figure 43 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0050] Figure 44 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0051] Figure 45 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0052] Figure 46 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0053] Figure 47 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0054] Figure 48 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device according to the second embodiment.

[0055] Figure 49 This is a schematic circuit diagram showing a portion of the structure of the semiconductor memory device.

[0056] Figure 50 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0057] Figure 51 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0058] Figure 52 It is along line A-A′ Figure 50and Figure 51 The structure shown is a schematic XZ sectional view observed along the direction of the arrow.

[0059] Figure 53 It is along line B-B' Figure 50 and Figure 51 The structure shown is a schematic YZ sectional view observed along the direction of the arrow.

[0060] Figure 54 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment.

[0061] Figure 55 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0062] Figure 56 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0063] Figure 57 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0064] Figure 58 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0065] Figure 59 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0066] Figure 60 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0067] Figure 61 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0068] Figure 62 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0069] Figure 63 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0070] Figure 64 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0071] Figure 65 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0072] Figure 66 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0073] Figure 67It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0074] Figure 68 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device according to the third embodiment.

[0075] Figure 69 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device.

[0076] Figure 70 It is along line A-A′ Figure 68 and Figure 69 The structure shown is a schematic XZ sectional view observed along the direction of the arrow.

[0077] Figure 71 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment.

[0078] Figure 72 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0079] Figure 73 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0080] Figure 74 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0081] Figure 75 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0082] Figure 76 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0083] Figure 77 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0084] Figure 78 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0085] Figure 79 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0086] Figure 80 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0087] Figure 81 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0088] Figure 82It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0089] Figure 83 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0090] Figure 84 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0091] Figure 85 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0092] Figure 86 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0093] Figure 87 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0094] Figure 88 It is a schematic cross-sectional view used to illustrate the manufacturing method.

[0095] Figure 89 It is a schematic cross-sectional view used to illustrate the manufacturing method. Detailed Implementation

[0096] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and sometimes parts of the structure are omitted for ease of explanation. Also, sometimes the same reference numerals are used for parts common to multiple embodiments, and descriptions are omitted.

[0097] Furthermore, when referred to as "semiconductor memory device" in this specification, it sometimes means a memory die, and sometimes it means a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Moreover, it sometimes also means the structure of a host computer, such as a smartphone, tablet, or personal computer.

[0098] Furthermore, in this specification, when the first structure is referred to as being "electrically connected" to the second structure, the first structure and the second structure can be directly connected, or the first structure can be connected to the second structure via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the off state, the first transistor is still "electrically connected" to the third transistor.

[0099] In addition, in this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0100] In addition, in this specification, the direction along the predetermined surface is sometimes referred to as the first direction, the direction along the predetermined surface that intersects the first direction is referred to as the second direction, and the direction that intersects the predetermined surface is referred to as the third direction. These first, second, and third directions may or may not correspond to one of the X, Y, and Z directions.

[0101] Furthermore, in this specification, the terms "upper" and "lower" are used with reference to the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when a structure is referred to as a lower surface or lower end, it signifies the surface or end of the structure on the substrate side; when referred to as an upper surface or upper end, it signifies the surface or end of the structure on the side opposite to the substrate. Furthermore, surfaces intersecting the X or Y direction are called side surfaces, etc.

[0102] [First Implementation]

[0103] [structure]

[0104] Figure 1 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device according to the first embodiment. Figure 2 This is a schematic circuit diagram showing a portion of the structure of the semiconductor memory device. Figure 3 and Figure 4 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device. Furthermore, Figure 3 and Figure 4 This represents a cross-section at different height positions. Figure 5 It is along line A-A′ Figure 3 and Figure 4 The structure shown is a schematic XZ sectional view observed along the direction of the arrow. Figure 6 It is along line B-B' Figure 3 and Figure 4 The structure shown is a schematic YZ sectional view observed along the direction of the arrow. Figure 7 It is along the C-C′ line Figure 3 and Figure 4 The structure shown is a schematic YZ sectional view observed along the direction of the arrow.

[0105] exist Figure 1The text indicates a portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub. The semiconductor substrate Sub is, for example, a semiconductor substrate containing p-type impurities such as boron (B) and silicon (Si).

[0106] like Figure 1 As shown, the memory cell array (MCA) includes a plurality of insulating layers 101 and conductive layers 102 arranged alternately in the X direction. Furthermore, a plurality of memory layers ML arranged in the Z direction and separated by an insulating layer 103, and a plurality of conductive layers 104 extending in the Z direction and arranged in the Y direction, are disposed between the insulating layers 101 and the conductive layers 102. Each memory layer ML includes a plurality of transistor structures 110 disposed along the outer peripheral surface of the plurality of conductive layers 104, a conductive layer 120 disposed between the plurality of transistor structures 110 and the insulating layers 101, and a plurality of capacitor structures 130 disposed between the plurality of transistor structures 110 and the conductive layers 102.

[0107] Insulating layers 101 and 103 may contain, for example, silicon oxide (SiO2).

[0108] The conductive layer 102 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 102 may serve as, for example, a plate line PL (…). Figure 2 ) to perform its function. The board line PL is connected to the common ground of multiple capacitors Cap included in the storage layer ML. In addition, although in Figure 2 The information is omitted in the text, but the board line PL is connected in a shared manner across multiple storage layers ML.

[0109] The conductive layer 104 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 104 may serve as, for example, a word line WL (…). Figure 2 The word lines WL correspond to multiple transistors Tr included in the memory layers ML, and multiple word lines are provided. Furthermore, the word lines WL are shared with the gate electrodes of the multiple transistors Tr corresponding to the multiple memory layers ML.

[0110] For example, Figures 4-6 As shown, the transistor structure 110 includes a conductive layer 111, a conductive layer 112 disposed on the upper surface, lower surface and outer peripheral surface of the conductive layer 111, an insulating layer 113 disposed on the upper surface, lower surface and outer peripheral surface of the conductive layer 112, and a semiconductor layer 114 disposed on the upper surface, lower surface and outer peripheral surface of the insulating layer 113.

[0111] In addition, in such Figure 4 In the illustrated XY cross-section, the two sides of these structures in the X direction can also be connected along the conductive layer 104 ( Figure 3The structure is formed by centered on a circle. Additionally, the two sides of these structures in the Y direction can also be formed in a straight line along the sides of the insulating layer 115.

[0112] Conductive layers 111 and 112 are, for example, used as transistor Tr( Figure 2 The gate electrode functions as such. Conductive layer 111 contains, for example, tungsten (W). Conductive layer 112 contains, for example, titanium nitride (TiN). Figure 5 and Figure 6 As shown, multiple conductive layers 111 and 112 arranged in the Z direction are connected to a conductive layer 104 extending in the Z direction.

[0113] Insulating layer 113, for example, serves as transistor Tr( Figure 2 The gate insulating film of the insulating layer 113 performs its function. The insulating layer 113 contains, for example, silicon oxide (SiO2).

[0114] Semiconductor layer 114, for example, serves as transistor Tr( Figure 2 The channel region functions. Semiconductor layer 114 can be, for example, a semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. Figure 3 As shown, an insulating layer 115, such as silicon oxide (SiO2), is disposed between two adjacent semiconductor layers 114 in the Y direction.

[0115] Conductive layer 120, for example, serves as the bit line BL of the memory cell array MCA. Figure 2 ) to perform its function. For example, Figure 3 As shown, the conductive layer 120 extends in the Y direction and is connected to the X-direction side surface of a plurality of semiconductor layers 114 arranged in the Y direction. For example, as Figure 5 As shown, the conductive layer 120 includes a conductive layer 121, a conductive layer 122 disposed on the upper surface, lower surface, and side surface in the X direction of the conductive layer 121, and a conductive layer 123 disposed on the upper surface, lower surface, and side surface in the X direction of the conductive layer 122. The conductive layer 121 may contain, for example, tungsten (W). The conductive layer 122 may contain, for example, titanium nitride (TiN). The conductive layer 123 may contain, for example, indium tin oxide (ITO).

[0116] For example, Figure 7As shown, the capacitor structure 130 includes a conductive layer 131, a conductive layer 132 disposed on the upper surface, lower surface and side surface in the Y direction of the conductive layer 131, an insulating layer 133 disposed on the upper surface, lower surface and side surface in the Y direction of the conductive layer 132, a conductive layer 134 disposed on the upper surface, lower surface and side surface in the Y direction of the insulating layer 133, an insulating layer 135 disposed on the upper surface, lower surface and side surface in the Y direction of the conductive layer 134, a conductive layer 136 disposed on the upper surface, lower surface and side surface in the Y direction of the insulating layer 135, and a conductive layer 137 disposed on the upper surface, lower surface and side surface in the Y direction of the conductive layer 136.

[0117] Conductive layers 131, 132, 136, and 137 serve as capacitor Cap( Figure 2 The electrode on one side functions. Conductive layers 131 and 137, for example, contain tungsten (W). Conductive layers 132 and 136, for example, contain titanium nitride (TiN). Figure 5 As shown, conductive layers 131, 132, 136, and 137 are connected to conductive layer 102.

[0118] Insulating layers 133 and 135 serve as capacitor Cap( Figure 2 The insulating layer 133 and 135 can be, for example, aluminum oxide (Al2O3) or other insulating metal oxides.

[0119] Conductive layer 134 serves as, for example, a capacitor Cap ( Figure 2 The other electrode functions. The conductive layer 134 includes, for example, indium tin oxide (ITO). The conductive layer 134 is insulated from the conductive layers 131, 132, 136, and 137 through insulating layers 133 and 135. The conductive layer 134 is connected to the X-direction side of the semiconductor layer 114.

[0120] [Manufacturing Method]

[0121] Figures 8 to 47 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the first embodiment. Figure 8 , Figure 10 , Figure 14 , Figure 17 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 , Figure 39 , Figure 42 , Figure 44 as well as Figure 46 Indicates and Figure 5 The corresponding part. Figure 9 , Figure 11 , Figure 13 , Figure 16 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 , Figure 31 , Figure 33 , Figure 35 , Figure 37 as well as Figure 41 Indicates and Figure 4 The corresponding part. Figure 12 , Figure 15 , Figure 18 , Figure 20 , Figure 40 , Figure 43 , Figure 45 as well as Figure 47 Indicates and Figure 6 The corresponding part.

[0122] In this manufacturing method, for example, Figure 8 As shown, multiple insulating layers 103 and multiple sacrificial layers 171 are alternately formed. The sacrificial layers 171 may contain, for example, silicon nitride (Si3N4). This process is performed, for example, by CVD (Chemical Vapor Deposition).

[0123] Next, for example, Figure 9 and Figure 10 As shown, an opening OP1 is formed. (As indicated...) Figure 9 As shown, opening OP1 extends in the X direction and is arranged in the Y direction. Additionally, as... Figure 10 As shown, the opening OP1 extends in the Z direction and penetrates the multiple insulating layers 103 and multiple sacrificial layers 171 arranged in the Z direction. This process is performed, for example, by RIE (Reactive Ion Etching).

[0124] Next, for example, Figure 11 and Figure 12 As shown, an insulating layer 115 is formed. This process is performed, for example, by CVD.

[0125] Next, for example, Figures 13-15 As shown, an opening OP2 is formed at a position corresponding to the conductive layer 104. (As indicated...) Figure 14 and Figure 15 As shown, the opening OP2 extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 171 arranged in the Z direction. This process is performed, for example, by a RIE (Residual Insulation Layer).

[0126] Next, for example, Figures 16-18 As shown, a portion of the sacrificial layer 171 is selectively removed via opening OP2. In this process, the Y-direction side of the insulating layer 115 is exposed inside the opening OP2, thereby separating the sacrificial layer 171 in the X direction. This process is performed, for example, by wet etching.

[0127] Next, for example, Figure 19 and Figure 20 As shown, a sacrificial layer 172 is formed inside the opening OP2. The sacrificial layer 172 may contain, for example, silicon (Si). This process is performed, for example, by CVD.

[0128] Next, for example, Figure 21 and Figure 22 As shown, an opening OP3 is formed at a position corresponding to the conductive layer 102. (As indicated...) Figure 21 As shown, opening OP3 extends in the Y direction and is arranged in the X direction. Additionally, as... Figure 22 As shown, the opening OP3 extends in the Z direction and penetrates the multiple insulating layers 103 and multiple sacrificial layers 171 arranged in the Z direction, separating these structures in the X direction. This process is performed, for example, by a RIE (Reinforcing Interchange).

[0129] Next, for example, Figure 23 and Figure 24 As shown, a portion of the sacrificial layer 171 is selectively removed via opening OP3. In this process, the X-direction side of the sacrificial layer 172 is exposed inside the opening OP3. This process is performed, for example, by wet etching.

[0130] Next, for example, Figure 25 and Figure 26 As shown, through opening OP3, on the side of sacrificial layer 172 in the X direction, on the side of insulating layer 115 in the X and Y directions, and on insulating layer 103 ( Figure 26 A conductive layer 134 is formed on the upper surface, lower surface, and side surface in the X direction of the opening OP3. Additionally, a sacrificial layer 173 is formed inside the opening OP3. The sacrificial layer 173 may contain, for example, silicon (Si). In this process, for example... Figure 26 As shown, the region between two adjacent insulating layers 103 in the Z direction is filled with a sacrificial layer 173. On the other hand, the region between two adjacent insulating layers 103 in the X direction is not filled with a sacrificial layer 173. This process is performed, for example, by ALD (Atomic Layer Deposition) and CVD.

[0131] Next, for example, Figure 27 and Figure 28As shown, a portion of the sacrificial layer 173 and the conductive layer 134 are removed via opening OP3. In this process, for example, a portion of the sacrificial layer 173 is removed, leaving the conductive layer 134 positioned on the insulating layer 115. Figure 27 ) and insulating layer 103 ( Figure 28 The portion of the side facing the X direction of the object is exposed and removed. This process is performed, for example, by wet etching.

[0132] Next, for example, Figure 29 and Figure 30 As shown, the sacrificial layer 173 and the insulating layer 115 are connected through the opening OP3. Figure 29 Part of ) and insulating layer 103 ( Figure 30 A portion of the sacrificial layer 173 is removed. In this process, the sacrificial layer 173 is completely removed. Additionally, the insulating layer 115 ( Figure 29 ) and insulating layer 103 ( Figure 30 The sacrificial layer 172 is removed to a degree that prevents the opening OP3 from being exposed. This process is performed, for example, by wet etching.

[0133] Next, for example, Figure 31 and Figure 32 As shown, insulating layers 133, 135, conductive layers 132, 136, and conductive layers 131, 137, 102 are formed on the upper surface, lower surface, X-direction side surface, and Y-direction side surface of conductive layer 134 via opening OP3. This process is performed, for example, by CVD.

[0134] Next, for example, Figure 33 and Figure 34 As shown, an opening OP4 is formed at a position corresponding to the insulating layer 101. (As indicated...) Figure 33 As shown, opening OP4 extends in the Y direction and is arranged in the X direction. Additionally, as... Figure 34 As shown, the opening OP4 extends in the Z direction and penetrates the multiple insulating layers 103 and multiple sacrificial layers 171 arranged in the Z direction, separating these structures in the X direction. This process is performed, for example, by a RIE (Reinforcing Interchange).

[0135] Next, for example, Figure 35 and Figure 36 As shown, the sacrificial layer 171 is removed via opening OP4. This process is performed, for example, by wet etching.

[0136] Next, for example, Figure 37 and Figure 38As shown, a conductive layer 120 and an insulating layer 101 are formed via an opening OP4. In this process, for example, by ALD or CVD, an insulating layer and a conductive layer are formed in the space between the opening OP4 and the insulating layer 103. At this time, the space between the insulating layers 103 is filled with the conductive layer. On the other hand, the opening OP4 is not filled with the conductive layer. Next, for example, by wet etching, the portions of these insulating and conductive layers located on the inner peripheral surface of the insulating layer 103 are removed. Then, an insulating layer 101 is formed inside the opening 101A.

[0137] Next, for example, Figure 39 and Figure 40 As shown, the sacrificial layer 172 is removed. This process is performed, for example, by wet etching.

[0138] Next, for example, Figures 41-43 As shown, via opening OP2, on the X-direction side surfaces of conductive layer 120 and conductive layer 134, the Y-direction side surface of insulating layer 115, and insulating layer 103 ( Figure 42 , Figure 43 A semiconductor layer 114 is formed on the upper surface, lower surface, and inner peripheral surface of the portion corresponding to the opening OP2. Additionally, a sacrificial layer 174 is formed inside the opening OP2. In this process, for example... Figure 42 and Figure 43 As shown, the area between two adjacent insulating layers 103 in the Z direction is filled with a sacrificial layer 174. On the other hand, the opening OP2 is not filled with the sacrificial layer 174. This process is performed, for example, by ALD and CVD.

[0139] Next, for example, Figure 44 and Figure 45 As shown, a portion of the sacrificial layer 174 and the semiconductor layer 114 are removed via the opening OP2. In this process, for example, a portion of the sacrificial layer 174 is removed, exposing a portion of the semiconductor layer 114 disposed on the inner peripheral surface of the insulating layer 103, and this portion is then removed. This process is performed, for example, by wet etching.

[0140] Next, for example, Figure 46 and Figure 47 As shown, the sacrificial layer 174 is removed via opening OP2. This process is performed, for example, by wet etching.

[0141] Next, for example, Figures 3-6 As shown, an insulating layer 113, a conductive layer 112, a conductive layer 111, and a conductive layer 104 are formed inside the opening OP2. This process is performed, for example, by CVD. Thus, a reference is formed. Figures 1 to 7 The structure is explained.

[0142] [Effect]

[0143] The semiconductor memory device according to this embodiment includes a plurality of semiconductor layers 114 arranged in the Z direction, a plurality of conductive layers 111 and 112 facing the plurality of semiconductor layers 114 respectively, and a conductive layer 104 connected to the plurality of conductive layers 111 and 112. In addition, the plurality of semiconductor layers 114 face the upper surface, lower surface and side surface in the Y direction of the conductive layers 111 and 112 respectively.

[0144] Even with an increased number of memory layers (MLs) included in the memory cell array (MCA), this structure can still be used in the stacking process (see reference). Figure 8 Manufacturing is carried out without increasing the number of processes other than those described. Therefore, high integration can be achieved relatively easily.

[0145] Furthermore, in this structure, the semiconductor layer 114 surrounds the upper surface, lower surface, and Y-direction side surface of the conductive layers 111 and 112. In this structure, channels are formed in the semiconductor layer 114 at the portions opposite the upper surface, the lower surface, and the Y-direction side surface of the conductive layers 111 and 112. Therefore, the on-state current of the transistor Tr can be relatively large. This allows for faster and more stable operation.

[0146] [Second Implementation]

[0147] [structure]

[0148] Figure 48 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device according to the second embodiment. Figure 49 This is a schematic circuit diagram showing a portion of the structure of the semiconductor memory device. Figure 50 and Figure 51 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device. Furthermore, Figure 50 and Figure 51 This represents a cross-section at different height positions. Figure 52 It is along line A-A′ Figure 50 and Figure 51 The structure shown is a schematic XZ sectional view observed along the direction of the arrow. Figure 53 It is along line B-B' Figure 50 and Figure 51 The structure shown is a schematic YZ sectional view observed along the direction of the arrow.

[0149] Furthermore, in the following description, the same reference numerals are assigned to the same structures as in the first embodiment, and the descriptions are omitted.

[0150] exist Figure 48The image shows a portion of a semiconductor substrate Sub and a memory cell array MCA2 disposed above the semiconductor substrate Sub.

[0151] like Figure 48 As shown, the memory cell array MCA2 includes a plurality of insulating layers 101 and conductive layers 102 arranged alternately in the X direction. Furthermore, a plurality of memory layers ML2 arranged in the Z direction and separated by an insulating layer 103 are disposed between the insulating layers 101 and the conductive layers 102, and a plurality of conductive layers 204 extending in the Z direction and arranged in the Y direction. Each memory layer ML2 includes a plurality of transistor structures 210 disposed along the outer peripheral surface of the plurality of conductive layers 204, a conductive layer 220 disposed between the plurality of transistor structures 210 and the insulating layers 101, and a plurality of capacitor structures 130 disposed between the plurality of transistor structures 210 and the conductive layers 102.

[0152] The conductive layer 204 may include, for example, a stacked structure of indium tin oxide (ITO), titanium nitride (TiN), and tungsten (W). The conductive layer 204 may serve as, for example, a bit line BL (…). Figure 49 The bit lines BL and 204 are configured to perform their functions. Multiple bit lines BL are provided, each corresponding to a plurality of transistors Tr within the memory layer ML2. Furthermore, the bit lines BL are sharedly connected to the source electrodes of the plurality of transistors Tr corresponding to the plurality of memory layers ML2. The conductive layer 204 contains, for example, tungsten (W).

[0153] For example, Figures 51-53 As shown, the transistor structure 210 includes an insulating layer 211 disposed on the outer peripheral surface of the conductive layer 204, a conductive layer 212 disposed on the outer peripheral surface of the insulating layer 211, an insulating layer 213 disposed on the upper surface, lower surface and outer peripheral surface of the conductive layer 212, and a semiconductor layer 214 disposed on the upper surface, lower surface and outer peripheral surface of the insulating layer 213.

[0154] In addition, in such Figure 51 In the illustrated XY cross-section, the outer peripheral surface of the insulating layer 211 can, for example, be formed along a circle centered on the center position of the conductive layer 204. Additionally, one side of the conductive layer 212, the insulating layer 213, and the semiconductor layer 214 in the X direction (the conductive layer 102 side) can also be formed along a circle centered on the center position of the conductive layer 204. Furthermore, both sides of the conductive layer 212, the insulating layer 213, and the semiconductor layer 214 in the Y direction can be formed as straight lines along the side of the insulating layer 115.

[0155] The insulating layer 211 may contain, for example, silicon oxide (SiO2). The insulating layer 211 covers the entire circumference of the outer peripheral surface of the conductive layer 204.

[0156] Conductive layer 212, for example, serves as transistor Tr( Figure 49The gate electrode functions as a conductor. The conductive layer 212 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 212 surrounds the outer peripheral surface of the insulating layer 211 throughout its entire circumference. Figure 51 As shown, multiple conductive layers 212 arranged in the Y direction are connected together to a conductive layer 220 extending in the Y direction.

[0157] Insulating layer 213, for example, serves as transistor Tr( Figure 49 The gate insulating film functions as such. The insulating layer 213 contains, for example, silicon oxide (SiO2). The insulating layer 213 covers both sides of the conductive layer 212 in the Y direction and one side in the X direction (the side of the conductive layer 102).

[0158] Semiconductor layer 214, for example, serves as transistor Tr( Figure 49 The channel region functions as a semiconductor layer. The semiconductor layer 214 can be, for example, a semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. The semiconductor layer 214 covers both sides of the conductive layer 212 in the Y direction and one side in the X direction (the conductive layer 102 side) via the insulating layer 213. Figure 52 and Figure 53 As shown, multiple semiconductor layers 214 arranged in the Z direction are collectively connected to a conductive layer 204 extending in the Z direction. Figure 50 As shown, an insulating layer 115, such as silicon oxide (SiO2), is disposed between two adjacent semiconductor layers 214 in the Y direction.

[0159] Conductive layer 220, for example, serves as word line WL of memory cell array MCA2. Figure 49 ) to perform its function. For example, Figure 51 As shown, the conductive layer 220 extends in the Y direction and is connected to a plurality of conductive layers 212 arranged in the Y direction. The conductive layer 220 may have, for example, a stacked structure of indium tin oxide (ITO), titanium nitride (TiN), and tungsten (W). Furthermore, the upper and lower surfaces of the conductive layer 220 are covered by an insulating layer 221 such as silicon oxide (SiO2). The insulating layer 221 is connected to insulating layers 211 and 213.

[0160] [Manufacturing Method]

[0161] Figures 54-67 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the second embodiment. Figure 54 , Figure 55 , Figure 57 , Figure 60 , Figure 62 , Figure 64 as well as Figure 66Indicates and Figure 52 The corresponding part. Figure 56 , Figure 59 , Figure 61 , Figure 63 as well as Figure 65 Indicates and Figure 51 The corresponding part. Figure 58 and Figure 67 Indicates and Figure 53 The corresponding part.

[0162] In this manufacturing method, the reference steps in the manufacturing process of the semiconductor memory device according to the first embodiment are performed. Figure 31 and Figure 32 The procedures that have been explained.

[0163] Next, for example, Figure 54 As shown, the sacrificial layer 172 is removed. This process is performed, for example, by wet etching.

[0164] Next, for example, Figure 55 As shown, via opening OP2, on the X-direction side of sacrificial layer 171 and conductive layer 134, the Y-direction side of insulating layer 115, and insulating layer 103 ( Figure 42 , Figure 43 Semiconductor layers 214 are formed on the upper and lower surfaces of the insulating layer 103. Additionally, a sacrificial layer 174 is formed in the region between two adjacent insulating layers 103 in the Z direction. This process is, for example, similar to a reference. Figures 41-45 The procedures described are performed in the same manner.

[0165] Next, for example, Figures 56-58 As shown, a conductive layer 204 is formed inside the opening OP2. This process is performed, for example, by ALD and CVD.

[0166] Next, for example, Figure 59 and Figure 60 As shown, an opening OP4 is formed at a position corresponding to the insulating layer 101. This process is performed, for example, by means of a RIE (Reinforcing Interchange).

[0167] Next, for example, Figure 61 and Figure 62 As shown, the sacrificial layer 171 is removed via opening OP4. This process is performed, for example, by wet etching.

[0168] Next, for example, Figure 63 and Figure 64 As shown, a portion of the semiconductor layer 214 is removed through the opening OP4, exposing a portion of the sacrificial layer 174. This process is performed, for example, by wet etching.

[0169] Next, for example, Figures 65-67As shown, the sacrificial layer 174 is removed through the opening OP4, exposing the outer peripheral surface of the conductive layer 204. This process is performed, for example, by wet etching.

[0170] Next, for example, Figures 51-53 As shown, insulating layers 211, 213, and 221 are formed inside the opening OP4, conductive layers 212 and 220 are formed, and insulating layer 101 is formed. This process is, for example, similar to the reference... Figure 37 and Figure 38 The procedures described are performed in the same manner. This forms a reference. Figures 48-53 The structure has been explained.

[0171] [Effect]

[0172] The semiconductor memory device according to this embodiment can also achieve the same effect as the semiconductor memory device according to the first embodiment.

[0173] [Third Implementation]

[0174] [structure]

[0175] Figure 68 and Figure 69 This is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device according to the third embodiment. Furthermore, Figure 68 and Figure 69 This represents a cross-section at different height positions. Figure 70 It is along line A-A′ Figure 68 and Figure 69 The structure shown is a schematic XZ sectional view observed along the direction of the arrow.

[0176] Furthermore, in the following description, the same reference numerals are assigned to the same structures as in the first embodiment, and the descriptions are omitted.

[0177] like Figure 68 As shown, the memory cell array MCA3 according to the third embodiment includes a plurality of insulating layers 101 arranged in the X direction. Additionally, as... Figure 70As shown, a plurality of storage layers ML3 arranged in the Z direction, separated by an insulating layer 103, are disposed between two insulating layers 101 arranged in the X direction. Additionally, a plurality of conductive layers 104 and 302 extending in the Z direction and arranged in both the X and Y directions are disposed between the two insulating layers 101 arranged in the X direction. A portion of the plurality of conductive layers 104 is disposed near one of the two insulating layers 101 and arranged in the Y direction. Another portion of the plurality of conductive layers 104 is disposed near the other of the two insulating layers 101 and arranged in the Y direction. Each conductive layer 302 is disposed corresponding to one of the plurality of conductive layers 104. In the illustrated example, two conductive layers 302 are disposed corresponding to one conductive layer 104. The conductive layers 302 are arranged in the X direction with their corresponding conductive layers 104. The storage layer ML3 includes a plurality of transistor structures 110' disposed along the outer peripheral surface of a plurality of conductive layers 104, a conductive layer 120 disposed between the plurality of transistor structures 110' and the insulating layer 101, and a plurality of capacitor structures 330 disposed along the outer peripheral surface of a plurality of conductive layers 302.

[0178] Basically, the transistor structure 110' is configured in the same way as the transistor structure 110 according to the first embodiment. However, in the case of... Figure 69 In the illustrated XY cross section, the outer peripheral surfaces of conductive layer 111, conductive layer 112, insulating layer 113, and semiconductor layer 114 can also extend throughout the entire circumference along the conductive layer 104 ( Figure 68 It is formed by centered on the center of the circle.

[0179] The conductive layer 302 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 302 may serve as, for example, a plate line PL (…). Figure 2 To fulfill its function.

[0180] For example, Figure 70 As shown, the capacitor structure 330 includes a conductive layer 331, an insulating layer 332 disposed on the upper surface, lower surface and side surfaces in the X and Y directions of the conductive layer 331, and a conductive layer 333 disposed on the upper surface, lower surface and side surfaces in the X and Y directions of the insulating layer 332.

[0181] In addition, in such Figure 69 In the illustrated XY cross-section, the outer peripheral surfaces of these structures can also be along the conductive layer 302 ( Figure 68 It is formed by centered on the center of the circle.

[0182] Conductive layer 331 serves as capacitor Cap( Figure 2 One electrode of the conductive layer 331 functions. The conductive layer 331 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). Figure 70As shown, multiple conductive layers 331 arranged in the Z direction are connected together to a conductive layer 302 extending in the Z direction.

[0183] Insulating layer 332 serves as capacitor Cap( Figure 2 The insulating layer 332 can function as an insulating layer. For example, the insulating layer 332 can also be aluminum oxide (Al2O3) or other insulating metal oxides.

[0184] Conductive layer 333, for example, serves as a capacitor Cap ( Figure 2 The other electrode functions. The conductive layer 333 contains, for example, indium tin oxide (ITO). The conductive layer 333 is insulated from the conductive layer 331 through the insulating layer 332. The conductive layer 333 is connected to the side of the semiconductor layer 114 in the X direction.

[0185] [Manufacturing Method]

[0186] Figures 71-89 This is a schematic cross-sectional view used to illustrate the manufacturing method of the semiconductor memory device according to the third embodiment. Figure 71 , Figure 73 , Figure 75 , Figure 77 , Figure 79 , Figure 81 , Figure 84 as well as Figure 87 Indicates and Figure 68 The corresponding part. Figure 82 , Figure 85 as well as Figure 88 Indicates and Figure 69 The corresponding part. Figure 72 , Figure 74 , Figure 76 , Figure 78 , Figure 80 , Figure 83 , Figure 86 as well as Figure 89 Indicates and Figure 70 The corresponding part.

[0187] In this manufacturing method, the reference steps in the manufacturing process of the semiconductor memory device according to the first embodiment are performed. Figure 8 The procedures that have been explained.

[0188] Next, for example, Figure 71 and Figure 72 As shown, an opening OP2 is formed at a position corresponding to the conductive layer 104. This process is performed, for example, by a RIE (Radio Interchange Equipment).

[0189] Next, for example, Figure 73 and Figure 74As shown, a portion of the sacrificial layer 171 is selectively removed via the opening OP2. In this process, the sacrificial layer 171 is removed to a degree that prevents two adjacent openings OP2 in the Y direction from communicating. This process is performed, for example, by wet etching.

[0190] Next, for example, Figure 75 and Figure 76 As shown, a sacrificial layer 172 is formed inside the opening OP2. This process is performed, for example, by CVD.

[0191] Next, for example, Figure 77 and Figure 78 As shown, an opening OP5 is formed at the position corresponding to the conductive layer 302. (As indicated...) Figure 78 As shown, the opening OP5 extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers 171 arranged in the Z direction. This process is performed, for example, by a RIE (Residual Insulation Layer).

[0192] Next, for example, Figure 79 and Figure 80 As shown, a portion of the sacrificial layer 171 is selectively removed via opening OP5. In this process, a portion of the outer peripheral surface of the sacrificial layer 172 is exposed inside opening OP5. Furthermore, in this process, two adjacent openings OP5 in the X direction are interconnected. This process is performed, for example, by wet etching.

[0193] Next, for example, Figures 81-83 As shown, via opening OP5, on the exposed surface of sacrificial layer 171 opposite to opening OP2 (a portion of the inner circumferential surface of opening OP2), insulating layer 103 ( Figure 83 A conductive layer 333 is formed on the upper and lower surfaces of the sample. This process is, for example, similar to that of a reference sample. Figures 41-47 The described process is performed in the same manner. However, in this process, instead of forming the semiconductor layer 114, a conductive layer 333 is formed.

[0194] Next, for example, Figures 84-86 As shown, an insulating layer 332 and a conductive layer 331 are formed inside the opening OP5. This process is performed, for example, by CVD.

[0195] Next, for example, Figures 87-89 As shown, a conductive layer 120 and an insulating layer 101 are formed. This process is, for example, similar to that described in the reference. Figures 33-38 The procedures described are performed in the same manner.

[0196] Next, for example, Figures 68-70 As shown, a transistor structure 110 is formed. This process is, for example, similar to the manufacturing process of a semiconductor memory device according to the first embodiment. Figure 39 and Figure 40The procedures described are then performed in the same manner for subsequent procedures. This forms a reference. Figures 68-70 The structure has been explained.

[0197] [Effect]

[0198] The semiconductor memory device according to this embodiment can also achieve the same effect as the semiconductor memory device according to the first embodiment.

[0199] [Other Implementation Methods]

[0200] The semiconductor memory devices according to the first to third embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely illustrative, and the specific structure, operation, etc., can be appropriately adjusted.

[0201] For example, as referenced Figures 1 to 7 As explained, the semiconductor memory device according to the first embodiment includes a transistor structure 110 and a capacitor structure 130. Additionally, for example, see reference... Figures 48-53 As explained, the semiconductor memory device according to the second embodiment includes a transistor structure 210 and a capacitor structure 130. Additionally, for example, see reference... Figures 68-70 As explained, the semiconductor memory device according to the third embodiment includes a transistor structure 110' and a capacitor structure 330. However, this structure is merely illustrative, and the specific structure can be appropriately adjusted. For example, the semiconductor memory device according to the third embodiment may not have a transistor structure 110', but instead has a transistor structure 210 (…). Figures 48-53 ).

[0202] Furthermore, the above description provided an example of connecting capacitor Cap in transistor structures 110 and 210. In such an example, the shape and structure of capacitor Cap can be adjusted appropriately.

[0203] Furthermore, in the above description, an example of using a capacitor Cap as a storage unit connected to transistor structures 110 and 210 was described. However, the storage unit may not be a capacitor Cap. For example, the storage unit may be a storage unit containing a chalcogenide material such as ferroelectric or ferromagnetic, GeSbTe, or other materials, and utilizing the properties of these materials to record data. For example, in any of the structures described above, the insulating layer between the electrodes forming the capacitor Cap may contain any of these materials.

[0204] [other]

[0205] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: Multiple storage units are arranged in the first direction; Multiple semiconductor layers are arranged in the first direction and electrically connected to the multiple memory units; A plurality of gate electrodes are arranged in the first direction and respectively facing the plurality of semiconductor layers; A gate insulating film is disposed between the plurality of semiconductor layers and the plurality of gate electrodes; A first wiring extends in the first direction and is connected to the plurality of gate electrodes; as well as Multiple second wirings, arranged in the first direction, are respectively connected to the multiple semiconductor layers. The plurality of semiconductor layers are respectively separated from the gate insulating film and face one side and the other side of the plurality of gate electrodes in the first direction.

2. The semiconductor memory device according to claim 1, When the first cross section is defined as the cross section extending in the first direction and in the second direction intersecting the first direction, and containing the plurality of gate electrodes, In the first cross section, the plurality of semiconductor layers are respectively separated from the gate insulating film and face one side and the other side of the plurality of gate electrodes in the second direction.

3. The semiconductor memory device according to claim 1, When the cross-section perpendicular to the first direction and containing a portion of one of the plurality of semiconductor layers is taken as the second cross-section... In the second cross section, one of the plurality of semiconductor layers surrounds the outer peripheral surface of the first wiring.

4. The semiconductor memory device according to claim 1, When the cross section perpendicular to the first direction and containing a portion of one of the plurality of gate electrodes is taken as the third cross section... In the third cross section, one of the plurality of semiconductor layers surrounds the outer peripheral surface of one of the plurality of gate electrodes through the gate insulating film.

5. The semiconductor memory device according to claim 1, comprising: A plurality of first electrodes are arranged in the first direction and connected to the plurality of semiconductor layers in a third direction intersecting the first direction; A second electrode, which faces the plurality of first electrodes; and A first insulating film is disposed between the plurality of first electrodes and the second electrodes.

6. The semiconductor memory device according to claim 1, The plurality of storage units are plurality of capacitors.

7. The semiconductor memory device according to claim 1, The plurality of semiconductor layers each comprise an oxide semiconductor.

8. The semiconductor memory device according to claim 1, The plurality of semiconductor layers respectively contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

9. A semiconductor memory device comprising: Multiple storage units are arranged in the first direction; Multiple semiconductor layers are arranged in the first direction and electrically connected to the multiple memory units; A plurality of gate electrodes are arranged in the first direction and respectively facing the plurality of semiconductor layers; Multiple gate insulating films are respectively disposed between the multiple semiconductor layers and the multiple gate electrodes; A first wiring extends in the first direction and connects to the plurality of semiconductor layers; as well as A plurality of second wirings, arranged in the first direction, are respectively connected to the plurality of gate electrodes. The plurality of semiconductor layers are respectively separated from the gate insulating film and face one side and the other side of the plurality of gate electrodes in the first direction.

10. The semiconductor memory device according to claim 9, When the first cross section is defined as the cross section extending in the first direction and in the second direction intersecting the first direction, and containing the plurality of gate electrodes, In the first cross section, the plurality of semiconductor layers are respectively separated from the gate insulating film and face one side and the other side of the plurality of gate electrodes in the second direction.

11. The semiconductor memory device according to claim 9, When the cross-section perpendicular to the first direction and containing a portion of one of the plurality of semiconductor layers is taken as the second cross-section... In the second cross section, one of the plurality of semiconductor layers surrounds the outer peripheral surface of the first wiring.

12. The semiconductor memory device according to claim 9, When the cross section perpendicular to the first direction and containing a portion of one of the plurality of gate electrodes is taken as the third cross section... In the third cross section, one of the plurality of gate electrodes surrounds the outer peripheral surface of the first wiring.

13. The semiconductor memory device according to claim 9, comprising: A plurality of first electrodes are arranged in the first direction and connected to the plurality of semiconductor layers in a third direction intersecting the first direction; A second electrode, which faces the plurality of first electrodes; and A first insulating film is disposed between the plurality of first electrodes and the second electrodes.

14. The semiconductor memory device according to claim 9, The plurality of storage units are plurality of capacitors.

15. The semiconductor memory device according to claim 9, The plurality of semiconductor layers each comprise an oxide semiconductor.

16. The semiconductor memory device according to claim 9, The plurality of semiconductor layers respectively contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

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