Storage system

Abstract

Embodiments provide a large-capacity, low-cost storage system. The storage system of the embodiments has an array of storage cells having a plurality of strings in which a plurality of storage cells are connected in series, and a controller that controls the transfer between potential wells of channels in the plurality of storage cells and the charge corresponding to data that should be stored or has been stored in the plurality of storage cells in the string.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-046262 (filed on March 19, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] One embodiment of the present invention relates to a memory system. Background Technology

[0003] Since the invention and commercialization of flash memory, there has been a constant demand for high-capacity, low-cost memory and storage. For example, in 3D NAND flash memory, efforts are being made to achieve both high capacity and low cost by increasing the number of word lines stacked vertically. Summary of the Invention

[0004] In 3D NAND flash memory, contacts are formed on word lines with over 100 layers for wiring. These contacts are connected to word line control circuitry at their front ends, allowing voltage to be applied to each word line. However, as the number of word lines increases, several problems arise: the area required for contact with the word lines and the word line control circuitry both increase, leading to larger chip size and higher costs. Additionally, the sensing current during read operations decreases with the number of layers, making operation more difficult.

[0005] The problem to be solved by this invention is to provide a high-capacity and low-cost storage system.

[0006] According to one embodiment of the present invention, a storage system is provided, comprising a memory cell array and a controller, the memory cell array having a plurality of strings formed by serially connecting a plurality of memory cells, the controller controlling the transfer (transmission) of charge corresponding to data to be stored or already stored in the plurality of memory cells between the potential-wells of the channels within the plurality of memory cells. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the general configuration of a storage system according to one embodiment.

[0008] Figure 2 It means Figure 1 A circuit diagram of an example of a memory cell array.

[0009] Figure 3It is a cross-sectional view that schematically represents the construction of a string.

[0010] Figure 4 It is a schematic representation of the use Figure 3 A diagram showing the order in which charges are transferred in the string.

[0011] Figure 5 This is a schematic representation of reading from storage. Figure 3 A diagram showing the order of data in the storage units within a string.

[0012] Figure 6A It is a diagram that schematically illustrates the order in which data from two or more memory units within a string are read in parallel.

[0013] Figure 6B Is following Figure 6A The following image.

[0014] Figure 7 This is a diagram illustrating the reading sequence used to speed up setup time.

[0015] Figure 8 It is a schematic representation of... Figure 3 A diagram showing the order in which data is written to storage units within a string.

[0016] Figure 9A It is a diagram showing the cross-sectional structure of the periphery of the memory cell MC that makes up the string.

[0017] Figure 9B Is as Figure 9A A detailed cross-sectional view of a portion of the storage unit.

[0018] Figure 10A It is a top view diagram showing the perimeter of the string.

[0019] Figure 10B It is a cross-sectional view of the connection between the word line and the gate of the memory cell.

[0020] Figure 11 This is a diagram illustrating an installation example of the storage system according to this embodiment.

[0021] Figure 12 This is a diagram representing the storage system of the first variation example.

[0022] Label Explanation

[0023] 2. Signal transmission cable; 3. First substrate; 4. Second substrate; 7. Refrigerant; 8. Enclosure; 10. Storage system; 11. String; 12. Gate; 13. Floating gate; 14. Channel; 15. Gate insulating film; 16. Potential well; 100. NAND flash memory; 101. NAND bus; 102. Host bus; 110. Memory cell array; 120. Row decoder; 130. Driver circuit; 140. Column control circuit; 150. Register set; 160. Sequencer; 200. Controller; 210. Host interface (I / F) circuit; 220. Internal RAM; 230. Processor (CPU); 240. Buffer memory; 250. NAND interface (I / F) circuit; 260. ECC circuit; 300. Host device. Detailed Implementation

[0024] Hereinafter, embodiments of the storage system will be described with reference to the accompanying drawings. The description will focus on the main components of the storage system, but the storage system may contain components and functions not shown or described. The following description does not exclude components and functions not shown or described.

[0025] The storage system of this embodiment includes a storage cell array and a controller. The storage cell array has multiple strings consisting of multiple storage cells connected in series. The controller controls the transfer of charge between the potential wells of the channels within the multiple storage cells, corresponding to the data to be stored or already stored in the multiple storage cells within the string.

[0026] The storage cell in this embodiment is a non-volatile memory. As a specific example of a storage cell, an example of having a device structure similar to that of a NAND flash memory (hereinafter referred to as NAND flash memory) and using the device structure will be mainly described.

[0027] The memory cell in this embodiment has a potential well in the channel. The potential well is a place where the charge passing through the channel can be temporarily retained, and the depth of the potential well can be adjusted by the voltage applied to the gate. The higher the voltage applied to the gate, the deeper the potential well. The deeper the potential well is than the potential well of the adjacent memory cell, the more stably more charge can be retained.

[0028] In this embodiment, the controller reads and writes data in units of strings. A string is formed by connecting multiple memory cells in series. In this embodiment, multiple word lines (first wirings) are provided, each connected to the gate of a plurality of memory cells within the string. Each of the multiple word lines is connected to the gate of two or more memory cells within the string. That is, in this embodiment, the number of word lines is less than the number of memory cells within the string, and the gates of multiple memory cells within the string are connected on a single word line.

[0029] Charge is transferred from the potential well in one memory cell to the potential well in another memory cell by making the voltages of the two word lines connected to the gates of two adjacent memory cells in a string different. When transferring data between the potential wells in multiple memory cells, multiple predetermined voltage levels are sequentially applied to the multiple word lines connected to the multiple memory cells.

[0030] The following describes in detail the configuration and operation of a storage system that uses a device structure similar to NAND flash memory as its storage unit.

[0031] Figure 1 This is a block diagram illustrating the general configuration of a storage system 10 according to one embodiment. Figure 1 The storage system 10 illustrates the internal structure of an SSD (Solid State Drive) that uses a device construction similar to NAND flash memory.

[0032] Figure 1 The storage system 10 includes a string cell device 100 and a controller 200, the string cell device 100 having a device configuration similar to that of NAND flash memory. As described later, the string cell device 100 and the controller 200 are sometimes mounted on different substrates.

[0033] Figure 1 The serial unit device 100 has multiple storage units that non-volatilely store data. The controller 200, for example, can be configured, as described later. Figure 12 The bus 101 within the signal transmission cable 2 shown is connected to the serial unit device 100 and to the host device 300 via the host bus 102. The controller 200 controls the serial unit device 100 and, in response to commands received from the host device 300, accesses the serial unit device 100. The host device 300 is, for example, an electronic device such as a personal computer, and the host bus is a bus based on various interfaces. The NAND bus transmits and receives signals using NAND interfaces such as the Toggle interface.

[0034] The controller 200 includes a host interface circuit 210, an internal memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, an interface circuit 250, and an ECC (Error Checking and Correcting) circuit 260.

[0035] The host interface circuit 210 is connected to the host device 300 via the host bus, and transmits commands and data received from the host device 300 to the CPU 230 and the buffer memory 240, respectively. In addition, in response to commands from the CPU 230, it transmits data in the buffer memory 240 to the host device 300.

[0036] CPU 230 controls the overall operation of controller 200. For example, when CPU 230 receives a write command from host device 300, it responds by issuing a write command to interface circuit 250. The same applies during read and erase operations. Additionally, CPU 230 performs various processes for managing serial unit devices 100, such as wear leveling. Furthermore, the operations of controller 200 described below can be implemented via firmware executed by the CPU, or they can be implemented via hardware.

[0037] Interface circuit 250 is connected to serial unit device 100 via a bus in signal transmission cable 2, and is responsible for communication with serial unit device 100. Furthermore, interface circuit 250 sends various signals to serial unit device 100 based on commands received from CPU 230, and also receives various signals from serial unit device 100. Buffer memory 240 temporarily holds data for writing and reading.

[0038] RAM 220, such as DRAM or SRAM, is a semiconductor memory used as the working area of ​​CPU 230. Furthermore, RAM 220 holds firmware, various management tables, and other data used to manage the serial unit device 100.

[0039] ECC circuit 260 performs error detection and correction processing related to the data stored in serial unit device 100. That is, ECC circuit 260 generates error correction codes when writing data and appends them to the written data, and decodes them when reading data.

[0040] Next, the configuration of the serial unit device 100 will be described. For example... Figure 1 As shown, the serial unit device 100 includes a storage unit array 110, a row decoder 120, a driver circuit 130, a column control circuit 140, a register group 150, and a sequencer 160.

[0041] The storage cell array 110 comprises multiple block BLKs, each BLK consisting of multiple non-volatile storage cells associated with rows and columns. Figure 1 As an example, four blocks BLK0 to BLK3 are shown in the diagram. Furthermore, the storage cell array 110 stores data supplied from the controller 200.

[0042] The line decoder 120 selects any one of blocks BLK0 to BLK3, and then selects the line direction in the selected block BLK. The drive circuit 130 supplies voltage to the selected block BLK via the line decoder 120.

[0043] During data reading, the column control circuit 140 senses the signal read from the memory cell array 110 and performs necessary calculations. The signal read is voltage, charge, or current. Furthermore, the column control circuit 140 outputs data corresponding to the signal read from the memory cell array 110 to the controller 200. During data writing, the write data received from the controller 200 is transmitted to the memory cell array 110.

[0044] During data writing, the column control circuit 140 sends a signal corresponding to the data to be written to the memory cell array 110 via the bit lines. The input signal is voltage, charge, or current.

[0045] Register set 150 includes an address register, an instruction register, etc. The address register stores the address received from the controller 200. The instruction register holds the instruction received from the controller 200.

[0046] The sequencer 160 controls the overall operation of the serial unit device 100 based on various information held in the register group 150.

[0047] Figure 2 It means Figure 1 A circuit diagram of an example of a memory cell array 110. Figure 2 This illustrates the internal structure of a block BLK within the memory cell array 110. Each block BLK has multiple strings 11. Each string 11 has multiple memory cell transistors MC (MT) connected in series. Since memory cells are composed of memory cell transistors MC, the memory cell transistors MC will be simply referred to as memory cells MC below. Select transistors Q1 and Q2 are connected to the two ends of the multiple memory cell MCs within the string 11.

[0048] Each string 11 is configured with a bit line (second wiring). Each bit line is connected to one end of the corresponding string 11 via a corresponding select transistor Q1. The other end of each string 11 is connected to a common source line SL via a corresponding select transistor Q2.

[0049] In typical NAND flash memory, the gates of multiple memory cells (MCs) within a string 11 are connected to different word lines, but... Figure 2In this configuration, three word lines, WL0 to WL2, are alternately connected to the gates of each memory cell MC within the string 11. Thus, each word line is connected to the gates of two or more memory cells MC within the string 11. This reduces the number of word line types compared to a typical NAND flash memory string. In particular, the more memory cells MC within the string 11, the more the number of word lines can be reduced. These word lines are connected to... Figure 1 The line decoder connection.

[0050] (charge transfer method)

[0051] Next, the charge transfer method for strings using this embodiment will be described. Figure 3 It is a schematic cross-sectional view representing the construction of a string. For example... Figure 3 As shown, each memory cell MC within the string 11 has a floating gate 13 disposed below a gate 12 and a channel 14 disposed below the floating gate 13. A gate insulating film 15 is disposed between the floating gate 13 and the channel 14. The depth of the potential well within the channel 14 changes according to the voltage of the gate 12. Figure 3 This illustrates an example where the gates 12 of each memory cell MC within string 11 are sequentially connected to three word lines WL0 to WL2.

[0052] Figure 4 It is a schematic representation of the use Figure 3 The diagram illustrates the sequence of charge transfer in string 11. First, in state ST1, word line WL0 is set to a predetermined voltage, and charge is maintained in potential well 16 within the memory cell MC connected to word line WL0. (Regarding...) Figure 4 State ST1 represents an example where two charges are held in the potential well 16 below the gate 12 connected to the left-hand word line WL0, and one charge is held in the potential well 16 within the memory cell MC connected to the third word line WL0 from the right. The number of charges indicates different data values. Figure 3 and Figure 4 This illustrates an example of storing two types of data: one case with one charge and the other case with two charges in the potential well 16.

[0053] Next, in state ST2, word line WL1 is set to a higher voltage than word line WL0. Therefore, the potential well 16 in the memory cell MC connected to word line WL1 is deeper than the potential well 16 in the memory cell MC connected to word line WL0. Consequently, charge transfers from the potential well 16 below word line WL0 to the potential well 16 below the adjacent word line WL1. Thus, as... Figure 3 As shown, the charge in the potential well 16 of the memory cell MC connected to the word line WL0 is transferred to the potential well 16 of the memory cell MC connected to the word line WL1 adjacent to the word line WL0.

[0054] Next, in state ST3, the voltage of word line WL0 is lower than that in state ST2. As a result, the potential well 16 below word line WL0 becomes shallower, and the charge in the potential well 16 below word line WL1 cannot move to the potential well 16 of the memory cell MC connected to word line WL0, and is thus stably maintained.

[0055] Next, in state ST4, the voltage of word line WL1 is lower than that in state ST3. However, the voltage of word line WL1 is higher than that of word lines WL0 and WL2. Thus, as in state ST3, the charge within the potential well 16 can be maintained.

[0056] Thus, by sequentially varying the voltage applied to word lines WL0 to WL2 in at least three ways, charge transfer can be continuously performed between the potential wells 16 in the multiple memory cells MC within the string 11. This allows data from each memory cell MC within the string 11 to be transmitted to the bit line, and data from the bit line to any memory cell MC within the string 11. Therefore, regardless of the number of memory cells MC connected in series within the string 11, charge movement, which becomes data, can be achieved through only the three word lines WL0 to WL2 in the channel portion of any memory cell.

[0057] (Reading method)

[0058] Figure 5 This is a schematic representation of reading from storage. Figure 3 A diagram showing the order of data in storage unit MC within string 11. Figure 3 and Figure 4 The text illustrates an example where two or more memory cells MC, each connected to word lines WL0 to WL2 within string 11, operate in parallel to perform charge transfer. Figure 5 This illustrates an example of controlling the gate voltage of each memory cell MC within string 11.

[0059] First, in state ST11, in order to read the data of the fourth memory cell MC from the left in string 11, the word line WL0 connected to its gate 12 is set to a predetermined voltage V_copy, causing the potential well 16 to generate a charge corresponding to the accumulated charge in the floating gate 13. In this case, an example is shown where the word lines WL0 to WL2 connected to the gates 12 of the first to third memory cells MC from the left in string 11 are set to a charge transfer voltage V_pass, each holding three charges in the potential well 16. Here, V_pass > V_copy.

[0060] The first to third memory cells MC from the left end of string 11 are not read targets, so it is necessary to ensure they do not obstruct charge transfer in the channel 14 of the read target memory cell MC. Therefore, in state ST12, the first to third memory cells MC from the left end are turned off. As a result, the potential wells 16 in these memory cells MC become shallower, and the charge held in the potential wells 16 is discarded as it transfers towards the source line SL. By connecting one end of string 11 to the bit line via select transistor Q1 and the other end of string 11 to the source line SL via select transistor Q2, the reference potential of the channel 14 of each memory cell MC is determined, and the time until charge is generated in the channel 14 can be shortened.

[0061] Additionally, in state ST2, a voltage V_well is applied to the word line WL0 connected to the gate 12 of the fourth memory cell MC from the left, which is the object to be read. Here, V_well > V_pass. As a result, the potential well 16 within this memory cell MC becomes deeper, enabling the stable retention of the charge generated in state ST11.

[0062] exist Figure 5 The example shown illustrates controlling the gate voltage of each memory cell MC within the string 11 separately. However, in this embodiment, we consider the case where fewer word lines than the number of memory cells MC within the string 11 are connected to each memory cell MC. This allows data from two or more memory cells MC within the string 11 to be read in parallel.

[0063] Figure 6A and Figure 6B This is a schematic diagram illustrating the order in which data is read in parallel from two or more memory units (MC) within string 11. Figure 6A and Figure 6B The diagram illustrates an example where three word lines WL0 to WL2 are sequentially connected to the gate 12 of multiple memory cells MC within string 11. In state ST21, word line WL0 is set to voltage V_copy, and word lines WL1 and WL2 are set to voltage V_pass, where V_pass > V_copy. This maintains an equal amount of charge (e.g., three charges) in the potential well 16 within the memory cell MC connected to word lines WL1 and WL2 that is not being read. Conversely, a charge corresponding to the amount of charge within the floating gate 13 is generated in the potential well 16 within the memory cell MC connected to word line WL0. Figure 6AThis illustrates an example where the charge accumulated in the floating gate 13 within the three memory cells MC connected to the word line WL0 varies. Specifically, the floating gate 13 in the leftmost memory cell MC accumulates 2 charges, the floating gate 13 in the fourth memory cell MC from the left accumulates 1 charge, and the third memory cell MC from the right is in an erased state, meaning no charge has accumulated in the floating gate 13. In this state, when a voltage V_copy is applied to the word line WL0, 1 charge is generated in the potential well 16 within the leftmost memory cell MC, 2 charges are generated in the potential well 16 within the fourth memory cell MC from the left, and 3 charges are generated in the potential well 16 within the third memory cell MC from the right. The more charge accumulated in the floating gate 13, the lower the threshold voltage of the memory cell MC becomes, and the less charge is generated in the potential well 16 within the channel 14 when V_copy is applied to the gate. Therefore, the amount of charge generated in the potential well 16 varies according to the storage cell MC, based on the accumulated charge of the floating gate 13.

[0064] Next, in state ST22, while maintaining the voltage V_copy of word line WL0, the memory cells MC connected to word lines WL1 and WL2 are turned off. As a result, the potential wells 16 within the memory cells MC connected to word lines WL1 and WL2 become shallower, and the charge generated in the potential wells 16 within these memory cells MC is discarded to the source line SL. Afterwards, in Figure 6B In state ST23, by changing the voltage of word line WL0 from V_copy to V_well, the charge can be stably maintained in the potential well 16 within the memory cell MC connected to word line WL0. Then, by sequentially changing the voltages of word lines WL0 to WL2, the charge maintained in the potential well 16 is sequentially transferred to the bit lines.

[0065] like Figure 6A and Figure 6B As shown, when reading data from a specific memory cell MC within string 11, it is necessary to discard the charge of the potential well 16 in the memory cell MC that is not being read, and then transfer the charge of the potential well 16 in the memory cell MC that is being read. Therefore, it is desirable to quickly discard the charge of the potential well 16 in the memory cell MC that is not being read, so as to speed up the setup time for reading data from the memory cell MC that is being read.

[0066] Figure 7 This is a schematic diagram illustrating the read sequence used to speed up setup time. Figure 7This illustrates an example where five word lines WL0 to WL4 are sequentially connected to the gates 12 of multiple memory cells MC within string 11. One of the five word lines WL0 to WL4 is used to concentrate the charge of the potential well 16 within the memory cell MC that is not being read. The voltage of the word line used for this purpose is set to V_collect, where V_collect > V_copy. The potential well 16 within the memory cell MC with the applied voltage V_collect becomes deeper.

[0067] exist Figure 7 Under state ST31, with Figure 6A Similarly, in state ST21, word line WL0 connected to the gate 12 of the memory cell MC to be read is set to voltage V_copy, and word lines WL1 to WL4 connected to the gate 12 of the memory cell MC not to be read are set to voltage V_pass. As a result, a charge corresponding to the accumulated charge in the corresponding floating gate 13 is generated in the potential well 16 within the memory cell MC to be read. Furthermore, an equal amount of charge (e.g., 3 charges) is maintained in the potential well 16 within the memory cell MC not to be read.

[0068] Next, in state ST32, the word line WL3 connected to the gate 12 of one of the non-read memory cells MC is set to voltage V_collect, and the other non-read memory cells MC are turned off. As a result, the potential wells 16 of the off-state memory cells MC become shallower, and the charge held in these potential wells 16 is transferred to the potential wells 16 of the memory cells MC to which voltage V_collect is applied. Thus, the charge in the potential wells 16 of the non-read memory cells MC can be concentrated into one potential well 16. The charge concentrated in this potential well 16 can be transferred sequentially to the potential wells 16 of adjacent memory cells MC, and finally transferred to the bit line and discarded.

[0069] (Write method)

[0070] For two or more memory cells (MCs) connected to the same word line within string 11, data is written simultaneously (in parallel) in a single write operation. For example, a method called Constant Charge Injection can be used for writing.

[0071] Figure 8 It is a schematic representation of... Figure 3 The diagram illustrates the sequence of data writing to the memory cell MC within string 11. During data writing, the charge corresponding to the data, transferred from the bit line to string 11, is transferred to the potential well 16 within the memory cell MC to be written. Figure 8This illustrates an example of setting word line WL0 to voltage V_well and writing data simultaneously (in parallel) to three memory cells MC connected to word line WL0. Figure 8 In the example, the potential well 16 in the leftmost memory cell MC holds 2 charges, the potential well 16 in the fourth memory cell MC from the left holds 1 charge, and the potential well 16 in the third memory cell MC from the right holds 3 charges. Thus, Figure 8 This illustrates an example of writing multiple values.

[0072] Next, in state ST42, word line WL0 is set to voltage V_prog, where V_prog > V_well. As a result, the charge in potential well 16 moves toward floating gate 13, writing data to the three memory cells MC connected to word line WL0 simultaneously (in parallel).

[0073] In this embodiment, the storage cell MC accumulates charge on the floating gate 13 instead of the charge trapping film. By accumulating charge on the floating gate 13, the charge from the potential well 16 in the channel 14 can be accumulated on the floating gate 13 with a capture rate of approximately 100%.

[0074] (Construction of a memory cell MC)

[0075] The memory cell array 110 of this embodiment can be formed on a two-dimensional plane or in a three-dimensional structure. Hereinafter, an example of a three-dimensional memory cell array 110 will be described. Figure 9A , Figure 9B , Figure 10A and Figure 10B This is a cross-sectional view of the main part of the storage cell array 110 in this embodiment. More specifically, Figure 9A This represents the cross-sectional structure of the periphery of the memory cell MC that constitutes string 11. Figure 9B Is as Figure 9A A detailed cross-sectional view of a portion of the memory cell MC. Hereinafter, the substrate surface will be referred to as the horizontal direction, and the normal direction of the substrate surface will be referred to as the vertical direction.

[0076] like Figure 10A As shown, the storage cell array 110 includes multiple pillars PL extending in the vertical direction and multiple contact plugs CC1 to CC3. Figure 9A As shown, multiple memory cells MC are arranged vertically on the sidewalls of each column PL. Multiple contact plugs CC1 to CC3 are arranged corresponding to multiple word lines. For example... Figure 10B As shown, each contact plug CC1 to CC3 is connected to the corresponding word line on its sidewall. The structure of the cylinder PL and the contact plugs CC1 to CC3 will be described in more detail below.

[0077] like Figure 9A As shown, on the sidewall portion of the core layer CR of each pillar PL, multiple strings 11 are formed along the vertical direction on the p-well region 40 of the semiconductor substrate. Each string 11 is constructed as follows: selection transistors SGS connected to multiple wiring layers 42, multiple memory cell transistors MT0 to MT7 connected to multiple wiring layers (word lines) 43, and selection transistors SGD connected to multiple wiring layers 44 are stacked in the vertical direction.

[0078] like Figure 9B As shown, the memory cell MC has a pillar PL with a stacked structure formed from the core layer CR, channel 14, channel insulating layer 41, floating gate 13, block insulating layer 45, and wiring layer 43 that serves as the gate electrode, extending from the center axis to the outer periphery. Multiple word lines WL connected to the gate electrode 43 are arranged on the sidewall portion of the pillar PL. The core layer CR functions as a current path for the series 11 and forms the region where the channel 14 is formed during the operation of the memory cell transistor MC (MT) and the select transistors SGS and SGD.

[0079] Additionally, an n+ type impurity diffusion layer and a p+ type impurity diffusion layer are formed within the surface of the p-type well region 40. A contact plug 50 is formed on the n+ type impurity diffusion layer, and a wiring layer functioning as a source line SL is formed on the contact plug 50. Furthermore, a contact plug 51 is formed on the p+ type impurity diffusion layer, and a wiring layer functioning as a well wiring CPWELL is formed on the contact plug 51. The well wiring CPWELL is used to apply an erase voltage.

[0080] Figure 9A The storage cell array 110 shown is in Figure 9A Multiple fingers are arranged along the depth direction of the paper. A single finger is formed by a collection of multiple strings of 11 arranged in a row along the depth direction. Other fingers are formed, for example, on... Figure 9A In the left and right directions.

[0081] A bit line BL is configured above the storage unit MC, and a bit line BL is configured in front of it. Figure 1 The column control circuit 140 is shown. A read / write circuit is built into the column control circuit 140. Through the read / write circuit, the memory cell array 110 can be operated as a shift register type memory. A shift register type memory refers to a memory that, as shown in... Figures 4-8 As described herein, it is a string cell device having a device construction similar to that of a NAND flash memory capable of sequentially transferring the charge held in the potential well 16 within each memory cell MC.

[0082] Thus, by providing a read / write circuit within the column control circuit 140 located at the front end of the bit line BL, weak signal transmission and reading are possible. Furthermore, unlike conventional NAND flash memory where word lines are controlled for writing and reading every single bit, word lines in shift register type memory involve charge transfer between adjacent memory cells MC. Therefore, as long as potential modulation can be performed between adjacent word lines, for example, multiple non-adjacent word lines can be bundled into several groups and connected to the row decoder 120. Additionally, the select gate line SGD connected to the select gate STD is also connected to the row decoder 120.

[0083] exist Figure 10A In this example, contact plugs CC1 to CC3 are disposed outside the forming area of ​​the memory cell array 110, which is composed of multiple pillars PL. The upper ends of contact plugs CC1 to CC3 are connected to the drive circuit 130 via upper layer wiring (not shown). Word lines WL0 to WL6 are arranged in the normal direction of the substrate surface, surrounding contact plugs CC1 to CC3.

[0084] like Figure 10B As shown, contact plug CC1 is connected to word lines WL2 and WL6 via flange F1 located at the height of word lines WL2 and WL6, and is not connected to other word lines. Contact plug CC2 is connected to word lines WL1 and WL5 via flange F2 located at the height of word lines WL1 and WL5, and is not connected to other word lines. Contact plug CC3 is connected to word lines WL0 and WL4 via flange F3 located at the height of word lines WL0 and WL4, and is not connected to other word lines.

[0085] In this way, word lines WL0 to WL6 are connected to any one of the contact plugs CC1 to CC3. In addition, adjacent word lines in the stacking direction are connected to each other to different contact plugs CC1 to CC3.

[0086] In this embodiment, data writing and reading are performed by sequentially transferring the charge held in the potential well 16 within the memory cell MC between the potential wells 16 of adjacent memory cells MC. The more miniaturized the device, the less charge is held in the potential well 16; furthermore, the higher the multi-level, the smaller the difference in the amount of charge held in the potential well 16. Therefore, data writing and reading must be performed in an environment where the charge in the floating gate 13 within the memory cell MC and in the potential well 16 does not disappear due to heat, leakage, or other reasons.

[0087] To stably accumulate and maintain charge within the floating gate 13 and potential well 16 of the memory cell MC, the memory cell array 110 can be placed in an extremely low-temperature environment. This prevents the charge within the floating gate 13 and potential well 16 from easily dissipating due to leakage. Furthermore, extremely low temperature refers to a temperature, for example, below -40°C.

[0088] Figure 11 This is a diagram illustrating an installation example of the storage system 10 according to this embodiment. Figure 11 The storage system 10 includes a first substrate 3 and a second substrate 4 interconnected by a signal transmission cable 2. The types of the first substrate 3 and the second substrate 4 are not particularly limited; for example, they are printed circuit boards, glass substrates, etc. The type and length of the signal transmission cable 2 are also not particularly limited; the signal transmission cable 2 may have a length of several tens of centimeters or more. The signal transmission cable 2 may be, for example, an FPC (Flexible Printed Circuit), or other signal transmission cables 2, such as a USB (Universal Serial Bus) signal transmission cable 2. The signal cable is made several tens of centimeters or more to prevent heat conduction between the first substrate 3 and the second substrate 4.

[0089] Mounted on the first substrate 3 Figure 1 The serial unit device 100 is set to -40°C or below. However, thermometers and temperature sensors contain measurement errors depending on environmental conditions, so "-40°C or below" in this specification is intended to set the target temperature to "-40°C or below". Due to measurement errors of temperature sensors, etc., there may be cases where the temperature is set to a temperature slightly higher than -40°C.

[0090] A controller 200 is mounted on the second substrate 4 and set to a temperature above -40°C. The controller 200 controls the writing, reading, or erasing of data on the memory 5 according to instructions from the host device. The controller 200 is constructed from CMOS circuitry, and its operating range is generally -40°C to 125°C, thus allowing the use of controllers manufactured using technologies employed in conventional SSD products.

[0091] exist Figure 1 In this example, the first substrate 3, on which the memory 5 is mounted, can also be immersed in liquid nitrogen, for example. Liquid nitrogen can be manufactured at a low industrial cost, so immersing the first substrate 3 in liquid nitrogen itself does not require much cost. Furthermore, the first substrate 3 only needs to be set to a temperature below -40°C, so a refrigerant other than liquid nitrogen can be used and the first substrate 3 can be placed in the refrigerant.

[0092] As a specific example of setting the first substrate 3, on which the memory 5 is installed, to a temperature below -40°C, one could consider, for example... Figure 12As shown in the storage system 10 of the first modified example, the first substrate 3 is placed in a housing 8 containing a refrigerant 7 at a temperature below -40°C. The refrigerant 7 is, for example, a liquid with a boiling point below -40°C, such as liquid nitrogen or liquid carbon dioxide. Furthermore, the refrigerant 7 is preferably not only harmless to humans but also readily available at low cost. To prevent the refrigerant 7 from contacting the atmosphere and causing its temperature to rise, and to prevent the refrigerant 7 from diffusing into the atmosphere and causing its quantity to decrease, the housing 8 is considered to be an insulated container with a minimized opening.

[0093] On the other hand, the second substrate 4 on which the controller 200 is installed can be set to -40°C or higher, so it can be set to room temperature, for example, without using refrigerant 7 and / or cooling components. However, if the controller 200 may generate heat, appropriate heat dissipation measures such as contacting cooling components such as heat sinks with the controller 200 can be implemented.

[0094] Thus, in this embodiment, by sequentially transferring the charge held in the potential well 16 of the channel 14 formed in the memory cell MC to the potential well 16 in adjacent memory cells MC, data writing and reading of multiple memory cells MC within the string 11 are performed. Therefore, the number of word lines connected to the multiple memory cells MC within the string 11 can be reduced, simplifying the structure of the memory cell array 110. Furthermore, since the potential well 16 can hold multiple charges, and the amount of charge held by the potential well 16 can be arbitrarily changed for each memory cell MC, multi-valued data writing and reading are also possible.

[0095] The storage system 10 of this embodiment can also write and read data while the storage cell array 110 is configured at extremely low temperatures. By configuring the storage cell array 110 at extremely low temperatures, leakage and / or disappearance of charge in the floating gate 13 and potential well 16 within the storage cell MC can be suppressed, enabling stable charge transfer.

[0096] The technical solutions disclosed herein are not limited to the various embodiments described above, but also include various modifications that can be conceived by those skilled in the art. Furthermore, the effects of this disclosure are not limited to the aforementioned content. That is, various additions, modifications, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure derived from the content defined in the claims and their equivalents.

Claims

1. A storage system comprising: A storage cell array, which has multiple strings of storage cells connected in series; A controller that controls the transfer of charge between potential wells in the channels within the plurality of memory cells, corresponding to data to be stored or already stored in the plurality of memory cells within the string; and Multiple first wirings that are gate-connected to the plurality of memory cells within the string, Each of the plurality of first wirings is connected to the gate of two or more of the memory cells within the string.

2. The storage system according to claim 1, The plurality of first wirings are sequentially connected to the corresponding gates according to the connection order of the plurality of memory cells in the string.

3. The storage system according to claim 1, By making the voltages of the two first wirings that are connected to the gates of two adjacent memory cells in the plurality of memory cells in the string different, charge is transferred from the potential well in one memory cell to the potential well in the other memory cell.

4. The storage system according to claim 1, When transmitting data between potential wells within the plurality of memory cells, a plurality of predetermined voltage levels are sequentially applied to the plurality of first wirings connected to the plurality of memory cells.

5. The storage system according to claim 1, The storage unit has: A gate, which is connected to any one of the plurality of first wirings; and A floating gate, which is disposed between the gate and the channel. The channel has a potential well whose depth is adjusted according to the voltage of the gate. The potential wells of each of the plurality of storage cells constituting the string are connected to each other.

6. The storage system according to claim 5, The floating grating accumulates the charge corresponding to the multi-valued data. The potential well transfers the charge corresponding to the multi-valued data.

7. The storage system according to claim 5, The controller causes the voltage applied to the gate when the accumulated charge of the floating gate moves to the potential well during data reading to be lower than the voltage applied to the gate when the gate receives a transfer of charge from the potential well of the adjacent memory cell during data transmission.

8. The storage system according to claim 5, The more charge accumulated in the floating gate, the less charge moves from the floating gate to the potential well during data reading.

9. The storage system according to claim 5, The controller causes the accumulated charge of the floating gates in two or more memory cells within the string that have gates connected to the same first wiring to move in parallel to the corresponding potential wells.

10. The storage system according to claim 5, The controller discards the charge in the potential well within the memory cell that is in the off state by cutting off the memory cell that is not being read.

11. The storage system according to claim 5, The plurality of storage cells within the string include charge collection storage cells, each charge collection storage cell having a potential well that allows charges in the potential wells within the storage cells in the cut-off state of the string to be collected. The voltage of the first wiring connected to the gate of the charge collection storage cell is set to a predetermined voltage for charge collection.

12. The storage system according to claim 5, After transferring charge to the potential wells of all memory cells of the write object in the plurality of memory cells in the string, the controller applies a programming voltage higher than the voltage during data transmission to a specific first wiring connected to the gate of all memory cells of the write object, thereby transferring charge from the corresponding potential well to the floating gate of all memory cells of the write object.

13. The storage system according to claim 12, In a single write operation, the controller transfers charge from the corresponding potential well to the floating gate for all memory cells connected to the first wiring to which the programming voltage is applied.

14. The storage system according to claim 1, It has multiple second wirings configured on one end of the multiple strings. Data transmitted between the potential wells of the channels in each of the plurality of storage cells is transmitted and received via the plurality of second wirings.

15. The storage system according to claim 14, It includes a read / write control circuit that reads signals on the plurality of second wirings and sends signals for data writing to the plurality of second wirings.

16. The storage system according to claim 1, The strings within the storage cell array have the same circuit structure as the strings in a NAND flash memory.

17. The storage system according to claim 1, comprising: Multiple first conductive layers are stacked on the substrate; Multiple second conductive layers are stacked between the multiple first conductive layers; A column extending in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers, forming the plurality of memory cells at the intersection with the plurality of first conductive layers and the plurality of second conductive layers; A first contact plug extends in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers, and is connected to the plurality of first conductive layers; and The second contact plug extends in the stacking direction of the plurality of first conductive layers and the plurality of second conductive layers and is connected to the plurality of second conductive layers.

18. The storage system according to claim 1, comprising: A first substrate, on which the memory cell array is mounted, is set to a temperature below -40°C; and The second substrate, on which the controller is mounted, has a temperature set above -40°C and transmits and receives signals with the first substrate via a signal transmission cable.

19. The storage system according to claim 18, The first substrate is disposed in liquid nitrogen.

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