Semiconductor memory device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor storage device and a manufacturing method thereof. One embodiment of the semiconductor storage device includes a plurality of conductive layers and a plurality of interlayer insulating layers alternately arranged in a first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; and a gate insulating film provided between the plurality of conductive layers and the semiconductor layer. The plurality of interlayer insulating layers includes a first interlayer insulating layer and a second interlayer insulating layer adjacent to each other in the first direction. The plurality of conductive layers includes a first conductive layer provided between the first interlayer insulating layer and the second interlayer insulating layer. The first conductive layer includes a first region, a second region provided between the first region and the gate insulating film, and a third region provided between the first region and the first interlayer insulating layer. The first to third regions contain metal. The third region contains silicon (Si). The first and second regions do not contain silicon, or the content of silicon in the first and second regions is lower than the content of silicon in the third region.

Description

[0001] This application is based on and pursues the interest in priority of Japanese Patent Application No. 2021-047984, filed on March 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0003] A semiconductor memory device is known, comprising a plurality of conductive layers and a plurality of interlayer insulating layers arranged alternately in a first direction, a semiconductor layer extending in the first direction and facing the plurality of conductive layers, and a gate insulating layer disposed between the plurality of conductive layers and the semiconductor layer. The gate insulating layer comprises a storage section capable of storing data, such as an insulating charge storage layer of silicon nitride (Si3N4) and a conductive charge storage layer of a floating gate. Summary of the Invention

[0004] One implementation provides a suitable semiconductor memory device and a method of manufacturing the same.

[0005] A semiconductor memory device according to one embodiment includes: a plurality of conductive layers and a plurality of interlayer insulating layers arranged alternately in a first direction; a semiconductor layer extending in the first direction and facing the plurality of conductive layers; and a gate insulating film disposed between the plurality of conductive layers and the semiconductor layer. The plurality of interlayer insulating layers includes a first interlayer insulating layer and a second interlayer insulating layer adjacent in the first direction. The plurality of conductive layers includes a first conductive layer disposed between the first interlayer insulating layer and the second interlayer insulating layer. The first conductive layer includes a first region, a second region disposed between the first region and the gate insulating film, and a third region disposed between the first region and the first interlayer insulating layer. The first region to the third region contain metal. The third region contains silicon (Si). The first region and the second region do not contain silicon (Si), or the silicon (Si) content in the first region and the second region is lower than the silicon (Si) content in the third region.

[0006] Based on the above configuration, a suitable semiconductor memory device and a method for manufacturing the same can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic top view of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 yes Figure 1 A schematic enlarged view of part A shown.

[0009] Figure 3 yes Figure 2A schematic enlarged view of part B shown.

[0010] Figure 4 yes Figure 3 A schematic enlarged view of part C.

[0011] Figure 5 It is Figure 4 The diagram shows a schematic cross-sectional view of the structure when cut along line DD′ and viewed in the direction of the arrow.

[0012] Figure 6 yes Figure 5 A schematic enlarged view of the portion shown as E.

[0013] Figure 7 It is shown Figure 6 The diagram shows a schematic coordinate graph of the content of the components contained in the portion of the structure along the FF′ line.

[0014] Figure 8 It is shown Figure 6 The diagram shows a schematic coordinate graph of the content of the components contained in the portion of the structure along the GG′ line.

[0015] Figure 9 It is Figure 3 The diagram shows a schematic cross-sectional view of the structure when cut along line HH′ and viewed in the direction of the arrow.

[0016] Figure 10 yes Figure 9 A schematic enlarged view of the portion shown as I.

[0017] Figure 11 yes Figure 2 A schematic enlarged view of the part shown as J.

[0018] Figure 12 It is Figure 11 The diagram shows a schematic cross-sectional view of the structure when cut along line KK′ and viewed in the direction of the arrow.

[0019] Figure 13 yes Figure 1 A schematic enlarged view of the portion shown as L.

[0020] Figure 14 yes Figure 13 A schematic enlarged view of the part shown as M.

[0021] Figure 15 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the first embodiment.

[0022] Figure 16 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0023] Figure 17 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0024] Figure 18 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0025] Figure 19 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0026] Figure 20 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0027] Figure 21 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0028] Figure 22 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0029] Figure 23 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0030] Figure 24 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0031] Figure 25 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0032] Figure 26 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0033] Figure 27 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0034] Figure 28 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0035] Figure 29 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0036] Figure 30 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0037] Figure 31 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0038] Figure 32 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0039] Figure 33 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0040] Figure 34 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0041] Figure 35 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0042] Figure 36 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0043] Figure 37 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0044] Figure 38 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0045] Figure 39 This is a schematic cross-sectional view illustrating the manufacturing method described above.

[0046] Figure 40 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0047] Figure 41 This is a schematic cross-sectional view illustrating a manufacturing method of a comparative example semiconductor memory device.

[0048] Figure 42 This is a schematic cross-sectional view showing the configuration of a portion of a comparative example semiconductor memory device.

[0049] Figure 43 This is a schematic cross-sectional view showing the configuration of a portion of a comparative example semiconductor memory device.

[0050] Figure 44 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to other embodiments.

[0051] Figure 45 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to other embodiments.

[0052] Figure 46 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to other embodiments.

[0053] Figure 47 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to other embodiments.

[0054] Figure 48 It is a schematic coordinate graph showing the content of a component included in a portion of a semiconductor memory device according to other embodiments.

[0055] Figure 49It is a schematic coordinate graph showing the content of a component included in a portion of a semiconductor memory device according to other embodiments.

[0056] Figure 50 It is a schematic coordinate graph showing the content of a component included in a portion of a semiconductor memory device according to other embodiments.

[0057] Figure 51 This is a schematic cross-sectional view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0058] Figure 52 This is a schematic cross-sectional view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0059] Figure 53 This is a schematic cross-sectional view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments.

[0060] Figure 54 This is a schematic cross-sectional view illustrating a portion of the configuration of a semiconductor memory device according to other embodiments. Detailed Implementation

[0061] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are illustrative, and for ease of explanation, some details, such as certain components, are sometimes omitted. Also, sometimes the same reference numerals are used to denote common parts in multiple embodiments, and descriptions are omitted.

[0062] Additionally, when referred to as "semiconductor memory device" in this specification, it sometimes means a memory die, and sometimes it means a storage system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Furthermore, it sometimes also refers to a device including a mainframe computer, such as a smartphone, tablet, or personal computer.

[0063] In addition, in this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0064] In addition, in this specification, the direction along the predetermined surface is sometimes referred to as the first direction, the direction along the predetermined surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the predetermined surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0065] Furthermore, in this specification, the terms "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction approaching the substrate along the Z direction is called "lower." Additionally, when referring to a configuration as a lower surface or lower end, it means the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it means the surface or end of that configuration on the side opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0066] In addition, when referring to components, parts, etc., in this specification as “width,” “length,” or “thickness” in a predetermined direction, it sometimes means the width, length, or thickness of a cross-section, etc., as observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0067] Additionally, when referred to as "content rate" in this specification, it sometimes means the ratio of the number of atoms constituting a component.

[0068] [First Implementation]

[0069] [constitute]

[0070] Figure 1 This is a schematic top view of a memory die (MD). Figure 2 yes Figure 1 A schematic enlarged view of part A shown. Figure 3 yes Figure 2 A schematic enlarged view of part B shown. Figure 4 yes Figure 3 A schematic enlarged view of part C. Figure 5 It is Figure 4 The diagram shows a schematic cross-sectional view of the structure when cut along line DD′ and viewed in the direction of the arrow. Figure 6 yes Figure 5 A schematic enlarged view of the portion shown as E. Figure 7 It is shown Figure 6 The diagram shows a schematic coordinate graph of the content of the components contained in the portion of the structure along the FF′ line. Figure 8 It is shown Figure 6 The diagram shows a schematic coordinate graph of the content of the components contained in the portion of the structure along the GG′ line. Figure 9 It is Figure 3 The diagram shows a schematic cross-sectional view of the structure when cut along line HH′ and viewed in the direction of the arrow. Figure 10 yes Figure 9A schematic enlarged view of the portion shown as I. Figure 11 yes Figure 2 A schematic enlarged view of the part shown as J. Figure 12 It is Figure 11 The diagram shows a schematic cross-sectional view of the structure when cut along line KK′ and viewed in the direction of the arrow. Figure 13 yes Figure 1 A schematic enlarged view of the portion shown as L. Figure 14 yes Figure 13 A schematic enlarged view of the part shown as M.

[0071] For example, Figure 1 As shown, the memory die MD includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a semiconductor substrate formed of P-type silicon (Si) containing P-type impurities such as boron (B).

[0072] In the illustrated example, a semiconductor substrate 100 is provided with an array region R of four memory cells arranged in the X and Y directions. MCA Additionally, in the memory cell array region R... MCA Multiple storage blocks (BLKs) are configured and arranged in the Y direction. For example, Figure 3 As shown, a memory block BLK has multiple string cells SU arranged in the Y direction. An inter-block insulating layer ST, such as silicon oxide (SiO2), is disposed between two adjacent memory blocks BLK in the Y direction. For example... Figure 4 As shown, an inter-string insulating layer SHE, such as silicon oxide (SiO2), is provided between two adjacent string units SU in the Y direction.

[0073] In addition, for example, Figure 1 As shown, the storage cell array region R MCA It has multiple storage hole regions R arranged in the X direction MH and located in these storage hole areas R MH Multiple contact connection areas R between C4T Additionally, in the memory cell array region R... MCA Two first hook-up regions R are set at the center position in the X direction. HU1 and set in these two first connection areas R HU1 The second connection region R between HU2 Additionally, in the memory cell array region R... MCA One end in the Y direction, and multiple storage hole regions R arranged in the X direction. MH Correspondingly, multiple contact connection areas R are provided arranged in the X direction. BLT .

[0074] [Storage Hole Area R]MH [Construction]

[0075] For example, Figure 5 As shown, the storage hole region R of storage block BLK MH It includes a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 disposed between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0076] The conductive layer 110 is a generally plate-shaped conductive layer extending in the X direction. A portion of the conductive layer 110 functions as, for example, the gate electrode and word line of a memory cell (memory transistor). Another portion of the conductive layer 110 functions as, for example, the gate electrode and select gate line of a select transistor. An interlayer insulating layer 101, such as silicon oxide (SiO2), is disposed between the plurality of conductive layers 110 arranged in the Z direction.

[0077] The conductive layer 110 may, for example, contain metals such as tungsten (W) or molybdenum (Mo) and silicon (Si). For example, in Figure 6 In the diagram, the region near the center of the YZ section of the conductive layer 110 is represented as region R. WL1 Additionally, the region near the gate insulating film 130 of the conductive layer 110 is denoted as region R. WL2 Additionally, the region near the lower surface of the conductive layer 110 is denoted as region R. WL3 Additionally, the region near the upper surface of the conductive layer 110 is denoted as region R. WL4 .

[0078] Here, as Figure 7 and Figure 8 As shown, in the first embodiment, region R WL3 The tungsten (W) content in region R is higher than that in region R. WL1 R WL2 R WL4 The tungsten (W) content in the region is low. Additionally, region R... WL3 The silicon (Si) content in region R is higher than that in region R. WL1 R WL2 R WL4 It has a high silicon (Si) content.

[0079] Furthermore, in the illustrated example, region R WL3 The silicon (Si) content in region R is higher than that in region R. WL1 The silicon (Si) content is high. Under such circumstances, region R... WL3 With region R WL1 The boundary can be defined, for example, in the following way: that is, along... Figure 6The composition of conductive layer 110 was analyzed using the FF′ line. Next, region R was obtained. WL3 The maximum silicon (Si) content was obtained in region R. WL1 The minimum silicon (Si) content in the sample was determined. Furthermore, the average of the obtained maximum and minimum values ​​was calculated. Additionally, [the following was done / contained / etc.]. Figure 6 The point on the FF′ line where the silicon (Si) content is the average value obtained is denoted as region R. WL3 With region R WL1 The boundary.

[0080] Furthermore, in this case, region R WL2 With region R WL1 The boundary and area R WL4 With region R WL1 The boundary of region R can be defined in the following way: that is, the boundary of region R is defined as follows. WL3 With region R WL1 The boundary is defined using the method described above, obtaining the distance from the boundary location to the lower surface of the conductive layer 110. Next, the location at which the upper surface of the conductive layer 110 moves away from this distance is defined as region R. WL4 With region R WL1 The boundary. Additionally, the region R is defined as the distance from the contact surface of the conductive layer 110 with the gate insulating film 130 at that distance. WL2 With region R WL1 The boundary.

[0081] Furthermore, this method can also be applied to region R. WL4 The silicon (Si) content in region R is higher than that in region R. WL1 R WL2 The silicon (Si) content is high.

[0082] For example, Figure 5 As shown, a semiconductor layer 112 is disposed below the conductive layer 110. The semiconductor layer 112 functions as part of a source line, for example. The semiconductor layer 112 may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An interlayer insulating layer 101, such as silicon oxide (SiO2), is disposed between the semiconductor layer 112 and the conductive layer 110.

[0083] For example, Figure 4 As shown, the semiconductor layer 120 is arranged in a predetermined pattern in the X and Y directions. The semiconductor layer 120 functions as the channel region for a plurality of memory cells (memory transistors) arranged in the Z direction and for selection transistors. The semiconductor layer 120 is, for example, a semiconductor layer of polycrystalline silicon (Si). Figure 5As shown, the semiconductor layer 120 has a generally cylindrical shape, and an insulating layer 125 such as silicon oxide is disposed in the central part.

[0084] Semiconductor layer 120 has semiconductor region 120 L and the semiconductor region 120 located above it U Additionally, the semiconductor layer 120 has connections to the semiconductor region 120. L The upper end and semiconductor region 120 U The lower semiconductor region 120 J Connected to semiconductor region 120 L The lower end of the impurity region 122 and the connection to the semiconductor region 120 U The impurity region 121 at the upper end.

[0085] Semiconductor Area 120 L It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 L The outer peripheral surface is surrounded by multiple conductive layers 110, and faces these multiple conductive layers 110.

[0086] Semiconductor Area 120 U It is a roughly cylindrical region extending in the Z direction. Semiconductor region 120 U The outer peripheral surface is surrounded by multiple conductive layers 110, and faces these multiple conductive layers 110.

[0087] Semiconductor Area 120 J Set in the semiconductor region 120 L The multiple conductive layers 110 facing each other are located at the top. Additionally, the semiconductor region 120... J Set in the semiconductor region 120 U The semiconductor region 120 is located below the multiple opposing conductive layers 110. J The width in the X and Y directions is 120 times that of the semiconductor region. L The width in the X and Y directions and the semiconductor region 120 U It has a large width in both the X and Y directions.

[0088] Impurity region 122 is connected to the aforementioned semiconductor layer 112. Figure 5 In the example, semiconductor region 120 L The boundary line between the lower end of the impurity region 122 and the upper end of the impurity region 122 is shown by a dashed line. The impurity region 122 contains, for example, P-type impurities such as boron (B).

[0089] Impurity region 121 contains, for example, N-type impurities such as phosphorus (P). Figure 5 In the example, semiconductor region 120U The boundary line between the upper end of the impurity region 121 and the lower end of the impurity region 121 is shown by a dashed line. The impurity region 121 is connected to contact element Ch and contact element Vy. Figure 4 And connected to bit line BL.

[0090] The gate insulating film 130 has a generally bottomed cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. For example, Figure 6 As shown, the gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, a bulk insulating film 133, and a high dielectric constant insulating film 134 stacked between the semiconductor layer 120 and the conductive layer 110. The tunnel insulating film 131 and the bulk insulating film 133 are insulating films such as silicon oxide (SiO2). The charge storage film 132 is a film capable of storing charge, such as silicon nitride (Si3N4). The high dielectric constant insulating film 134 is a metal oxide film such as aluminum oxide (Al2O3). The tunnel insulating film 131, the charge storage film 132, the bulk insulating film 133, and the high dielectric constant insulating film 134 have a generally cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120, except for the contact portion between the semiconductor layer 120 and the semiconductor layer 112.

[0091] [Contact Connection Area R] C4T [Construction]

[0092] For example, Figure 3 As shown, the contact connection area R of the storage block BLK C4T It has two insulating layers OST arranged in the Y direction. Additionally, a small contact connection area r is provided between these two insulating layers OST. C4T Additionally, a small conductive layer connection region r is provided between the inter-block insulating layer ST and the insulating layer OST. 110 These regions extend in the X direction along the inter-block insulation layer ST.

[0093] For example, Figure 9 As shown, the insulating layer OST extends in the Z direction and is connected to the semiconductor layer 112 at its lower end. The insulating layer OST may contain, for example, silicon oxide (SiO2).

[0094] Contact connection small area r C4T It has a plurality of insulating layers 110A arranged in the Z direction corresponding to a plurality of conductive layers 110 and a plurality of contacts C4a extending in the Z direction.

[0095] The insulating layer 110A is a generally plate-shaped insulating layer extending in the X direction. The insulating layer 110A may include an insulating layer such as silicon nitride (SiN). An interlayer insulating layer 101 such as silicon oxide (SiO2) is provided between the plurality of insulating layers 110A arranged in the Z direction. Additionally, as... Figure 10As shown, a silicon layer 110B containing silicon (Si) is disposed between the lower surface of the insulating layer 110A and the upper surface of the interlayer insulating layer 101.

[0096] Furthermore, the silicon layer 110B may be primarily composed of silicon (Si). Additionally, the silicon layer 110B may not contain oxygen (O), or the oxygen (O) content in the silicon layer 110B may be lower than the oxygen (O) content in the insulating layer 101. Furthermore, the silicon layer 110B may not contain nitrogen (N), or the nitrogen (N) content in the silicon layer 110B may be lower than the nitrogen (N) content in the insulating layer 110A.

[0097] Insulation layer 110A ( Figure 10 For example, set in reference Figure 6 The region R of the conductive layer 110 is described. WL1 R WL4 Corresponding height position. Silicon layer 110B ( Figure 10 For example, set in reference Figure 6 The region R of the conductive layer 110 is described. WL3 Corresponding height position. Contact connection area R C4T Interlayer insulating layer 101 is provided, for example, in the storage hole region R. MH The height position corresponding to the interlayer insulation layer 101 in the middle.

[0098] For example, Figure 2 As shown, multiple contacts C4a are arranged in the X direction. Contacts C4a may include laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). The outer peripheral surfaces of contacts C4a are surrounded by an insulating layer 110A and an interlayer insulating layer 101.

[0099] For example, Figure 10 As shown, an insulating layer 110C is provided between the contact C4a and the insulating layer 110A. Additionally, an insulating layer 110D is provided between the contact C4a and the silicon layer 110B. The insulating layers 110C and 110D may contain, for example, silicon oxide (SiO2). The insulating layers 110C and 110D are respectively positioned at heights corresponding to those of the insulating layer 110A and the silicon layer 110B.

[0100] For example, Figure 3 As shown, the conductive layer connects to a small region r. 110 Narrow portion 110 having conductive layer 110 C4T For example, Figure 2 As shown, two adjacent storage hole regions R in the X direction MH The multiple conductive layers 110 contained therein pass through the narrow portion 110 C4T And they are interconnected.

[0101] [Contact Connection Area R] BLT [Construction]

[0102] For example, Figure 12 As shown, the contact connection area R BLT It has a plurality of insulating layers 110A arranged in the Z direction corresponding to a plurality of conductive layers 110 and a plurality of contacts C4b extending in the Z direction.

[0103] In the contact connection area R BLT In the middle, the small contact area r C4T Similarly, in the region R of the conductive layer 110 WL1 R WL4 An insulating layer 110A is provided at the corresponding height position. Additionally, in the region R with the conductive layer 110... WL3 A silicon layer 110B is positioned at the corresponding height location. Additionally, the contact connection area R... BLT Interlayer insulating layer 101 is provided, for example, in the storage hole region R. MH The height position corresponding to the interlayer insulation layer 101 in the middle.

[0104] For example, Figure 11 As shown, multiple contacts C4b are arranged in the X and Y directions. Contacts C4b may include laminated films of barrier conductive films such as titanium nitride (TiN) and metal films such as tungsten (W). The outer peripheral surfaces of contacts C4b are surrounded by an insulating layer 110A and an interlayer insulating layer 101.

[0105] A reference is provided between the contact C4b and the insulating layer 110A. Figure 10 The insulating layer 110C is described. Additionally, a reference is provided between the contact C4b and the silicon layer 110B. Figure 10 The insulating layer 110D is described. Insulating layers 110C and 110D are respectively disposed at height positions corresponding to insulating layer 110A and silicon layer 110B.

[0106] [First Connection Region R] HU1 [Construction]

[0107] like Figure 13 As shown, the first connection region R of storage block BLK HU1 It has a small contact connection area r CC1 Additionally, the first join region R of a portion of the storage block BLK. HU1 Having the contact connection area r as described above C4T .

[0108] like Figure 14 As shown, the small contact connection area r CC1 The end in the X direction has multiple conductive layers 110. Additionally, in the contact connection small region r...CC1 Multiple contacts CC are provided, arranged in a matrix when viewed from the Z direction. These multiple contacts CC are connected to the conductive layer 110. Furthermore, these multiple contacts CC are connected via a first connection region R. HU1 The contact C4a is electrically connected to the transistor disposed on the upper surface of the semiconductor substrate 100.

[0109] Additionally, in the first connection region R HU1 A support structure HR is provided near the contact element CC. The support structure HR may contain, for example, silicon oxide (SiO2).

[0110] [Second Connection Region R] HU2 [Construction]

[0111] like Figure 13 As shown, the second join region R of storage block BLK HU2 It has a small contact connection area r CC2 Additionally, the storage block BLK has the contact connection area r as described above. C4T .

[0112] Contact connection small area r CC2 It comprises a portion of multiple conductive layers 110. Additionally, in the small contact connection region r... CC2 A plurality of contacts CC are provided, arranged in the X direction. These contacts CC are connected to the conductive layer 110. Furthermore, these contacts CC are connected via a second connection region R. HU2 The contact C4a is electrically connected to the transistor disposed on the upper surface of the semiconductor substrate 100.

[0113] Additionally, although the diagram is omitted, it is in the second connection region R HU2 References are also set. Figure 14 The supporting structure HR is described.

[0114] [Manufacturing Method]

[0115] Next, refer to Figures 15-39 The manufacturing method of memory die MD is explained. Figures 15-39 This is a schematic cross-sectional view illustrating a method for manufacturing a memory die (MD). Furthermore, Figures 15-25 , Figures 28-33 , Figure 35 and Figure 37 It shows the relationship with Figure 5 The corresponding cross-section. Additionally... Figure 26 , Figure 27 , Figure 34 , Figure 36 , Figure 38 and Figure 39 It shows the relationship with Figure 9 The corresponding cross section.

[0116] During the manufacturing of the memory die MD in this embodiment, for example, Figure 15 As shown, a semiconductor layer 112A of silicon or the like, a sacrificial layer 112B of silicon nitride or the like, and a semiconductor layer 112C of silicon or the like are formed on the interlayer insulating layer 101. Furthermore, for example, the formation of the interlayer insulating layer 101, the formation of the silicon layer 110B, and the formation of the insulating layer 110A are repeatedly performed. This process is performed, for example, by a method such as CVD (Chemical Vapor Deposition).

[0117] Next, for example, Figure 16 As shown, a plurality of memory vias LMH are formed at positions corresponding to semiconductor layer 120. Each memory via LMH is a through-hole extending in the Z direction and penetrating the interlayer insulating layer 101, insulating layer 110A, semiconductor layer 112C, and sacrificial layer 112B, exposing the upper surface of semiconductor layer 112A. This process is performed, for example, by methods such as RIE.

[0118] Next, for example, Figure 17 As shown, an amorphous silicon film 120A is formed inside the storage hole LMH. This process is performed, for example, by a method such as CVD. Furthermore, in this process, an insulating film such as silicon oxide (SiO2) or silicon nitride (SiN) may also be formed before the formation of the amorphous silicon film 120A.

[0119] Next, for example, Figure 18 As shown, the portion located near the upper end of the storage hole LMH is removed. This process is performed, for example, by methods such as RIE.

[0120] Next, for example, Figure 19 As shown, a portion of the topmost interlayer insulating layer 101 is removed to enlarge the radius of the upper end of the memory via LMH. This process is performed, for example, by wet etching.

[0121] Next, for example, Figure 20 As shown, an amorphous silicon film 120A is formed near the upper end of the storage via LMH. This process is performed, for example, by a method such as CVD.

[0122] Next, for example, Figure 21 As shown, for reference Figure 20 On the upper surface of the structure described, the formation of interlayer insulating layer 101, silicon layer 110B, and insulating layer 110A are repeatedly performed. This process is carried out, for example, by a method such as CVD.

[0123] Next, for example, Figure 22As shown, a plurality of memory vias UMH are formed at positions corresponding to the semiconductor layer 120. Each memory via UMH is a through-hole extending in the Z direction and penetrating the interlayer insulating layer 101 and the insulating layer 110A, exposing the upper surface of the amorphous silicon film 120A. This process is performed, for example, by a method such as RIE (Residual Insulation).

[0124] Next, for example, Figure 23 As shown, the amorphous silicon film 120A is removed. This process is performed, for example, by wet etching.

[0125] Next, for example, Figure 24 As shown, a gate insulating film 130, a semiconductor layer 120, and an insulating layer 125 are formed inside the memory holes LMH and UMH. In this process, for example, a film formation based on CVD is performed to form an amorphous silicon film inside the memory holes LMH and UMH. Furthermore, for example, the crystal structure of the amorphous silicon film is modified by annealing or the like.

[0126] Next, for example, Figure 25 and Figure 26 As shown, a trench STA (through-hole) is formed at the position corresponding to the interlayer insulating layer ST, and a trench OSTA (through-hole) is formed at the position corresponding to the insulating layer OST. The trenches STA and OSTA are trenches (through-holes) that extend in the Z and X directions and truncate the interlayer insulating layer 101, insulating layer 110A, and semiconductor layer 112C in the Y direction, exposing the upper surface of the sacrificial layer 112B. This process is performed, for example, by a method such as RIE (Residual Insulation).

[0127] Next, for example, Figure 27 As shown, an insulating layer OST is formed inside the OSTA tank. This process is performed, for example, by methods such as CVD.

[0128] Next, for example, Figure 28 As shown, a protective film STB, such as silicon nitride, is formed on the side surface of the tank STA in the Y direction. In this process, an insulating film, such as silicon nitride, is formed on the side surface and bottom surface of the tank STA in the Y direction, for example, by a method such as CVD. Furthermore, the portion of the insulating film covering the bottom surface of the tank STA is removed by a method such as RIE.

[0129] Next, for example, Figure 29 and Figure 30 As shown, a portion of the sacrificial layer 112B and the gate insulating film 130 are removed, exposing a portion of the semiconductor layer 120. This process is performed, for example, by a wet etching method.

[0130] Next, for example, Figure 31 As shown, a semiconductor layer 112 is formed. This process is performed, for example, by methods such as epitaxial growth.

[0131] Next, for example, Figure 32 As shown, the protective film STB is removed. This process is performed, for example, by wet etching.

[0132] Next, for example, Figure 33 and Figure 34 As shown, the insulating layer 110A is removed via the slot STA. This forms a hollow structure comprising a plurality of interlayer insulating layers 101 arranged in the Z direction and the structures (semiconductor layer 120, gate insulating film 130, and insulating layer 125) within the memory holes LMH and UMH supporting the interlayer insulating layers 101. Furthermore, a portion of the lower surface of the interlayer insulating layer 101, the upper surface of the silicon layer 110B, and the outer peripheral surface of the gate insulating film 130 are exposed. This process is performed, for example, by a wet etching method.

[0133] In addition, such as Figure 34 As shown, in this process, in the small contact connection area r C4T Residual insulation layer 110A. Additionally, although not shown in the diagram, in the contact connection area R... BLT Residual insulation layer 110A (reference) Figure 12 ).

[0134] Next, for example, Figure 35 and Figure 36 As shown, a conductive layer 110 is formed. This process is performed, for example, by using CVD methods with metal halides such as tungsten hexafluoride (WF6), tungsten hexachloride (WCl6), tungsten hexabromide (WBr6), molybdenum hexafluoride (MoF6), molybdenum hexachloride (MoCl6), and molybdenum hexabromide (MoBr6). When tungsten hexafluoride (WF6) is used, a chemical reaction occurs between tungsten hexafluoride (WF6) and the silicon layer 110B: 2WF6 (gas) + 3Si (solid) → 2W (gas) + 3SiF4 (gas). Therefore, tungsten (W) is formed as a solid on the upper and lower surfaces of the interlayer insulating layer 101, while silicon (Si) and fluorine (F) are released as gases.

[0135] Furthermore, in this embodiment, the silicon layer 110B is formed on the upper surface of the interlayer insulating layer 101. In this method, even after the conductive layer 110 is formed, silicon (Si) in the silicon layer 110B remains in the conductive layer 110. As a result, for example, as shown in the reference... Figures 6-8 As explained, sometimes the region R near the lower surface of the conductive layer 110 WL3 The silicon (Si) content in this layer is higher than that in other regions of the conductive layer 110.

[0136] Next, for example, Figure 37As shown, an inter-block insulating layer ST is formed within the STA trench. This process is performed, for example, by methods such as CVD and RIE.

[0137] Next, for example, Figure 38 As shown, a contact hole CH is formed at the position corresponding to contact C4a. Additionally, although not shown in the diagram, a contact hole CH is also formed at the position corresponding to contact C4b. The contact hole CH is a through-hole extending in the Z direction and penetrating the interlayer insulating layer 101, the insulating layer 110A, and the silicon layer 110B. This process is performed, for example, by a method such as RIE (Reinforcing Interlayer).

[0138] Next, for example, Figure 39 As shown, insulating layers 110C and 110D are formed on the inner peripheral surface of the contact hole CH. This process can be performed, for example, by oxidation. Alternatively, this process can be performed by selectively removing a portion of the insulating layer 110A and the silicon layer 110B using methods such as wet etching, and then forming an insulating layer in the removed portion using methods such as CVD.

[0139] Next, for example, Figure 9 and Figure 12 As shown, contacts C4a and C4b are formed inside the contact hole CH. This process is performed, for example, by methods such as CVD and RIE.

[0140] After that, wiring is formed, and the wafer is divided by slicing to form the memory die (MD).

[0141] [Comparative Example]

[0142] Next, refer to Figure 40 and Figure 41 The manufacturing method of the comparative example semiconductor memory device will be described. Figure 40 and Figure 41 This is a schematic cross-sectional view used to illustrate the manufacturing method of a comparative example semiconductor memory device.

[0143] In the manufacturing method of the comparative example semiconductor memory device, in conjunction with Figure 15 In the corresponding process, such as Figure 40 As shown, no silicon layer 110B is formed. Additionally, in relation to... Figure 21 In the corresponding process, such as Figure 41 As shown, no silicon layer 110B is formed.

[0144] In the manufacturing method of the comparative example semiconductor memory device, in conjunction with Figure 35 and Figure 36In the corresponding process, a conductive layer 110 is formed. This process is carried out, for example, by using a CVD method with a tungsten hexafluoride (WF6) metal halide. When the conductive layer 110 is formed by such a method, fluorine (F) may sometimes remain in the conductive layer 110.

[0145] Here, fluorine (F) in conductive layer 110 may sometimes diffuse into other components during subsequent thermal processes, thereby removing the insulating film, such as silicon oxide (SiO2).

[0146] For example, in Figure 42 In this example, fluorine (F) in conductive layer 110 reaches bulk insulating film 133 via high dielectric constant insulating film 134, and a portion of bulk insulating film 133 is removed to form voids V. In such cases, leakage current may sometimes occur between semiconductor layer 120 and conductive layer 110.

[0147] Additionally, for example, in Figure 43 In this example, fluorine (F) in conductive layer 110 reaches interlayer insulating layer 101, and a portion of interlayer insulating layer 101 is removed, forming a void V. In such cases, leakage current may sometimes occur between two adjacent conductive layers 110 in the Z direction.

[0148] [Effect]

[0149] In the method for manufacturing a semiconductor memory device according to this embodiment, referring to Figure 15 Explanation of procedures and references Figure 21 In the described process, a silicon layer 110B is formed. Therefore, as described above, it is possible to... Figure 35 and Figure 36 In the corresponding process, fluorine (F) and other substances are appropriately removed to suppress the generation of leakage current as described above.

[0150] Furthermore, in semiconductor memory devices manufactured using this method, for example, as shown in the reference... Figures 6-8 As explained, silicon (Si) is sometimes included in the conductive layer 110.

[0151] Here, if the silicon (Si) content in the conductive layer 110 increases, the resistivity of the conductive layer 110 may sometimes increase. Therefore, for example, if the region R in the YZ cross section of the conductive layer 110... WL1 ( Figure 6 If the silicon (Si) content in the conductive layer 110 increases, the charging and discharging time required for the conductive layer 110 may sometimes increase. Additionally, for example, if the region R near the gate insulating film 130 of the conductive layer 110... WL2 ( Figure 6 If the silicon (Si) content in the gate insulating film becomes too high, it may sometimes be impossible to supply an electric field to the gate insulating film 130 appropriately.

[0152] Here, as described above, in the semiconductor memory device manufacturing method of this embodiment, the silicon layer 110B is provided on the upper surface of the interlayer insulating layer 101, and is not provided on, for example, the outer peripheral surface of the gate insulating film 130. Therefore, in the region R near the center of the YZ cross-section of the conductive layer 110... WL1 and the region R near the gate insulating film 130 of the conductive layer 110 WL2 It does not contain silicon (Si), or it can make these regions R WL1 R WL2 The silicon (Si) content in this region is lower than that in other regions. Therefore, a semiconductor memory device can be provided that suppresses the generation of leakage current as described above and operates appropriately.

[0153] [Other Implementation Methods]

[0154] The semiconductor memory device and its manufacturing method according to the first embodiment have been described above. However, the semiconductor memory device and its manufacturing method according to the first embodiment are merely examples, and the specific configuration and method can be appropriately adjusted.

[0155] For example, in the first embodiment, when referring to Figure 15 Explanation of procedures and references Figure 21 In the described process, a silicon layer 110B is formed at the location where it is in contact with the upper surface of the interlayer insulating layer 101 and the lower surface of the insulating layer 110A. However, in these processes, it is also possible to, for example... Figure 44 As illustrated, a silicon layer 110B is formed at a location where it is in contact with the lower surface of the interlayer insulating layer 101 and the upper surface of the insulating layer 110A. Alternatively, for example... Figure 45 As illustrated, a silicon layer 110B is formed at both the position where it contacts the upper surface of the interlayer insulating layer 101 and the lower surface of the insulating layer 110A, and at the position where it contacts the lower surface of the interlayer insulating layer 101 and the upper surface of the insulating layer 110A.

[0156] Additionally, for example, in the examples above, when referring to Figure 15 Explanation of procedures and references Figure 21 In the described process, a silicon layer 110B is formed on at least one of the upper and lower surfaces of the entire insulating layer 110A. However, in these processes, it is also possible to, for example, Figure 46 and Figure 47 As illustrated, a silicon layer 110B is formed only on the upper surface of a portion of the insulating layer 110A, only on the lower surface of a portion of the insulating layer 110A, or only on both the upper and lower surfaces of a portion of the insulating layer 110A.

[0157] In addition, Figure 46 and Figure 47In this context, the insulating layer 110A with a silicon layer 110B is referred to as insulating layer 110Aa, and the insulating layer 110A without a silicon layer 110B is referred to as insulating layer 110Ab.

[0158] Alternatively, in such cases, for example... Figure 46 As illustrated, the thickness of the insulating layer 110A in the Z direction is adjusted so that the combined thickness of the insulating layer 110Aa and the silicon layer 110B in the Z direction is the same as the thickness of the insulating layer 110Ab in the Z direction. Alternatively, for example... Figure 47 As illustrated, the thickness of the insulating layer 110A in the Z direction is adjusted in such a way that the thickness of the insulating layer 110Aa in the Z direction is the same as the thickness of the insulating layer 110Ab in the Z direction.

[0159] Furthermore, in the first embodiment, as described above, the silicon layer 110B is formed on the upper surface of the interlayer insulating layer 101. As a result, for example, see... Figures 6-8 As explained, sometimes the region R near the lower surface of the conductive layer 110 WL3 The silicon (Si) content in this layer is higher than that in other regions of the conductive layer 110.

[0160] Here, for example, refer to Figure 44 As explained, when the silicon layer 110B is formed on the lower surface of the interlayer insulating layer 101, for example... Figure 6 , Figure 8 and Figure 48 As shown, sometimes the region R near the upper surface of the conductive layer 110 WL4 The silicon (Si) content in this layer is higher than that in other regions of the conductive layer 110.

[0161] Similarly, in, for example, refer to Figure 45 As explained, when the silicon layer 110B is formed on the upper and lower surfaces of the interlayer insulating layer 101, for example... Figure 6 , Figure 8 and Figure 49 As shown, sometimes the region R near the lower surface of the conductive layer 110 WL3 The silicon (Si) content and the region R near the upper surface of the conductive layer 110. WL4 The silicon (Si) content in this layer is higher than that in other regions of the conductive layer 110.

[0162] In addition, when using, for example, reference Figure 46 and Figure 47In the case of the described method, the distribution of silicon (Si) content in the conductive layer 110 (hereinafter referred to as "conductive layer 110a") corresponding to the insulating layer 110Aa is sometimes used as a reference. Figure 6 and Figure 8 and Figure 7 , Figure 48 or Figure 49 The distribution is explained. On the other hand, the distribution of silicon (Si) content in the conductive layer 110 (hereinafter referred to as "conductive layer 110b") corresponding to the insulating layer 110Ab sometimes becomes as follows: Figure 6 , Figure 8 and Figure 50 The distribution shown indicates that sometimes silicon (Si) is not included in the conductive layer 110b. Additionally, sometimes region R of the conductive layer 110b... WL3 R WL4 The silicon (Si) content in the conductive layer 110a region R is higher than that in the region R. WL3 R WL4 The silicon (Si) content in it is low.

[0163] Additionally, as described above, the storage hole area R is provided with MH Insulation layer 110A in reference Figure 33 and Figure 34 It was removed during the described process. Additionally, it is located in the storage hole area R. MH The silicon layer 110B in the reference Figure 35 and Figure 36 In the described process, the gas produced is either released through a chemical reaction or contained within the conductive layer 110. On the other hand, as described above, in the small contact connection area r... C4T and contact connection area R BLT In the process, the insulating layer 110A and the silicon layer 110B are not removed and remain.

[0164] Therefore, in, for example, as reference Figure 45 As explained, when silicon layers 110B are formed on the upper and lower surfaces of insulating layer 110A, for example, Figure 51 and Figure 52 As illustrated, in the contact connection small area r C4T and contact connection area R BLT Such a structure remains. (This was achieved using a reference...) Figure 44 , Figure 46 or Figure 47 The same applies to the methods described.

[0165] Additionally, in, for example, refer to Figure 46As explained, when the thickness of the insulating layer 110A in the Z direction is adjusted so that the total thickness of the insulating layer 110Aa and the silicon layer 110B in the Z direction is the same as the thickness of the insulating layer 110Ab in the Z direction, for example, as... Figure 53 As illustrated, the thickness of the conductive layers 110a and 110b corresponding to these insulating layers 110Aa and 110Ab in the Z direction is also the same.

[0166] On the other hand, in, for example, reference Figure 47 As explained, when the thickness of the insulating layer 110A in the Z direction is adjusted to be the same as the thickness of the insulating layer 110Ab in the Z direction, for example, as... Figure 54 As illustrated, the thickness of the conductive layer 110a corresponding to the insulating layer 110Aa in the Z direction is greater than the thickness of the conductive layer 110b corresponding to the insulating layer 110Ab in the Z direction.

[0167] Furthermore, in the above examples, the small contact connection region r is exemplified as the area remaining in the final structure of the insulating layer 110A and the silicon layer 110B. C4T and contact connection area R BLT However, these areas are merely illustrative; the remaining areas of insulating layer 110A and silicon layer 110B in the final structure can be any area within the memory die MD. Alternatively, the memory die MD may not have such remaining areas of insulating layer 110A and silicon layer 110B in the final structure.

[0168] [other]

[0169] While some embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: Multiple conductive layers and multiple interlayer insulating layers are arranged alternately in the first direction; A semiconductor layer extends in the first direction and faces the plurality of conductive layers; and A gate insulating film is disposed between the plurality of conductive layers and the semiconductor layer. The plurality of interlayer insulating layers includes a first interlayer insulating layer and a second interlayer insulating layer that are adjacent in the first direction. The plurality of conductive layers includes a first conductive layer disposed between the first interlayer insulating layer and the second interlayer insulating layer. The first conductive layer is a single, independent layer, possessing: Area 1; The second region is disposed between the first region and the gate insulating film; and The third region is located between the first region and the first interlayer insulation layer. Regions 1 through 3 contain metal. The third region contains silicon. The first region and the second region do not contain silicon, or the silicon content in the first region and the second region is lower than the silicon content in the third region.

2. The semiconductor memory device according to claim 1, The first conductive layer includes a fourth region disposed between the first region and the insulating layer between the second layer. The fourth region contains metal and silicon. The first region and the second region do not contain silicon, or the silicon content in the first region and the second region is lower than the silicon content in the fourth region.

3. The semiconductor memory device according to claim 1, The first conductive layer includes a fourth region disposed between the first region and the insulating layer between the second layer. The fourth region contains metal. The fourth region does not contain silicon, or the silicon content in the fourth region is lower than the silicon content in the third region.

4. The semiconductor memory device according to claim 1, The plurality of interlayer insulating layers includes a third interlayer insulating layer and a fourth interlayer insulating layer that are adjacent in the first direction. The plurality of conductive layers includes a second conductive layer disposed between the third interlayer insulating layer and the fourth interlayer insulating layer. The second conductive layer comprises: Area 5; A sixth region is disposed between the fifth region and the gate insulating film; and The seventh region is located between the fifth region and the third layer of insulation. Regions 5 through 7 contain metal. The seventh region contains silicon. The fifth and sixth regions do not contain silicon, or the silicon content in the fifth and sixth regions is lower than the silicon content in the seventh region.

5. The semiconductor memory device according to claim 4, The second conductive layer includes an eighth region disposed between the fifth region and the insulating layer between the fourth layer. The eighth region contains metal and silicon. The fifth and sixth regions do not contain silicon, or the silicon content in the fifth and sixth regions is lower than the silicon content in the eighth region.

6. The semiconductor memory device according to claim 1, The plurality of interlayer insulating layers includes a fifth interlayer insulating layer and a sixth interlayer insulating layer adjacent to each other in the first direction. The plurality of conductive layers includes a third conductive layer disposed between the fifth interlayer insulating layer and the sixth interlayer insulating layer. The third conductive layer comprises: Area 9; The 10th region is disposed between the 9th region and the gate insulating film; and Region 11 is located between Region 9 and the insulating layer of Layer 5. Regions 9 through 11 contain metal. Regions 9, 10, and 11 do not contain silicon, or the silicon content in regions 9, 10, and 11 is lower than the silicon content in region 3.

7. The semiconductor memory device according to claim 6, The third conductive layer includes a 12th region disposed between the 9th region and the insulating layer between the 6th layer. The 12th region contains metal. The 12th region does not contain silicon, or the silicon content in the 12th region is lower than the silicon content in the 3rd region.

8. A method for manufacturing a semiconductor memory device, comprising the method for manufacturing the semiconductor memory device according to any one of claims 1 to 7. A layered structure is formed, the layered structure comprising: Multiple first insulating layers and multiple interlayer insulating layers are arranged alternately in the first direction; A silicon layer, disposed between one of the plurality of first insulating layers and one of the plurality of interlayer insulating layers, comprising silicon, A first through hole is formed, penetrating the stacked structure. A gate insulating film and a semiconductor layer extending in the first direction are formed inside the first through-hole. A second through hole is formed, penetrating the stacked structure. The plurality of first insulating layers are removed through the second through-hole, exposing at least a portion of the gate insulating film and at least a portion of the silicon layer. Metal halide is supplied to at least a portion of the gate insulating film and at least a portion of the silicon layer through the second through-hole to form a plurality of conductive layers facing the semiconductor layer across the gate insulating film.

9. The method for manufacturing a semiconductor memory device according to claim 8, The first insulating layer comprises nitrogen and silicon. The interlayer insulation layer contains oxygen and silicon.

10. The method for manufacturing a semiconductor memory device according to claim 8, The metal halide comprises: Tungsten or molybdenum; and Fluorine, chlorine, or bromine.

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