Semiconductor memory device and method of manufacturing the same

Abstract

Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the same. The semiconductor memory device of the embodiment includes: a first interlayer insulating layer and a second interlayer insulating layer arranged along a first direction; a gate electrode layer disposed between the first interlayer insulating layer and the second interlayer insulating layer; a semiconductor layer extending along the first direction and facing the gate electrode layer in a second direction intersecting the first direction; a first insulating layer disposed between the gate electrode layer and the semiconductor layer; a charge accumulation layer disposed between the gate electrode layer and the first insulating layer and comprising a metal element; a second insulating layer disposed between the gate electrode layer and the charge accumulation layer; and a first region disposed between the charge accumulation layer and the first insulating layer and comprising manganese (Mn), silicon (Si), and oxygen (O).

Description

[0001] This application is based on and claims the priority of Japanese Patent Application No. 2021-046802, filed on March 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor memory devices and methods for manufacturing the same. Background Technology

[0003] Three-dimensional NAND flash memory, with its storage cells arranged in three dimensions, enables high integration and low cost. The storage cells of a three-dimensional NAND flash memory include a charge accumulation layer for maintaining charge. To improve the performance of three-dimensional NAND flash memory, the application of a layer containing metal elements in the charge accumulation layer has been investigated. However, when a layer containing metal elements is applied to the charge accumulation layer, the metal elements diffuse, raising concerns about a decrease in the reliability of the three-dimensional NAND flash memory. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor memory device with improved reliability.

[0005] The semiconductor memory device of the embodiment includes: a first interlayer insulating layer and a second interlayer insulating layer arranged along a first direction; a gate electrode layer disposed between the first interlayer insulating layer and the second interlayer insulating layer; a semiconductor layer extending along the first direction and facing the gate electrode layer in a second direction intersecting the first direction; a first insulating layer disposed between the gate electrode layer and the semiconductor layer; a charge storage layer disposed between the gate electrode layer and the first insulating layer and comprising a metal element; a second insulating layer disposed between the gate electrode layer and the charge storage layer; and a first region disposed between the charge storage layer and the first insulating layer and comprising manganese (Mn), silicon (Si), and oxygen (O).

[0006] Based on the above configuration, a semiconductor memory device with improved reliability can be provided. Attached Figure Description

[0007] Figure 1 It is a semiconductor memory device implemented in this way.

[0008] Figure 2 This is an equivalent circuit diagram of the memory cell array of a semiconductor memory device according to an implementation method.

[0009] Figure 3 This is a schematic cross-sectional view of a portion of the memory cell array of a semiconductor memory device according to an embodiment.

[0010] Figure 4 This is a schematic cross-sectional view of a portion of the memory cell array of a semiconductor memory device according to an embodiment.

[0011] Figure 5 This is an enlarged schematic cross-sectional view of a portion of the memory cell array of a semiconductor memory device according to an embodiment.

[0012] Figure 6 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0013] Figure 7 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0014] Figure 8 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0015] Figure 9 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0016] Figure 10 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0017] Figure 11 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0018] Figure 12 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0019] Figure 13 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0020] Figure 14 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0021] Figure 15 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0022] Figure 16 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0023] Figure 17 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0024] Figure 18 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0025] Figure 19 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0026] Figure 20 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0027] Figure 21 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0028] Figure 22 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0029] Figure 23 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0030] Figure 24 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment.

[0031] Figure 25 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Detailed Implementation

[0032] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have already been described will be omitted as appropriate.

[0033] Additionally, in this specification, terms such as "upper" or "lower" are sometimes used for convenience. "Upper" or "lower" are merely terms indicating relative positional relationships within the accompanying drawings, and do not specify positional relationships relative to gravity.

[0034] In the qualitative and quantitative analysis of the chemical composition of the components constituting the semiconductor memory device described in this specification, methods such as secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), or electron energy loss spectrometry (EELS) can be used. Furthermore, in measuring the thickness of the components constituting the semiconductor memory device, the distance between components, etc., transmission electron microscopy (TEM) can be used, for example. In addition, in the identification of the constituent materials of the components constituting the semiconductor memory device and the comparison of their proportions, methods such as transmission electron microscopy, X-ray diffraction (XRD), electron beam diffraction (EBD), X-ray photoelectron spectroscopy (XPS), or synchronous radiation X-ray absorption fine structure (XAFS) can be used.

[0035] The semiconductor memory device of the embodiment includes: a first interlayer insulating layer and a second interlayer insulating layer arranged along a first direction; a gate electrode layer disposed between the first interlayer insulating layer and the second interlayer insulating layer; a semiconductor layer extending along the first direction and facing the gate electrode layer in a second direction intersecting the first direction; a first insulating layer disposed between the gate electrode layer and the semiconductor layer; a charge storage layer disposed between the gate electrode layer and the first insulating layer and containing a metal element; a second insulating layer disposed between the gate electrode layer and the charge storage layer; and a first region disposed between the charge storage layer and the first insulating layer and containing manganese (Mn), silicon (Si), and oxygen (O).

[0036] The semiconductor memory device described in this embodiment is a three-dimensional NAND flash memory 100. The three-dimensional NAND flash memory 100 uses a layer containing metal elements in its charge accumulation layer.

[0037] Figure 1 This is a block diagram of a semiconductor memory device according to an implementation method. Figure 1 The circuit configuration of the three-dimensional NAND flash memory 100 according to the embodiment is shown. For example... Figure 1As shown, the three-dimensional NAND flash memory 100 includes a memory cell array 101, a word line driver circuit 102, a row decoder circuit 103, a sense amplifier circuit 104, a column decoder circuit 105, and a control circuit 106.

[0038] Figure 2 This is an equivalent circuit diagram of the memory cell array of a semiconductor memory device according to an implementation method. Figure 2 The wiring structure within the memory cell array 101 is schematically shown. The memory cell array 101 of the embodiment has a three-dimensional structure formed by arranging a plurality of memory cells MC in a three-dimensional manner.

[0039] the following, Figure 2 The z-direction shown is an example of a first direction. The y-direction is an example of a second direction. The x-direction is an example of a third direction. The y-direction intersects the x-direction. The z-direction intersects both the x-direction and the y-direction. For example, the x-direction is orthogonal to the y-direction. For example, the z-direction is orthogonal to both the x-direction and the y-direction. Furthermore, directions opposite to the z-direction are also considered first directions. Additionally, directions opposite to the y-direction are also considered second directions. Additionally, directions opposite to the x-direction are also considered third directions.

[0040] Storage cell array 101, such as Figure 2 The device shown has multiple memory cells MC, source select transistor SST, drain select transistor SDT, multiple word lines WLa and WLb, multiple bit lines BL1 to BL4, a common source line CSL, a source select gate line SGS, and multiple drain select gate lines SGD.

[0041] Multiple memory cells MC are connected in series in the z-direction. These multiple memory cells MC are connected between the source selection transistor SST and the drain selection transistor SDT.

[0042] The memory cell MC stores data corresponding to the amount of charge stored in the charge accumulation layer. The threshold voltage of the transistor in the memory cell MC changes according to the amount of charge stored in the charge accumulation layer. This change in the threshold voltage causes a change in the transistor's on-state current. For example, if a state with a high threshold voltage and low on-state current is defined as data "0", and a state with a low threshold voltage and high on-state current is defined as data "1", then the memory cell MC can store one bit of data, either "0" or "1".

[0043] Word lines WLa and WLb extend along the x-direction. Word lines WLa and WLb are connected to the gate electrode of the memory cell MC. Word lines WLa and WLb control the gate voltage of the memory cell MC.

[0044] Word lines WLa and WLb are electrically disconnected. Word lines WLa and WLb are electrically connected. Word lines WLb and WLb are electrically connected.

[0045] The source-select transistor SST is electrically connected to the common source line CSL. The source-select transistor SST is controlled by the voltage applied to the source-select gate line SGS.

[0046] The drain-select transistor SDT is connected to BL1 through BL4. The drain-select transistor SDT is controlled by the voltage applied to the drain-select gate line SGD.

[0047] Multiple word lines WLa and WLb are electrically connected to the word line driver circuit 102. Multiple bit lines BL1 to BL4 are connected to the sense amplifier circuit 104.

[0048] The line decoder circuit 103 has the function of selecting word lines WLa and WLb according to the input line address signal. The word line driver circuit 102 has the function of applying a predetermined voltage to the word lines WLa and Wlb selected by the line decoder circuit 103.

[0049] The column decoder circuit 105 has the function of selecting a bit line BL based on the input column address signal. The sense amplifier circuit 104 has the function of applying a predetermined voltage to the bit line BL selected by the column decoder circuit 105. In addition, it has the function of detecting and amplifying the current or voltage flowing in the selected bit line BL.

[0050] The control circuit 106 has the functions of controlling the word line driver circuit 102, the row decoder circuit 103, the sense amplifier circuit 104, the column decoder circuit 105, and other circuits not shown.

[0051] The word line driver circuit 102, the row decoder circuit 103, the sense amplifier circuit 104, the column decoder circuit 105, and other circuits are composed, for example, of transistors and wiring layers using semiconductor layers (not shown).

[0052] For example, in Figure 2 In the process of reading data stored in the memory cell MC (enclosed by dashed lines), a readout voltage is applied to the word line WLa connected to the gate electrode of the memory cell MC. The transistor of the memory cell MC becomes ON, thereby allowing current to flow between the common source line CSL and the bit line BL1. Based on the current flowing between the common source line CSL and the bit line BL1, the data stored in the memory cell MC is determined.

[0053] For example, the current flowing in the bit line BL1 is amplified by the sensing amplifier circuit 104, and the data stored in the memory cell MC is determined by the control circuit 106. Alternatively, the voltage change of the bit line BL1 is amplified by the sensing amplifier circuit 104, and the data stored in the memory cell MC is determined by the control circuit 106.

[0054] exist Figure 2 The example illustrates a case where there are four memory cells (MCs) connected in series and four bit lines. However, the number of memory cells (MCs) connected in series and the number of bit lines are not limited to four or four.

[0055] Figure 3 , Figure 4 This is a schematic cross-sectional view of a portion of the memory cell array of a semiconductor memory device according to an embodiment. Figure 3 This is the xy section of the storage cell array 101. Figure 3 For inclusion Figure 4 The cross section of the BB' surface. Figure 4 This is the yz section of the storage cell array 101. Figure 4 for Figure 3 AA' section.

[0056] exist Figure 3 and Figure 4 In the diagram, the area enclosed by a dashed line represents a storage unit (MC). Figure 3 and Figure 4 The example shows memory cells MC1 and MC2 that are adjacent in the y direction.

[0057] Figure 5 An enlarged schematic cross-sectional view of a portion of the memory cell array of a semiconductor memory device according to an embodiment. Figure 5 This is the yz section of the storage cell array 101. Figure 5 This is a cross-section of storage cell MC1.

[0058] The memory cell array 101 has a gate electrode layer 10, a semiconductor layer 12, a tunnel insulating layer 14, a charge storage layer 16, a block insulating layer 18, a barrier insulating layer 20, a barrier region 22, a trench insulating layer 24, an interlayer insulating layer 26, and a core insulating layer 28.

[0059] The gate electrode layer 10 includes a first gate electrode layer 10a and a second gate electrode layer 10b. The blocking region 22 includes a first region 22a, a second region 22b, and a third region 22c. The interlayer insulating layer 26 includes a first interlayer insulating layer 26a and a second interlayer insulating layer 26b.

[0060] Tunnel insulation layer 14 is an example of a first insulation layer. Block insulation layer 18 is an example of a second insulation layer. Barrier insulation layer 20 is an example of a third insulation layer.

[0061] The gate electrode layer 10 extends along the x-direction. Multiple gate electrode layers 10 are arranged along the y-direction. Each gate electrode layer 10 includes a barrier metal layer 10x and a metal layer 10y. The gate electrode layer 10 is disposed between interlayer insulating layers 26. For example, the gate electrode layer 10 is disposed between a first interlayer insulating layer 26a and a second interlayer insulating layer 26b.

[0062] The barrier metal layer 10x is, for example, a metal nitride or a metal carbide. The barrier metal layer 10x may contain, for example, titanium nitride. The barrier metal layer 10x may be, for example, titanium nitride.

[0063] Metal layer 10y is, for example, a metal. Metal layer 10y contains, for example, tungsten (W). Metal layer 10y is, for example, tungsten.

[0064] The first gate electrode layer 10a extends along the x-direction. The first gate electrode layer 10a, for example, is... Figure 2 The word line WLa shown corresponds to this. The first gate electrode layer 10a functions as the gate electrode of the transistor in the memory cell MC1. The first gate electrode layer 10a includes a barrier metal layer 10ax and a metal layer 10ay.

[0065] The second gate electrode layer 10b extends along the x-direction. The second gate electrode layer 10b is configured to be separated from the first gate electrode layer 10a in the y-direction. The second gate electrode layer 10b is adjacent to the first gate electrode layer 10a in the y-direction. For example, the second gate electrode layer 10b is adjacent to... Figure 2 The word line WLb shown corresponds to this. The second gate electrode layer 10b is electrically separated from the first gate electrode layer 10a. The second gate electrode layer 10b functions as the gate electrode of the transistor in the memory cell MC2. The second gate electrode layer 10b includes a barrier metal layer 10bx and a metal layer 10by.

[0066] Semiconductor layer 12 extends along the z-direction. Semiconductor layer 12 is disposed in the y-direction of gate electrode layer 10. Semiconductor layer 12 is disposed, for example, between first gate electrode layer 10a and second gate electrode layer 10b. Semiconductor layer 12 is, for example, cylindrical in shape.

[0067] Semiconductor layer 12 functions as the channel for the transistors in the memory cell MC.

[0068] Semiconductor layer 12 is, for example, a polycrystalline semiconductor. Semiconductor layer 12 may contain polycrystalline silicon. Semiconductor layer 12 may be, for example, polycrystalline silicon. The thickness of semiconductor layer 12 in the xy plane is, for example, 5 nm or more and 30 nm or less. The thickness of semiconductor layer 12 in the y direction is, for example, 5 nm or more and 30 nm or less.

[0069] A tunnel insulating layer 14 is disposed between the gate electrode layer 10 and the semiconductor layer 12. For example, the tunnel insulating layer 14 surrounds the semiconductor layer 12. The tunnel insulating layer 14 is disposed between the charge storage layer 16 and the semiconductor layer 12. The tunnel insulating layer 14 is disposed between the first region 22a of the blocking region 22 and the semiconductor layer 12.

[0070] The tunnel insulating layer 14 functions as a path for charge movement between the semiconductor layer 12 and the charge storage layer 16 when writing data to and erasing data from the memory cell MC. Additionally, when the memory cell MC is in a charge-holding state, it prevents the movement of charge between the semiconductor layer 12 and the charge storage layer 16.

[0071] The tunnel insulation layer 14 is an insulator. The tunnel insulation layer 14 may contain, for example, oxides, nitrides, or oxynitrides.

[0072] The tunnel insulation layer 14 may contain, for example, silicon (Si) and oxygen (O). The tunnel insulation layer 14 may contain, for example, silicon oxide. The tunnel insulation layer 14 may be, for example, silicon oxide.

[0073] The tunnel insulation layer 14 contains, for example, nitrogen (N).

[0074] The thickness of the tunnel insulation layer 14 in the y direction is, for example, more than 1 nm and less than 10 nm.

[0075] A charge storage layer 16 is disposed between the gate electrode layer 10 and the tunnel insulating layer 14. A charge storage layer 16 is disposed between the block insulating layer 18 and the tunnel insulating layer 14. A charge storage layer 16 is disposed between the block insulating layer 18 and the first region 22a of the blocking region 22. A charge storage layer 16 is disposed between the blocking insulating layer 20 and the first region 22a of the blocking region 22.

[0076] The charge storage layer 16 has the function of storing charge. Based on the charge stored in the charge storage layer 16, data is stored in the storage unit MC.

[0077] The charge accumulation layer 16 is a layer containing a metallic element. The charge accumulation layer 16 contains at least one metallic element selected from titanium (Ti), tantalum (Ta), and aluminum (Al). For example, among the metallic elements contained in the charge accumulation layer 16, the atomic concentration of the aforementioned at least one metallic element is the highest.

[0078] The charge accumulation layer 16 is, for example, a conductor. The charge accumulation layer 16 may contain, for example, a metal, a metal nitride, or a metal carbide.

[0079] The charge accumulation layer 16 contains, for example, nitrogen (N).

[0080] The charge accumulation layer 16 may contain, for example, titanium nitride. The charge accumulation layer 16 may be primarily composed of titanium nitride. Titanium nitride being the primary component of the charge accumulation layer 16 means that titanium nitride has the highest molar ratio among the substances contained in the charge accumulation layer 16. The charge accumulation layer 16 may be, for example, titanium nitride.

[0081] The charge accumulation layer 16 may contain, for example, tantalum nitride. The charge accumulation layer 16 may be primarily composed of tantalum nitride. The charge accumulation layer 16 may be, for example, tantalum nitride.

[0082] The charge accumulation layer 16 is, for example, aluminum nitride. The charge accumulation layer 16 is, for example, primarily composed of aluminum nitride. The charge accumulation layer 16 is, for example, aluminum nitride.

[0083] The charge accumulation layer 16 contains, for example, manganese (Mn).

[0084] The thickness of the charge accumulation layer 16 in the y-direction is, for example, greater than the thickness of the tunnel insulation layer 14 in the y-direction. The thickness of the charge accumulation layer 16 in the y-direction is, for example, more than 2 nm and less than 20 nm.

[0085] A block insulating layer 18 is disposed between the gate electrode layer 10 and the charge storage layer 16. A block insulating layer 18 is disposed between the gate electrode layer 10 and the barrier insulating layer 20.

[0086] The block insulating layer 18 has the function of preventing the movement of charge between the gate electrode layer 10 and the charge accumulation layer 16.

[0087] The block insulating layer 18 is an insulator. The block insulating layer 18 may contain, for example, oxides, nitrides, or oxynitrides.

[0088] The bulk insulating layer 18 may contain, for example, aluminum (Al) and oxygen (O). The bulk insulating layer 18 may contain, for example, aluminum oxide.

[0089] The bulk insulating layer 18 may contain, for example, silicon (Si) and oxygen (O). The bulk insulating layer 18 may contain, for example, silicon oxide.

[0090] The block insulating layer 18, for example, has a stacked structure. The block insulating layer 18, for example, has a stacked structure of a silicon oxide layer and an aluminum oxide layer disposed on the gate electrode layer 10 side of the silicon oxide layer.

[0091] The thickness of the block insulating layer 18 in the y-direction is, for example, greater than the thickness of the tunnel insulating layer 14 in the y-direction. The thickness of the block insulating layer 18 in the y-direction is, for example, 5 nm or more and 20 nm or less.

[0092] A barrier insulating layer 20 is disposed between the block insulating layer 18 and the charge accumulation layer 16. The barrier insulating layer 20 has the function of preventing the diffusion of the metal elements contained in the charge accumulation layer 16.

[0093] The barrier insulating layer 20 comprises silicon (Si) and nitrogen (N). For example, the barrier insulating layer 20 comprises silicon nitride. The barrier insulating layer 20 is silicon nitride.

[0094] The material of the barrier insulation layer 20 is different from that of the block insulation layer 18.

[0095] The thickness of the barrier insulating layer 20 in the y-direction is, for example, thinner than the thickness of the block insulating layer 18 in the y-direction. The thickness of the barrier insulating layer 20 in the y-direction is, for example, 0.5 nm or more and 3 nm or less.

[0096] A blocking region 22 is disposed between the charge accumulation layer 16 and the tunnel insulation layer 14. The blocking region 22 includes a first region 22a, a second region 22b, and a third region 22c. The blocking region 22 has the function of preventing the diffusion of metal elements contained in the charge accumulation layer 16.

[0097] A first region 22a is disposed between the charge accumulation layer 16 and the tunnel insulating layer 14. The first region 22a comprises manganese (Mn), silicon (Si), and oxygen (O). The first region 22a may, for example, comprise manganese silicate. The first region 22a may, for example, be primarily composed of manganese silicate. The thickness of the first region 22a in the y-direction is, for example, 0.5 nm or more and 3 nm or less.

[0098] The second region 22b is disposed between the charge storage layer 16 and the first interlayer insulating layer 26a. The second region 22b is, for example, in contact with the barrier insulating layer 20.

[0099] The second region 22b contains manganese (Mn), silicon (Si), and oxygen (O). The second region 22b may contain, for example, manganese silicate. The second region 22b may be predominantly composed of manganese silicate. The thickness of the second region 22b in the z-direction may be, for example, 0.5 nm or more and 3 nm or less.

[0100] The third region 22c is disposed between the charge storage layer 16 and the second interlayer insulating layer 26b. The third region 22c is, for example, in contact with the barrier insulating layer 20.

[0101] The third region 22c contains manganese (Mn), silicon (Si), and oxygen (O). The third region 22c may contain, for example, manganese silicate. The third region 22c may be predominantly composed of manganese silicate. The thickness of the third region 22c in the z-direction may be, for example, 0.5 nm or more and 3 nm or less.

[0102] The trench insulating layer 24 may contain, for example, silicon (Si) and oxygen (O). The trench insulating layer 24 may contain, for example, silicon oxide. The trench insulating layer 24 may be, for example, silicon oxide.

[0103] The trench insulating layer 24 is disposed between adjacent gate electrode layers 10 in the y direction. For example, it is disposed between the first gate electrode layer 10a and the second gate electrode layer 10b.

[0104] The trench insulating layer 24 is, for example, an oxide, a nitride, or a nitride. The trench insulating layer 24 may contain, for example, silicon oxide or aluminum oxide.

[0105] Interlayer insulating layers 26 are arranged in the z-direction. For example, a first interlayer insulating layer 26a and a second interlayer insulating layer 26b are arranged in the z-direction. They are disposed between adjacent gate electrode layers 10 in the z-direction. The gate electrode layer 10 is sandwiched between two interlayer insulating layers 26 in the z-direction. For example, as Figure 5 As shown, a gate electrode layer 10 is provided in the z-direction of the first interlayer insulating layer 26a. Furthermore, a second interlayer insulating layer 26b is provided in the z-direction of the gate electrode layer 10.

[0106] Interlayer insulating layer 26 is, for example, an oxide, oxynitride, or nitride. Interlayer insulating layer 26 may contain, for example, silicon (Si) and oxygen (O). Interlayer insulating layer 26 may contain, for example, silicon oxide. Interlayer insulating layer 26 may be, for example, silicon oxide. First interlayer insulating layer 26a and second interlayer insulating layer 26b may contain, for example, silicon (Si) and oxygen (O). First interlayer insulating layer 26a and second interlayer insulating layer 26b may contain, for example, silicon oxide. First interlayer insulating layer 26a and second interlayer insulating layer 26b may be, for example, silicon oxide. The thickness of interlayer insulating layer 26 in the z-direction is, for example, 5 nm or more and 30 nm or less.

[0107] The core insulating layer 28 is surrounded by the semiconductor layer 12. The core insulating layer 28 extends along the z-direction. The core insulating layer 28 is, for example, cylindrical in shape.

[0108] The core insulating layer 28 is, for example, an oxide, a nitride, or a nitride. The core insulating layer 28 may contain, for example, silicon oxide.

[0109] Next, an example of a method for manufacturing a semiconductor memory device according to an embodiment will be described.

[0110] A method for manufacturing a semiconductor memory device according to an embodiment includes: alternately and repeatedly forming a first insulating film and a second insulating film; forming a first opening penetrating the first insulating film and the second insulating film; selectively removing a portion of the second insulating film exposed on the inner surface of the first opening relative to the first insulating film; forming a first film containing a metal element in the portion where the second insulating film has been removed; forming a third insulating film on the first film; forming a semiconductor film on the third insulating film within the first opening; forming a second opening penetrating the first insulating film and the second insulating film; selectively removing the second insulating film relative to the first insulating film through the second opening, exposing the first film; forming a first metal film containing copper (Cu) and manganese (Mn) in the portion where the second insulating film has been removed, in contact with the first film; performing a first heat treatment after forming the first metal film to form a region containing manganese (Mn) between the first film and the third insulating film; removing the first metal film; forming a fourth insulating film in the portion where the first metal film has been removed; and forming a second metal film on the fourth insulating film in the portion where the first metal film has been removed.

[0111] Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment. Figures 6 to 25 This is a diagram illustrating an example of a method for manufacturing the memory cell array 101 of a three-dimensional NAND flash memory 100.

[0112] Figures 6 to 25 This is the yz section of the storage cell array 101.

[0113] Initially, a first silicon oxide film 51 and a first silicon nitride film 52 are alternately and repeatedly stacked on a semiconductor substrate (not shown). Figure 6 The first silicon oxide film 51 is an example of a first insulating film. The first silicon nitride film 52 is an example of a second insulating film.

[0114] The first silicon oxide film 51 and the first silicon nitride film 52 are formed, for example, by chemical vapor deposition (CVD). A portion of the first silicon oxide film 51 eventually becomes the interlayer insulating layer 26.

[0115] Next, a storage trench 55 is formed between the first silicon oxide film 51 and the first silicon nitride film 52. Figure 7 The storage trench 55 extends through the first silicon oxide film 51 and the first silicon nitride film 52.

[0116] Storage trench 55 is formed, for example, by photolithography and reactive ion etching (RIE).

[0117] Next, the storage trench 55 is filled with a second silicon oxide film 56. Figure 8 The second silicon oxide film 56 is formed, for example, by CVD. The second silicon oxide film 56 ultimately becomes the trench insulating layer 24.

[0118] Next, a storage hole 57 is formed that penetrates the second silicon oxide film 56, the first silicon oxide film 51, and the first silicon nitride film 52. Figure 9 Storage hole 57 is an example of a first opening. Storage hole 57 is formed, for example, by photolithography and RIE.

[0119] Next, a portion of the first silicon nitride film 52 exposed on the inner surface of the storage hole 57 is selectively removed relative to the first silicon oxide film 51. Figure 10 The first silicon nitride film 52 is moved backward in the y-direction. The first silicon nitride film 52 is removed, for example, by wet etching. The first silicon nitride film 52 is etched, for example, using a phosphoric acid solution. Then, the surface of the first silicon nitride film 52 is oxidized to form an oxide layer (not shown).

[0120] Next, a first titanium nitride film 58 is formed in the storage hole 57. Figure 11 The first titanium nitride film 58 is an example of a first film. The first titanium nitride film 58 is formed, for example, by CVD.

[0121] Next, the first titanium nitride film 58 on the first silicon oxide film 51 on the inner surface of the storage hole 57 is removed. Figure 12 The first titanium nitride film 58 is removed, for example, by the RIE method.

[0122] The first titanium nitride film 58 remains in the recess where the first silicon nitride film 52 has been removed. The first titanium nitride film 58 is formed in the portion where the first silicon nitride film 52 has been removed. The first titanium nitride film 58 ultimately becomes the charge accumulation layer 16.

[0123] Next, a third silicon oxide film 59 is formed on top of the first titanium nitride film 58 within the storage hole 57. The third silicon oxide film 59 is an example of a third insulating film. The third silicon oxide film 59 is formed, for example, by CVD. The third silicon oxide film 59 ultimately becomes the tunnel insulating layer 14.

[0124] Next, a polycrystalline silicon film 60 is formed on the third silicon oxide film 59 on the inner surface of the storage hole 57. Figure 13 The polycrystalline silicon film 60 is an example of a semiconductor film. The polycrystalline silicon film 60 is formed, for example, by a CVD method. The polycrystalline silicon film 60 ultimately becomes the semiconductor layer 12.

[0125] Next, the storage holes 57 are filled with the fourth silicon oxide film 61. Figure 14 The fourth silicon oxide film 61 is formed, for example, by CVD. The fourth silicon oxide film 61 ultimately becomes the core insulating layer 28.

[0126] Next, a slit trench 62 is formed on the first silicon oxide film 51 and the first silicon nitride film 52. Figure 15 The slit trench 62 is an example of a second opening. The slit trench 62 penetrates the first silicon oxide film 51 and the first silicon nitride film 52. Furthermore, the slit trench 62 is disposed at the end of the memory cell array 101.

[0127] Next, the first silicon nitride film 52 is selectively removed relative to the first silicon oxide film 51 via the slit trench 62. The first silicon nitride film 52 is removed, for example, by wet etching. The first silicon nitride film 52 is etched, for example, using a phosphoric acid solution. Then, the oxide layer (not shown) is removed by wet etching, exposing the first titanium nitride film 58. Figure 16 ).

[0128] Next, a copper film 63 containing manganese is formed in the portion where the first silicon nitride film 52 has been removed, in connection with the first titanium nitride film 58. Figure 17 The copper film 63 is an example of a first metal film. The copper film 63 is formed, for example, by CVD.

[0129] Next, a fifth silicon oxide film 64 is formed on the copper film 63 on the inner surface of the slit trench 62. The fifth silicon oxide film 64 is an example of a fifth insulating film.

[0130] Next, manganese diffusion annealing is performed. Figure 18 Manganese diffusion annealing is an example of the first heat treatment. Manganese diffusion annealing is carried out, for example, in an atmosphere containing argon and hydrogen. The temperature of manganese diffusion annealing is, for example, above 350°C and below 500°C.

[0131] A manganese-containing region 65 is formed between the first titanium nitride film 58 and the third silicon oxide film 59 by manganese diffusion annealing. Region 65 is also formed between the first titanium nitride film 58 and the first silicon oxide film 51, and between the copper film 63 and the first silicon oxide film 51.

[0132] Manganese diffuses within the first titanium nitride film 58, forming a manganese-containing region 65 between the first titanium nitride film 58 and the third silicon oxide film 59. The manganese-containing region 65 is manganese silicate. The diffusion of manganese within the first titanium nitride film 58 is facilitated by forming a fifth silicon oxide film 64 over a copper film 63 on the inner surface of the slit trench 62.

[0133] Manganese diffusion is halted by the formation of region 65. In other words, region 65 is self-aligned and formed between the first titanium nitride film 58 and the third silicon oxide film 59. Region 65 is self-aligned and formed between the first titanium nitride film 58 and the first silicon oxide film 51.

[0134] Next, the fifth silicon oxide film 64 on the inner surface of the slit trench 62 is removed. Figure 19 The fifth silicon oxide film 64 is removed, for example, by wet etching. The fifth silicon oxide film 64 is also removed, for example, using dilute hydrofluoric acid.

[0135] Next, the remaining manganese is removed by annealing. Figure 20 Residual manganese annealing is an example of a second heat treatment. Residual manganese annealing is carried out, for example, in an atmosphere containing argon and hydrogen. Residual manganese annealing is, for example, at a temperature above 350°C and below 500°C.

[0136] By annealing with residual manganese, an oxide film 66 containing manganese is formed on the copper film 63 on the inner surface of the slit groove 62. The oxide film 66 is formed by the reaction of residual oxygen in the heat treatment furnace with the remaining manganese in the copper film 63. By annealing with residual manganese, the remaining manganese in the copper film 63 is removed.

[0137] Next, remove the oxide film 66 ( Figure 21 The oxide film 66 is removed, for example, by wet etching. The oxide film 66 is also removed, for example, using dilute hydrofluoric acid.

[0138] Next, remove the copper film 63 ( Figure 22 The copper film 63 is removed, for example, by wet etching. Since the remaining manganese is removed, the copper film 63 can be etched, for example, by using ammonia treatment.

[0139] Next, the manganese-containing region 65 on the first silicon oxide film 51 is removed. Figure 23Region 65 deteriorates into dendrite-like hydroxide during etching of the copper film 63. The deteriorated region 65 can be removed, for example, by wet etching. Alternatively, the deteriorated region 65 can be removed using dilute hydrochloric acid. Furthermore, for region 65 between the first titanium nitride film 58 and the third silicon oxide film 59, since the first titanium nitride film 58 acts as a protective film and is not exposed to the etching solution of the copper film 63, region 65 does not deteriorate and remains as manganese silicate.

[0140] Next, a second silicon nitride film 67 and a laminated film 68 of silicon oxide and aluminum oxide are formed on the first titanium nitride film 58. Figure 24 The laminated film 68 is an example of a fourth insulating film. The second silicon nitride film 67 and the laminated film 68 are formed, for example, by CVD. The second silicon nitride film 67 ultimately becomes the barrier insulating layer 20. The laminated film 68 ultimately becomes the bulk insulating layer 18.

[0141] Next, crystallization annealing is performed. Crystallization annealing is an example of the third heat treatment. Crystallization annealing is performed, for example, in an argon atmosphere. The temperature of crystallization annealing is higher than that of manganese diffusion annealing. The temperature of crystallization annealing is, for example, above 900°C and below 1100°C. Through crystallization annealing, for example, the aluminum contained in the laminated film 68 crystallizes.

[0142] Next, a second titanium nitride film 69 and a tungsten film 70 are formed on the laminated film 68. The second titanium nitride film 69 is an example of a second metal film. The second titanium nitride film 69 and the tungsten film 70 are formed, for example, by CVD.

[0143] Next, the second titanium nitride film 69 and tungsten film 70 on the inner surface of the slit trench 62 are removed. The second titanium nitride film 69 and tungsten film 70 are removed, for example, by wet etching. The second titanium nitride film 69 and tungsten film 70 are removed, for example, using a mixed acid. The second titanium nitride film 69 ultimately becomes the barrier metal layer 10x of the gate electrode layer 10. The tungsten film 70 ultimately becomes the metal layer 10y of the gate electrode layer 10.

[0144] Then, the slit trench 62 is filled, for example, by a silica film not shown.

[0145] The storage cell array 101 of the three-dimensional NAND flash memory 100 of the embodiment is manufactured by the above manufacturing method.

[0146] Furthermore, as a variation of the above manufacturing method, in addition to the copper film 63 containing manganese, a laminated film containing both manganese and copper films can also be used as the first metal film. In this case, for example, a manganese metal film is formed by CVD in contact with the first titanium nitride film 58. Then, a copper film is formed on top of the manganese metal film.

[0147] After forming region 65 in the same manner as described above, the copper film 63 is removed. Then, the manganese film on the first titanium nitride film 58 is selectively removed relative to the first titanium nitride film 58 using a surfactant. Then, the memory cell array 101 is manufactured using the same method as described above.

[0148] Next, the function and effects of the semiconductor memory device and the manufacturing method of the semiconductor memory device according to the embodiments will be explained.

[0149] Three-dimensional NAND flash memory, which arranges storage cells in three dimensions, enables high integration and low cost. The storage cells of a three-dimensional NAND flash memory have a charge accumulation layer for maintaining charge. To improve the performance of three-dimensional NAND flash memory, the application of a layer containing metal elements in the charge accumulation layer has been investigated. For example, by applying a layer containing metal elements to the charge accumulation layer, it is expected to reduce the data write voltage and achieve a lower operating voltage.

[0150] On the other hand, when a layer containing metal elements is used in the charge accumulation layer, there are concerns about the diffusion of the metal elements contained in the charge accumulation layer, which could reduce the reliability of 3D NAND flash memory. In particular, there are concerns about the diffusion of metal elements during high-temperature annealing processes such as crystallization annealing, which crystallize the block insulating layer.

[0151] For example, the diffusion of metallic elements from the charge accumulation layer into the tunnel insulation layer may increase the leakage current and decrease the insulation withstand voltage of the tunnel insulation layer. If the leakage current of the tunnel insulation layer increases, for example, the charge retention characteristics may deteriorate. Additionally, for example, the diffusion of metallic elements from the charge accumulation layer into the bulk insulation layer may increase the leakage current and decrease the insulation withstand voltage of the bulk insulation layer.

[0152] The three-dimensional NAND flash memory 100 of this embodiment has a blocking region 22 between the charge accumulation layer 16 and the tunnel insulating layer 14. A first region 22a of the blocking region 22 is provided between the charge accumulation layer 16 and the tunnel insulating layer 14. The first region 22a is a region containing manganese (Mn), silicon (Si), and oxygen (O). The first region 22a is, for example, manganese silicate. The first region 22a has high diffusion resistance relative to metal elements, suppressing the diffusion of metal elements contained in the charge accumulation layer 16 into the tunnel insulating layer 14.

[0153] Furthermore, the three-dimensional NAND flash memory 100 of this embodiment has a second region 22b with a blocking region 22 between the charge accumulation layer 16 and the first interlayer insulating layer 26a. Furthermore, a third region 22c with a blocking region 22 is provided between the charge accumulation layer 16 and the second interlayer insulating layer 26b. The second region 22b and the third region 22c have high diffusion resistance to metal elements, suppressing the diffusion of metal elements contained in the charge accumulation layer 16 to the tunnel insulating layer 14 via the first interlayer insulating layer 26a or the second interlayer insulating layer 26b.

[0154] According to the embodiment of the three-dimensional NAND flash memory 100, by having a blocking region 22, the diffusion of metal elements contained in the charge accumulation layer 16 into the tunnel insulating layer 14 can be suppressed. Therefore, a three-dimensional NAND flash memory 100 with improved reliability can be realized.

[0155] The three-dimensional NAND flash memory 100 of this embodiment has a barrier insulating layer 20 disposed between the charge accumulation layer 16 and the block insulating layer 18. The barrier insulating layer 20 comprises silicon (Si) and nitrogen (N). The barrier insulating layer 20 is, for example, silicon nitride. The barrier insulating layer 20 prevents the diffusion of metal elements contained in the charge accumulation layer 16 into the block insulating layer 18.

[0156] According to the embodiment of the three-dimensional NAND flash memory 100, by providing a barrier insulating layer 20, the diffusion of metal elements contained in the charge accumulation layer 16 into the block insulating layer 18 can be suppressed. Therefore, a three-dimensional NAND flash memory 100 with improved reliability can be realized.

[0157] In the three-dimensional NAND flash memory 100 of the embodiment, the charge accumulation layer 16 is surrounded by the blocking region 22 and the blocking insulating layer 20, thereby effectively suppressing the diffusion of metal elements from the charge accumulation layer 16.

[0158] From the viewpoint of ensuring sufficient charge accumulation in the memory cell, the thickness of the charge accumulation layer 16 in the y-direction is preferably 2 nm or more, and more preferably 3 nm or more. From the viewpoint of miniaturizing the memory cell, the thickness of the charge accumulation layer 16 in the y-direction is preferably 20 nm or less, and more preferably 10 nm or less.

[0159] Considering ease of manufacturing, high oxidation resistance, and large charge accumulation, the charge accumulation layer 16 is preferably titanium nitride or tantalum nitride.

[0160] From the viewpoint of increasing the amount of charge accumulation, the charge accumulation layer 16 preferably contains manganese (Mn).

[0161] According to the manufacturing method of the three-dimensional NAND flash memory 100 according to the embodiment, the blocking region 22 can be self-aligned and formed between the charge accumulation layer 16 and the tunnel insulating layer 14. Therefore, it is possible to stably manufacture a three-dimensional NAND flash memory 100 with improved reliability.

[0162] In this embodiment, a memory cell array structure in which a semiconductor layer 12, which functions as a channel, is disposed between two electrically separated gate electrode layers 10 is described as an example. However, the memory cell array structure of the three-dimensional NAND flash memory is not limited to the memory cell array structure of this embodiment. For example, a memory cell array structure in which the semiconductor layer, which functions as a channel, penetrates through a plate-shaped gate electrode layer and is surrounded by the gate electrode layer can also be used.

[0163] The foregoing has described several embodiments of the present invention, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent materials of one embodiment may be substituted or modified to be the constituent materials of other embodiments. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: The first interlayer insulation layer and the second interlayer insulation layer are arranged along the first direction; A gate electrode layer is disposed between the first interlayer insulating layer and the second interlayer insulating layer; A semiconductor layer that extends along the first direction and faces the gate electrode layer in a second direction that intersects the first direction; A first insulating layer is disposed between the gate electrode layer and the semiconductor layer; A charge accumulation layer is disposed between the gate electrode layer and the first insulating layer and contains a metallic element; A second insulating layer is disposed between the gate electrode layer and the charge storage layer; A first region is disposed between the charge storage layer and the first insulating layer and comprises manganese (Mn), silicon (Si) and oxygen (O); The second region is disposed between the charge storage layer and the first interlayer insulating layer and contains manganese (Mn), silicon (Si) and oxygen (O); and The third region is disposed between the charge storage layer and the second interlayer insulating layer and contains manganese (Mn), silicon (Si) and oxygen (O).

2. The semiconductor memory device according to claim 1, further comprising: A third insulating layer is disposed between the second insulating layer and the charge accumulation layer and comprises silicon (Si) and nitrogen (N).

3. The semiconductor memory device according to claim 1, The metal element is at least one selected from titanium (Ti), tantalum (Ta), and aluminum (Al).

4. The semiconductor memory device according to claim 1, The charge accumulation layer contains nitrogen (N).

5. The semiconductor memory device according to claim 1, The charge accumulation layer contains manganese (Mn).

6. The semiconductor memory device according to claim 1, The thickness of the charge accumulation layer in the second direction is greater than 2 nm.

7. The semiconductor memory device according to claim 1, The thickness of the charge accumulation layer in the second direction is greater than the thickness of the first insulating layer in the second direction.

8. The semiconductor memory device according to claim 1, The first insulating layer comprises silicon (Si) and oxygen (O).

9. The semiconductor memory device according to claim 1, The second insulating layer comprises aluminum (Al) and oxygen (O).

10. The semiconductor memory device according to claim 1, The first interlayer insulating layer and the second interlayer insulating layer comprise silicon (Si) and oxygen (O).

11. A method for manufacturing a semiconductor memory device, comprising: The first insulating film and the second insulating film are formed alternately and repeatedly; A first opening is formed that penetrates the first insulating film and the second insulating film; The portion of the second insulating film exposed on the inner surface of the first opening is selectively removed relative to the first insulating film; A first film containing metallic elements is formed in the portion where the second insulating film has been removed; A third insulating film is formed on top of the first film; A semiconductor film is formed on the third insulating film within the first opening; A second opening is formed that penetrates the first insulating film and the second insulating film; The second insulating film is selectively removed relative to the first insulating film through the second opening, exposing the first film; A first metal film containing copper (Cu) and manganese (Mn) is formed in a manner that connects the portion where the second insulating film has been removed to the first film; After the first metal film is formed, a first heat treatment is performed to form a region containing manganese (Mn) between the first film and the third insulating film and between the first film and the first insulating film. Remove the first metal film, and form a fourth insulating film in the portion where the first metal film has been removed; as well as A second metal film is formed on the fourth insulating film on which the portion of the first metal film has been removed.

12. The method for manufacturing a semiconductor memory device according to claim 11, The metal element is at least one selected from titanium (Ti), tantalum (Ta), and aluminum (Al).

13. The method for manufacturing a semiconductor memory device according to claim 11 or 12, The first membrane contains nitrogen (N).

14. The method of manufacturing a semiconductor memory device according to claim 11, comprising: After the first metal film is formed and before the first heat treatment, a fifth insulating film is formed on the first metal film; and After the first heat treatment, the fifth insulating film is removed.

15. A method for manufacturing a semiconductor memory device according to claim 14, comprising: After the fifth insulating film is removed and before the first metal film is removed, a second heat treatment is performed to form an oxide film containing manganese (Mn) on the first metal film. and The oxide film is removed before the first metal film is removed.

16. The method of manufacturing a semiconductor memory device according to claim 11, comprising: After the fourth insulating film is formed and before the second metal film is formed, a third heat treatment is performed at a temperature higher than that of the first heat treatment.

17. The method for manufacturing a semiconductor memory device according to claim 11, The first metal film is a laminated film containing manganese (Mn) and copper (Cu).

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